[llvm] [GlobalISel] Avoid redundant copies of GEPs results (PR #218352)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 24 01:52:29 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Cullen Rhodes (c-rhodes)
<details>
<summary>Changes</summary>
Improves aarch64-O0-g CTMark geomean -0.09%.
http://llvm-compile-time-tracker.com/compare.php?from=a49d90627bd44d2e76c20b9d4e0cafb339fb806f&to=93d6aa1f114cfe43c4bd7b569cd36f703fa0a9c8&stat=instructions%3Au
Assisted-by: codex
---
Full diff: https://github.com/llvm/llvm-project/pull/218352.diff
7 Files Affected:
- (modified) llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp (+1-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll (+2-6)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-gep-flags.ll (+5-10)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-one-by-n-vector-ptr-add.ll (+2-4)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll (+6-12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll (+1-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll (+6-12)
``````````diff
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 4c4527c016271..0a9d6926410c2 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -2513,8 +2513,7 @@ bool IRTranslatorImpl::translateGetElementPtr(const User &U,
return true;
}
- MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg);
- return true;
+ return translateCopy(U, BaseReg, MIRBuilder);
}
bool IRTranslatorImpl::translateMemFunc(const CallInst &CI,
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
index 269597cbd730b..edc1b0a974b9f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
@@ -15,8 +15,7 @@ define i32 @cse_gep(ptr %ptr, i32 %idx) {
; O0-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; O0-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
; O0-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](i64)
- ; O0-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; O0-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY2]](p0) :: (load (i32) from %ir.gep1)
+ ; O0-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD]](p0) :: (load (i32) from %ir.gep1)
; O0-NEXT: [[MUL1:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
; O0-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL1]](i64)
; O0-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
@@ -36,8 +35,7 @@ define i32 @cse_gep(ptr %ptr, i32 %idx) {
; O3-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; O3-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
; O3-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](i64)
- ; O3-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; O3-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY2]](p0) :: (load (i32) from %ir.gep1)
+ ; O3-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD]](p0) :: (load (i32) from %ir.gep1)
; O3-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
; O3-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD]], [[C1]](i64)
; O3-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD1]](p0) :: (load (i32) from %ir.gep2)
@@ -65,7 +63,6 @@ define void @ossfuzz65052() {
; O0-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; O0-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[TRUNC]], [[C1]]
; O0-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[MUL]](i64)
- ; O0-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; O0-NEXT: G_BR %bb.2
; O0-NEXT: {{ $}}
; O0-NEXT: bb.2.BB:
@@ -83,7 +80,6 @@ define void @ossfuzz65052() {
; O3-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; O3-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[TRUNC]], [[C1]]
; O3-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[MUL]](i64)
- ; O3-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; O3-NEXT: {{ $}}
; O3-NEXT: bb.2.BB:
; O3-NEXT: successors: %bb.2(0x80000000)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-gep-flags.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-gep-flags.ll
index 24e85f566e0c5..7f596ca20234d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-gep-flags.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-gep-flags.ll
@@ -12,8 +12,7 @@ define i32 @gep_nusw_nuw(ptr %ptr, i32 %idx) {
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](i64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY2]](p0) :: (load (i32) from %ir.gep1)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD]](p0) :: (load (i32) from %ir.gep1)
; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(i64) = nuw nsw G_MUL [[SEXT]], [[C]]
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[COPY]], [[MUL1]](i64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
@@ -42,8 +41,7 @@ define i32 @gep_nuw(ptr %ptr, i32 %idx) {
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](i64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY2]](p0) :: (load (i32) from %ir.gep1)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD]](p0) :: (load (i32) from %ir.gep1)
; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(i64) = nuw G_MUL [[SEXT]], [[C]]
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[MUL1]](i64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
@@ -72,8 +70,7 @@ define i32 @gep_nusw(ptr %ptr, i32 %idx) {
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](i64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY2]](p0) :: (load (i32) from %ir.gep1)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD]](p0) :: (load (i32) from %ir.gep1)
; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nusw G_PTR_ADD [[COPY]], [[MUL1]](i64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
@@ -102,8 +99,7 @@ define i32 @gep_none(ptr %ptr, i32 %idx) {
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](i64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY2]](p0) :: (load (i32) from %ir.gep1)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD]](p0) :: (load (i32) from %ir.gep1)
; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(i64) = G_MUL [[SEXT]], [[C]]
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL1]](i64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
@@ -132,8 +128,7 @@ define i32 @gep_nusw_negative(ptr %ptr, i32 %idx) {
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](i64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY2]](p0) :: (load (i32) from %ir.gep1)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD]](p0) :: (load (i32) from %ir.gep1)
; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nusw G_PTR_ADD [[COPY]], [[MUL1]](i64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 -4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-one-by-n-vector-ptr-add.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-one-by-n-vector-ptr-add.ll
index 07d406726e253..e9a02e768b305 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-one-by-n-vector-ptr-add.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-one-by-n-vector-ptr-add.ll
@@ -17,8 +17,7 @@ define <1 x ptr> @one_elt_vector_ptr_add_non_vector_idx(<1 x ptr> %vec) {
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY [[C]](i32)
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[SEXT]](i64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; CHECK-NEXT: $d0 = COPY [[COPY2]](p0)
+ ; CHECK-NEXT: $d0 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $d0
;
; CHECK-CI-LABEL: name: one_elt_vector_ptr_add_non_vector_idx
@@ -47,8 +46,7 @@ define <1 x ptr> @one_elt_vector_ptr_add_non_vector_ptr(ptr %vec) {
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY [[C]](i32)
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[SEXT]](i64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; CHECK-NEXT: $d0 = COPY [[COPY2]](p0)
+ ; CHECK-NEXT: $d0 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $d0
;
; CHECK-CI-LABEL: name: one_elt_vector_ptr_add_non_vector_ptr
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll b/llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
index 641efb51dd72a..46271256fc840 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
@@ -11,8 +11,7 @@ define ptr @translate_element_size1(i64 %arg) {
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
; CHECK-NEXT: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[C]], [[COPY]](i64)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; CHECK-NEXT: $x0 = COPY [[COPY1]](p0)
+ ; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%tmp = getelementptr i8, ptr null, i64 %arg
ret ptr %tmp
@@ -57,8 +56,7 @@ define ptr @first_offset_variable(ptr %addr, i64 %idx) {
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[COPY1]], [[C]]
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](i64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)
+ ; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%res = getelementptr %type, ptr %addr, i64 %idx
ret ptr %res
@@ -76,8 +74,7 @@ define ptr @first_offset_ext(ptr %addr, i32 %idx) {
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[SEXT]], [[C]]
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](i64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)
+ ; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%res = getelementptr %type, ptr %addr, i32 %idx
ret ptr %res
@@ -97,8 +94,7 @@ define ptr @const_then_var(ptr %addr, i64 %idx) {
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[COPY1]], [[C1]]
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[MUL]](i64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD1]](p0)
- ; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)
+ ; CHECK-NEXT: $x0 = COPY [[PTR_ADD1]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%res = getelementptr %type1, ptr %addr, i32 4, i32 1, i64 %idx
ret ptr %res
@@ -137,8 +133,7 @@ define <2 x ptr> @vec_gep_scalar_base(<2 x i64> %offs) {
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<2 x i64>) = nsw G_MUL [[COPY]], [[BUILD_VECTOR1]]
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(<2 x p0>) = nusw inbounds G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x i64>)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY [[PTR_ADD]](<2 x p0>)
- ; CHECK-NEXT: $q0 = COPY [[COPY1]](<2 x p0>)
+ ; CHECK-NEXT: $q0 = COPY [[PTR_ADD]](<2 x p0>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
entry:
%0 = getelementptr inbounds [8 x i32], ptr @arr, i64 0, <2 x i64> %offs
@@ -158,8 +153,7 @@ define <4 x ptr> @vector_gep_v4i32(<4 x ptr> %b, <4 x i32> %off) {
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x i32>) = COPY $q2
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<4 x i64>) = G_SEXT [[COPY2]](<4 x i32>)
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(<4 x p0>) = G_PTR_ADD [[CONCAT_VECTORS]], [[SEXT]](<4 x i64>)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x p0>) = COPY [[PTR_ADD]](<4 x p0>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x i64>), [[UV1:%[0-9]+]]:_(<2 x i64>) = G_UNMERGE_VALUES [[COPY3]](<4 x p0>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x i64>), [[UV1:%[0-9]+]]:_(<2 x i64>) = G_UNMERGE_VALUES [[PTR_ADD]](<4 x p0>)
; CHECK-NEXT: $q0 = COPY [[UV]](<2 x i64>)
; CHECK-NEXT: $q1 = COPY [[UV1]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
index 898e987f4a826..7ea054e6a7bb7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
@@ -999,8 +999,7 @@ define <33 x i32> @v33i32_func_v33i32_i32(ptr addrspace(1) %p, i32 %idx) #0 {
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 256
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = nusw inbounds G_PTR_ADD [[MV]], [[MUL]](i64)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(p1) = COPY [[PTR_ADD]](p1)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<33 x i32>) = G_LOAD [[COPY4]](p1) :: (load (<33 x i32>) from %ir.gep, align 256, addrspace 1)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<33 x i32>) = G_LOAD [[PTR_ADD]](p1) :: (load (<33 x i32>) from %ir.gep, align 256, addrspace 1)
; CHECK-NEXT: G_STORE [[LOAD]](<33 x i32>), [[COPY]](p5) :: (store (<33 x i32>), align 256, addrspace 5)
; CHECK-NEXT: SI_RETURN
%gep = getelementptr inbounds <33 x i32>, ptr addrspace(1) %p, i32 %idx
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll
index 524d9ea5a423d..fd7b7056ad57d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll
@@ -25,8 +25,7 @@ define <2 x ptr addrspace(1)> @vector_gep_v2p1_index_v2i64(<2 x ptr addrspace(1)
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<2 x i64>) = G_MUL [[BUILD_VECTOR1]], [[BUILD_VECTOR2]]
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x i64>)
- ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY8]](<2 x p1>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[PTR_ADD]](<2 x p1>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
; CHECK-NEXT: $vgpr2 = COPY [[UV2]](i32)
@@ -52,8 +51,7 @@ define <2 x ptr addrspace(3)> @vector_gep_v2p3_index_v2i32(<2 x ptr addrspace(3)
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C]](i32), [[C]](i32)
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<2 x i32>) = G_MUL [[BUILD_VECTOR1]], [[BUILD_VECTOR2]]
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(<2 x p3>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x i32>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<2 x p3>) = COPY [[PTR_ADD]](<2 x p3>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY4]](<2 x p3>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[PTR_ADD]](<2 x p3>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
@@ -82,8 +80,7 @@ define <2 x ptr addrspace(1)> @vector_gep_v2p1_index_v2i32(<2 x ptr addrspace(1)
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<2 x i64>) = G_MUL [[SEXT]], [[BUILD_VECTOR2]]
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x i64>)
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY6]](<2 x p1>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[PTR_ADD]](<2 x p1>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
; CHECK-NEXT: $vgpr2 = COPY [[UV2]](i32)
@@ -115,8 +112,7 @@ define <2 x ptr addrspace(1)> @vector_gep_v2p1_index_i64(<2 x ptr addrspace(1)>
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<2 x i64>) = G_MUL [[COPY6]], [[BUILD_VECTOR2]]
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x i64>)
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY7]](<2 x p1>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[PTR_ADD]](<2 x p1>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
; CHECK-NEXT: $vgpr2 = COPY [[UV2]](i32)
@@ -146,8 +142,7 @@ define <2 x ptr addrspace(1)> @vector_gep_v2p1_index_i32(<2 x ptr addrspace(1)>
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<2 x i64>) = G_MUL [[SEXT]], [[BUILD_VECTOR2]]
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x i64>)
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY5]](<2 x p1>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[PTR_ADD]](<2 x p1>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
; CHECK-NEXT: $vgpr2 = COPY [[UV2]](i32)
@@ -185,8 +180,7 @@ define <2 x ptr addrspace(1)> @vector_gep_v2p1_index_v2i64_constant(<2 x ptr add
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
; CHECK-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C2]](i64), [[C3]](i64)
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[BUILD_VECTOR4]](<2 x i64>)
- ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY8]](<2 x p1>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[PTR_ADD]](<2 x p1>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
; CHECK-NEXT: $vgpr2 = COPY [[UV2]](i32)
``````````
</details>
https://github.com/llvm/llvm-project/pull/218352
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