[llvm] [RISCV] Disable shrink wrapping for SiFive CLIC preemptible handlers (PR #218347)

[Zeyi Xu via llvm-commits]

https://github.com/zeyi2 created https://github.com/llvm/llvm-project/pull/218347

None

>From a870096c253d16caf9d774232a377e092b063206 Mon Sep 17 00:00:00 2001
From: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: Mon, 24 Aug 2026 16:24:26 +0800
Subject: [PATCH] [RISCV] Disable shrink wrapping for SiFive CLIC preemptible
 handlers

---
 llvm/docs/ReleaseNotes.md                     |  2 ++
 llvm/lib/Target/RISCV/RISCVFrameLowering.cpp  |  3 +++
 .../RISCV/sifive-interrupt-shrink-wrap.ll     | 25 +++++++++++++++++++
 3 files changed, 30 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/sifive-interrupt-shrink-wrap.ll

diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 051d726b7aa8d..2defe92321cbf 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -122,6 +122,8 @@ Makes programs 10x faster by doing Special New Thing.
   vectoring extensions.
 * Added experimental MC support for the `Smip` and `Ssip` interrupt handler
   push/pop extensions.
+* Fixed SiFive CLIC preemptible interrupt handlers potentially executing
+  without their required prologue when shrink wrapping was enabled.
 * Bump Svukte extension to 1.0.
 * Remove experimental from Zicfiss.
 
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 35a36497d4f65..498b3b9be33dd 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -2647,6 +2647,9 @@ bool RISCVFrameLowering::restoreCalleeSavedRegisters(
 }
 
 bool RISCVFrameLowering::enableShrinkWrapping(const MachineFunction &MF) const {
+  if (MF.getInfo<RISCVMachineFunctionInfo>()->isSiFivePreemptibleInterrupt(MF))
+    return false;
+
   // Keep the conventional code flow when not optimizing.
   if (MF.getFunction().hasOptNone())
     return false;
diff --git a/llvm/test/CodeGen/RISCV/sifive-interrupt-shrink-wrap.ll b/llvm/test/CodeGen/RISCV/sifive-interrupt-shrink-wrap.ll
new file mode 100644
index 0000000000000..9214e4b490fe2
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/sifive-interrupt-shrink-wrap.ll
@@ -0,0 +1,25 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xsfmclic \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-xsfmclic \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s
+
+declare ptr @llvm.thread.pointer()
+declare void @panic() noreturn
+
+define void @handler() "interrupt"="SiFive-CLIC-preemptible" {
+; CHECK-LABEL: handler:
+; CHECK:       csrsi mstatus, 8
+; CHECK:       beqz tp,
+entry:
+  %tp = call ptr @llvm.thread.pointer()
+  %isnull = icmp eq ptr %tp, null
+  br i1 %isnull, label %panic, label %return
+
+return:
+  store volatile i32 0, ptr %tp
+  ret void
+
+panic:
+  call void @panic()
+  unreachable
+}