[llvm] [GlobalISel] Preserve specific LLTs in constrainRegAttrs (PR #218345)

[Keshav Vinayak Jha via llvm-commits]

https://github.com/keshavvinayak01 created https://github.com/llvm/llvm-project/pull/218345

With extended LLTs, an any-scalar type such as `s64` is compatible with a more specific type such as `i64`. `constrainRegAttrs` currently unconditionally adopts the constraining register's type, so `i64` can be degraded to `s64` depending on argument order.

Only update the type when the current type is invalid or any-scalar. This preserves specific LLTs while continuing to refine `s64` to `i64`. Add unit coverage for both argument orders.

Tests: `AMDGPUGISelMITest.ConstrainRegAttrsPreservesSpecificLLT`. Also verified the AMDGPU CSE reproducer in a stacked checkout.


>From dbd41d3235983fbf8e0c8c94f836c9ef4a3348de Mon Sep 17 00:00:00 2001
From: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Date: Mon, 24 Aug 2026 13:51:20 +0530
Subject: [PATCH] [GlobalISel] Preserve specific LLTs in constrainRegAttrs

Do not replace a specific extended LLT with a compatible any-scalar type when constraining register attributes. Continue refining an any-scalar type to a more specific constraining type, and cover both argument orders.

Co-authored-by: GPT-5 <noreply at openai.com>
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
---
 llvm/lib/CodeGen/MachineRegisterInfo.cpp      |  5 +++-
 .../CodeGen/GlobalISel/CMakeLists.txt         |  1 +
 .../GlobalISel/MachineRegisterInfoTest.cpp    | 27 +++++++++++++++++++
 3 files changed, 32 insertions(+), 1 deletion(-)
 create mode 100644 llvm/unittests/CodeGen/GlobalISel/MachineRegisterInfoTest.cpp

diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
index dbba413548018..fb7430195aef6 100644
--- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -111,7 +111,10 @@ MachineRegisterInfo::constrainRegAttrs(Register Reg,
     } else if (RegCB != ConstrainingRegCB)
       return false;
   }
-  if (ConstrainingRegTy.isValid())
+  // Refine an any-scalar element type to the constraining type, but do not
+  // discard a more specific extended LLT in favor of an any-scalar type.
+  if (ConstrainingRegTy.isValid() &&
+      (!RegTy.isValid() || RegTy.getScalarType().isAnyScalar()))
     setType(Reg, ConstrainingRegTy);
   return true;
 }
diff --git a/llvm/unittests/CodeGen/GlobalISel/CMakeLists.txt b/llvm/unittests/CodeGen/GlobalISel/CMakeLists.txt
index e85a3aa72c961..a16d70bf6d973 100644
--- a/llvm/unittests/CodeGen/GlobalISel/CMakeLists.txt
+++ b/llvm/unittests/CodeGen/GlobalISel/CMakeLists.txt
@@ -22,6 +22,7 @@ add_llvm_unittest(GlobalISelTests
   LegalizerHelperTest.cpp
   LegalizerInfoTest.cpp
   MachineIRBuilderTest.cpp
+  MachineRegisterInfoTest.cpp
   GISelMITest.cpp
   PatternMatchTest.cpp
   KnownBitsTest.cpp
diff --git a/llvm/unittests/CodeGen/GlobalISel/MachineRegisterInfoTest.cpp b/llvm/unittests/CodeGen/GlobalISel/MachineRegisterInfoTest.cpp
new file mode 100644
index 0000000000000..1af169c43d83d
--- /dev/null
+++ b/llvm/unittests/CodeGen/GlobalISel/MachineRegisterInfoTest.cpp
@@ -0,0 +1,27 @@
+//===- MachineRegisterInfoTest.cpp ---------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "GISelMITest.h"
+
+TEST_F(AMDGPUGISelMITest, ConstrainRegAttrsPreservesSpecificLLT) {
+  setUp();
+  if (!TM)
+    GTEST_SKIP();
+
+  const LLT S64 = LLT::scalar(64);
+  const LLT I64 = LLT::integer(64);
+  Register SpecificReg = MRI->createGenericVirtualRegister(I64);
+  Register AnyReg = MRI->createGenericVirtualRegister(S64);
+
+  EXPECT_TRUE(MRI->constrainRegAttrs(SpecificReg, AnyReg));
+  EXPECT_TRUE(MRI->getType(SpecificReg).isInteger());
+
+  EXPECT_TRUE(MRI->constrainRegAttrs(AnyReg, SpecificReg));
+  EXPECT_TRUE(MRI->getType(AnyReg).isInteger());
+}