[llvm] [AArch64][GlobalISel] Enable constant_fold_cast_op post-legalization (PR #218332)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 23 23:34:50 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: David Green (davemgreen)
<details>
<summary>Changes</summary>
We were not enabling constant_fold_cast_op post-legalization. Doing so allows us to clear up some s/z/anyext(constant)'s.
---
Patch is 55.35 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/218332.diff
11 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64Combine.td (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-and-trivial-mask.mir (+1-2)
- (modified) llvm/test/CodeGen/AArch64/combine-sdiv.ll (+142-166)
- (modified) llvm/test/CodeGen/AArch64/cttz.ll (+11-17)
- (modified) llvm/test/CodeGen/AArch64/fcvt-i256.ll (+42-74)
- (modified) llvm/test/CodeGen/AArch64/is_fpclass.ll (+21-43)
- (modified) llvm/test/CodeGen/AArch64/neon-anyof-splat.ll (+1-5)
- (modified) llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll (+8-20)
- (modified) llvm/test/CodeGen/AArch64/neon-compare-instructions.ll (+5-15)
- (modified) llvm/test/CodeGen/AArch64/rem-by-const.ll (+134-164)
- (modified) llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll (+16-33)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64Combine.td b/llvm/lib/Target/AArch64/AArch64Combine.td
index 092906bcbe4a1..7a8083e3ceb44 100644
--- a/llvm/lib/Target/AArch64/AArch64Combine.td
+++ b/llvm/lib/Target/AArch64/AArch64Combine.td
@@ -397,7 +397,7 @@ def AArch64PostLegalizerLowering
// Post-legalization combines which are primarily optimizations.
def AArch64PostLegalizerCombiner
: GICombiner<"AArch64PostLegalizerCombinerImpl",
- [copy_prop, cast_of_cast_combines, constant_fold_fp_ops,
+ [copy_prop, cast_of_cast_combines, constant_fold_fp_ops,
buildvector_of_truncate, integer_of_truncate,
mutate_anyext_to_zext, combines_for_extload,
combine_indexed_load_store, sext_trunc_sextload,
@@ -411,7 +411,7 @@ def AArch64PostLegalizerCombiner
icmp_to_true_false_known_bits, overflow_combines,
select_combines, select_zero_true, select_zero_false, select_not,
fold_merge_to_zext, merge_combines,
- constant_fold_binops, identity_combines,
+ constant_fold_binops, constant_fold_cast_op, identity_combines,
ptr_add_immed_chain, overlapping_and,
split_store_zero_128, undef_combines,
select_to_minmax, or_to_bsp, trunc_or_to_addhn,
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-and-trivial-mask.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-and-trivial-mask.mir
index 5dc61236279dc..7a287acc6a3ce 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-and-trivial-mask.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-and-trivial-mask.mir
@@ -161,8 +161,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:_(i32) = COPY $w0
; CHECK-NEXT: %y:_(i32) = COPY $w1
- ; CHECK-NEXT: %z:_(i32) = G_CONSTANT i32 42
- ; CHECK-NEXT: %ext:_(i64) = G_SEXT %z(i32)
+ ; CHECK-NEXT: %ext:_(i64) = G_CONSTANT i64 42
; CHECK-NEXT: $x0 = COPY %ext(i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%x:_(i32) = COPY $w0
diff --git a/llvm/test/CodeGen/AArch64/combine-sdiv.ll b/llvm/test/CodeGen/AArch64/combine-sdiv.ll
index fbb33db3fb7a9..b160333edb487 100644
--- a/llvm/test/CodeGen/AArch64/combine-sdiv.ll
+++ b/llvm/test/CodeGen/AArch64/combine-sdiv.ll
@@ -163,20 +163,17 @@ define <4 x i32> @combine_vec_sdiv_by_pos1(<4 x i32> %x) {
;
; CHECK-GI-LABEL: combine_vec_sdiv_by_pos1:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #1 // =0x1
-; CHECK-GI-NEXT: movi v2.2d, #0x0000ff000000ff
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: adrp x8, .LCPI11_0
-; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI11_0]
-; CHECK-GI-NEXT: mov v1.s[1], wzr
-; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-GI-NEXT: neg v2.4s, v3.4s
-; CHECK-GI-NEXT: sshl v2.4s, v0.4s, v2.4s
-; CHECK-GI-NEXT: mov v1.s[2], wzr
-; CHECK-GI-NEXT: mov v1.s[3], wzr
-; CHECK-GI-NEXT: shl v1.4s, v1.4s, #31
-; CHECK-GI-NEXT: cmlt v1.4s, v1.4s, #0
-; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b
+; CHECK-GI-NEXT: movi v1.2d, #0x0000ff000000ff
+; CHECK-GI-NEXT: adrp x8, .LCPI11_1
+; CHECK-GI-NEXT: adrp x9, .LCPI11_0
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI11_1]
+; CHECK-GI-NEXT: ldr q3, [x9, :lo12:.LCPI11_0]
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: neg v1.4s, v2.4s
+; CHECK-GI-NEXT: shl v2.4s, v3.4s, #31
+; CHECK-GI-NEXT: sshl v1.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: cmlt v2.4s, v2.4s, #0
+; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
; CHECK-GI-NEXT: ret
%1 = and <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
%2 = sdiv <4 x i32> %1, <i32 1, i32 4, i32 8, i32 16>
@@ -418,24 +415,21 @@ define <4 x i32> @combine_vec_sdiv_by_pow2b_v4i32(<4 x i32> %x) {
;
; CHECK-GI-LABEL: combine_vec_sdiv_by_pow2b_v4i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #1 // =0x1
-; CHECK-GI-NEXT: cmlt v3.4s, v0.4s, #0
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: adrp x8, .LCPI18_0
-; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI18_0]
; CHECK-GI-NEXT: adrp x8, .LCPI18_1
-; CHECK-GI-NEXT: mov v1.s[1], wzr
+; CHECK-GI-NEXT: cmlt v2.4s, v0.4s, #0
+; CHECK-GI-NEXT: adrp x9, .LCPI18_0
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI18_1]
+; CHECK-GI-NEXT: adrp x8, .LCPI18_2
+; CHECK-GI-NEXT: ldr q3, [x9, :lo12:.LCPI18_0]
+; CHECK-GI-NEXT: neg v1.4s, v1.4s
+; CHECK-GI-NEXT: shl v3.4s, v3.4s, #31
+; CHECK-GI-NEXT: ushl v1.4s, v2.4s, v1.4s
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI18_2]
; CHECK-GI-NEXT: neg v2.4s, v2.4s
-; CHECK-GI-NEXT: ushl v2.4s, v3.4s, v2.4s
-; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI18_1]
-; CHECK-GI-NEXT: mov v1.s[2], wzr
-; CHECK-GI-NEXT: neg v3.4s, v3.4s
-; CHECK-GI-NEXT: add v2.4s, v0.4s, v2.4s
-; CHECK-GI-NEXT: mov v1.s[3], wzr
-; CHECK-GI-NEXT: sshl v2.4s, v2.4s, v3.4s
-; CHECK-GI-NEXT: shl v1.4s, v1.4s, #31
-; CHECK-GI-NEXT: cmlt v1.4s, v1.4s, #0
-; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b
+; CHECK-GI-NEXT: add v1.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: sshl v1.4s, v1.4s, v2.4s
+; CHECK-GI-NEXT: cmlt v2.4s, v3.4s, #0
+; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
; CHECK-GI-NEXT: ret
%1 = sdiv <4 x i32> %x, <i32 1, i32 4, i32 8, i32 16>
ret <4 x i32> %1
@@ -464,30 +458,27 @@ define <8 x i32> @combine_vec_sdiv_by_pow2b_v8i32(<8 x i32> %x) {
;
; CHECK-GI-LABEL: combine_vec_sdiv_by_pow2b_v8i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #1 // =0x1
-; CHECK-GI-NEXT: cmlt v4.4s, v0.4s, #0
-; CHECK-GI-NEXT: cmlt v5.4s, v1.4s, #0
-; CHECK-GI-NEXT: fmov s2, w8
-; CHECK-GI-NEXT: adrp x8, .LCPI19_0
-; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI19_0]
; CHECK-GI-NEXT: adrp x8, .LCPI19_1
-; CHECK-GI-NEXT: mov v2.h[1], wzr
-; CHECK-GI-NEXT: neg v3.4s, v3.4s
-; CHECK-GI-NEXT: ushl v4.4s, v4.4s, v3.4s
-; CHECK-GI-NEXT: ushl v3.4s, v5.4s, v3.4s
-; CHECK-GI-NEXT: ldr q5, [x8, :lo12:.LCPI19_1]
-; CHECK-GI-NEXT: mov v2.h[2], wzr
-; CHECK-GI-NEXT: neg v5.4s, v5.4s
-; CHECK-GI-NEXT: add v4.4s, v0.4s, v4.4s
-; CHECK-GI-NEXT: add v3.4s, v1.4s, v3.4s
-; CHECK-GI-NEXT: mov v2.h[3], wzr
-; CHECK-GI-NEXT: sshl v4.4s, v4.4s, v5.4s
-; CHECK-GI-NEXT: sshl v3.4s, v3.4s, v5.4s
-; CHECK-GI-NEXT: ushll v2.4s, v2.4h, #0
-; CHECK-GI-NEXT: shl v2.4s, v2.4s, #31
-; CHECK-GI-NEXT: cmlt v2.4s, v2.4s, #0
-; CHECK-GI-NEXT: bif v0.16b, v4.16b, v2.16b
-; CHECK-GI-NEXT: bif v1.16b, v3.16b, v2.16b
+; CHECK-GI-NEXT: cmlt v3.4s, v0.4s, #0
+; CHECK-GI-NEXT: cmlt v4.4s, v1.4s, #0
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI19_1]
+; CHECK-GI-NEXT: adrp x8, .LCPI19_0
+; CHECK-GI-NEXT: ldr d5, [x8, :lo12:.LCPI19_0]
+; CHECK-GI-NEXT: adrp x8, .LCPI19_2
+; CHECK-GI-NEXT: neg v2.4s, v2.4s
+; CHECK-GI-NEXT: ushll v5.4s, v5.4h, #0
+; CHECK-GI-NEXT: ushl v3.4s, v3.4s, v2.4s
+; CHECK-GI-NEXT: ushl v2.4s, v4.4s, v2.4s
+; CHECK-GI-NEXT: ldr q4, [x8, :lo12:.LCPI19_2]
+; CHECK-GI-NEXT: shl v5.4s, v5.4s, #31
+; CHECK-GI-NEXT: neg v4.4s, v4.4s
+; CHECK-GI-NEXT: add v3.4s, v0.4s, v3.4s
+; CHECK-GI-NEXT: add v2.4s, v1.4s, v2.4s
+; CHECK-GI-NEXT: sshl v3.4s, v3.4s, v4.4s
+; CHECK-GI-NEXT: sshl v2.4s, v2.4s, v4.4s
+; CHECK-GI-NEXT: cmlt v4.4s, v5.4s, #0
+; CHECK-GI-NEXT: bif v0.16b, v3.16b, v4.16b
+; CHECK-GI-NEXT: bif v1.16b, v2.16b, v4.16b
; CHECK-GI-NEXT: ret
%1 = sdiv <8 x i32> %x, <i32 1, i32 4, i32 8, i32 16, i32 1, i32 4, i32 8, i32 16>
ret <8 x i32> %1
@@ -526,40 +517,37 @@ define <16 x i32> @combine_vec_sdiv_by_pow2b_v16i32(<16 x i32> %x) {
;
; CHECK-GI-LABEL: combine_vec_sdiv_by_pow2b_v16i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #1 // =0x1
-; CHECK-GI-NEXT: cmlt v6.4s, v0.4s, #0
-; CHECK-GI-NEXT: cmlt v7.4s, v1.4s, #0
-; CHECK-GI-NEXT: fmov s4, w8
-; CHECK-GI-NEXT: adrp x8, .LCPI20_0
-; CHECK-GI-NEXT: cmlt v16.4s, v2.4s, #0
-; CHECK-GI-NEXT: ldr q5, [x8, :lo12:.LCPI20_0]
-; CHECK-GI-NEXT: cmlt v17.4s, v3.4s, #0
; CHECK-GI-NEXT: adrp x8, .LCPI20_1
-; CHECK-GI-NEXT: mov v4.h[1], wzr
-; CHECK-GI-NEXT: neg v5.4s, v5.4s
-; CHECK-GI-NEXT: ushl v6.4s, v6.4s, v5.4s
-; CHECK-GI-NEXT: ushl v7.4s, v7.4s, v5.4s
-; CHECK-GI-NEXT: ushl v16.4s, v16.4s, v5.4s
-; CHECK-GI-NEXT: mov v4.h[2], wzr
-; CHECK-GI-NEXT: ushl v5.4s, v17.4s, v5.4s
-; CHECK-GI-NEXT: ldr q17, [x8, :lo12:.LCPI20_1]
-; CHECK-GI-NEXT: neg v17.4s, v17.4s
-; CHECK-GI-NEXT: add v6.4s, v0.4s, v6.4s
-; CHECK-GI-NEXT: add v7.4s, v1.4s, v7.4s
-; CHECK-GI-NEXT: add v16.4s, v2.4s, v16.4s
-; CHECK-GI-NEXT: add v5.4s, v3.4s, v5.4s
-; CHECK-GI-NEXT: mov v4.h[3], wzr
-; CHECK-GI-NEXT: sshl v6.4s, v6.4s, v17.4s
-; CHECK-GI-NEXT: sshl v7.4s, v7.4s, v17.4s
-; CHECK-GI-NEXT: sshl v16.4s, v16.4s, v17.4s
-; CHECK-GI-NEXT: sshl v5.4s, v5.4s, v17.4s
-; CHECK-GI-NEXT: ushll v4.4s, v4.4h, #0
-; CHECK-GI-NEXT: shl v4.4s, v4.4s, #31
-; CHECK-GI-NEXT: cmlt v4.4s, v4.4s, #0
-; CHECK-GI-NEXT: bif v0.16b, v6.16b, v4.16b
-; CHECK-GI-NEXT: bif v1.16b, v7.16b, v4.16b
-; CHECK-GI-NEXT: bif v2.16b, v16.16b, v4.16b
-; CHECK-GI-NEXT: bif v3.16b, v5.16b, v4.16b
+; CHECK-GI-NEXT: cmlt v5.4s, v0.4s, #0
+; CHECK-GI-NEXT: cmlt v6.4s, v1.4s, #0
+; CHECK-GI-NEXT: ldr q4, [x8, :lo12:.LCPI20_1]
+; CHECK-GI-NEXT: adrp x8, .LCPI20_0
+; CHECK-GI-NEXT: cmlt v7.4s, v2.4s, #0
+; CHECK-GI-NEXT: cmlt v16.4s, v3.4s, #0
+; CHECK-GI-NEXT: ldr d17, [x8, :lo12:.LCPI20_0]
+; CHECK-GI-NEXT: adrp x8, .LCPI20_2
+; CHECK-GI-NEXT: neg v4.4s, v4.4s
+; CHECK-GI-NEXT: ushll v17.4s, v17.4h, #0
+; CHECK-GI-NEXT: ushl v5.4s, v5.4s, v4.4s
+; CHECK-GI-NEXT: ushl v6.4s, v6.4s, v4.4s
+; CHECK-GI-NEXT: ushl v7.4s, v7.4s, v4.4s
+; CHECK-GI-NEXT: ushl v4.4s, v16.4s, v4.4s
+; CHECK-GI-NEXT: ldr q16, [x8, :lo12:.LCPI20_2]
+; CHECK-GI-NEXT: shl v17.4s, v17.4s, #31
+; CHECK-GI-NEXT: neg v16.4s, v16.4s
+; CHECK-GI-NEXT: add v5.4s, v0.4s, v5.4s
+; CHECK-GI-NEXT: add v6.4s, v1.4s, v6.4s
+; CHECK-GI-NEXT: add v7.4s, v2.4s, v7.4s
+; CHECK-GI-NEXT: add v4.4s, v3.4s, v4.4s
+; CHECK-GI-NEXT: cmlt v17.4s, v17.4s, #0
+; CHECK-GI-NEXT: sshl v5.4s, v5.4s, v16.4s
+; CHECK-GI-NEXT: sshl v6.4s, v6.4s, v16.4s
+; CHECK-GI-NEXT: sshl v7.4s, v7.4s, v16.4s
+; CHECK-GI-NEXT: sshl v4.4s, v4.4s, v16.4s
+; CHECK-GI-NEXT: bif v0.16b, v5.16b, v17.16b
+; CHECK-GI-NEXT: bif v1.16b, v6.16b, v17.16b
+; CHECK-GI-NEXT: bif v2.16b, v7.16b, v17.16b
+; CHECK-GI-NEXT: bif v3.16b, v4.16b, v17.16b
; CHECK-GI-NEXT: ret
%1 = sdiv <16 x i32> %x, <i32 1, i32 4, i32 8, i32 16, i32 1, i32 4, i32 8, i32 16, i32 1, i32 4, i32 8, i32 16, i32 1, i32 4, i32 8, i32 16>
ret <16 x i32> %1
@@ -694,53 +682,50 @@ define <8 x i64> @combine_vec_sdiv_by_pow2b_v8i64(<8 x i64> %x) {
;
; CHECK-GI-LABEL: combine_vec_sdiv_by_pow2b_v8i64:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: adrp x8, .LCPI23_2
; CHECK-GI-NEXT: adrp x9, .LCPI23_0
; CHECK-GI-NEXT: cmlt v7.2d, v0.2d, #0
-; CHECK-GI-NEXT: fmov s4, w8
+; CHECK-GI-NEXT: ldr q4, [x8, :lo12:.LCPI23_2]
; CHECK-GI-NEXT: adrp x8, .LCPI23_1
-; CHECK-GI-NEXT: ldr q6, [x9, :lo12:.LCPI23_0]
-; CHECK-GI-NEXT: ldr q5, [x8, :lo12:.LCPI23_1]
+; CHECK-GI-NEXT: ldr d5, [x9, :lo12:.LCPI23_0]
+; CHECK-GI-NEXT: ldr q6, [x8, :lo12:.LCPI23_1]
; CHECK-GI-NEXT: cmlt v16.2d, v1.2d, #0
; CHECK-GI-NEXT: cmlt v17.2d, v2.2d, #0
+; CHECK-GI-NEXT: neg v4.2d, v4.2d
+; CHECK-GI-NEXT: ushll v5.4s, v5.4h, #0
+; CHECK-GI-NEXT: cmlt v19.2d, v3.2d, #0
; CHECK-GI-NEXT: neg v6.2d, v6.2d
-; CHECK-GI-NEXT: cmlt v18.2d, v3.2d, #0
+; CHECK-GI-NEXT: adrp x8, .LCPI23_4
+; CHECK-GI-NEXT: ldr q18, [x8, :lo12:.LCPI23_4]
; CHECK-GI-NEXT: adrp x8, .LCPI23_3
-; CHECK-GI-NEXT: mov v4.h[1], wzr
-; CHECK-GI-NEXT: neg v5.2d, v5.2d
-; CHECK-GI-NEXT: adrp x9, .LCPI23_2
-; CHECK-GI-NEXT: ldr q19, [x8, :lo12:.LCPI23_3]
-; CHECK-GI-NEXT: ldr q20, [x9, :lo12:.LCPI23_2]
+; CHECK-GI-NEXT: ushl v7.2d, v7.2d, v4.2d
+; CHECK-GI-NEXT: ushll v20.2d, v5.2s, #0
+; CHECK-GI-NEXT: ushl v4.2d, v17.2d, v4.2d
; CHECK-GI-NEXT: ushl v16.2d, v16.2d, v6.2d
-; CHECK-GI-NEXT: ushl v6.2d, v18.2d, v6.2d
-; CHECK-GI-NEXT: ushl v7.2d, v7.2d, v5.2d
-; CHECK-GI-NEXT: ushl v5.2d, v17.2d, v5.2d
-; CHECK-GI-NEXT: neg v19.2d, v19.2d
-; CHECK-GI-NEXT: mov v4.h[2], wzr
-; CHECK-GI-NEXT: neg v20.2d, v20.2d
-; CHECK-GI-NEXT: add v16.2d, v1.2d, v16.2d
-; CHECK-GI-NEXT: add v6.2d, v3.2d, v6.2d
+; CHECK-GI-NEXT: ushll v17.2d, v5.2s, #0
+; CHECK-GI-NEXT: ushl v6.2d, v19.2d, v6.2d
+; CHECK-GI-NEXT: ushll2 v5.2d, v5.4s, #0
+; CHECK-GI-NEXT: ldr q19, [x8, :lo12:.LCPI23_3]
+; CHECK-GI-NEXT: neg v18.2d, v18.2d
; CHECK-GI-NEXT: add v7.2d, v0.2d, v7.2d
-; CHECK-GI-NEXT: add v5.2d, v2.2d, v5.2d
-; CHECK-GI-NEXT: mov v4.h[3], wzr
-; CHECK-GI-NEXT: sshl v16.2d, v16.2d, v20.2d
-; CHECK-GI-NEXT: sshl v6.2d, v6.2d, v20.2d
-; CHECK-GI-NEXT: sshl v7.2d, v7.2d, v19.2d
-; CHECK-GI-NEXT: sshl v5.2d, v5.2d, v19.2d
-; CHECK-GI-NEXT: ushll v4.4s, v4.4h, #0
-; CHECK-GI-NEXT: ushll v17.2d, v4.2s, #0
-; CHECK-GI-NEXT: ushll2 v18.2d, v4.4s, #0
-; CHECK-GI-NEXT: ushll v4.2d, v4.2s, #0
-; CHECK-GI-NEXT: shl v17.2d, v17.2d, #63
-; CHECK-GI-NEXT: shl v18.2d, v18.2d, #63
-; CHECK-GI-NEXT: shl v4.2d, v4.2d, #63
-; CHECK-GI-NEXT: cmlt v17.2d, v17.2d, #0
-; CHECK-GI-NEXT: cmlt v18.2d, v18.2d, #0
-; CHECK-GI-NEXT: cmlt v4.2d, v4.2d, #0
-; CHECK-GI-NEXT: bif v0.16b, v7.16b, v17.16b
-; CHECK-GI-NEXT: bif v1.16b, v16.16b, v18.16b
-; CHECK-GI-NEXT: bif v2.16b, v5.16b, v4.16b
-; CHECK-GI-NEXT: bif v3.16b, v6.16b, v18.16b
+; CHECK-GI-NEXT: shl v20.2d, v20.2d, #63
+; CHECK-GI-NEXT: add v4.2d, v2.2d, v4.2d
+; CHECK-GI-NEXT: add v1.2d, v1.2d, v16.2d
+; CHECK-GI-NEXT: shl v16.2d, v17.2d, #63
+; CHECK-GI-NEXT: neg v17.2d, v19.2d
+; CHECK-GI-NEXT: add v3.2d, v3.2d, v6.2d
+; CHECK-GI-NEXT: shl v5.2d, v5.2d, #63
+; CHECK-GI-NEXT: sshl v6.2d, v7.2d, v18.2d
+; CHECK-GI-NEXT: cmlt v7.2d, v20.2d, #0
+; CHECK-GI-NEXT: sshl v4.2d, v4.2d, v18.2d
+; CHECK-GI-NEXT: cmlt v16.2d, v16.2d, #0
+; CHECK-GI-NEXT: sshl v1.2d, v1.2d, v17.2d
+; CHECK-GI-NEXT: sshl v3.2d, v3.2d, v17.2d
+; CHECK-GI-NEXT: cmlt v5.2d, v5.2d, #0
+; CHECK-GI-NEXT: bif v0.16b, v6.16b, v7.16b
+; CHECK-GI-NEXT: bif v2.16b, v4.16b, v16.16b
+; CHECK-GI-NEXT: bic v1.16b, v1.16b, v5.16b
+; CHECK-GI-NEXT: bic v3.16b, v3.16b, v5.16b
; CHECK-GI-NEXT: ret
%1 = sdiv <8 x i64> %x, <i64 1, i64 4, i64 8, i64 16, i64 1, i64 4, i64 8, i64 16>
ret <8 x i64> %1
@@ -767,29 +752,25 @@ define <4 x i32> @combine_vec_sdiv_by_pow2b_PosAndNeg(<4 x i32> %x) {
;
; CHECK-GI-LABEL: combine_vec_sdiv_by_pow2b_PosAndNeg:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #1 // =0x1
-; CHECK-GI-NEXT: adrp x9, .LCPI24_0
-; CHECK-GI-NEXT: cmlt v4.4s, v0.4s, #0
-; CHECK-GI-NEXT: fmov s2, w8
-; CHECK-GI-NEXT: ldr q3, [x9, :lo12:.LCPI24_0]
-; CHECK-GI-NEXT: movi d1, #0000000000000000
+; CHECK-GI-NEXT: adrp x8, .LCPI24_2
+; CHECK-GI-NEXT: cmlt v2.4s, v0.4s, #0
; CHECK-GI-NEXT: adrp x9, .LCPI24_1
-; CHECK-GI-NEXT: neg v3.4s, v3.4s
-; CHECK-GI-NEXT: mov v2.s[1], wzr
-; CHECK-GI-NEXT: mov v1.s[1], w8
-; CHECK-GI-NEXT: ushl v3.4s, v4.4s, v3.4s
-; CHECK-GI-NEXT: ldr q4, [x9, :lo12:.LCPI24_1]
-; CHECK-GI-NEXT: mov v2.s[2], wzr
-; CHECK-GI-NEXT: neg v4.4s, v4.4s
-; CHECK-GI-NEXT: add v3.4s, v0.4s, v3.4s
-; CHECK-GI-NEXT: mov v1.d[1], v1.d[0]
-; CHECK-GI-NEXT: mov v2.s[3], wzr
-; CHECK-GI-NEXT: sshl v3.4s, v3.4s, v4.4s
-; CHECK-GI-NEXT: shl v1.4s, v1.4s, #31
-; CHECK-GI-NEXT: shl v2.4s, v2.4s, #31
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI24_2]
+; CHECK-GI-NEXT: adrp x8, .LCPI24_3
+; CHECK-GI-NEXT: ldr q3, [x9, :lo12:.LCPI24_1]
+; CHECK-GI-NEXT: neg v1.4s, v1.4s
+; CHECK-GI-NEXT: shl v3.4s, v3.4s, #31
+; CHECK-GI-NEXT: ushl v1.4s, v2.4s, v1.4s
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI24_3]
+; CHECK-GI-NEXT: adrp x8, .LCPI24_0
+; CHECK-GI-NEXT: neg v2.4s, v2.4s
+; CHECK-GI-NEXT: add v1.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: sshl v1.4s, v1.4s, v2.4s
+; CHECK-GI-NEXT: cmlt v2.4s, v3.4s, #0
+; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI24_0]
+; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: shl v1.4s, v3.4s, #31
; CHECK-GI-NEXT: cmlt v1.4s, v1.4s, #0
-; CHECK-GI-NEXT: cmlt v2.4s, v2.4s, #0
-; CHECK-GI-NEXT: bif v0.16b, v3.16b, v2.16b
; CHECK-GI-NEXT: neg v2.4s, v0.4s
; CHECK-GI-NEXT: bit v0.16b, v2.16b, v1.16b
; CHECK-GI-NEXT: ret
@@ -926,29 +907,24 @@ define <4 x i32> @non_splat_minus_one_divisor_2(<4 x i32> %A) {
;
; CHECK-GI-LABEL: non_splat_minus_one_divisor_2:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #1 // =0x1
-; CHECK-GI-NEXT: adrp x9, .LCPI27_0
-; CHECK-GI-NEXT: cmlt v3.4s, v0.4s, #0
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: ldr q2, [x9, :lo12:.LCPI27_0]
-; CHECK-GI-NEXT: fmov s4, w8
+; CHECK-GI-NEXT: adrp x8, .LCPI27_2
+; CHECK-GI-NEXT: cmlt v2.4s, v0.4s, #0
; CHECK-GI-NEXT: adrp x9, .LCPI27_1
-; CHECK-GI-NEXT: neg v2.4s, v2.4s
-; CHECK-GI-NEXT: mov v1.s[1], w8
-; CHECK-GI-NEXT: mov v4.s[1], wzr
-; CHECK-GI-NEXT: ushl v2.4s, v3.4s, v2.4s
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI27_2]
+; CHECK-GI-NEXT: adrp x8, .LCPI27_3
; CHECK-GI-NEXT: ldr q3, [x9, :lo12:.LCPI27_1]
-; CHECK-GI-NEXT: mov v1.s[2], wzr
-; CHECK-GI-NEXT: mov v4.s[2], wzr
-; CHECK-GI-NEXT: neg v3.4s, v3.4s
-; CHECK-GI-NEXT: add v2.4s, v0.4s, v2.4s
-; CHECK-GI-NEXT: mov v1.s[3], wzr
-; CHECK-GI-NEXT: sshl v2.4s, v2.4s, v3.4s
-; CHECK-GI-NEXT: mov v4.s[3], w8
-; CHECK-GI-NEXT: shl v1.4s, v1.4s, #31
-; CHECK-GI-NEXT: cmlt v1.4s, v1.4s, #0
-; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b
-; CHECK-GI-NEXT: shl v1.4s, v4.4s, #31
+; CHECK-GI-NEXT: neg v1.4s, v1.4s
+; CHECK-GI-NEXT: shl v3.4s, v3.4s, #31
+; CHECK-GI-NEXT: ushl v1.4s, v2.4s, v1.4s
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI27_3]
+; CHECK-GI-NEXT: adrp x8, .LCPI27_0
+; CHECK-GI-NEXT: neg v2.4s, v2.4s
+; CHECK-GI-NEXT: add v1.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: sshl v1.4s, v1.4s, v2.4s
+; CHECK-GI-NEXT: cmlt v2.4s, v3.4s, #0
+; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI27_0]
+; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: shl v1.4s, v3.4s, #31
; CHECK-GI-NEXT: cmlt v1.4s, v1.4s, #0
; CHECK-GI-NEXT: neg v2.4s, v0.4s
; CHECK-GI-NEXT: bit v0.16b, v2.16b, v1.16b
diff --git a/llvm/test/CodeGen/AArch64/cttz.ll b/llvm/test/CodeGen/AArch64/cttz.ll
index 1f4ac01c485e5..a7cb028537088 100644
--- a/llvm/test/CodeGen/AArch64/cttz.ll
+++ b/llvm/test/CodeGen/AArch64/cttz.ll
@@ -103,16 +103,12 @@ define void @v4i8(ptr %p1) {
;
; CHECK-GI-LABEL: v4i8:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov w8, #255 // =0xff
; CHECK-GI-NEXT: ldr s1, [x0]
-; CHECK-GI-NEXT: fmov s0, w8
+; CHECK-GI-NEXT: movi d0, #0xff00ff00ff00ff
; CHECK-GI-NEXT: zip1 v2.8b, v1.8b, v1.8b
-; CHECK-GI-NEXT: mov v0.h[1], w8
-; CHECK-GI-NEXT: mov v0.h[2], w8
-; CHECK-GI-NEXT: mov v0.h[3], w8
-; CHECK-GI-NEXT: eor v2.8b, v2.8b, v0.8b
-; CHECK-GI-NEXT: uaddw v0.8h, v0.8h, v1.8b
-; CHECK-GI-NEXT: and v0.8b, v2.8b, v0.8b
+; CHECK-GI-NEXT: uaddw v1.8h, v0.8h, v1.8b
+; CHECK-GI-NEXT: eor v0.8b, v2.8b, v0.8b
+; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
; CHECK-GI-NEXT: cnt v0.8b, v0.8b
; CHECK-GI-NEXT: str s0, [x0]
@@ -202,16 +198,14 @@ define void @v2i16(ptr %p1) {
;
; CHECK-GI-LABEL: v2i16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov w8, #65535 // =0xffff
-; CHECK-GI-NEXT: ld1 { v0.h }[0], [x0]
-; CHECK-GI-NEXT: ldr h1, [x0, #2]
-; CHECK-GI-NEXT: fmov s2, w8
-; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
-; CHECK-GI-NEXT: mov v2.s[1], w8
+; CHECK-GI-NEXT: ld1 { v1.h }[0], [x0]
+; CHECK-GI-NEXT: ldr h2, [x0, #2]
+; CHECK-GI-NEXT: movi d0, #0x00ffff0000ffff
; CHECK-GI-NEXT: add...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/218332
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