[llvm] [AMDGPU] Register allocation anti-hints to reduce MFMA hazard NOPs (PR #156943)

[Syadus Sefat via llvm-commits]

mssefat wrote:

I have divided the current implementation into 4 new stacked PRs. 

PR1: Target agnostic anti-hints infrastructure https://github.com/llvm/llvm-project/pull/218071
PR2: MIR serialize support: https://github.com/llvm/llvm-project/pull/218073
PR3: Occupancy aware allocation order: https://github.com/llvm/llvm-project/pull/218074
PR4: Anti-hints insertion for MFMA in GCNPreRAOptimizations: https://github.com/llvm/llvm-project/pull/218075

PR4 has new changes. I have abstracted the anti-hints insertion mechanism to rule based. To add anti-hints support for new type instructions we need to add rules.

https://github.com/llvm/llvm-project/pull/156943