[llvm] [CodeGenPrepare] Invert select predicates when profitable (PR #218296)
Kevin Choi via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 23 19:25:06 PDT 2026
https://github.com/choikwa updated https://github.com/llvm/llvm-project/pull/218296
>From c0dfbd4f9a534339b1dc3574bf8410d9de8b6fed Mon Sep 17 00:00:00 2001
From: choikwa <code.kchoi at gmail.com>
Date: Sun, 23 Aug 2026 18:30:36 -0400
Subject: [PATCH 1/2] [CodeGenPrepare] Invert select predicates when profitable
Use the target cost model to compare an integer comparison with its inverse, and invert it while swapping the select operands when that is strictly cheaper. Look through one-use shuffle chains needed by vector selects, preserve profile metadata, and retain canonical predicates when costs are equal or the comparison is shared.
Assisted by gpt-5.6-sol
---
llvm/lib/CodeGen/CodeGenPrepare.cpp | 49 ++++++++++++++--
.../CodeGenPrepare/X86/invert-icmp-select.ll | 56 +++++++++++++++++++
2 files changed, 101 insertions(+), 4 deletions(-)
create mode 100644 llvm/test/Transforms/CodeGenPrepare/X86/invert-icmp-select.ll
diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp
index 53b7a81537975..3ec30357a8589 100644
--- a/llvm/lib/CodeGen/CodeGenPrepare.cpp
+++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp
@@ -434,6 +434,7 @@ class CodeGenPrepare {
bool optimizeLoadExt(LoadInst *Load);
bool optimizeShiftInst(BinaryOperator *BO);
bool optimizeFunnelShift(IntrinsicInst *Fsh);
+ bool invertSelectPredicateIfProfitable(SelectInst *SI);
bool optimizeSelectInst(SelectInst *SI);
bool optimizeShuffleVectorInst(ShuffleVectorInst *SVI);
bool optimizeSwitchType(SwitchInst *SI);
@@ -7717,15 +7718,55 @@ bool CodeGenPrepare::optimizeFunnelShift(IntrinsicInst *Fsh) {
return true;
}
+/// Invert an integer comparison feeding \p SI and swap the select operands if
+/// the target reports that the inverse predicate is strictly cheaper.
+bool CodeGenPrepare::invertSelectPredicateIfProfitable(SelectInst *SI) {
+ Value *Cond = SI->getCondition();
+
+ // Look through one-use shuffles of the compare result. Inverting a compare
+ // commutes with a shuffle whose second input is poison or undef.
+ while (auto *SVI = dyn_cast<ShuffleVectorInst>(Cond)) {
+ if (!SVI->hasOneUse() || !isa<PoisonValue, UndefValue>(SVI->getOperand(1)))
+ return false;
+ Cond = SVI->getOperand(0);
+ }
+
+ auto *Cmp = dyn_cast<ICmpInst>(Cond);
+ if (!Cmp || !Cmp->hasOneUse())
+ return false;
+
+ Type *ValTy = Cmp->getOperand(0)->getType();
+ Type *CondTy = Cmp->getType();
+ CmpInst::Predicate Pred = Cmp->getPredicate();
+ CmpInst::Predicate InversePred = Cmp->getInversePredicate();
+ TTI::OperandValueInfo Op1Info = TTI::getOperandInfo(Cmp->getOperand(0));
+ TTI::OperandValueInfo Op2Info = TTI::getOperandInfo(Cmp->getOperand(1));
+ InstructionCost Cost =
+ TTI->getCmpSelInstrCost(Instruction::ICmp, ValTy, CondTy, Pred,
+ TTI::TCK_RecipThroughput, Op1Info, Op2Info, Cmp);
+ InstructionCost InverseCost =
+ TTI->getCmpSelInstrCost(Instruction::ICmp, ValTy, CondTy, InversePred,
+ TTI::TCK_RecipThroughput, Op1Info, Op2Info, Cmp);
+ if (!Cost.isValid() || !InverseCost.isValid() || InverseCost >= Cost)
+ return false;
+
+ Cmp->setPredicate(InversePred);
+ SI->swapValues();
+ SI->swapProfMetadata();
+ return true;
+}
+
/// If we have a SelectInst that will likely profit from branch prediction,
/// turn it into a branch.
bool CodeGenPrepare::optimizeSelectInst(SelectInst *SI) {
+ bool Changed = invertSelectPredicateIfProfitable(SI);
+
if (DisableSelectToBranch)
- return false;
+ return Changed;
// If the SelectOptimize pass is enabled, selects have already been optimized.
if (!getCGPassBuilderOption().DisableSelectOptimize)
- return false;
+ return Changed;
// Find all consecutive select instructions that share the same condition.
SmallVector<SelectInst *, 2> ASI;
@@ -7754,7 +7795,7 @@ bool CodeGenPrepare::optimizeSelectInst(SelectInst *SI) {
// Can we convert the 'select' to CF ?
if (VectorCond || SI->getMetadata(LLVMContext::MD_unpredictable))
- return false;
+ return Changed;
TargetLowering::SelectSupportKind SelectKind;
if (SI->getType()->isVectorTy())
@@ -7765,7 +7806,7 @@ bool CodeGenPrepare::optimizeSelectInst(SelectInst *SI) {
if (TLI->isSelectSupported(SelectKind) &&
(!isFormingBranchFromSelectProfitable(TTI, TLI, SI) ||
llvm::shouldOptimizeForSize(SI->getParent(), PSI, BFI)))
- return false;
+ return Changed;
// Transform a sequence like this:
// start:
diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/invert-icmp-select.ll b/llvm/test/Transforms/CodeGenPrepare/X86/invert-icmp-select.ll
new file mode 100644
index 0000000000000..2d6c2bacac211
--- /dev/null
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/invert-icmp-select.ll
@@ -0,0 +1,56 @@
+; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' \
+; RUN: -mtriple=x86_64 -mattr=+avx2 %s | FileCheck %s --check-prefix=AVX2
+; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' \
+; RUN: -mtriple=x86_64 -mattr=+avx512bw %s | FileCheck %s --check-prefix=AVX512
+
+define <8 x i8> @direct(<8 x i8> %a, <8 x i8> %b, <8 x i8> %x, <8 x i8> %y) {
+; AVX2-LABEL: @direct(
+; AVX2: %cmp = icmp uge <8 x i8> %a, %b
+; AVX2: %sel = select <8 x i1> %cmp, <8 x i8> %y, <8 x i8> %x, !prof [[INVERTED_WEIGHTS:![0-9]+]]
+; AVX512-LABEL: @direct(
+; AVX512: %cmp = icmp ult <8 x i8> %a, %b
+; AVX512: %sel = select <8 x i1> %cmp, <8 x i8> %x, <8 x i8> %y, !prof [[ORIGINAL_WEIGHTS:![0-9]+]]
+ %cmp = icmp ult <8 x i8> %a, %b
+ %sel = select <8 x i1> %cmp, <8 x i8> %x, <8 x i8> %y, !prof !0
+ ret <8 x i8> %sel
+}
+
+define <4 x i8> @through_shuffle(<8 x i8> %a, <8 x i8> %b,
+ <4 x i8> %x, <4 x i8> %y) {
+; AVX2-LABEL: @through_shuffle(
+; AVX2: %cmp = icmp uge <8 x i8> %a, %b
+; AVX2: %cond = shufflevector <8 x i1> %cmp, <8 x i1> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; AVX2: %sel = select <4 x i1> %cond, <4 x i8> %y, <4 x i8> %x
+ %cmp = icmp ult <8 x i8> %a, %b
+ %cond = shufflevector <8 x i1> %cmp, <8 x i1> poison,
+ <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+ %sel = select <4 x i1> %cond, <4 x i8> %x, <4 x i8> %y
+ ret <4 x i8> %sel
+}
+
+define <8 x i8> @not_profitable(<8 x i8> %a, <8 x i8> %b,
+ <8 x i8> %x, <8 x i8> %y) {
+; AVX2-LABEL: @not_profitable(
+; AVX2: %cmp = icmp eq <8 x i8> %a, %b
+; AVX2: %sel = select <8 x i1> %cmp, <8 x i8> %x, <8 x i8> %y
+ %cmp = icmp eq <8 x i8> %a, %b
+ %sel = select <8 x i1> %cmp, <8 x i8> %x, <8 x i8> %y
+ ret <8 x i8> %sel
+}
+
+define <8 x i8> @shared_cmp(<8 x i8> %a, <8 x i8> %b,
+ <8 x i8> %x, <8 x i8> %y) {
+; AVX2-LABEL: @shared_cmp(
+; AVX2: %cmp = icmp ult <8 x i8> %a, %b
+; AVX2: %sel1 = select <8 x i1> %cmp, <8 x i8> %x, <8 x i8> %y
+; AVX2: %sel2 = select <8 x i1> %cmp, <8 x i8> %sel1, <8 x i8> %a
+ %cmp = icmp ult <8 x i8> %a, %b
+ %sel1 = select <8 x i1> %cmp, <8 x i8> %x, <8 x i8> %y
+ %sel2 = select <8 x i1> %cmp, <8 x i8> %sel1, <8 x i8> %a
+ ret <8 x i8> %sel2
+}
+
+; AVX2: [[INVERTED_WEIGHTS]] = !{!"branch_weights", i32 90, i32 10}
+; AVX512: [[ORIGINAL_WEIGHTS]] = !{!"branch_weights", i32 10, i32 90}
+
+!0 = !{!"branch_weights", i32 10, i32 90}
>From be1e356805ae85edafba1bc242c69f6fe98cff6b Mon Sep 17 00:00:00 2001
From: choikwa <code.kchoi at gmail.com>
Date: Sun, 23 Aug 2026 22:24:22 -0400
Subject: [PATCH 2/2] Fix lit test failures
---
llvm/test/CodeGen/X86/combine-shl.ll | 52 ++---
llvm/test/CodeGen/X86/combine-srl.ll | 33 +--
llvm/test/CodeGen/X86/paddus.ll | 328 +++++++++++++--------------
llvm/test/CodeGen/X86/psubus.ll | 8 +-
4 files changed, 209 insertions(+), 212 deletions(-)
diff --git a/llvm/test/CodeGen/X86/combine-shl.ll b/llvm/test/CodeGen/X86/combine-shl.ll
index 4417666112452..7a8fad3c9f006 100644
--- a/llvm/test/CodeGen/X86/combine-shl.ll
+++ b/llvm/test/CodeGen/X86/combine-shl.ll
@@ -117,7 +117,7 @@ define <4 x i32> @combine_vec_shl_trunc_and(<4 x i32> %x, <4 x i64> %y) {
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]
; SSE2-NEXT: pslld $23, %xmm1
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
-; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [1065353216,1065353216,1065353216,1065353216]
; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -133,7 +133,7 @@ define <4 x i32> @combine_vec_shl_trunc_and(<4 x i32> %x, <4 x i64> %y) {
; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]
; SSE41-NEXT: pslld $23, %xmm1
; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
-; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [1065353216,1065353216,1065353216,1065353216]
; SSE41-NEXT: cvttps2dq %xmm1, %xmm1
; SSE41-NEXT: pmulld %xmm1, %xmm0
; SSE41-NEXT: retq
@@ -649,7 +649,7 @@ define <4 x i32> @combine_vec_shl_add0(<4 x i32> %x) {
; SSE-LABEL: combine_vec_shl_add0:
; SSE: # %bb.0:
; SSE-NEXT: pslld $2, %xmm0
-; SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [20,20,20,20]
; SSE-NEXT: retq
;
; AVX2-LABEL: combine_vec_shl_add0:
@@ -678,19 +678,19 @@ define <4 x i32> @combine_vec_shl_add1(<4 x i32> %x) {
; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [4,4,16,16]
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [10,24,56,128]
; SSE2-NEXT: retq
;
; SSE41-LABEL: combine_vec_shl_add1:
; SSE41: # %bb.0:
; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [2,4,8,16]
-; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [10,24,56,128]
; SSE41-NEXT: retq
;
; AVX-LABEL: combine_vec_shl_add1:
; AVX: # %bb.0:
; AVX-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [10,24,56,128]
; AVX-NEXT: retq
%1 = add <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8>
%2 = shl <4 x i32> %1, <i32 1, i32 2, i32 3, i32 4>
@@ -937,7 +937,7 @@ define <4 x i32> @combine_vec_shl_clamped1(<4 x i32> %sh, <4 x i32> %amt) {
; SSE2-NEXT: pxor %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: pslld $23, %xmm1
-; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [1065353216,1065353216,1065353216,1065353216]
; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; SSE2-NEXT: pmuludq %xmm1, %xmm0
@@ -956,7 +956,7 @@ define <4 x i32> @combine_vec_shl_clamped1(<4 x i32> %sh, <4 x i32> %amt) {
; SSE41-NEXT: pminud %xmm1, %xmm2
; SSE41-NEXT: pcmpeqd %xmm1, %xmm2
; SSE41-NEXT: pslld $23, %xmm1
-; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [1065353216,1065353216,1065353216,1065353216]
; SSE41-NEXT: cvttps2dq %xmm1, %xmm1
; SSE41-NEXT: pmulld %xmm1, %xmm0
; SSE41-NEXT: pand %xmm2, %xmm0
@@ -980,7 +980,7 @@ define <4 x i32> @combine_vec_shl_clamped2(<4 x i32> %sh, <4 x i32> %amt) {
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: pandn %xmm0, %xmm2
; SSE2-NEXT: pslld $23, %xmm1
-; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [1065353216,1065353216,1065353216,1065353216]
; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
; SSE2-NEXT: pmuludq %xmm1, %xmm2
@@ -998,7 +998,7 @@ define <4 x i32> @combine_vec_shl_clamped2(<4 x i32> %sh, <4 x i32> %amt) {
; SSE41-NEXT: pcmpeqd %xmm1, %xmm2
; SSE41-NEXT: pand %xmm2, %xmm0
; SSE41-NEXT: pslld $23, %xmm1
-; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [1065353216,1065353216,1065353216,1065353216]
; SSE41-NEXT: cvttps2dq %xmm1, %xmm1
; SSE41-NEXT: pmulld %xmm1, %xmm0
; SSE41-NEXT: retq
@@ -1021,7 +1021,7 @@ define <4 x i32> @combine_vec_shl_commuted_clamped(<4 x i32> %sh, <4 x i32> %amt
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: pandn %xmm0, %xmm2
; SSE2-NEXT: pslld $23, %xmm1
-; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [1065353216,1065353216,1065353216,1065353216]
; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
; SSE2-NEXT: pmuludq %xmm1, %xmm2
@@ -1039,7 +1039,7 @@ define <4 x i32> @combine_vec_shl_commuted_clamped(<4 x i32> %sh, <4 x i32> %amt
; SSE41-NEXT: pcmpeqd %xmm1, %xmm2
; SSE41-NEXT: pand %xmm2, %xmm0
; SSE41-NEXT: pslld $23, %xmm1
-; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [1065353216,1065353216,1065353216,1065353216]
; SSE41-NEXT: cvttps2dq %xmm1, %xmm1
; SSE41-NEXT: pmulld %xmm1, %xmm0
; SSE41-NEXT: retq
@@ -1057,21 +1057,21 @@ define <4 x i32> @combine_vec_shl_commuted_clamped(<4 x i32> %sh, <4 x i32> %amt
define <4 x i32> @combine_vec_shl_commuted_clamped1(<4 x i32> %sh, <4 x i32> %amt) {
; SSE2-LABEL: combine_vec_shl_commuted_clamped1:
; SSE2: # %bb.0:
-; SSE2-NEXT: movdqa %xmm1, %xmm2
-; SSE2-NEXT: pslld $23, %xmm2
-; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
-; SSE2-NEXT: cvttps2dq %xmm2, %xmm2
+; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
+; SSE2-NEXT: pxor %xmm1, %xmm2
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; SSE2-NEXT: pslld $23, %xmm1
+; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [1065353216,1065353216,1065353216,1065353216]
+; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
-; SSE2-NEXT: pmuludq %xmm2, %xmm0
+; SSE2-NEXT: pmuludq %xmm1, %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
-; SSE2-NEXT: pmuludq %xmm3, %xmm2
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
-; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
-; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
-; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
-; SSE2-NEXT: pandn %xmm0, %xmm1
-; SSE2-NEXT: movdqa %xmm1, %xmm0
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
+; SSE2-NEXT: pmuludq %xmm3, %xmm1
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
+; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-NEXT: pandn %xmm0, %xmm2
+; SSE2-NEXT: movdqa %xmm2, %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: combine_vec_shl_commuted_clamped1:
@@ -1080,7 +1080,7 @@ define <4 x i32> @combine_vec_shl_commuted_clamped1(<4 x i32> %sh, <4 x i32> %am
; SSE41-NEXT: pminud %xmm1, %xmm2
; SSE41-NEXT: pcmpeqd %xmm1, %xmm2
; SSE41-NEXT: pslld $23, %xmm1
-; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [1065353216,1065353216,1065353216,1065353216]
; SSE41-NEXT: cvttps2dq %xmm1, %xmm1
; SSE41-NEXT: pmulld %xmm1, %xmm0
; SSE41-NEXT: pand %xmm2, %xmm0
diff --git a/llvm/test/CodeGen/X86/combine-srl.ll b/llvm/test/CodeGen/X86/combine-srl.ll
index 7bc90534dcc6e..4c3a03f2e3254 100644
--- a/llvm/test/CodeGen/X86/combine-srl.ll
+++ b/llvm/test/CodeGen/X86/combine-srl.ll
@@ -784,25 +784,26 @@ define <4 x i32> @combine_vec_lshr_commuted_clamped(<4 x i32> %sh, <4 x i32> %am
define <4 x i32> @combine_vec_lshr_commuted_clamped1(<4 x i32> %sh, <4 x i32> %amt) {
; SSE2-LABEL: combine_vec_lshr_commuted_clamped1:
; SSE2: # %bb.0:
-; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]
-; SSE2-NEXT: movdqa %xmm0, %xmm3
-; SSE2-NEXT: psrld %xmm2, %xmm3
-; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[0,1,1,1,4,5,6,7]
+; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
+; SSE2-NEXT: pxor %xmm1, %xmm2
+; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm1[2,3,3,3,4,5,6,7]
; SSE2-NEXT: movdqa %xmm0, %xmm4
-; SSE2-NEXT: psrld %xmm2, %xmm4
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm3[0]
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,2,3]
-; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm2[2,3,3,3,4,5,6,7]
+; SSE2-NEXT: psrld %xmm3, %xmm4
+; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm1[0,1,1,1,4,5,6,7]
; SSE2-NEXT: movdqa %xmm0, %xmm5
; SSE2-NEXT: psrld %xmm3, %xmm5
-; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,1,1,1,4,5,6,7]
-; SSE2-NEXT: psrld %xmm2, %xmm0
-; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm5[1]
-; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,3],xmm0[0,3]
-; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
-; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
-; SSE2-NEXT: pandn %xmm4, %xmm1
-; SSE2-NEXT: movdqa %xmm1, %xmm0
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
+; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm1[2,3,3,3,4,5,6,7]
+; SSE2-NEXT: movdqa %xmm0, %xmm4
+; SSE2-NEXT: psrld %xmm3, %xmm4
+; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]
+; SSE2-NEXT: psrld %xmm1, %xmm0
+; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm4[1]
+; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,3],xmm0[0,3]
+; SSE2-NEXT: pandn %xmm5, %xmm2
+; SSE2-NEXT: movdqa %xmm2, %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: combine_vec_lshr_commuted_clamped1:
diff --git a/llvm/test/CodeGen/X86/paddus.ll b/llvm/test/CodeGen/X86/paddus.ll
index 26c55d6371b51..23ae730876c5e 100644
--- a/llvm/test/CodeGen/X86/paddus.ll
+++ b/llvm/test/CodeGen/X86/paddus.ll
@@ -308,18 +308,18 @@ define <32 x i8> @test11(<32 x i8> %x) {
; SSE-LABEL: test11:
; SSE: # %bb.0:
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
-; SSE-NEXT: movdqa %xmm0, %xmm3
+; SSE-NEXT: movdqa %xmm1, %xmm3
; SSE-NEXT: pxor %xmm2, %xmm3
-; SSE-NEXT: pxor %xmm1, %xmm2
-; SSE-NEXT: pmaxub %xmm2, %xmm1
-; SSE-NEXT: pcmpeqb %xmm2, %xmm1
+; SSE-NEXT: pxor %xmm0, %xmm2
+; SSE-NEXT: pmaxub %xmm2, %xmm0
+; SSE-NEXT: pcmpeqb %xmm2, %xmm0
; SSE-NEXT: pcmpeqd %xmm4, %xmm4
-; SSE-NEXT: pxor %xmm4, %xmm1
-; SSE-NEXT: pmaxub %xmm3, %xmm0
-; SSE-NEXT: pcmpeqb %xmm3, %xmm0
; SSE-NEXT: pxor %xmm4, %xmm0
-; SSE-NEXT: por %xmm3, %xmm0
-; SSE-NEXT: por %xmm2, %xmm1
+; SSE-NEXT: por %xmm2, %xmm0
+; SSE-NEXT: pmaxub %xmm3, %xmm1
+; SSE-NEXT: pcmpeqb %xmm3, %xmm1
+; SSE-NEXT: pxor %xmm4, %xmm1
+; SSE-NEXT: por %xmm3, %xmm1
; SSE-NEXT: retq
;
; AVX1-LABEL: test11:
@@ -584,75 +584,75 @@ define <64 x i8> @test16(<64 x i8> %x) {
define <64 x i8> @test17(<64 x i8> %x) {
; SSE-LABEL: test17:
; SSE: # %bb.0:
-; SSE-NEXT: movdqa {{.*#+}} xmm4 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
-; SSE-NEXT: movdqa %xmm0, %xmm5
-; SSE-NEXT: pxor %xmm4, %xmm5
-; SSE-NEXT: movdqa %xmm1, %xmm6
-; SSE-NEXT: pxor %xmm4, %xmm6
-; SSE-NEXT: movdqa %xmm2, %xmm7
-; SSE-NEXT: pxor %xmm4, %xmm7
-; SSE-NEXT: pxor %xmm3, %xmm4
-; SSE-NEXT: pmaxub %xmm4, %xmm3
-; SSE-NEXT: pcmpeqb %xmm4, %xmm3
-; SSE-NEXT: pcmpeqd %xmm8, %xmm8
-; SSE-NEXT: pxor %xmm8, %xmm3
-; SSE-NEXT: pmaxub %xmm7, %xmm2
-; SSE-NEXT: pcmpeqb %xmm7, %xmm2
-; SSE-NEXT: pxor %xmm8, %xmm2
-; SSE-NEXT: pmaxub %xmm6, %xmm1
-; SSE-NEXT: pcmpeqb %xmm6, %xmm1
-; SSE-NEXT: pxor %xmm8, %xmm1
+; SSE-NEXT: movdqa {{.*#+}} xmm5 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
+; SSE-NEXT: movdqa %xmm3, %xmm4
+; SSE-NEXT: pxor %xmm5, %xmm4
+; SSE-NEXT: movdqa %xmm2, %xmm6
+; SSE-NEXT: pxor %xmm5, %xmm6
+; SSE-NEXT: movdqa %xmm1, %xmm7
+; SSE-NEXT: pxor %xmm5, %xmm7
+; SSE-NEXT: pxor %xmm0, %xmm5
; SSE-NEXT: pmaxub %xmm5, %xmm0
; SSE-NEXT: pcmpeqb %xmm5, %xmm0
+; SSE-NEXT: pcmpeqd %xmm8, %xmm8
; SSE-NEXT: pxor %xmm8, %xmm0
; SSE-NEXT: por %xmm5, %xmm0
-; SSE-NEXT: por %xmm6, %xmm1
-; SSE-NEXT: por %xmm7, %xmm2
+; SSE-NEXT: pmaxub %xmm7, %xmm1
+; SSE-NEXT: pcmpeqb %xmm7, %xmm1
+; SSE-NEXT: pxor %xmm8, %xmm1
+; SSE-NEXT: por %xmm7, %xmm1
+; SSE-NEXT: pmaxub %xmm6, %xmm2
+; SSE-NEXT: pcmpeqb %xmm6, %xmm2
+; SSE-NEXT: pxor %xmm8, %xmm2
+; SSE-NEXT: por %xmm6, %xmm2
+; SSE-NEXT: pmaxub %xmm4, %xmm3
+; SSE-NEXT: pcmpeqb %xmm4, %xmm3
+; SSE-NEXT: pxor %xmm8, %xmm3
; SSE-NEXT: por %xmm4, %xmm3
; SSE-NEXT: retq
;
; AVX1-LABEL: test17:
; AVX1: # %bb.0:
; AVX1-NEXT: vbroadcastss {{.*#+}} ymm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
-; AVX1-NEXT: vxorps %ymm2, %ymm0, %ymm3
-; AVX1-NEXT: vxorps %ymm2, %ymm1, %ymm2
+; AVX1-NEXT: vxorps %ymm2, %ymm1, %ymm3
+; AVX1-NEXT: vxorps %ymm2, %ymm0, %ymm2
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4
-; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5
; AVX1-NEXT: vpmaxub %xmm5, %xmm4, %xmm5
; AVX1-NEXT: vpcmpeqb %xmm5, %xmm4, %xmm4
; AVX1-NEXT: vpcmpeqd %xmm5, %xmm5, %xmm5
; AVX1-NEXT: vpxor %xmm5, %xmm4, %xmm4
-; AVX1-NEXT: vpmaxub %xmm1, %xmm2, %xmm1
-; AVX1-NEXT: vpcmpeqb %xmm1, %xmm2, %xmm1
-; AVX1-NEXT: vpxor %xmm5, %xmm1, %xmm1
-; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm1, %ymm1
-; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm4
-; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm6
-; AVX1-NEXT: vpmaxub %xmm6, %xmm4, %xmm6
-; AVX1-NEXT: vpcmpeqb %xmm6, %xmm4, %xmm4
-; AVX1-NEXT: vpxor %xmm5, %xmm4, %xmm4
-; AVX1-NEXT: vpmaxub %xmm0, %xmm3, %xmm0
-; AVX1-NEXT: vpcmpeqb %xmm0, %xmm3, %xmm0
+; AVX1-NEXT: vpmaxub %xmm0, %xmm2, %xmm0
+; AVX1-NEXT: vpcmpeqb %xmm0, %xmm2, %xmm0
; AVX1-NEXT: vpxor %xmm5, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
-; AVX1-NEXT: vorps %ymm3, %ymm0, %ymm0
-; AVX1-NEXT: vorps %ymm2, %ymm1, %ymm1
+; AVX1-NEXT: vorps %ymm2, %ymm0, %ymm0
+; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm2
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4
+; AVX1-NEXT: vpmaxub %xmm4, %xmm2, %xmm4
+; AVX1-NEXT: vpcmpeqb %xmm4, %xmm2, %xmm2
+; AVX1-NEXT: vpxor %xmm5, %xmm2, %xmm2
+; AVX1-NEXT: vpmaxub %xmm1, %xmm3, %xmm1
+; AVX1-NEXT: vpcmpeqb %xmm1, %xmm3, %xmm1
+; AVX1-NEXT: vpxor %xmm5, %xmm1, %xmm1
+; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
+; AVX1-NEXT: vorps %ymm3, %ymm1, %ymm1
; AVX1-NEXT: retq
;
; AVX2-LABEL: test17:
; AVX2: # %bb.0:
; AVX2-NEXT: vpbroadcastb {{.*#+}} ymm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
-; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm3
-; AVX2-NEXT: vpxor %ymm2, %ymm1, %ymm2
-; AVX2-NEXT: vpmaxub %ymm1, %ymm2, %ymm1
-; AVX2-NEXT: vpcmpeqb %ymm1, %ymm2, %ymm1
+; AVX2-NEXT: vpxor %ymm2, %ymm1, %ymm3
+; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm2
+; AVX2-NEXT: vpmaxub %ymm0, %ymm2, %ymm0
+; AVX2-NEXT: vpcmpeqb %ymm0, %ymm2, %ymm0
; AVX2-NEXT: vpcmpeqd %ymm4, %ymm4, %ymm4
-; AVX2-NEXT: vpxor %ymm4, %ymm1, %ymm1
-; AVX2-NEXT: vpmaxub %ymm0, %ymm3, %ymm0
-; AVX2-NEXT: vpcmpeqb %ymm0, %ymm3, %ymm0
; AVX2-NEXT: vpxor %ymm4, %ymm0, %ymm0
-; AVX2-NEXT: vpor %ymm3, %ymm0, %ymm0
-; AVX2-NEXT: vpor %ymm2, %ymm1, %ymm1
+; AVX2-NEXT: vpor %ymm2, %ymm0, %ymm0
+; AVX2-NEXT: vpmaxub %ymm1, %ymm3, %ymm1
+; AVX2-NEXT: vpcmpeqb %ymm1, %ymm3, %ymm1
+; AVX2-NEXT: vpxor %ymm4, %ymm1, %ymm1
+; AVX2-NEXT: vpor %ymm3, %ymm1, %ymm1
; AVX2-NEXT: retq
;
; AVX512-LABEL: test17:
@@ -1042,50 +1042,50 @@ define <16 x i16> @test29(<16 x i16> %x) {
; SSE2-LABEL: test29:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [32768,32768,32768,32768,32768,32768,32768,32768]
-; SSE2-NEXT: movdqa %xmm0, %xmm4
+; SSE2-NEXT: movdqa %xmm1, %xmm4
; SSE2-NEXT: pxor %xmm3, %xmm4
-; SSE2-NEXT: pxor %xmm1, %xmm3
+; SSE2-NEXT: pxor %xmm0, %xmm3
; SSE2-NEXT: movdqa %xmm3, %xmm2
-; SSE2-NEXT: pcmpgtw %xmm1, %xmm2
-; SSE2-NEXT: movdqa %xmm4, %xmm1
-; SSE2-NEXT: pcmpgtw %xmm0, %xmm1
-; SSE2-NEXT: por %xmm4, %xmm1
+; SSE2-NEXT: pcmpgtw %xmm0, %xmm2
; SSE2-NEXT: por %xmm3, %xmm2
-; SSE2-NEXT: movdqa %xmm1, %xmm0
-; SSE2-NEXT: movdqa %xmm2, %xmm1
+; SSE2-NEXT: movdqa %xmm4, %xmm3
+; SSE2-NEXT: pcmpgtw %xmm1, %xmm3
+; SSE2-NEXT: por %xmm4, %xmm3
+; SSE2-NEXT: movdqa %xmm2, %xmm0
+; SSE2-NEXT: movdqa %xmm3, %xmm1
; SSE2-NEXT: retq
;
; SSSE3-LABEL: test29:
; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm3 = [32768,32768,32768,32768,32768,32768,32768,32768]
-; SSSE3-NEXT: movdqa %xmm0, %xmm4
+; SSSE3-NEXT: movdqa %xmm1, %xmm4
; SSSE3-NEXT: pxor %xmm3, %xmm4
-; SSSE3-NEXT: pxor %xmm1, %xmm3
+; SSSE3-NEXT: pxor %xmm0, %xmm3
; SSSE3-NEXT: movdqa %xmm3, %xmm2
-; SSSE3-NEXT: pcmpgtw %xmm1, %xmm2
-; SSSE3-NEXT: movdqa %xmm4, %xmm1
-; SSSE3-NEXT: pcmpgtw %xmm0, %xmm1
-; SSSE3-NEXT: por %xmm4, %xmm1
+; SSSE3-NEXT: pcmpgtw %xmm0, %xmm2
; SSSE3-NEXT: por %xmm3, %xmm2
-; SSSE3-NEXT: movdqa %xmm1, %xmm0
-; SSSE3-NEXT: movdqa %xmm2, %xmm1
+; SSSE3-NEXT: movdqa %xmm4, %xmm3
+; SSSE3-NEXT: pcmpgtw %xmm1, %xmm3
+; SSSE3-NEXT: por %xmm4, %xmm3
+; SSSE3-NEXT: movdqa %xmm2, %xmm0
+; SSSE3-NEXT: movdqa %xmm3, %xmm1
; SSSE3-NEXT: retq
;
; SSE41-LABEL: test29:
; SSE41: # %bb.0:
; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768]
-; SSE41-NEXT: movdqa %xmm0, %xmm3
+; SSE41-NEXT: movdqa %xmm1, %xmm3
; SSE41-NEXT: pxor %xmm2, %xmm3
-; SSE41-NEXT: pxor %xmm1, %xmm2
-; SSE41-NEXT: pmaxuw %xmm2, %xmm1
-; SSE41-NEXT: pcmpeqw %xmm2, %xmm1
+; SSE41-NEXT: pxor %xmm0, %xmm2
+; SSE41-NEXT: pmaxuw %xmm2, %xmm0
+; SSE41-NEXT: pcmpeqw %xmm2, %xmm0
; SSE41-NEXT: pcmpeqd %xmm4, %xmm4
-; SSE41-NEXT: pxor %xmm4, %xmm1
-; SSE41-NEXT: pmaxuw %xmm3, %xmm0
-; SSE41-NEXT: pcmpeqw %xmm3, %xmm0
; SSE41-NEXT: pxor %xmm4, %xmm0
-; SSE41-NEXT: por %xmm3, %xmm0
-; SSE41-NEXT: por %xmm2, %xmm1
+; SSE41-NEXT: por %xmm2, %xmm0
+; SSE41-NEXT: pmaxuw %xmm3, %xmm1
+; SSE41-NEXT: pcmpeqw %xmm3, %xmm1
+; SSE41-NEXT: pxor %xmm4, %xmm1
+; SSE41-NEXT: por %xmm3, %xmm1
; SSE41-NEXT: retq
;
; AVX1-LABEL: test29:
@@ -1383,130 +1383,130 @@ define <32 x i16> @test35(<32 x i16> %x) {
; SSE2-LABEL: test35:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [32768,32768,32768,32768,32768,32768,32768,32768]
-; SSE2-NEXT: movdqa %xmm0, %xmm6
-; SSE2-NEXT: pxor %xmm5, %xmm6
-; SSE2-NEXT: movdqa %xmm1, %xmm7
-; SSE2-NEXT: pxor %xmm5, %xmm7
-; SSE2-NEXT: movdqa %xmm2, %xmm8
+; SSE2-NEXT: movdqa %xmm3, %xmm8
; SSE2-NEXT: pxor %xmm5, %xmm8
-; SSE2-NEXT: pxor %xmm3, %xmm5
+; SSE2-NEXT: movdqa %xmm2, %xmm7
+; SSE2-NEXT: pxor %xmm5, %xmm7
+; SSE2-NEXT: movdqa %xmm1, %xmm6
+; SSE2-NEXT: pxor %xmm5, %xmm6
+; SSE2-NEXT: pxor %xmm0, %xmm5
; SSE2-NEXT: movdqa %xmm5, %xmm4
-; SSE2-NEXT: pcmpgtw %xmm3, %xmm4
-; SSE2-NEXT: movdqa %xmm8, %xmm3
-; SSE2-NEXT: pcmpgtw %xmm2, %xmm3
-; SSE2-NEXT: movdqa %xmm7, %xmm2
-; SSE2-NEXT: pcmpgtw %xmm1, %xmm2
-; SSE2-NEXT: movdqa %xmm6, %xmm1
-; SSE2-NEXT: pcmpgtw %xmm0, %xmm1
-; SSE2-NEXT: por %xmm6, %xmm1
-; SSE2-NEXT: por %xmm7, %xmm2
-; SSE2-NEXT: por %xmm8, %xmm3
+; SSE2-NEXT: pcmpgtw %xmm0, %xmm4
; SSE2-NEXT: por %xmm5, %xmm4
-; SSE2-NEXT: movdqa %xmm1, %xmm0
-; SSE2-NEXT: movdqa %xmm2, %xmm1
-; SSE2-NEXT: movdqa %xmm3, %xmm2
-; SSE2-NEXT: movdqa %xmm4, %xmm3
+; SSE2-NEXT: movdqa %xmm6, %xmm5
+; SSE2-NEXT: pcmpgtw %xmm1, %xmm5
+; SSE2-NEXT: por %xmm6, %xmm5
+; SSE2-NEXT: movdqa %xmm7, %xmm6
+; SSE2-NEXT: pcmpgtw %xmm2, %xmm6
+; SSE2-NEXT: por %xmm7, %xmm6
+; SSE2-NEXT: movdqa %xmm8, %xmm7
+; SSE2-NEXT: pcmpgtw %xmm3, %xmm7
+; SSE2-NEXT: por %xmm8, %xmm7
+; SSE2-NEXT: movdqa %xmm4, %xmm0
+; SSE2-NEXT: movdqa %xmm5, %xmm1
+; SSE2-NEXT: movdqa %xmm6, %xmm2
+; SSE2-NEXT: movdqa %xmm7, %xmm3
; SSE2-NEXT: retq
;
; SSSE3-LABEL: test35:
; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm5 = [32768,32768,32768,32768,32768,32768,32768,32768]
-; SSSE3-NEXT: movdqa %xmm0, %xmm6
-; SSSE3-NEXT: pxor %xmm5, %xmm6
-; SSSE3-NEXT: movdqa %xmm1, %xmm7
-; SSSE3-NEXT: pxor %xmm5, %xmm7
-; SSSE3-NEXT: movdqa %xmm2, %xmm8
+; SSSE3-NEXT: movdqa %xmm3, %xmm8
; SSSE3-NEXT: pxor %xmm5, %xmm8
-; SSSE3-NEXT: pxor %xmm3, %xmm5
+; SSSE3-NEXT: movdqa %xmm2, %xmm7
+; SSSE3-NEXT: pxor %xmm5, %xmm7
+; SSSE3-NEXT: movdqa %xmm1, %xmm6
+; SSSE3-NEXT: pxor %xmm5, %xmm6
+; SSSE3-NEXT: pxor %xmm0, %xmm5
; SSSE3-NEXT: movdqa %xmm5, %xmm4
-; SSSE3-NEXT: pcmpgtw %xmm3, %xmm4
-; SSSE3-NEXT: movdqa %xmm8, %xmm3
-; SSSE3-NEXT: pcmpgtw %xmm2, %xmm3
-; SSSE3-NEXT: movdqa %xmm7, %xmm2
-; SSSE3-NEXT: pcmpgtw %xmm1, %xmm2
-; SSSE3-NEXT: movdqa %xmm6, %xmm1
-; SSSE3-NEXT: pcmpgtw %xmm0, %xmm1
-; SSSE3-NEXT: por %xmm6, %xmm1
-; SSSE3-NEXT: por %xmm7, %xmm2
-; SSSE3-NEXT: por %xmm8, %xmm3
+; SSSE3-NEXT: pcmpgtw %xmm0, %xmm4
; SSSE3-NEXT: por %xmm5, %xmm4
-; SSSE3-NEXT: movdqa %xmm1, %xmm0
-; SSSE3-NEXT: movdqa %xmm2, %xmm1
-; SSSE3-NEXT: movdqa %xmm3, %xmm2
-; SSSE3-NEXT: movdqa %xmm4, %xmm3
+; SSSE3-NEXT: movdqa %xmm6, %xmm5
+; SSSE3-NEXT: pcmpgtw %xmm1, %xmm5
+; SSSE3-NEXT: por %xmm6, %xmm5
+; SSSE3-NEXT: movdqa %xmm7, %xmm6
+; SSSE3-NEXT: pcmpgtw %xmm2, %xmm6
+; SSSE3-NEXT: por %xmm7, %xmm6
+; SSSE3-NEXT: movdqa %xmm8, %xmm7
+; SSSE3-NEXT: pcmpgtw %xmm3, %xmm7
+; SSSE3-NEXT: por %xmm8, %xmm7
+; SSSE3-NEXT: movdqa %xmm4, %xmm0
+; SSSE3-NEXT: movdqa %xmm5, %xmm1
+; SSSE3-NEXT: movdqa %xmm6, %xmm2
+; SSSE3-NEXT: movdqa %xmm7, %xmm3
; SSSE3-NEXT: retq
;
; SSE41-LABEL: test35:
; SSE41: # %bb.0:
-; SSE41-NEXT: movdqa {{.*#+}} xmm4 = [32768,32768,32768,32768,32768,32768,32768,32768]
-; SSE41-NEXT: movdqa %xmm0, %xmm5
-; SSE41-NEXT: pxor %xmm4, %xmm5
-; SSE41-NEXT: movdqa %xmm1, %xmm6
-; SSE41-NEXT: pxor %xmm4, %xmm6
-; SSE41-NEXT: movdqa %xmm2, %xmm7
-; SSE41-NEXT: pxor %xmm4, %xmm7
-; SSE41-NEXT: pxor %xmm3, %xmm4
-; SSE41-NEXT: pmaxuw %xmm4, %xmm3
-; SSE41-NEXT: pcmpeqw %xmm4, %xmm3
-; SSE41-NEXT: pcmpeqd %xmm8, %xmm8
-; SSE41-NEXT: pxor %xmm8, %xmm3
-; SSE41-NEXT: pmaxuw %xmm7, %xmm2
-; SSE41-NEXT: pcmpeqw %xmm7, %xmm2
-; SSE41-NEXT: pxor %xmm8, %xmm2
-; SSE41-NEXT: pmaxuw %xmm6, %xmm1
-; SSE41-NEXT: pcmpeqw %xmm6, %xmm1
-; SSE41-NEXT: pxor %xmm8, %xmm1
+; SSE41-NEXT: movdqa {{.*#+}} xmm5 = [32768,32768,32768,32768,32768,32768,32768,32768]
+; SSE41-NEXT: movdqa %xmm3, %xmm4
+; SSE41-NEXT: pxor %xmm5, %xmm4
+; SSE41-NEXT: movdqa %xmm2, %xmm6
+; SSE41-NEXT: pxor %xmm5, %xmm6
+; SSE41-NEXT: movdqa %xmm1, %xmm7
+; SSE41-NEXT: pxor %xmm5, %xmm7
+; SSE41-NEXT: pxor %xmm0, %xmm5
; SSE41-NEXT: pmaxuw %xmm5, %xmm0
; SSE41-NEXT: pcmpeqw %xmm5, %xmm0
+; SSE41-NEXT: pcmpeqd %xmm8, %xmm8
; SSE41-NEXT: pxor %xmm8, %xmm0
; SSE41-NEXT: por %xmm5, %xmm0
-; SSE41-NEXT: por %xmm6, %xmm1
-; SSE41-NEXT: por %xmm7, %xmm2
+; SSE41-NEXT: pmaxuw %xmm7, %xmm1
+; SSE41-NEXT: pcmpeqw %xmm7, %xmm1
+; SSE41-NEXT: pxor %xmm8, %xmm1
+; SSE41-NEXT: por %xmm7, %xmm1
+; SSE41-NEXT: pmaxuw %xmm6, %xmm2
+; SSE41-NEXT: pcmpeqw %xmm6, %xmm2
+; SSE41-NEXT: pxor %xmm8, %xmm2
+; SSE41-NEXT: por %xmm6, %xmm2
+; SSE41-NEXT: pmaxuw %xmm4, %xmm3
+; SSE41-NEXT: pcmpeqw %xmm4, %xmm3
+; SSE41-NEXT: pxor %xmm8, %xmm3
; SSE41-NEXT: por %xmm4, %xmm3
; SSE41-NEXT: retq
;
; AVX1-LABEL: test35:
; AVX1: # %bb.0:
; AVX1-NEXT: vbroadcastss {{.*#+}} ymm2 = [32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768]
-; AVX1-NEXT: vxorps %ymm2, %ymm0, %ymm3
-; AVX1-NEXT: vxorps %ymm2, %ymm1, %ymm2
+; AVX1-NEXT: vxorps %ymm2, %ymm1, %ymm3
+; AVX1-NEXT: vxorps %ymm2, %ymm0, %ymm2
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4
-; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5
; AVX1-NEXT: vpmaxuw %xmm5, %xmm4, %xmm5
; AVX1-NEXT: vpcmpeqw %xmm5, %xmm4, %xmm4
; AVX1-NEXT: vpcmpeqd %xmm5, %xmm5, %xmm5
; AVX1-NEXT: vpxor %xmm5, %xmm4, %xmm4
-; AVX1-NEXT: vpmaxuw %xmm1, %xmm2, %xmm1
-; AVX1-NEXT: vpcmpeqw %xmm1, %xmm2, %xmm1
-; AVX1-NEXT: vpxor %xmm5, %xmm1, %xmm1
-; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm1, %ymm1
-; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm4
-; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm6
-; AVX1-NEXT: vpmaxuw %xmm6, %xmm4, %xmm6
-; AVX1-NEXT: vpcmpeqw %xmm6, %xmm4, %xmm4
-; AVX1-NEXT: vpxor %xmm5, %xmm4, %xmm4
-; AVX1-NEXT: vpmaxuw %xmm0, %xmm3, %xmm0
-; AVX1-NEXT: vpcmpeqw %xmm0, %xmm3, %xmm0
+; AVX1-NEXT: vpmaxuw %xmm0, %xmm2, %xmm0
+; AVX1-NEXT: vpcmpeqw %xmm0, %xmm2, %xmm0
; AVX1-NEXT: vpxor %xmm5, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
-; AVX1-NEXT: vorps %ymm3, %ymm0, %ymm0
-; AVX1-NEXT: vorps %ymm2, %ymm1, %ymm1
+; AVX1-NEXT: vorps %ymm2, %ymm0, %ymm0
+; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm2
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4
+; AVX1-NEXT: vpmaxuw %xmm4, %xmm2, %xmm4
+; AVX1-NEXT: vpcmpeqw %xmm4, %xmm2, %xmm2
+; AVX1-NEXT: vpxor %xmm5, %xmm2, %xmm2
+; AVX1-NEXT: vpmaxuw %xmm1, %xmm3, %xmm1
+; AVX1-NEXT: vpcmpeqw %xmm1, %xmm3, %xmm1
+; AVX1-NEXT: vpxor %xmm5, %xmm1, %xmm1
+; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
+; AVX1-NEXT: vorps %ymm3, %ymm1, %ymm1
; AVX1-NEXT: retq
;
; AVX2-LABEL: test35:
; AVX2: # %bb.0:
; AVX2-NEXT: vpbroadcastw {{.*#+}} ymm2 = [32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768]
-; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm3
-; AVX2-NEXT: vpxor %ymm2, %ymm1, %ymm2
-; AVX2-NEXT: vpmaxuw %ymm1, %ymm2, %ymm1
-; AVX2-NEXT: vpcmpeqw %ymm1, %ymm2, %ymm1
+; AVX2-NEXT: vpxor %ymm2, %ymm1, %ymm3
+; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm2
+; AVX2-NEXT: vpmaxuw %ymm0, %ymm2, %ymm0
+; AVX2-NEXT: vpcmpeqw %ymm0, %ymm2, %ymm0
; AVX2-NEXT: vpcmpeqd %ymm4, %ymm4, %ymm4
-; AVX2-NEXT: vpxor %ymm4, %ymm1, %ymm1
-; AVX2-NEXT: vpmaxuw %ymm0, %ymm3, %ymm0
-; AVX2-NEXT: vpcmpeqw %ymm0, %ymm3, %ymm0
; AVX2-NEXT: vpxor %ymm4, %ymm0, %ymm0
-; AVX2-NEXT: vpor %ymm3, %ymm0, %ymm0
-; AVX2-NEXT: vpor %ymm2, %ymm1, %ymm1
+; AVX2-NEXT: vpor %ymm2, %ymm0, %ymm0
+; AVX2-NEXT: vpmaxuw %ymm1, %ymm3, %ymm1
+; AVX2-NEXT: vpcmpeqw %ymm1, %ymm3, %ymm1
+; AVX2-NEXT: vpxor %ymm4, %ymm1, %ymm1
+; AVX2-NEXT: vpor %ymm3, %ymm1, %ymm1
; AVX2-NEXT: retq
;
; AVX512-LABEL: test35:
diff --git a/llvm/test/CodeGen/X86/psubus.ll b/llvm/test/CodeGen/X86/psubus.ll
index b93862be0a1b4..156d705457db0 100644
--- a/llvm/test/CodeGen/X86/psubus.ll
+++ b/llvm/test/CodeGen/X86/psubus.ll
@@ -961,8 +961,6 @@ define <16 x i8> @test14(<16 x i8> %x, <16 x i32> %y) nounwind {
; AVX2-NEXT: vpmaxud %ymm3, %ymm2, %ymm3
; AVX2-NEXT: vpcmpeqd %ymm3, %ymm2, %ymm3
; AVX2-NEXT: vpackssdw %ymm3, %ymm4, %ymm3
-; AVX2-NEXT: vpcmpeqd %ymm4, %ymm4, %ymm4
-; AVX2-NEXT: vpxor %ymm4, %ymm3, %ymm3
; AVX2-NEXT: vextracti128 $1, %ymm3, %xmm4
; AVX2-NEXT: vpacksswb %xmm4, %xmm3, %xmm3
; AVX2-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[0,2,1,3]
@@ -974,7 +972,7 @@ define <16 x i8> @test14(<16 x i8> %x, <16 x i32> %y) nounwind {
; AVX2-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,2,1,3]
; AVX2-NEXT: vpsubb %xmm0, %xmm1, %xmm0
-; AVX2-NEXT: vpandn %xmm0, %xmm3, %xmm0
+; AVX2-NEXT: vpand %xmm0, %xmm3, %xmm0
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
@@ -1186,14 +1184,12 @@ define <8 x i16> @test16(<8 x i16> %x, <8 x i32> %y) nounwind {
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX2-NEXT: vpmaxud %ymm2, %ymm1, %ymm2
; AVX2-NEXT: vpcmpeqd %ymm2, %ymm1, %ymm2
-; AVX2-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3
-; AVX2-NEXT: vpxor %ymm3, %ymm2, %ymm2
; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm3
; AVX2-NEXT: vpackssdw %xmm3, %xmm2, %xmm2
; AVX2-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u,16,17,20,21,24,25,28,29,u,u,u,u,u,u,u,u]
; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
; AVX2-NEXT: vpsubw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpand %xmm0, %xmm2, %xmm0
+; AVX2-NEXT: vpandn %xmm0, %xmm2, %xmm0
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
More information about the llvm-commits
mailing list