[llvm] [AMDGPU][CodeGen] Incrementally update reserved regs for SIPreAllocateWWMRegs pass in RegisterClassInfo (PR #212201)

[Carl Ritson via llvm-commits]

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@@ -180,8 +172,10 @@ void SIPreAllocateWWMRegs::rewriteRegs(MachineFunction &MF) {
 
   RegsToRewrite.clear();
 
-  // Update the set of reserved registers to include WWM ones.
+  // Update the set of reserved registers to include WWM ones
+  // without unnecessarily invalidating RegClassInfo.
   MRI->freezeReservedRegs();
+  RegClassInfo.updateReservedRegs(MRI->getReservedRegs());
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perlfu wrote:

Just call this `RCI` for consistency?

https://github.com/llvm/llvm-project/pull/212201