[llvm] 20826cc - [EarlyIfConversion] Extend data dependent analysis across multiple blocks (#180623)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 23 03:51:20 PDT 2026
Author: Jonathan Cohen
Date: 2026-08-23T13:51:15+03:00
New Revision: 20826ccc55d853480acfaa158e50fdc73bb537a4
URL: https://github.com/llvm/llvm-project/commit/20826ccc55d853480acfaa158e50fdc73bb537a4
DIFF: https://github.com/llvm/llvm-project/commit/20826ccc55d853480acfaa158e50fdc73bb537a4.diff
LOG: [EarlyIfConversion] Extend data dependent analysis across multiple blocks (#180623)
This extends the new data dependent analysis for branches to cover loads
which feed conditions which are not within the same Machine Basic Block.
To still try to catch loads which are "close in program time" we
limit on the number of instructions between the branch and the
load. We also bail out if we detect a function call or loop between the two
instructions.
Added:
llvm/test/CodeGen/AArch64/early-ifcvt-load-to-cond-br-limit.mir
Modified:
llvm/lib/CodeGen/EarlyIfConversion.cpp
llvm/test/CodeGen/AArch64/early-ifcvt-load-to-cond-br.mir
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/EarlyIfConversion.cpp b/llvm/lib/CodeGen/EarlyIfConversion.cpp
index c1e82ec4e9569..bf2664fd4225c 100644
--- a/llvm/lib/CodeGen/EarlyIfConversion.cpp
+++ b/llvm/lib/CodeGen/EarlyIfConversion.cpp
@@ -17,12 +17,14 @@
#include "llvm/CodeGen/EarlyIfConversion.h"
#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/PostOrderIterator.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SparseSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/OptimizationRemarkEmitter.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
@@ -70,6 +72,13 @@ static cl::opt<unsigned>
cl::desc("Limit the number of steps taken when searching for a "
"recently loaded value"));
+// Limit the work done when looking for calls between a load and the condition
+// it feeds.
+static cl::opt<unsigned> MaxRegionInstrs(
+ "early-ifcvt-max-region-instrs", cl::Hidden, cl::init(64),
+ cl::desc("Limit the number of blocks and instructions examined when "
+ "searching for calls between a load and the condition it feeds"));
+
STATISTIC(NumDiamondsSeen, "Number of diamonds");
STATISTIC(NumDiamondsConv, "Number of diamonds converted");
STATISTIC(NumTrianglesSeen, "Number of triangles");
@@ -830,6 +839,10 @@ class EarlyIfConverter {
MachineBranchProbabilityInfo *MBPI = nullptr;
SSAIfConv IfConv;
+ /// Cache of basic blocks verified to contain no call instructions, mapping
+ /// each block to the number of instructions scanned in it.
+ DenseMap<const MachineBasicBlock *, unsigned> NoCallBlocksCache;
+
public:
EarlyIfConverter(MachineDominatorTree &DT, MachineLoopInfo &LI,
MachineTraceMetrics &MTM, MachineBranchProbabilityInfo *MBPI)
@@ -843,7 +856,8 @@ class EarlyIfConverter {
void invalidateTraces();
bool shouldConvertIf();
bool isConditionDataDependent();
- bool doOperandsComeFromMemory(Register Reg);
+ bool doOperandsComeFromMemory(const MachineInstr *ConditionDef);
+ bool hasCallOrLoopInRange(const MachineInstr *From, const MachineInstr *To);
};
class EarlyIfConverterLegacy : public MachineFunctionPass {
@@ -925,31 +939,132 @@ static bool isConstantPoolLoad(const MachineInstr *MI) {
});
}
-/// Check if there are any calls in the range (From, To].
-static bool callInRange(const MachineInstr *From, const MachineInstr *To) {
- constexpr int MaxInstructionsToCheck = 64;
- int Count = 0;
- auto InstrRange =
- make_range(std::next(From->getIterator()), To->getIterator());
- return any_of(InstrRange, [&](const MachineInstr &MI) {
- return ++Count > MaxInstructionsToCheck || MI.isCall();
- });
+/// Check whether the load in From and the condition in To are far apart, i.e.
+/// whether a call or a loop can be executed between them. This is done by first
+/// scanning the instructions within From and To MBBs. If no call is found, we
+/// then scan all blocks which are dominated by From (the load) and can reach To
+/// (the condition), looking for calls and for blocks belonging to a loop the
+/// condition is not part of.
+bool EarlyIfConverter::hasCallOrLoopInRange(const MachineInstr *From,
+ const MachineInstr *To) {
+ if (From == To)
+ return false;
+
+ LLVM_DEBUG(dbgs() << " checking for a call or loop between " << *From
+ << " and " << *To);
+ assert(DomTree->dominates(From, To) && "From is expected to dominate To");
+
+ const MachineBasicBlock *FromBB = From->getParent();
+ const MachineBasicBlock *ToBB = To->getParent();
+
+ unsigned NumScanned = 0;
+ auto HitSearchLimit = [&](unsigned N) {
+ NumScanned += N;
+ if (NumScanned <= MaxRegionInstrs)
+ return false;
+ LLVM_DEBUG(dbgs() << " hasCallOrLoopInRange scanned more than "
+ << MaxRegionInstrs << " instructions\n");
+ return true;
+ };
+ auto FoundCall = [](const MachineInstr &MI) {
+ LLVM_DEBUG(dbgs() << " found a call before the condition: " << MI);
+ return true;
+ };
+ auto IsCallOrHitSearchLimit = [&](const MachineInstr &MI) {
+ if (HitSearchLimit(1))
+ return true;
+ if (!MI.isCall())
+ return false;
+ return FoundCall(MI);
+ };
+
+ // If From and To are in the same block, just check (From, To).
+ if (FromBB == ToBB) {
+ for (const MachineInstr &MI :
+ make_range(std::next(From->getIterator()), To->getIterator()))
+ if (IsCallOrHitSearchLimit(MI))
+ return true;
+ return false;
+ }
+
+ // Check (From, end of From's block] and [start of To's block, To).
+ for (const MachineInstr &MI :
+ make_range(std::next(From->getIterator()), FromBB->instr_end()))
+ if (IsCallOrHitSearchLimit(MI))
+ return true;
+ for (const MachineInstr &MI :
+ make_range(ToBB->instr_begin(), To->getIterator()))
+ if (IsCallOrHitSearchLimit(MI))
+ return true;
+
+ // Enqueued guards the traversal: the endpoint blocks are traversed through
+ // but their instructions were already handled above.
+ SmallPtrSet<const MachineBasicBlock *, 16> Enqueued = {FromBB, ToBB};
+ SmallVector<const MachineBasicBlock *, 16> Worklist;
+ auto Enqueue = [&](const MachineBasicBlock *BB) {
+ if (DomTree->dominates(FromBB, BB) && Enqueued.insert(BB).second)
+ Worklist.push_back(BB);
+ };
+
+ for (const MachineBasicBlock *Pred : ToBB->predecessors())
+ Enqueue(Pred);
+
+ while (!Worklist.empty()) {
+ const MachineBasicBlock *BB = Worklist.pop_back_val();
+
+ // If the block belongs to a loop containing neither the load nor the
+ // condition, that loop is executed entirely between the two, so consider
+ // them far apart.
+ if (const MachineLoop *BBLoop = Loops->getLoopFor(BB)) {
+ if (!BBLoop->contains(ToBB) && !BBLoop->contains(FromBB)) {
+ LLVM_DEBUG(dbgs() << " found a loop before the condition in "
+ << printMBBReference(*BB) << '\n');
+ return true;
+ }
+ }
+
+ // Next check for calls in the block.
+ auto CacheIt = NoCallBlocksCache.find(BB);
+ if (CacheIt != NoCallBlocksCache.end()) {
+ if (HitSearchLimit(CacheIt->second))
+ return true;
+ } else {
+ for (const MachineInstr &MI : *BB)
+ if (IsCallOrHitSearchLimit(MI))
+ return true;
+ NoCallBlocksCache[BB] = BB->size();
+ }
+
+ for (const MachineBasicBlock *Pred : BB->predecessors())
+ Enqueue(Pred);
+ }
+
+ return false;
}
/// Check if a register's value comes from a memory load by walking the
/// def-use chain. We want to prioritize converting branches which
/// depend on values loaded from memory (unless they are loop invariant,
-/// or come from a constant pool). Only consider loads that are in the
-/// same basic block as the branch to ensure the load is "immediately"
-/// before the branch in program time.
-bool EarlyIfConverter::doOperandsComeFromMemory(Register Reg) {
+/// or come from a constant pool). The walk starts from the definition of
+/// ConditionDef's first operand, which is not ConditionDef itself for
+/// instructions such as FCMPSrr, where that operand is a use.
+bool EarlyIfConverter::doOperandsComeFromMemory(
+ const MachineInstr *ConditionDef) {
+ Register Reg = ConditionDef->getOperand(0).getReg();
if (!Reg.isVirtual())
return false;
+ LLVM_DEBUG(dbgs() << " doOperandsComeFromMemory starting from reg "
+ << printReg(Reg) << "\n");
+
+ // The condition is consumed by the branch terminating Head, so this is the
+ // end of the interval a load has to survive without a call in between.
+ const MachineInstr *Br = &*IfConv.Head->getFirstTerminator();
+ MachineLoop *IfConvLoop = Loops->getLoopFor(IfConv.Head);
+
// Walk the def-use chain.
SmallPtrSet<const MachineInstr *, 8> VisitedInstrs;
SmallVector<const MachineInstr *> Worklist;
- SmallVector<Register, 16> VisitedRegs;
MachineInstr *DefMI = MRI->getVRegDef(Reg);
// The operand is defined outside of the function - it does not
@@ -958,24 +1073,39 @@ bool EarlyIfConverter::doOperandsComeFromMemory(Register Reg) {
return false;
Worklist.push_back(DefMI);
- VisitedRegs.push_back(Reg);
while (!Worklist.empty() && VisitedInstrs.size() < MaxNumSteps) {
const MachineInstr *MI = Worklist.pop_back_val();
if (!VisitedInstrs.insert(MI).second)
continue;
- // Stop walking if we encounter an instruction outside the head block.
- if (MI->getParent() != IfConv.Head)
- break;
+ // Don't walk through PHIs: a value arriving on a back edge is loaded in a
+ // previous iteration, so the interval between the load and the branch is
+ // not the one hasCallOrLoopInRange measures.
+ if (MI->isPHI())
+ continue;
+
+ const MachineBasicBlock *Parent = MI->getParent();
+ MachineLoop *ParentLoop = Loops->getLoopFor(Parent);
+
+ // If the instruction is outside the loop, skip it (loop-invariant).
+ if (IfConvLoop && ParentLoop != IfConvLoop)
+ continue;
- // Check if this instruction is a load, and there are no calls between
- // the load and the branch (which would break the "close in time"
- // assumption).
+ // Check if this instruction is a load, and there are no calls or loops
+ // between the load and the condition (which would break the "close in
+ // time" assumption).
if (MI->mayLoad() && !isConstantPoolLoad(MI) &&
- !MI->isDereferenceableInvariantLoad() &&
- !callInRange(MI, &*IfConv.Head->getFirstTerminator()))
+ !MI->isDereferenceableInvariantLoad()) {
+ // If the load doesn't dominate the branch (e.g., comes after it in
+ // the same block via a loop back-edge), it can't affect this iteration.
+ // If not - check if there is a call or a loop between the load
+ // instruction and the branch.
+ if (!DomTree->dominates(MI, Br) || hasCallOrLoopInRange(MI, Br))
+ continue;
+
return true;
+ }
// Walk through all register use operands and find their definitions.
for (const MachineOperand &MO : MI->operands()) {
@@ -988,7 +1118,6 @@ bool EarlyIfConverter::doOperandsComeFromMemory(Register Reg) {
if (MachineInstr *UseDef = MRI->getVRegDef(UseReg)) {
if (!VisitedInstrs.count(UseDef)) {
Worklist.push_back(UseDef);
- VisitedRegs.push_back(UseReg);
}
}
}
@@ -1019,7 +1148,7 @@ bool EarlyIfConverter::isConditionDataDependent() {
// Check if operands used to compute the branch condition were loaded recently
// from memory, starting by the ConditionDef itself and walking up the use-def
// chain.
- if (doOperandsComeFromMemory(MBP.ConditionDef->getOperand(0).getReg())) {
+ if (doOperandsComeFromMemory(MBP.ConditionDef)) {
++NumDataDependant;
return true;
}
@@ -1270,8 +1399,13 @@ bool EarlyIfConverter::tryConvertIf(MachineBasicBlock *MBB) {
Changed = true;
updateDomTree(DomTree, IfConv, RemoveBlocks);
updateLoops(Loops, RemoveBlocks);
- for (MachineBasicBlock *MBB : RemoveBlocks)
+ // Head absorbs the instructions of the removed blocks, including any calls,
+ // so a Head cached as call-free may no longer be.
+ NoCallBlocksCache.erase(IfConv.Head);
+ for (MachineBasicBlock *MBB : RemoveBlocks) {
+ NoCallBlocksCache.erase(MBB);
MBB->eraseFromParent();
+ }
}
return Changed;
}
diff --git a/llvm/test/CodeGen/AArch64/early-ifcvt-load-to-cond-br-limit.mir b/llvm/test/CodeGen/AArch64/early-ifcvt-load-to-cond-br-limit.mir
new file mode 100644
index 0000000000000..12170733e2332
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/early-ifcvt-load-to-cond-br-limit.mir
@@ -0,0 +1,186 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=aarch64 -mcpu=apple-m1 -run-pass=early-ifcvt -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=CHECK-DEFAULT
+# RUN: llc -mtriple=aarch64 -mcpu=apple-m1 -run-pass=early-ifcvt -enable-early-ifcvt-data-dependent -early-ifcvt-max-region-instrs=3 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=CHECK-SMALL-BUDGET
+# RUN: llc -mtriple=aarch64 -mcpu=apple-m1 -run-pass=early-ifcvt -enable-early-ifcvt-data-dependent -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=CHECK-LARGE-BUDGET
+
+---
+name: load_in_pred_region_over_instruction_budget
+alignment: 4
+tracksRegLiveness: true
+body: |
+ ; CHECK-DEFAULT-LABEL: name: load_in_pred_region_over_instruction_budget
+ ; CHECK-DEFAULT: bb.0:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-DEFAULT-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-DEFAULT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-DEFAULT-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.1:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-DEFAULT-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[LDRWui]], 0, 0, implicit-def $nzcv
+ ; CHECK-DEFAULT-NEXT: Bcc 0, %bb.2, implicit $nzcv
+ ; CHECK-DEFAULT-NEXT: B %bb.3
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.2:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: STRWui $wzr, [[COPY]], 0 :: (store (s32))
+ ; CHECK-DEFAULT-NEXT: STRWui $wzr, [[COPY]], 1 :: (store (s32))
+ ; CHECK-DEFAULT-NEXT: STRWui $wzr, [[COPY]], 2 :: (store (s32))
+ ; CHECK-DEFAULT-NEXT: STRWui $wzr, [[COPY]], 3 :: (store (s32))
+ ; CHECK-DEFAULT-NEXT: STRWui $wzr, [[COPY]], 4 :: (store (s32))
+ ; CHECK-DEFAULT-NEXT: STRWui $wzr, [[COPY]], 5 :: (store (s32))
+ ; CHECK-DEFAULT-NEXT: B %bb.3
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.3:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.4(0x40000000), %bb.5(0x40000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[ADDWri:%[0-9]+]]:gpr32common = ADDWri [[LDRWui]], 1, 0
+ ; CHECK-DEFAULT-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[ADDWri]], 100, 0, implicit-def $nzcv
+ ; CHECK-DEFAULT-NEXT: Bcc 12, %bb.5, implicit $nzcv
+ ; CHECK-DEFAULT-NEXT: B %bb.4
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.4:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.5(0x80000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-DEFAULT-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.5:
+ ; CHECK-DEFAULT-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.3, [[MADDWrrr1]], %bb.4
+ ; CHECK-DEFAULT-NEXT: $w0 = COPY [[PHI]]
+ ; CHECK-DEFAULT-NEXT: RET_ReallyLR implicit $w0
+ ;
+ ; CHECK-SMALL-BUDGET-LABEL: name: load_in_pred_region_over_instruction_budget
+ ; CHECK-SMALL-BUDGET: bb.0:
+ ; CHECK-SMALL-BUDGET-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-SMALL-BUDGET-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-SMALL-BUDGET-NEXT: {{ $}}
+ ; CHECK-SMALL-BUDGET-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-SMALL-BUDGET-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-SMALL-BUDGET-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-SMALL-BUDGET-NEXT: {{ $}}
+ ; CHECK-SMALL-BUDGET-NEXT: bb.1:
+ ; CHECK-SMALL-BUDGET-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
+ ; CHECK-SMALL-BUDGET-NEXT: {{ $}}
+ ; CHECK-SMALL-BUDGET-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-SMALL-BUDGET-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[LDRWui]], 0, 0, implicit-def $nzcv
+ ; CHECK-SMALL-BUDGET-NEXT: Bcc 0, %bb.2, implicit $nzcv
+ ; CHECK-SMALL-BUDGET-NEXT: B %bb.3
+ ; CHECK-SMALL-BUDGET-NEXT: {{ $}}
+ ; CHECK-SMALL-BUDGET-NEXT: bb.2:
+ ; CHECK-SMALL-BUDGET-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-SMALL-BUDGET-NEXT: {{ $}}
+ ; CHECK-SMALL-BUDGET-NEXT: STRWui $wzr, [[COPY]], 0 :: (store (s32))
+ ; CHECK-SMALL-BUDGET-NEXT: STRWui $wzr, [[COPY]], 1 :: (store (s32))
+ ; CHECK-SMALL-BUDGET-NEXT: STRWui $wzr, [[COPY]], 2 :: (store (s32))
+ ; CHECK-SMALL-BUDGET-NEXT: STRWui $wzr, [[COPY]], 3 :: (store (s32))
+ ; CHECK-SMALL-BUDGET-NEXT: STRWui $wzr, [[COPY]], 4 :: (store (s32))
+ ; CHECK-SMALL-BUDGET-NEXT: STRWui $wzr, [[COPY]], 5 :: (store (s32))
+ ; CHECK-SMALL-BUDGET-NEXT: B %bb.3
+ ; CHECK-SMALL-BUDGET-NEXT: {{ $}}
+ ; CHECK-SMALL-BUDGET-NEXT: bb.3:
+ ; CHECK-SMALL-BUDGET-NEXT: successors: %bb.4(0x40000000), %bb.5(0x40000000)
+ ; CHECK-SMALL-BUDGET-NEXT: {{ $}}
+ ; CHECK-SMALL-BUDGET-NEXT: [[ADDWri:%[0-9]+]]:gpr32common = ADDWri [[LDRWui]], 1, 0
+ ; CHECK-SMALL-BUDGET-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[ADDWri]], 100, 0, implicit-def $nzcv
+ ; CHECK-SMALL-BUDGET-NEXT: Bcc 12, %bb.5, implicit $nzcv
+ ; CHECK-SMALL-BUDGET-NEXT: B %bb.4
+ ; CHECK-SMALL-BUDGET-NEXT: {{ $}}
+ ; CHECK-SMALL-BUDGET-NEXT: bb.4:
+ ; CHECK-SMALL-BUDGET-NEXT: successors: %bb.5(0x80000000)
+ ; CHECK-SMALL-BUDGET-NEXT: {{ $}}
+ ; CHECK-SMALL-BUDGET-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-SMALL-BUDGET-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-SMALL-BUDGET-NEXT: {{ $}}
+ ; CHECK-SMALL-BUDGET-NEXT: bb.5:
+ ; CHECK-SMALL-BUDGET-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.3, [[MADDWrrr1]], %bb.4
+ ; CHECK-SMALL-BUDGET-NEXT: $w0 = COPY [[PHI]]
+ ; CHECK-SMALL-BUDGET-NEXT: RET_ReallyLR implicit $w0
+ ;
+ ; CHECK-LARGE-BUDGET-LABEL: name: load_in_pred_region_over_instruction_budget
+ ; CHECK-LARGE-BUDGET: bb.0:
+ ; CHECK-LARGE-BUDGET-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-LARGE-BUDGET-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-LARGE-BUDGET-NEXT: {{ $}}
+ ; CHECK-LARGE-BUDGET-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-LARGE-BUDGET-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-LARGE-BUDGET-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-LARGE-BUDGET-NEXT: {{ $}}
+ ; CHECK-LARGE-BUDGET-NEXT: bb.1:
+ ; CHECK-LARGE-BUDGET-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
+ ; CHECK-LARGE-BUDGET-NEXT: {{ $}}
+ ; CHECK-LARGE-BUDGET-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-LARGE-BUDGET-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[LDRWui]], 0, 0, implicit-def $nzcv
+ ; CHECK-LARGE-BUDGET-NEXT: Bcc 0, %bb.2, implicit $nzcv
+ ; CHECK-LARGE-BUDGET-NEXT: B %bb.3
+ ; CHECK-LARGE-BUDGET-NEXT: {{ $}}
+ ; CHECK-LARGE-BUDGET-NEXT: bb.2:
+ ; CHECK-LARGE-BUDGET-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-LARGE-BUDGET-NEXT: {{ $}}
+ ; CHECK-LARGE-BUDGET-NEXT: STRWui $wzr, [[COPY]], 0 :: (store (s32))
+ ; CHECK-LARGE-BUDGET-NEXT: STRWui $wzr, [[COPY]], 1 :: (store (s32))
+ ; CHECK-LARGE-BUDGET-NEXT: STRWui $wzr, [[COPY]], 2 :: (store (s32))
+ ; CHECK-LARGE-BUDGET-NEXT: STRWui $wzr, [[COPY]], 3 :: (store (s32))
+ ; CHECK-LARGE-BUDGET-NEXT: STRWui $wzr, [[COPY]], 4 :: (store (s32))
+ ; CHECK-LARGE-BUDGET-NEXT: STRWui $wzr, [[COPY]], 5 :: (store (s32))
+ ; CHECK-LARGE-BUDGET-NEXT: B %bb.3
+ ; CHECK-LARGE-BUDGET-NEXT: {{ $}}
+ ; CHECK-LARGE-BUDGET-NEXT: bb.3:
+ ; CHECK-LARGE-BUDGET-NEXT: [[ADDWri:%[0-9]+]]:gpr32common = ADDWri [[LDRWui]], 1, 0
+ ; CHECK-LARGE-BUDGET-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[ADDWri]], 100, 0, implicit-def $nzcv
+ ; CHECK-LARGE-BUDGET-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-LARGE-BUDGET-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-LARGE-BUDGET-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY1]], [[MADDWrrr1]], 12, implicit $nzcv
+ ; CHECK-LARGE-BUDGET-NEXT: $w0 = COPY [[CSELWr]]
+ ; CHECK-LARGE-BUDGET-NEXT: RET_ReallyLR implicit $w0
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $x0, $w1, $w2
+
+ %0:gpr64common = COPY $x0
+ %1:gpr32 = COPY $w1
+ %2:gpr32 = COPY $w2
+
+ bb.1:
+ successors: %bb.2(0x40000000), %bb.3(0x40000000)
+
+ %3:gpr32common = LDRWui %0, 0 :: (load (s32))
+ %9:gpr32 = SUBSWri %3, 0, 0, implicit-def $nzcv
+ Bcc 0, %bb.2, implicit $nzcv
+ B %bb.3
+
+ bb.2:
+ successors: %bb.3(0x80000000)
+
+ STRWui $wzr, %0, 0 :: (store (s32))
+ STRWui $wzr, %0, 1 :: (store (s32))
+ STRWui $wzr, %0, 2 :: (store (s32))
+ STRWui $wzr, %0, 3 :: (store (s32))
+ STRWui $wzr, %0, 4 :: (store (s32))
+ STRWui $wzr, %0, 5 :: (store (s32))
+ B %bb.3
+
+ bb.3:
+ successors: %bb.4(0x40000000), %bb.5(0x40000000)
+
+ %4:gpr32common = ADDWri %3, 1, 0
+ %5:gpr32 = SUBSWri %4, 100, 0, implicit-def $nzcv
+ Bcc 12, %bb.5, implicit $nzcv
+ B %bb.4
+
+ bb.4:
+ successors: %bb.5(0x80000000)
+
+ %6:gpr32 = MADDWrrr %1, %2, $wzr
+ %7:gpr32 = MADDWrrr %6, %1, $wzr
+
+ bb.5:
+ %8:gpr32 = PHI %1, %bb.3, %7, %bb.4
+ $w0 = COPY %8
+ RET_ReallyLR implicit $w0
+...
diff --git a/llvm/test/CodeGen/AArch64/early-ifcvt-load-to-cond-br.mir b/llvm/test/CodeGen/AArch64/early-ifcvt-load-to-cond-br.mir
index ba37de47e6b64..79d0fdcf5c5bb 100644
--- a/llvm/test/CodeGen/AArch64/early-ifcvt-load-to-cond-br.mir
+++ b/llvm/test/CodeGen/AArch64/early-ifcvt-load-to-cond-br.mir
@@ -1,55 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=aarch64 -mcpu=apple-m1 -run-pass=early-ifcvt -o - %s | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK-DEFAULT
-# RUN: llc -mtriple=aarch64 -mcpu=apple-m1 -run-pass=early-ifcvt -enable-early-ifcvt-data-dependent -o - %s | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK-DATA-DEPENDENT
-
---- |
- define i32 @arg_to_cond_branch(i32 %val, i32 %x, i32 %y) {
- ret i32 0
- }
- define i32 @load_from_constant_pool_to_cond_branch(ptr %p, i32 %x, i32 %y) {
- ret i32 0
- }
- define i32 @load_from_constant_pool_to_cond_branch_with_cbz(ptr %p, i32 %x, i32 %y) {
- ret i32 0
- }
- define i32 @load_to_cond_branch(ptr %p, i32 %x, i32 %y) {
- ret i32 0
- }
- define i32 @cbz_arg_to_cond_branch(i32 %val, i32 %x, i32 %y) {
- ret i32 0
- }
- define i32 @cbz_load_to_cond_branch(ptr %p, i32 %x, i32 %y) {
- ret i32 0
- }
- define i32 @tbz_arg_to_cond_branch(i32 %val, i32 %x, i32 %y) {
- ret i32 0
- }
- define i32 @tbz_load_to_cond_branch(ptr %p, i32 %x, i32 %y) {
- ret i32 0
- }
- define i32 @mixed_cp_and_mem_load_to_cond_branch(ptr %p, i32 %x, i32 %y) {
- ret i32 0
- }
- define i32 @hot_branch_load_to_cond_branch(ptr %p, i32 %x, i32 %y) {
- ret i32 0
- }
- define i32 @invariant_load_to_cond_branch(ptr %p, i32 %x, i32 %y) {
- ret i32 0
- }
- define i32 @load_outside_loop_branch_inside(ptr %p, i32 %x, i32 %y) {
- ret i32 0
- }
- define i32 @load_inside_loop_branch_inside(ptr %p, i32 %x, i32 %y) {
- ret i32 0
- }
- define i32 @load_branch_separate_bbs_in_loop(ptr %p, i32 %x, i32 %y) {
- ret i32 0
- }
- define i32 @call_between_load_and_branch(ptr %p, i32 %x, i32 %y) {
- ret i32 0
- }
- declare void @foo()
-...
+# RUN: llc -mtriple=aarch64 -mcpu=apple-m1 -run-pass=early-ifcvt -verify-machine-dom-info -o - %s | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK-DEFAULT
+# RUN: llc -mtriple=aarch64 -mcpu=apple-m1 -run-pass=early-ifcvt -enable-early-ifcvt-data-dependent -verify-machine-dom-info -o - %s | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK-DATA-DEPENDENT
+
---
name: arg_to_cond_branch
alignment: 4
@@ -853,44 +805,73 @@ name: load_branch_separate_bbs_in_loop
alignment: 4
tracksRegLiveness: true
body: |
- ; CHECK-COMMON-LABEL: name: load_branch_separate_bbs_in_loop
- ; CHECK-COMMON: bb.0:
- ; CHECK-COMMON-NEXT: successors: %bb.1(0x80000000)
- ; CHECK-COMMON-NEXT: liveins: $x0, $w1, $w2
- ; CHECK-COMMON-NEXT: {{ $}}
- ; CHECK-COMMON-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
- ; CHECK-COMMON-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
- ; CHECK-COMMON-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
- ; CHECK-COMMON-NEXT: {{ $}}
- ; CHECK-COMMON-NEXT: bb.1:
- ; CHECK-COMMON-NEXT: successors: %bb.2(0x80000000)
- ; CHECK-COMMON-NEXT: {{ $}}
- ; CHECK-COMMON-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
- ; CHECK-COMMON-NEXT: {{ $}}
- ; CHECK-COMMON-NEXT: bb.2:
- ; CHECK-COMMON-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)
- ; CHECK-COMMON-NEXT: {{ $}}
- ; CHECK-COMMON-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[LDRWui]], 100, 0, implicit-def $nzcv
- ; CHECK-COMMON-NEXT: Bcc 12, %bb.4, implicit $nzcv
- ; CHECK-COMMON-NEXT: B %bb.3
- ; CHECK-COMMON-NEXT: {{ $}}
- ; CHECK-COMMON-NEXT: bb.3:
- ; CHECK-COMMON-NEXT: successors: %bb.4(0x80000000)
- ; CHECK-COMMON-NEXT: {{ $}}
- ; CHECK-COMMON-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
- ; CHECK-COMMON-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
- ; CHECK-COMMON-NEXT: {{ $}}
- ; CHECK-COMMON-NEXT: bb.4:
- ; CHECK-COMMON-NEXT: successors: %bb.1(0x7c000000), %bb.5(0x04000000)
- ; CHECK-COMMON-NEXT: {{ $}}
- ; CHECK-COMMON-NEXT: [[PHI:%[0-9]+]]:gpr32sp = PHI [[COPY1]], %bb.2, [[MADDWrrr1]], %bb.3
- ; CHECK-COMMON-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI]], 0, 0, implicit-def $nzcv
- ; CHECK-COMMON-NEXT: Bcc 12, %bb.1, implicit $nzcv
- ; CHECK-COMMON-NEXT: B %bb.5
- ; CHECK-COMMON-NEXT: {{ $}}
- ; CHECK-COMMON-NEXT: bb.5:
- ; CHECK-COMMON-NEXT: $w0 = COPY [[PHI]]
- ; CHECK-COMMON-NEXT: RET_ReallyLR implicit $w0
+ ; CHECK-DEFAULT-LABEL: name: load_branch_separate_bbs_in_loop
+ ; CHECK-DEFAULT: bb.0:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-DEFAULT-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-DEFAULT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-DEFAULT-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.1:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.2:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[LDRWui]], 100, 0, implicit-def $nzcv
+ ; CHECK-DEFAULT-NEXT: Bcc 12, %bb.4, implicit $nzcv
+ ; CHECK-DEFAULT-NEXT: B %bb.3
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.3:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.4(0x80000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-DEFAULT-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.4:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.1(0x7c000000), %bb.5(0x04000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[PHI:%[0-9]+]]:gpr32sp = PHI [[COPY1]], %bb.2, [[MADDWrrr1]], %bb.3
+ ; CHECK-DEFAULT-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI]], 0, 0, implicit-def $nzcv
+ ; CHECK-DEFAULT-NEXT: Bcc 12, %bb.1, implicit $nzcv
+ ; CHECK-DEFAULT-NEXT: B %bb.5
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.5:
+ ; CHECK-DEFAULT-NEXT: $w0 = COPY [[PHI]]
+ ; CHECK-DEFAULT-NEXT: RET_ReallyLR implicit $w0
+ ;
+ ; CHECK-DATA-DEPENDENT-LABEL: name: load_branch_separate_bbs_in_loop
+ ; CHECK-DATA-DEPENDENT: bb.0:
+ ; CHECK-DATA-DEPENDENT-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-DATA-DEPENDENT-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-DATA-DEPENDENT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-DATA-DEPENDENT-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: bb.1:
+ ; CHECK-DATA-DEPENDENT-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: bb.2:
+ ; CHECK-DATA-DEPENDENT-NEXT: successors: %bb.1(0x7c000000), %bb.5(0x04000000)
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[LDRWui]], 100, 0, implicit-def $nzcv
+ ; CHECK-DATA-DEPENDENT-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-DATA-DEPENDENT-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-DATA-DEPENDENT-NEXT: [[CSELWr:%[0-9]+]]:gpr32common = CSELWr [[COPY1]], [[MADDWrrr1]], 12, implicit $nzcv
+ ; CHECK-DATA-DEPENDENT-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[CSELWr]], 0, 0, implicit-def $nzcv
+ ; CHECK-DATA-DEPENDENT-NEXT: Bcc 12, %bb.1, implicit $nzcv
+ ; CHECK-DATA-DEPENDENT-NEXT: B %bb.5
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: bb.5:
+ ; CHECK-DATA-DEPENDENT-NEXT: $w0 = COPY [[CSELWr]]
+ ; CHECK-DATA-DEPENDENT-NEXT: RET_ReallyLR implicit $w0
bb.0:
successors: %bb.1(0x80000000)
liveins: $x0, $w1, $w2
@@ -943,7 +924,7 @@ body: |
; CHECK-COMMON-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-COMMON-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
; CHECK-COMMON-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
- ; CHECK-COMMON-NEXT: BL @foo, implicit-def $lr
+ ; CHECK-COMMON-NEXT: BL &foo, implicit-def $lr
; CHECK-COMMON-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[LDRWui]], 100, 0, implicit-def $nzcv
; CHECK-COMMON-NEXT: Bcc 12, %bb.2, implicit $nzcv
; CHECK-COMMON-NEXT: B %bb.1
@@ -966,7 +947,7 @@ body: |
%1:gpr32 = COPY $w1
%2:gpr32 = COPY $w2
%3:gpr32common = LDRWui %0, 0 :: (load (s32))
- BL @foo, implicit-def $lr
+ BL &foo, implicit-def $lr
%4:gpr32 = SUBSWri %3, 100, 0, implicit-def $nzcv
Bcc 12, %bb.2, implicit $nzcv
B %bb.1
@@ -981,3 +962,1561 @@ body: |
%7:gpr32 = PHI %1, %bb.0, %6, %bb.1
$w0 = COPY %7
RET_ReallyLR implicit $w0
+...
+---
+name: load_cond_and_branch_pred_bb
+alignment: 4
+tracksRegLiveness: true
+body: |
+ ; CHECK-DEFAULT-LABEL: name: load_cond_and_branch_pred_bb
+ ; CHECK-DEFAULT: bb.0:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-DEFAULT-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-DEFAULT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-DEFAULT-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-DEFAULT-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-DEFAULT-NEXT: B %bb.1
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.1:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[LDRWui]], 100, 0, implicit-def $nzcv
+ ; CHECK-DEFAULT-NEXT: Bcc 12, %bb.3, implicit $nzcv
+ ; CHECK-DEFAULT-NEXT: B %bb.2
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.2:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-DEFAULT-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.3:
+ ; CHECK-DEFAULT-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[MADDWrrr1]], %bb.2
+ ; CHECK-DEFAULT-NEXT: $w0 = COPY [[PHI]]
+ ; CHECK-DEFAULT-NEXT: RET_ReallyLR implicit $w0
+ ;
+ ; CHECK-DATA-DEPENDENT-LABEL: name: load_cond_and_branch_pred_bb
+ ; CHECK-DATA-DEPENDENT: bb.0:
+ ; CHECK-DATA-DEPENDENT-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-DATA-DEPENDENT-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-DATA-DEPENDENT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-DATA-DEPENDENT-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-DATA-DEPENDENT-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-DATA-DEPENDENT-NEXT: B %bb.1
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: bb.1:
+ ; CHECK-DATA-DEPENDENT-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[LDRWui]], 100, 0, implicit-def $nzcv
+ ; CHECK-DATA-DEPENDENT-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-DATA-DEPENDENT-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-DATA-DEPENDENT-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY1]], [[MADDWrrr1]], 12, implicit $nzcv
+ ; CHECK-DATA-DEPENDENT-NEXT: $w0 = COPY [[CSELWr]]
+ ; CHECK-DATA-DEPENDENT-NEXT: RET_ReallyLR implicit $w0
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $x0, $w1, $w2
+
+ %0:gpr64common = COPY $x0
+ %1:gpr32 = COPY $w1
+ %2:gpr32 = COPY $w2
+ %3:gpr32common = LDRWui %0, 0 :: (load (s32))
+ B %bb.1
+
+ bb.1:
+ successors: %bb.2(0x40000000), %bb.3(0x40000000)
+
+ %4:gpr32 = SUBSWri %3, 100, 0, implicit-def $nzcv
+ Bcc 12, %bb.3, implicit $nzcv
+ B %bb.2
+
+ bb.2:
+ successors: %bb.3(0x80000000)
+
+ %5:gpr32 = MADDWrrr %1, %2, $wzr
+ %6:gpr32 = MADDWrrr %5, %1, $wzr
+
+ bb.3:
+ %7:gpr32 = PHI %1, %bb.1, %6, %bb.2
+ $w0 = COPY %7
+ RET_ReallyLR implicit $w0
+...
+---
+name: load_cond_and_branch_pred_bb_with_call
+alignment: 4
+tracksRegLiveness: true
+body: |
+ ; CHECK-COMMON-LABEL: name: load_cond_and_branch_pred_bb_with_call
+ ; CHECK-COMMON: bb.0:
+ ; CHECK-COMMON-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-COMMON-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-COMMON-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-COMMON-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-COMMON-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-COMMON-NEXT: BL &foo, implicit-def $lr
+ ; CHECK-COMMON-NEXT: B %bb.1
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.1:
+ ; CHECK-COMMON-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[LDRWui]], 100, 0, implicit-def $nzcv
+ ; CHECK-COMMON-NEXT: Bcc 12, %bb.3, implicit $nzcv
+ ; CHECK-COMMON-NEXT: B %bb.2
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.2:
+ ; CHECK-COMMON-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-COMMON-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.3:
+ ; CHECK-COMMON-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[MADDWrrr1]], %bb.2
+ ; CHECK-COMMON-NEXT: $w0 = COPY [[PHI]]
+ ; CHECK-COMMON-NEXT: RET_ReallyLR implicit $w0
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $x0, $w1, $w2
+
+ %0:gpr64common = COPY $x0
+ %1:gpr32 = COPY $w1
+ %2:gpr32 = COPY $w2
+ %3:gpr32common = LDRWui %0, 0 :: (load (s32))
+ BL &foo, implicit-def $lr
+ B %bb.1
+
+ bb.1:
+ successors: %bb.2(0x40000000), %bb.3(0x40000000)
+
+ %4:gpr32 = SUBSWri %3, 100, 0, implicit-def $nzcv
+ Bcc 12, %bb.3, implicit $nzcv
+ B %bb.2
+
+ bb.2:
+ successors: %bb.3(0x80000000)
+
+ %5:gpr32 = MADDWrrr %1, %2, $wzr
+ %6:gpr32 = MADDWrrr %5, %1, $wzr
+
+ bb.3:
+ %7:gpr32 = PHI %1, %bb.1, %6, %bb.2
+ $w0 = COPY %7
+ RET_ReallyLR implicit $w0
+...
+---
+name: load_in_pred_call_in_head
+alignment: 4
+tracksRegLiveness: true
+body: |
+ ; CHECK-COMMON-LABEL: name: load_in_pred_call_in_head
+ ; CHECK-COMMON: bb.0:
+ ; CHECK-COMMON-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-COMMON-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-COMMON-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-COMMON-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-COMMON-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-COMMON-NEXT: B %bb.1
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.1:
+ ; CHECK-COMMON-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: BL &foo, implicit-def $lr
+ ; CHECK-COMMON-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[LDRWui]], 100, 0, implicit-def $nzcv
+ ; CHECK-COMMON-NEXT: Bcc 12, %bb.3, implicit $nzcv
+ ; CHECK-COMMON-NEXT: B %bb.2
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.2:
+ ; CHECK-COMMON-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-COMMON-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.3:
+ ; CHECK-COMMON-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[MADDWrrr1]], %bb.2
+ ; CHECK-COMMON-NEXT: $w0 = COPY [[PHI]]
+ ; CHECK-COMMON-NEXT: RET_ReallyLR implicit $w0
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $x0, $w1, $w2
+
+ %0:gpr64common = COPY $x0
+ %1:gpr32 = COPY $w1
+ %2:gpr32 = COPY $w2
+ %3:gpr32common = LDRWui %0, 0 :: (load (s32))
+ B %bb.1
+
+ bb.1:
+ successors: %bb.2(0x40000000), %bb.3(0x40000000)
+
+ BL &foo, implicit-def $lr
+ %4:gpr32 = SUBSWri %3, 100, 0, implicit-def $nzcv
+ Bcc 12, %bb.3, implicit $nzcv
+ B %bb.2
+
+ bb.2:
+ successors: %bb.3(0x80000000)
+
+ %5:gpr32 = MADDWrrr %1, %2, $wzr
+ %6:gpr32 = MADDWrrr %5, %1, $wzr
+
+ bb.3:
+ %7:gpr32 = PHI %1, %bb.1, %6, %bb.2
+ $w0 = COPY %7
+ RET_ReallyLR implicit $w0
+...
+---
+name: load_in_loop_not_immediate_pred
+alignment: 4
+tracksRegLiveness: true
+body: |
+ ; CHECK-DEFAULT-LABEL: name: load_in_loop_not_immediate_pred
+ ; CHECK-DEFAULT: bb.0:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-DEFAULT-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-DEFAULT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-DEFAULT-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.1:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.2:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[ADDWri:%[0-9]+]]:gpr32common = ADDWri [[LDRWui]], 1, 0
+ ; CHECK-DEFAULT-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[ADDWri]], 100, 0, implicit-def $nzcv
+ ; CHECK-DEFAULT-NEXT: Bcc 12, %bb.4, implicit $nzcv
+ ; CHECK-DEFAULT-NEXT: B %bb.3
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.3:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.4(0x80000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-DEFAULT-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.4:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.1(0x7c000000), %bb.5(0x04000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[PHI:%[0-9]+]]:gpr32sp = PHI [[COPY1]], %bb.2, [[MADDWrrr1]], %bb.3
+ ; CHECK-DEFAULT-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI]], 0, 0, implicit-def $nzcv
+ ; CHECK-DEFAULT-NEXT: Bcc 12, %bb.1, implicit $nzcv
+ ; CHECK-DEFAULT-NEXT: B %bb.5
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.5:
+ ; CHECK-DEFAULT-NEXT: $w0 = COPY [[PHI]]
+ ; CHECK-DEFAULT-NEXT: RET_ReallyLR implicit $w0
+ ;
+ ; CHECK-DATA-DEPENDENT-LABEL: name: load_in_loop_not_immediate_pred
+ ; CHECK-DATA-DEPENDENT: bb.0:
+ ; CHECK-DATA-DEPENDENT-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-DATA-DEPENDENT-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-DATA-DEPENDENT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-DATA-DEPENDENT-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: bb.1:
+ ; CHECK-DATA-DEPENDENT-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: bb.2:
+ ; CHECK-DATA-DEPENDENT-NEXT: successors: %bb.1(0x7c000000), %bb.5(0x04000000)
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: [[ADDWri:%[0-9]+]]:gpr32common = ADDWri [[LDRWui]], 1, 0
+ ; CHECK-DATA-DEPENDENT-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[ADDWri]], 100, 0, implicit-def $nzcv
+ ; CHECK-DATA-DEPENDENT-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-DATA-DEPENDENT-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-DATA-DEPENDENT-NEXT: [[CSELWr:%[0-9]+]]:gpr32common = CSELWr [[COPY1]], [[MADDWrrr1]], 12, implicit $nzcv
+ ; CHECK-DATA-DEPENDENT-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[CSELWr]], 0, 0, implicit-def $nzcv
+ ; CHECK-DATA-DEPENDENT-NEXT: Bcc 12, %bb.1, implicit $nzcv
+ ; CHECK-DATA-DEPENDENT-NEXT: B %bb.5
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: bb.5:
+ ; CHECK-DATA-DEPENDENT-NEXT: $w0 = COPY [[CSELWr]]
+ ; CHECK-DATA-DEPENDENT-NEXT: RET_ReallyLR implicit $w0
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $x0, $w1, $w2
+
+ %0:gpr64common = COPY $x0
+ %1:gpr32 = COPY $w1
+ %2:gpr32 = COPY $w2
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ %3:gpr32common = LDRWui %0, 0 :: (load (s32))
+
+ bb.2:
+ successors: %bb.3(0x40000000), %bb.4(0x40000000)
+
+ %4:gpr32common = ADDWri %3, 1, 0
+ %5:gpr32 = SUBSWri %4, 100, 0, implicit-def $nzcv
+ Bcc 12, %bb.4, implicit $nzcv
+ B %bb.3
+
+ bb.3:
+ successors: %bb.4(0x80000000)
+
+ %6:gpr32 = MADDWrrr %1, %2, $wzr
+ %7:gpr32 = MADDWrrr %6, %1, $wzr
+
+ bb.4:
+ successors: %bb.1(0x7c000000), %bb.5(0x04000000)
+
+ %8:gpr32sp = PHI %1, %bb.2, %7, %bb.3
+ %9:gpr32 = SUBSWri %8, 0, 0, implicit-def $nzcv
+ Bcc 12, %bb.1, implicit $nzcv
+ B %bb.5
+
+ bb.5:
+ $w0 = COPY %8
+ RET_ReallyLR implicit $w0
+...
+---
+name: load_in_loop_call_in_intermediate_block
+alignment: 4
+tracksRegLiveness: true
+body: |
+ ; CHECK-COMMON-LABEL: name: load_in_loop_call_in_intermediate_block
+ ; CHECK-COMMON: bb.0:
+ ; CHECK-COMMON-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-COMMON-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-COMMON-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-COMMON-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.1:
+ ; CHECK-COMMON-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.2:
+ ; CHECK-COMMON-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: BL &foo, implicit-def $lr
+ ; CHECK-COMMON-NEXT: [[ADDWri:%[0-9]+]]:gpr32common = ADDWri [[LDRWui]], 1, 0
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.3:
+ ; CHECK-COMMON-NEXT: successors: %bb.4(0x40000000), %bb.5(0x40000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[ADDWri]], 100, 0, implicit-def $nzcv
+ ; CHECK-COMMON-NEXT: Bcc 12, %bb.5, implicit $nzcv
+ ; CHECK-COMMON-NEXT: B %bb.4
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.4:
+ ; CHECK-COMMON-NEXT: successors: %bb.5(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-COMMON-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.5:
+ ; CHECK-COMMON-NEXT: successors: %bb.1(0x7c000000), %bb.6(0x04000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[PHI:%[0-9]+]]:gpr32sp = PHI [[COPY1]], %bb.3, [[MADDWrrr1]], %bb.4
+ ; CHECK-COMMON-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI]], 0, 0, implicit-def $nzcv
+ ; CHECK-COMMON-NEXT: Bcc 12, %bb.1, implicit $nzcv
+ ; CHECK-COMMON-NEXT: B %bb.6
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.6:
+ ; CHECK-COMMON-NEXT: $w0 = COPY [[PHI]]
+ ; CHECK-COMMON-NEXT: RET_ReallyLR implicit $w0
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $x0, $w1, $w2
+
+ %0:gpr64common = COPY $x0
+ %1:gpr32 = COPY $w1
+ %2:gpr32 = COPY $w2
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ %3:gpr32common = LDRWui %0, 0 :: (load (s32))
+
+ bb.2:
+ successors: %bb.3(0x80000000)
+
+ BL &foo, implicit-def $lr
+ %4:gpr32common = ADDWri %3, 1, 0
+
+ bb.3:
+ successors: %bb.4(0x40000000), %bb.5(0x40000000)
+
+ %5:gpr32 = SUBSWri %4, 100, 0, implicit-def $nzcv
+ Bcc 12, %bb.5, implicit $nzcv
+ B %bb.4
+
+ bb.4:
+ successors: %bb.5(0x80000000)
+
+ %6:gpr32 = MADDWrrr %1, %2, $wzr
+ %7:gpr32 = MADDWrrr %6, %1, $wzr
+
+ bb.5:
+ successors: %bb.1(0x7c000000), %bb.6(0x04000000)
+
+ %8:gpr32sp = PHI %1, %bb.3, %7, %bb.4
+ %9:gpr32 = SUBSWri %8, 0, 0, implicit-def $nzcv
+ Bcc 12, %bb.1, implicit $nzcv
+ B %bb.6
+
+ bb.6:
+ $w0 = COPY %8
+ RET_ReallyLR implicit $w0
+...
+---
+name: load_to_cond_in_backedge
+alignment: 4
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr64sp }
+ - { id: 1, class: gpr32 }
+ - { id: 2, class: gpr32 }
+ - { id: 3, class: gpr64 }
+ - { id: 4, class: gpr32 }
+ - { id: 5, class: gpr32all }
+ - { id: 6, class: gpr32 }
+body: |
+ ; CHECK-COMMON-LABEL: name: load_to_cond_in_backedge
+ ; CHECK-COMMON: bb.0:
+ ; CHECK-COMMON-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-COMMON-NEXT: liveins: $x0
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK-COMMON-NEXT: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
+ ; CHECK-COMMON-NEXT: B %bb.1
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.1:
+ ; CHECK-COMMON-NEXT: successors: %bb.5(0x04000000), %bb.1(0x7c000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI undef [[DEF]], %bb.0, %5, %bb.1
+ ; CHECK-COMMON-NEXT: [[LDRHHroW:%[0-9]+]]:gpr32 = LDRHHroW undef [[COPY]], undef [[PHI]], 0, 1 :: (load (s16))
+ ; CHECK-COMMON-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHroW]]
+ ; CHECK-COMMON-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
+ ; CHECK-COMMON-NEXT: Bcc 1, %bb.1, implicit undef $nzcv
+ ; CHECK-COMMON-NEXT: B %bb.5
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.5:
+ ; CHECK-COMMON-NEXT: RET_ReallyLR
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $x0
+
+ %0:gpr64sp = COPY $x0
+ %1:gpr32 = IMPLICIT_DEF
+ B %bb.1
+
+ bb.1:
+ successors: %bb.2(0x40000000), %bb.3(0x40000000)
+
+ %2:gpr32 = PHI undef %1, %bb.0, %5, %bb.4
+ %4:gpr32 = LDRHHroW undef %0, undef %2, 0, 1 :: (load (s16))
+ %5:gpr32all = COPY %4
+ TBNZW undef %2, 0, %bb.3
+ B %bb.2
+
+ bb.2:
+ successors: %bb.4(0x80000000)
+
+ B %bb.4
+
+ bb.3:
+ successors: %bb.4(0x80000000)
+
+ bb.4:
+ successors: %bb.5(0x04000000), %bb.1(0x7c000000)
+
+ %6:gpr32 = PHI undef %5, %bb.3, undef %5, %bb.2
+ Bcc 1, %bb.1, implicit undef $nzcv
+ B %bb.5
+
+ bb.5:
+ RET_ReallyLR
+...
+---
+name: load_in_pred_call_in_empty_intermediate_block
+alignment: 4
+tracksRegLiveness: true
+body: |
+ ; CHECK-COMMON-LABEL: name: load_in_pred_call_in_empty_intermediate_block
+ ; CHECK-COMMON: bb.0:
+ ; CHECK-COMMON-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-COMMON-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-COMMON-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-COMMON-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.1:
+ ; CHECK-COMMON-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.2:
+ ; CHECK-COMMON-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: BL &foo, implicit-def $lr
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.3:
+ ; CHECK-COMMON-NEXT: successors: %bb.4(0x40000000), %bb.5(0x40000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[ADDWri:%[0-9]+]]:gpr32common = ADDWri [[LDRWui]], 1, 0
+ ; CHECK-COMMON-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[ADDWri]], 100, 0, implicit-def $nzcv
+ ; CHECK-COMMON-NEXT: Bcc 12, %bb.5, implicit $nzcv
+ ; CHECK-COMMON-NEXT: B %bb.4
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.4:
+ ; CHECK-COMMON-NEXT: successors: %bb.5(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-COMMON-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.5:
+ ; CHECK-COMMON-NEXT: successors: %bb.6(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[PHI:%[0-9]+]]:gpr32sp = PHI [[COPY1]], %bb.3, [[MADDWrrr1]], %bb.4
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.6:
+ ; CHECK-COMMON-NEXT: $w0 = COPY [[PHI]]
+ ; CHECK-COMMON-NEXT: RET_ReallyLR implicit $w0
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $x0, $w1, $w2
+
+ %0:gpr64common = COPY $x0
+ %1:gpr32 = COPY $w1
+ %2:gpr32 = COPY $w2
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ %3:gpr32common = LDRWui %0, 0 :: (load (s32))
+
+ bb.2:
+ successors: %bb.3(0x80000000)
+
+ BL &foo, implicit-def $lr
+
+ bb.3:
+ successors: %bb.4(0x40000000), %bb.5(0x40000000)
+
+ %4:gpr32common = ADDWri %3, 1, 0
+ %5:gpr32 = SUBSWri %4, 100, 0, implicit-def $nzcv
+ Bcc 12, %bb.5, implicit $nzcv
+ B %bb.4
+
+ bb.4:
+ successors: %bb.5(0x80000000)
+
+ %6:gpr32 = MADDWrrr %1, %2, $wzr
+ %7:gpr32 = MADDWrrr %6, %1, $wzr
+
+ bb.5:
+ successors: %bb.6(0x80000000)
+
+ %8:gpr32sp = PHI %1, %bb.3, %7, %bb.4
+
+ bb.6:
+ $w0 = COPY %8
+ RET_ReallyLR implicit $w0
+...
+---
+name: load_in_pred_diamond_call_in_one_arm
+alignment: 4
+tracksRegLiveness: true
+body: |
+ ; CHECK-COMMON-LABEL: name: load_in_pred_diamond_call_in_one_arm
+ ; CHECK-COMMON: bb.0:
+ ; CHECK-COMMON-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-COMMON-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-COMMON-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-COMMON-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.1:
+ ; CHECK-COMMON-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-COMMON-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[LDRWui]], 0, 0, implicit-def $nzcv
+ ; CHECK-COMMON-NEXT: Bcc 0, %bb.2, implicit $nzcv
+ ; CHECK-COMMON-NEXT: B %bb.3
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.2:
+ ; CHECK-COMMON-NEXT: successors: %bb.4(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: BL &foo, implicit-def $lr
+ ; CHECK-COMMON-NEXT: B %bb.4
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.3:
+ ; CHECK-COMMON-NEXT: successors: %bb.4(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: B %bb.4
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.4:
+ ; CHECK-COMMON-NEXT: successors: %bb.5(0x40000000), %bb.6(0x40000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[ADDWri:%[0-9]+]]:gpr32common = ADDWri [[LDRWui]], 1, 0
+ ; CHECK-COMMON-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[ADDWri]], 100, 0, implicit-def $nzcv
+ ; CHECK-COMMON-NEXT: Bcc 12, %bb.6, implicit $nzcv
+ ; CHECK-COMMON-NEXT: B %bb.5
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.5:
+ ; CHECK-COMMON-NEXT: successors: %bb.6(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-COMMON-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.6:
+ ; CHECK-COMMON-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.4, [[MADDWrrr1]], %bb.5
+ ; CHECK-COMMON-NEXT: $w0 = COPY [[PHI]]
+ ; CHECK-COMMON-NEXT: RET_ReallyLR implicit $w0
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $x0, $w1, $w2
+
+ %0:gpr64common = COPY $x0
+ %1:gpr32 = COPY $w1
+ %2:gpr32 = COPY $w2
+
+ bb.1:
+ successors: %bb.2(0x40000000), %bb.3(0x40000000)
+
+ %3:gpr32common = LDRWui %0, 0 :: (load (s32))
+ %10:gpr32 = SUBSWri %3, 0, 0, implicit-def $nzcv
+ Bcc 0, %bb.2, implicit $nzcv
+ B %bb.3
+
+ bb.2:
+ successors: %bb.4(0x80000000)
+
+ BL &foo, implicit-def $lr
+ B %bb.4
+
+ bb.3:
+ successors: %bb.4(0x80000000)
+
+ B %bb.4
+
+ bb.4:
+ successors: %bb.5(0x40000000), %bb.6(0x40000000)
+
+ %4:gpr32common = ADDWri %3, 1, 0
+ %5:gpr32 = SUBSWri %4, 100, 0, implicit-def $nzcv
+ Bcc 12, %bb.6, implicit $nzcv
+ B %bb.5
+
+ bb.5:
+ successors: %bb.6(0x80000000)
+
+ %6:gpr32 = MADDWrrr %1, %2, $wzr
+ %7:gpr32 = MADDWrrr %6, %1, $wzr
+
+ bb.6:
+ %8:gpr32 = PHI %1, %bb.4, %7, %bb.5
+ $w0 = COPY %8
+ RET_ReallyLR implicit $w0
+...
+---
+name: load_in_pred_call_on_unreachable_path
+alignment: 4
+tracksRegLiveness: true
+body: |
+ ; CHECK-DEFAULT-LABEL: name: load_in_pred_call_on_unreachable_path
+ ; CHECK-DEFAULT: bb.0:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-DEFAULT-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-DEFAULT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-DEFAULT-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.1:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-DEFAULT-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[LDRWui]], 0, 0, implicit-def $nzcv
+ ; CHECK-DEFAULT-NEXT: Bcc 0, %bb.2, implicit $nzcv
+ ; CHECK-DEFAULT-NEXT: B %bb.3
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.2:
+ ; CHECK-DEFAULT-NEXT: successors:
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: BL &foo, implicit-def $lr
+ ; CHECK-DEFAULT-NEXT: BRK 1
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.3:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.4(0x40000000), %bb.5(0x40000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[ADDWri:%[0-9]+]]:gpr32common = ADDWri [[LDRWui]], 1, 0
+ ; CHECK-DEFAULT-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[ADDWri]], 100, 0, implicit-def $nzcv
+ ; CHECK-DEFAULT-NEXT: Bcc 12, %bb.5, implicit $nzcv
+ ; CHECK-DEFAULT-NEXT: B %bb.4
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.4:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.5(0x80000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-DEFAULT-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.5:
+ ; CHECK-DEFAULT-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.3, [[MADDWrrr1]], %bb.4
+ ; CHECK-DEFAULT-NEXT: $w0 = COPY [[PHI]]
+ ; CHECK-DEFAULT-NEXT: RET_ReallyLR implicit $w0
+ ;
+ ; CHECK-DATA-DEPENDENT-LABEL: name: load_in_pred_call_on_unreachable_path
+ ; CHECK-DATA-DEPENDENT: bb.0:
+ ; CHECK-DATA-DEPENDENT-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-DATA-DEPENDENT-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-DATA-DEPENDENT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-DATA-DEPENDENT-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: bb.1:
+ ; CHECK-DATA-DEPENDENT-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-DATA-DEPENDENT-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[LDRWui]], 0, 0, implicit-def $nzcv
+ ; CHECK-DATA-DEPENDENT-NEXT: Bcc 0, %bb.2, implicit $nzcv
+ ; CHECK-DATA-DEPENDENT-NEXT: B %bb.3
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: bb.2:
+ ; CHECK-DATA-DEPENDENT-NEXT: successors:
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: BL &foo, implicit-def $lr
+ ; CHECK-DATA-DEPENDENT-NEXT: BRK 1
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: bb.3:
+ ; CHECK-DATA-DEPENDENT-NEXT: [[ADDWri:%[0-9]+]]:gpr32common = ADDWri [[LDRWui]], 1, 0
+ ; CHECK-DATA-DEPENDENT-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[ADDWri]], 100, 0, implicit-def $nzcv
+ ; CHECK-DATA-DEPENDENT-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-DATA-DEPENDENT-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-DATA-DEPENDENT-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY1]], [[MADDWrrr1]], 12, implicit $nzcv
+ ; CHECK-DATA-DEPENDENT-NEXT: $w0 = COPY [[CSELWr]]
+ ; CHECK-DATA-DEPENDENT-NEXT: RET_ReallyLR implicit $w0
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $x0, $w1, $w2
+
+ %0:gpr64common = COPY $x0
+ %1:gpr32 = COPY $w1
+ %2:gpr32 = COPY $w2
+
+ bb.1:
+ successors: %bb.2(0x40000000), %bb.3(0x40000000)
+
+ %3:gpr32common = LDRWui %0, 0 :: (load (s32))
+ %10:gpr32 = SUBSWri %3, 0, 0, implicit-def $nzcv
+ Bcc 0, %bb.2, implicit $nzcv
+ B %bb.3
+
+ bb.2:
+ successors:
+
+ BL &foo, implicit-def $lr
+ BRK 1
+
+ bb.3:
+ successors: %bb.4(0x40000000), %bb.5(0x40000000)
+
+ %4:gpr32common = ADDWri %3, 1, 0
+ %5:gpr32 = SUBSWri %4, 100, 0, implicit-def $nzcv
+ Bcc 12, %bb.5, implicit $nzcv
+ B %bb.4
+
+ bb.4:
+ successors: %bb.5(0x80000000)
+
+ %6:gpr32 = MADDWrrr %1, %2, $wzr
+ %7:gpr32 = MADDWrrr %6, %1, $wzr
+
+ bb.5:
+ %8:gpr32 = PHI %1, %bb.3, %7, %bb.4
+ $w0 = COPY %8
+ RET_ReallyLR implicit $w0
+...
+---
+name: call_in_block_with_early_exit_before_condition
+alignment: 4
+tracksRegLiveness: true
+body: |
+ ; CHECK-COMMON-LABEL: name: call_in_block_with_early_exit_before_condition
+ ; CHECK-COMMON: bb.0:
+ ; CHECK-COMMON-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-COMMON-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-COMMON-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-COMMON-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-COMMON-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.1:
+ ; CHECK-COMMON-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: BL &foo, implicit-def $lr
+ ; CHECK-COMMON-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY1]], [[COPY2]], implicit-def $nzcv
+ ; CHECK-COMMON-NEXT: Bcc 0, %bb.2, implicit $nzcv
+ ; CHECK-COMMON-NEXT: B %bb.3
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.2:
+ ; CHECK-COMMON-NEXT: $w0 = COPY [[COPY1]]
+ ; CHECK-COMMON-NEXT: RET_ReallyLR implicit $w0
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.3:
+ ; CHECK-COMMON-NEXT: successors: %bb.4(0x40000000), %bb.5(0x40000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[ADDWri:%[0-9]+]]:gpr32common = ADDWri [[LDRWui]], 1, 0
+ ; CHECK-COMMON-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[ADDWri]], 100, 0, implicit-def $nzcv
+ ; CHECK-COMMON-NEXT: Bcc 12, %bb.5, implicit $nzcv
+ ; CHECK-COMMON-NEXT: B %bb.4
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.4:
+ ; CHECK-COMMON-NEXT: successors: %bb.5(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-COMMON-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.5:
+ ; CHECK-COMMON-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.3, [[MADDWrrr1]], %bb.4
+ ; CHECK-COMMON-NEXT: $w0 = COPY [[PHI]]
+ ; CHECK-COMMON-NEXT: RET_ReallyLR implicit $w0
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $x0, $w1, $w2
+
+ %0:gpr64common = COPY $x0
+ %1:gpr32 = COPY $w1
+ %2:gpr32 = COPY $w2
+ %3:gpr32common = LDRWui %0, 0 :: (load (s32))
+
+ bb.1:
+ successors: %bb.2(0x40000000), %bb.3(0x40000000)
+
+ BL &foo, implicit-def $lr
+ %10:gpr32 = SUBSWrr %1, %2, implicit-def $nzcv
+ Bcc 0, %bb.2, implicit $nzcv
+ B %bb.3
+
+ bb.2:
+ $w0 = COPY %1
+ RET_ReallyLR implicit $w0
+
+ bb.3:
+ successors: %bb.4(0x40000000), %bb.5(0x40000000)
+
+ %4:gpr32common = ADDWri %3, 1, 0
+ %5:gpr32 = SUBSWri %4, 100, 0, implicit-def $nzcv
+ Bcc 12, %bb.5, implicit $nzcv
+ B %bb.4
+
+ bb.4:
+ successors: %bb.5(0x80000000)
+
+ %6:gpr32 = MADDWrrr %1, %2, $wzr
+ %7:gpr32 = MADDWrrr %6, %1, $wzr
+
+ bb.5:
+ %8:gpr32 = PHI %1, %bb.3, %7, %bb.4
+ $w0 = COPY %8
+ RET_ReallyLR implicit $w0
+...
+---
+name: call_in_block_before_load
+alignment: 4
+tracksRegLiveness: true
+body: |
+ ; CHECK-DEFAULT-LABEL: name: call_in_block_before_load
+ ; CHECK-DEFAULT: bb.0:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-DEFAULT-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-DEFAULT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-DEFAULT-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-DEFAULT-NEXT: BL &foo, implicit-def $lr
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.1:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.2:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[LDRWui]], 100, 0, implicit-def $nzcv
+ ; CHECK-DEFAULT-NEXT: Bcc 12, %bb.4, implicit $nzcv
+ ; CHECK-DEFAULT-NEXT: B %bb.3
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.3:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.4(0x80000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-DEFAULT-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.4:
+ ; CHECK-DEFAULT-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.2, [[MADDWrrr1]], %bb.3
+ ; CHECK-DEFAULT-NEXT: $w0 = COPY [[PHI]]
+ ; CHECK-DEFAULT-NEXT: RET_ReallyLR implicit $w0
+ ;
+ ; CHECK-DATA-DEPENDENT-LABEL: name: call_in_block_before_load
+ ; CHECK-DATA-DEPENDENT: bb.0:
+ ; CHECK-DATA-DEPENDENT-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-DATA-DEPENDENT-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-DATA-DEPENDENT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-DATA-DEPENDENT-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-DATA-DEPENDENT-NEXT: BL &foo, implicit-def $lr
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: bb.1:
+ ; CHECK-DATA-DEPENDENT-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: bb.2:
+ ; CHECK-DATA-DEPENDENT-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[LDRWui]], 100, 0, implicit-def $nzcv
+ ; CHECK-DATA-DEPENDENT-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-DATA-DEPENDENT-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-DATA-DEPENDENT-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY1]], [[MADDWrrr1]], 12, implicit $nzcv
+ ; CHECK-DATA-DEPENDENT-NEXT: $w0 = COPY [[CSELWr]]
+ ; CHECK-DATA-DEPENDENT-NEXT: RET_ReallyLR implicit $w0
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $x0, $w1, $w2
+
+ %0:gpr64common = COPY $x0
+ %1:gpr32 = COPY $w1
+ %2:gpr32 = COPY $w2
+ BL &foo, implicit-def $lr
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ %3:gpr32common = LDRWui %0, 0 :: (load (s32))
+
+ bb.2:
+ successors: %bb.3(0x40000000), %bb.4(0x40000000)
+
+ %4:gpr32 = SUBSWri %3, 100, 0, implicit-def $nzcv
+ Bcc 12, %bb.4, implicit $nzcv
+ B %bb.3
+
+ bb.3:
+ successors: %bb.4(0x80000000)
+
+ %5:gpr32 = MADDWrrr %1, %2, $wzr
+ %6:gpr32 = MADDWrrr %5, %1, $wzr
+
+ bb.4:
+ %7:gpr32 = PHI %1, %bb.2, %6, %bb.3
+ $w0 = COPY %7
+ RET_ReallyLR implicit $w0
+...
+---
+name: load_in_pred_call_in_block_behind_load
+alignment: 4
+tracksRegLiveness: true
+body: |
+ ; CHECK-DEFAULT-LABEL: name: load_in_pred_call_in_block_behind_load
+ ; CHECK-DEFAULT: bb.0:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-DEFAULT-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-DEFAULT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-DEFAULT-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-DEFAULT-NEXT: B %bb.1
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.1:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: B %bb.2
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.2:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-DEFAULT-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY1]], [[COPY2]], implicit-def $nzcv
+ ; CHECK-DEFAULT-NEXT: Bcc 0, %bb.3, implicit $nzcv
+ ; CHECK-DEFAULT-NEXT: B %bb.4
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.3:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: BL &foo, implicit-def $lr
+ ; CHECK-DEFAULT-NEXT: B %bb.1
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.4:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.5(0x40000000), %bb.6(0x40000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[ADDWri:%[0-9]+]]:gpr32common = ADDWri [[LDRWui]], 1, 0
+ ; CHECK-DEFAULT-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[ADDWri]], 100, 0, implicit-def $nzcv
+ ; CHECK-DEFAULT-NEXT: Bcc 12, %bb.6, implicit $nzcv
+ ; CHECK-DEFAULT-NEXT: B %bb.5
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.5:
+ ; CHECK-DEFAULT-NEXT: successors: %bb.6(0x80000000)
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-DEFAULT-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-DEFAULT-NEXT: {{ $}}
+ ; CHECK-DEFAULT-NEXT: bb.6:
+ ; CHECK-DEFAULT-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.4, [[MADDWrrr1]], %bb.5
+ ; CHECK-DEFAULT-NEXT: $w0 = COPY [[PHI]]
+ ; CHECK-DEFAULT-NEXT: RET_ReallyLR implicit $w0
+ ;
+ ; CHECK-DATA-DEPENDENT-LABEL: name: load_in_pred_call_in_block_behind_load
+ ; CHECK-DATA-DEPENDENT: bb.0:
+ ; CHECK-DATA-DEPENDENT-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-DATA-DEPENDENT-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-DATA-DEPENDENT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-DATA-DEPENDENT-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-DATA-DEPENDENT-NEXT: B %bb.1
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: bb.1:
+ ; CHECK-DATA-DEPENDENT-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: B %bb.2
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: bb.2:
+ ; CHECK-DATA-DEPENDENT-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-DATA-DEPENDENT-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY1]], [[COPY2]], implicit-def $nzcv
+ ; CHECK-DATA-DEPENDENT-NEXT: Bcc 0, %bb.3, implicit $nzcv
+ ; CHECK-DATA-DEPENDENT-NEXT: B %bb.4
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: bb.3:
+ ; CHECK-DATA-DEPENDENT-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: BL &foo, implicit-def $lr
+ ; CHECK-DATA-DEPENDENT-NEXT: B %bb.1
+ ; CHECK-DATA-DEPENDENT-NEXT: {{ $}}
+ ; CHECK-DATA-DEPENDENT-NEXT: bb.4:
+ ; CHECK-DATA-DEPENDENT-NEXT: [[ADDWri:%[0-9]+]]:gpr32common = ADDWri [[LDRWui]], 1, 0
+ ; CHECK-DATA-DEPENDENT-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[ADDWri]], 100, 0, implicit-def $nzcv
+ ; CHECK-DATA-DEPENDENT-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-DATA-DEPENDENT-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-DATA-DEPENDENT-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY1]], [[MADDWrrr1]], 12, implicit $nzcv
+ ; CHECK-DATA-DEPENDENT-NEXT: $w0 = COPY [[CSELWr]]
+ ; CHECK-DATA-DEPENDENT-NEXT: RET_ReallyLR implicit $w0
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $x0, $w1, $w2
+
+ %0:gpr64common = COPY $x0
+ %1:gpr32 = COPY $w1
+ %2:gpr32 = COPY $w2
+ B %bb.1
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ B %bb.2
+
+ bb.2:
+ successors: %bb.3(0x40000000), %bb.4(0x40000000)
+
+ %3:gpr32common = LDRWui %0, 0 :: (load (s32))
+ %10:gpr32 = SUBSWrr %1, %2, implicit-def $nzcv
+ Bcc 0, %bb.3, implicit $nzcv
+ B %bb.4
+
+ bb.3:
+ successors: %bb.1(0x80000000)
+
+ BL &foo, implicit-def $lr
+ B %bb.1
+
+ bb.4:
+ successors: %bb.5(0x40000000), %bb.6(0x40000000)
+
+ %4:gpr32common = ADDWri %3, 1, 0
+ %5:gpr32 = SUBSWri %4, 100, 0, implicit-def $nzcv
+ Bcc 12, %bb.6, implicit $nzcv
+ B %bb.5
+
+ bb.5:
+ successors: %bb.6(0x80000000)
+
+ %6:gpr32 = MADDWrrr %1, %2, $wzr
+ %7:gpr32 = MADDWrrr %6, %1, $wzr
+
+ bb.6:
+ %8:gpr32 = PHI %1, %bb.4, %7, %bb.5
+ $w0 = COPY %8
+ RET_ReallyLR implicit $w0
+...
+---
+name: load_in_pred_call_in_chained_diamond_arm
+alignment: 4
+tracksRegLiveness: true
+body: |
+ ; CHECK-COMMON-LABEL: name: load_in_pred_call_in_chained_diamond_arm
+ ; CHECK-COMMON: bb.0:
+ ; CHECK-COMMON-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-COMMON-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-COMMON-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-COMMON-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.1:
+ ; CHECK-COMMON-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-COMMON-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[LDRWui]], 0, 0, implicit-def $nzcv
+ ; CHECK-COMMON-NEXT: Bcc 0, %bb.2, implicit $nzcv
+ ; CHECK-COMMON-NEXT: B %bb.3
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.2:
+ ; CHECK-COMMON-NEXT: successors: %bb.4(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: B %bb.4
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.3:
+ ; CHECK-COMMON-NEXT: successors: %bb.4(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: B %bb.4
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.4:
+ ; CHECK-COMMON-NEXT: successors: %bb.5(0x40000000), %bb.6(0x40000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY1]], [[COPY2]], implicit-def $nzcv
+ ; CHECK-COMMON-NEXT: Bcc 0, %bb.5, implicit $nzcv
+ ; CHECK-COMMON-NEXT: B %bb.6
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.5:
+ ; CHECK-COMMON-NEXT: successors: %bb.7(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: BL &foo, implicit-def $lr
+ ; CHECK-COMMON-NEXT: B %bb.7
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.6:
+ ; CHECK-COMMON-NEXT: successors: %bb.7(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: B %bb.7
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.7:
+ ; CHECK-COMMON-NEXT: successors: %bb.8(0x40000000), %bb.9(0x40000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[ADDWri:%[0-9]+]]:gpr32common = ADDWri [[LDRWui]], 1, 0
+ ; CHECK-COMMON-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[ADDWri]], 100, 0, implicit-def $nzcv
+ ; CHECK-COMMON-NEXT: Bcc 12, %bb.9, implicit $nzcv
+ ; CHECK-COMMON-NEXT: B %bb.8
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.8:
+ ; CHECK-COMMON-NEXT: successors: %bb.9(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-COMMON-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.9:
+ ; CHECK-COMMON-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.7, [[MADDWrrr1]], %bb.8
+ ; CHECK-COMMON-NEXT: $w0 = COPY [[PHI]]
+ ; CHECK-COMMON-NEXT: RET_ReallyLR implicit $w0
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $x0, $w1, $w2
+
+ %0:gpr64common = COPY $x0
+ %1:gpr32 = COPY $w1
+ %2:gpr32 = COPY $w2
+
+ bb.1:
+ successors: %bb.2(0x40000000), %bb.3(0x40000000)
+
+ %3:gpr32common = LDRWui %0, 0 :: (load (s32))
+ %10:gpr32 = SUBSWri %3, 0, 0, implicit-def $nzcv
+ Bcc 0, %bb.2, implicit $nzcv
+ B %bb.3
+
+ bb.2:
+ successors: %bb.4(0x80000000)
+
+ B %bb.4
+
+ bb.3:
+ successors: %bb.4(0x80000000)
+
+ B %bb.4
+
+ bb.4:
+ successors: %bb.5(0x40000000), %bb.6(0x40000000)
+
+ %11:gpr32 = SUBSWrr %1, %2, implicit-def $nzcv
+ Bcc 0, %bb.5, implicit $nzcv
+ B %bb.6
+
+ bb.5:
+ successors: %bb.7(0x80000000)
+
+ BL &foo, implicit-def $lr
+ B %bb.7
+
+ bb.6:
+ successors: %bb.7(0x80000000)
+
+ B %bb.7
+
+ bb.7:
+ successors: %bb.8(0x40000000), %bb.9(0x40000000)
+
+ %4:gpr32common = ADDWri %3, 1, 0
+ %5:gpr32 = SUBSWri %4, 100, 0, implicit-def $nzcv
+ Bcc 12, %bb.9, implicit $nzcv
+ B %bb.8
+
+ bb.8:
+ successors: %bb.9(0x80000000)
+
+ %6:gpr32 = MADDWrrr %1, %2, $wzr
+ %7:gpr32 = MADDWrrr %6, %1, $wzr
+
+ bb.9:
+ %8:gpr32 = PHI %1, %bb.7, %7, %bb.8
+ $w0 = COPY %8
+ RET_ReallyLR implicit $w0
+...
+---
+name: call_between_load_and_cbz
+alignment: 4
+tracksRegLiveness: true
+body: |
+ ; CHECK-COMMON-LABEL: name: call_between_load_and_cbz
+ ; CHECK-COMMON: bb.0:
+ ; CHECK-COMMON-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-COMMON-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-COMMON-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-COMMON-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-COMMON-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-COMMON-NEXT: BL &foo, implicit-def $lr
+ ; CHECK-COMMON-NEXT: CBZW [[LDRWui]], %bb.2
+ ; CHECK-COMMON-NEXT: B %bb.1
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.1:
+ ; CHECK-COMMON-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-COMMON-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.2:
+ ; CHECK-COMMON-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.0, [[MADDWrrr1]], %bb.1
+ ; CHECK-COMMON-NEXT: $w0 = COPY [[PHI]]
+ ; CHECK-COMMON-NEXT: RET_ReallyLR implicit $w0
+ bb.0:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $x0, $w1, $w2
+
+ %0:gpr64common = COPY $x0
+ %1:gpr32 = COPY $w1
+ %2:gpr32 = COPY $w2
+ %3:gpr32 = LDRWui %0, 0 :: (load (s32))
+ BL &foo, implicit-def $lr
+ CBZW %3, %bb.2
+ B %bb.1
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ %4:gpr32 = MADDWrrr %1, %2, $wzr
+ %5:gpr32 = MADDWrrr %4, %1, $wzr
+
+ bb.2:
+ %6:gpr32 = PHI %1, %bb.0, %5, %bb.1
+ $w0 = COPY %6
+ RET_ReallyLR implicit $w0
+...
+---
+name: cbz_cond_def_in_pred_call_in_head
+alignment: 4
+tracksRegLiveness: true
+body: |
+ ; CHECK-COMMON-LABEL: name: cbz_cond_def_in_pred_call_in_head
+ ; CHECK-COMMON: bb.0:
+ ; CHECK-COMMON-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-COMMON-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-COMMON-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-COMMON-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-COMMON-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-COMMON-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[LDRWui]], [[LDRWui]], $wzr
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.1:
+ ; CHECK-COMMON-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: BL &foo, implicit-def $lr
+ ; CHECK-COMMON-NEXT: CBZW [[MADDWrrr]], %bb.3
+ ; CHECK-COMMON-NEXT: B %bb.2
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.2:
+ ; CHECK-COMMON-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-COMMON-NEXT: [[MADDWrrr2:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr1]], [[COPY1]], $wzr
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.3:
+ ; CHECK-COMMON-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[MADDWrrr2]], %bb.2
+ ; CHECK-COMMON-NEXT: $w0 = COPY [[PHI]]
+ ; CHECK-COMMON-NEXT: RET_ReallyLR implicit $w0
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $x0, $w1, $w2
+
+ %0:gpr64common = COPY $x0
+ %1:gpr32 = COPY $w1
+ %2:gpr32 = COPY $w2
+ %3:gpr32 = LDRWui %0, 0 :: (load (s32))
+ %4:gpr32 = MADDWrrr %3, %3, $wzr
+
+ bb.1:
+ successors: %bb.2(0x40000000), %bb.3(0x40000000)
+
+ BL &foo, implicit-def $lr
+ CBZW %4, %bb.3
+ B %bb.2
+
+ bb.2:
+ successors: %bb.3(0x80000000)
+
+ %5:gpr32 = MADDWrrr %1, %2, $wzr
+ %6:gpr32 = MADDWrrr %5, %1, $wzr
+
+ bb.3:
+ %7:gpr32 = PHI %1, %bb.1, %6, %bb.2
+ $w0 = COPY %7
+ RET_ReallyLR implicit $w0
+...
+---
+name: call_before_load_carried_by_phi
+alignment: 4
+tracksRegLiveness: true
+body: |
+ ; CHECK-COMMON-LABEL: name: call_before_load_carried_by_phi
+ ; CHECK-COMMON: bb.0:
+ ; CHECK-COMMON-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-COMMON-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-COMMON-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-COMMON-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.1:
+ ; CHECK-COMMON-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[PHI:%[0-9]+]]:gpr32common = PHI [[COPY1]], %bb.0, %4, %bb.5
+ ; CHECK-COMMON-NEXT: BL &foo, implicit-def $lr
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.2:
+ ; CHECK-COMMON-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.3:
+ ; CHECK-COMMON-NEXT: successors: %bb.4(0x40000000), %bb.5(0x40000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32common = MADDWrrr [[PHI]], [[PHI]], $wzr
+ ; CHECK-COMMON-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32common = MADDWrrr [[MADDWrrr]], [[MADDWrrr]], $wzr
+ ; CHECK-COMMON-NEXT: [[MADDWrrr2:%[0-9]+]]:gpr32common = MADDWrrr [[MADDWrrr1]], [[MADDWrrr1]], $wzr
+ ; CHECK-COMMON-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[MADDWrrr2]], 100, 0, implicit-def $nzcv
+ ; CHECK-COMMON-NEXT: Bcc 12, %bb.5, implicit $nzcv
+ ; CHECK-COMMON-NEXT: B %bb.4
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.4:
+ ; CHECK-COMMON-NEXT: successors: %bb.5(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[MADDWrrr3:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-COMMON-NEXT: [[MADDWrrr4:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr3]], [[COPY1]], $wzr
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.5:
+ ; CHECK-COMMON-NEXT: successors: %bb.1(0x7c000000), %bb.6(0x04000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[PHI1:%[0-9]+]]:gpr32sp = PHI [[COPY1]], %bb.3, [[MADDWrrr4]], %bb.4
+ ; CHECK-COMMON-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI1]], 0, 0, implicit-def $nzcv
+ ; CHECK-COMMON-NEXT: Bcc 12, %bb.1, implicit $nzcv
+ ; CHECK-COMMON-NEXT: B %bb.6
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.6:
+ ; CHECK-COMMON-NEXT: $w0 = COPY [[PHI1]]
+ ; CHECK-COMMON-NEXT: RET_ReallyLR implicit $w0
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $x0, $w1, $w2
+
+ %0:gpr64common = COPY $x0
+ %1:gpr32 = COPY $w1
+ %2:gpr32 = COPY $w2
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ %3:gpr32common = PHI %1, %bb.0, %4, %bb.5
+ BL &foo, implicit-def $lr
+
+ bb.2:
+ successors: %bb.3(0x80000000)
+
+ %4:gpr32common = LDRWui %0, 0 :: (load (s32))
+
+ bb.3:
+ successors: %bb.4(0x40000000), %bb.5(0x40000000)
+
+ %5:gpr32common = MADDWrrr %3, %3, $wzr
+ %6:gpr32common = MADDWrrr %5, %5, $wzr
+ %7:gpr32common = MADDWrrr %6, %6, $wzr
+ %8:gpr32 = SUBSWri %7, 100, 0, implicit-def $nzcv
+ Bcc 12, %bb.5, implicit $nzcv
+ B %bb.4
+
+ bb.4:
+ successors: %bb.5(0x80000000)
+
+ %9:gpr32 = MADDWrrr %1, %2, $wzr
+ %10:gpr32 = MADDWrrr %9, %1, $wzr
+
+ bb.5:
+ successors: %bb.1(0x7c000000), %bb.6(0x04000000)
+
+ %11:gpr32sp = PHI %1, %bb.3, %10, %bb.4
+ %12:gpr32 = SUBSWri %11, 0, 0, implicit-def $nzcv
+ Bcc 12, %bb.1, implicit $nzcv
+ B %bb.6
+
+ bb.6:
+ $w0 = COPY %11
+ RET_ReallyLR implicit $w0
+...
+---
+name: two_regions_share_call_block
+alignment: 4
+tracksRegLiveness: true
+body: |
+ ; CHECK-COMMON-LABEL: name: two_regions_share_call_block
+ ; CHECK-COMMON: bb.0:
+ ; CHECK-COMMON-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-COMMON-NEXT: liveins: $x0, $w1, $w2
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-COMMON-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-COMMON-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-COMMON-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-COMMON-NEXT: [[LDRWui1:%[0-9]+]]:gpr32common = LDRWui [[COPY]], 1 :: (load (s32))
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.1:
+ ; CHECK-COMMON-NEXT: successors: %bb.2(0x40000000), %bb.5(0x40000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: BL &foo, implicit-def $lr
+ ; CHECK-COMMON-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY1]], [[COPY2]], implicit-def $nzcv
+ ; CHECK-COMMON-NEXT: Bcc 0, %bb.5, implicit $nzcv
+ ; CHECK-COMMON-NEXT: B %bb.2
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.2:
+ ; CHECK-COMMON-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[ADDWri:%[0-9]+]]:gpr32common = ADDWri [[LDRWui]], 1, 0
+ ; CHECK-COMMON-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[ADDWri]], 100, 0, implicit-def $nzcv
+ ; CHECK-COMMON-NEXT: Bcc 12, %bb.4, implicit $nzcv
+ ; CHECK-COMMON-NEXT: B %bb.3
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.3:
+ ; CHECK-COMMON-NEXT: successors: %bb.4(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-COMMON-NEXT: [[MADDWrrr1:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr]], [[COPY1]], $wzr
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.4:
+ ; CHECK-COMMON-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.2, [[MADDWrrr1]], %bb.3
+ ; CHECK-COMMON-NEXT: $w0 = COPY [[PHI]]
+ ; CHECK-COMMON-NEXT: RET_ReallyLR implicit $w0
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.5:
+ ; CHECK-COMMON-NEXT: successors: %bb.6(0x40000000), %bb.7(0x40000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[ADDWri1:%[0-9]+]]:gpr32common = ADDWri [[LDRWui1]], 1, 0
+ ; CHECK-COMMON-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[ADDWri1]], 100, 0, implicit-def $nzcv
+ ; CHECK-COMMON-NEXT: Bcc 12, %bb.7, implicit $nzcv
+ ; CHECK-COMMON-NEXT: B %bb.6
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.6:
+ ; CHECK-COMMON-NEXT: successors: %bb.7(0x80000000)
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: [[MADDWrrr2:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY2]], $wzr
+ ; CHECK-COMMON-NEXT: [[MADDWrrr3:%[0-9]+]]:gpr32 = MADDWrrr [[MADDWrrr2]], [[COPY1]], $wzr
+ ; CHECK-COMMON-NEXT: {{ $}}
+ ; CHECK-COMMON-NEXT: bb.7:
+ ; CHECK-COMMON-NEXT: [[PHI1:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.5, [[MADDWrrr3]], %bb.6
+ ; CHECK-COMMON-NEXT: $w0 = COPY [[PHI1]]
+ ; CHECK-COMMON-NEXT: RET_ReallyLR implicit $w0
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $x0, $w1, $w2
+
+ %0:gpr64common = COPY $x0
+ %1:gpr32 = COPY $w1
+ %2:gpr32 = COPY $w2
+ %3:gpr32common = LDRWui %0, 0 :: (load (s32))
+ %4:gpr32common = LDRWui %0, 1 :: (load (s32))
+
+ bb.1:
+ successors: %bb.2(0x40000000), %bb.5(0x40000000)
+
+ BL &foo, implicit-def $lr
+ %5:gpr32 = SUBSWrr %1, %2, implicit-def $nzcv
+ Bcc 0, %bb.5, implicit $nzcv
+ B %bb.2
+
+ bb.2:
+ successors: %bb.3(0x40000000), %bb.4(0x40000000)
+
+ %6:gpr32common = ADDWri %3, 1, 0
+ %7:gpr32 = SUBSWri %6, 100, 0, implicit-def $nzcv
+ Bcc 12, %bb.4, implicit $nzcv
+ B %bb.3
+
+ bb.3:
+ successors: %bb.4(0x80000000)
+
+ %8:gpr32 = MADDWrrr %1, %2, $wzr
+ %9:gpr32 = MADDWrrr %8, %1, $wzr
+
+ bb.4:
+ %10:gpr32 = PHI %1, %bb.2, %9, %bb.3
+ $w0 = COPY %10
+ RET_ReallyLR implicit $w0
+
+ bb.5:
+ successors: %bb.6(0x40000000), %bb.7(0x40000000)
+
+ %11:gpr32common = ADDWri %4, 1, 0
+ %12:gpr32 = SUBSWri %11, 100, 0, implicit-def $nzcv
+ Bcc 12, %bb.7, implicit $nzcv
+ B %bb.6
+
+ bb.6:
+ successors: %bb.7(0x80000000)
+
+ %13:gpr32 = MADDWrrr %1, %2, $wzr
+ %14:gpr32 = MADDWrrr %13, %1, $wzr
+
+ bb.7:
+ %15:gpr32 = PHI %1, %bb.5, %14, %bb.6
+ $w0 = COPY %15
+ RET_ReallyLR implicit $w0
+...
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