[llvm] [VPlan] Expand AddRecs in VPSCEVExpander (PR #209921)
Ramkumar Ramachandra via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 23 00:31:15 PDT 2026
https://github.com/artagnon updated https://github.com/llvm/llvm-project/pull/209921
>From 057abf4f72b3d2938de91ea2a4a5c47939ea7f97 Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: Mon, 10 Aug 2026 15:25:47 +0100
Subject: [PATCH 1/2] [VPlan] Pre-commit expand-scev test
---
.../LoopVectorize/VPlan/expand-scev.ll | 42 +++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll b/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
index e6cc0cbfc5c95..137eebf488c80 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
@@ -689,6 +689,48 @@ exit:
ret void
}
+define void @addrec_nonscevable(ptr %dst) {
+; CHECK-LABEL: VPlan for loop in 'addrec_nonscevable'
+; CHECK: VPlan 'Final VPlan for VF={4},UF={1}' {
+; CHECK-NEXT: Live-in ir<%2> = original trip-count
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<outer>:
+; CHECK-NEXT: IR %fp.phi = phi float [ 0.000000e+00, %entry ], [ %fp.next, %outer.latch ]
+; CHECK-NEXT: IR %outer.iv = phi i64 [ 0, %entry ], [ %outer.iv.next, %outer.latch ]
+; CHECK-NEXT: IR %0 = add i64 %outer.iv, 4
+; CHECK-NEXT: IR %1 = udiv i64 %0, 3
+; CHECK-NEXT: IR %2 = add nuw nsw i64 %1, 1
+; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult ir<%2>, ir<4>
+; CHECK-NEXT: EMIT branch-on-cond vp<%min.iters.check>
+; CHECK-NEXT: Successor(s): ir-bb<scalar.ph>, vector.ph
+;
+entry:
+ br label %outer
+
+outer:
+ %fp.phi = phi float [ 0.0, %entry ], [ %fp.next, %outer.latch ]
+ %outer.iv = phi i64 [ 0, %entry ], [ %outer.iv.next, %outer.latch ]
+ br label %inner
+
+inner:
+ %iv = phi i64 [ 0, %outer ], [ %iv.next, %inner ]
+ %gep = getelementptr i8, ptr %dst, i64 %iv
+ store float %fp.phi, ptr %gep
+ %iv.next = add nuw i64 %iv, 3
+ %bound = add i64 %outer.iv, 5
+ %ec.inner = icmp ult i64 %iv.next, %bound
+ br i1 %ec.inner, label %inner, label %outer.latch
+
+outer.latch:
+ %fp.next = fadd float %fp.phi, 1.0
+ %outer.iv.next = add nuw i64 %outer.iv, 1
+ %ec.outer = icmp ult i64 %outer.iv.next, 100
+ br i1 %ec.outer, label %outer, label %exit
+
+exit:
+ ret void
+}
+
!0 = distinct !{!0, !1, !2}
!1 = !{!"llvm.loop.vectorize.scalable.enable"}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
>From 7974be423af24efe693ec1e80291dfddcafac46e Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: Wed, 15 Jul 2026 22:14:03 +0100
Subject: [PATCH 2/2] [VPlan] Expand AddRecs in VPSCEVExpander
Extend VPSCEVExpander to expand AddRecs. In the general case, an
AddRec's loop header refers to a BasicBlock that is no longer in the
Plan, and we have to fall back to the IR SCEV expander. However, when an
identical BasicBlock is present in the Plan as a VPIRBasicBlock, and
when it has a canonical IV that we can re-use as a VPIRPhi, expand the
AddRec to VPInstructions. In particular it is impossible for an AddRec's
loop to correspond to the vector loop.
Co-authored-by: Florian Hahn <flo at fhahn.com>
---
llvm/lib/Transforms/Vectorize/VPlan.h | 2 +-
llvm/lib/Transforms/Vectorize/VPlanUtils.cpp | 44 +++++++++++++++++++
.../LoopVectorize/RISCV/strided-accesses.ll | 18 ++++----
.../LoopVectorize/VPlan/expand-scev.ll | 29 ++++++------
.../nested-loops-scev-expansion.ll | 3 +-
5 files changed, 68 insertions(+), 28 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h
index deabeb97183c2..5b3b9e75bf241 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.h
+++ b/llvm/lib/Transforms/Vectorize/VPlan.h
@@ -1806,7 +1806,7 @@ struct LLVM_ABI_FOR_TEST VPIRPhi : public VPIRInstruction,
return R && classof(R);
}
- PHINode &getIRPhi() { return cast<PHINode>(getInstruction()); }
+ PHINode &getIRPhi() const { return cast<PHINode>(getInstruction()); }
void execute(VPTransformState &State) override;
diff --git a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
index e6b267493d987..9488ccb127c43 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
@@ -1059,6 +1059,50 @@ VPValue *VPSCEVExpander::tryToExpand(const SCEV *S) {
ResultTy, DL);
return Result;
}
+ case scAddRecExpr: {
+ // AddRecs never appear in the vector loop; the AR's loop would correspond
+ // to an outer loop outside the vector loop, and its header would be modeled
+ // as a VPIRBasicBlock.
+ auto *AR = cast<SCEVAddRecExpr>(S);
+ VPlan &Plan = Builder.getPlan();
+
+ // If a canonical IV to re-use is present, it would be in the Plan's entry.
+ // We cannot create a phi in the Plan's entry, which would be required in
+ // the absence of a canonical IV to re-use or if AR is non-affine, because
+ // its predecessors are not modeled. This code seems to be unreachable for
+ // AddRecs of pointer type.
+ if (!AR->isAffine() || AR->getType()->isPointerTy())
+ return nullptr;
+ auto FoundCanIV =
+ find_if(Plan.getEntry()->phis(), [&](const VPRecipeBase &R) {
+ if (!SE.isSCEVable(cast<VPIRPhi>(R).getIRPhi().getType()))
+ return false;
+ const SCEV *Candidate = SE.getSCEV(&cast<VPIRPhi>(R).getIRPhi());
+ return match(Candidate,
+ m_scev_AffineAddRec(m_scev_Zero(), m_scev_One(),
+ m_SpecificLoop(AR->getLoop()))) &&
+ Candidate->getType() == AR->getType();
+ });
+ if (FoundCanIV == Plan.getEntry()->phis().end())
+ return nullptr;
+
+ VPValue *CanonicalIV =
+ Plan.getOrAddLiveIn(&cast<VPIRPhi>(FoundCanIV)->getIRPhi());
+ VPValue *Start;
+ Start = tryToExpand(AR->getStart());
+ if (!Start)
+ return nullptr;
+ VPValue *Step = tryToExpand(AR->getStepRecurrence(SE));
+ if (!Step)
+ return nullptr;
+
+ // {X,+,F} --> X + {0,+,F}
+ // {0,+,F} --> {0,+,1} * F
+ VPIRFlags::WrapFlagsTy NWFlags = {AR->hasNoUnsignedWrap(), false};
+ VPValue *Offset = Builder.createOverflowingOp(Instruction::Mul,
+ {CanonicalIV, Step}, NWFlags);
+ return Builder.createAdd(Start, Offset, DL, "", NWFlags);
+ }
default:
return nullptr;
}
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll b/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
index 300d28be48054..77f4d52717ed7 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
@@ -2079,20 +2079,20 @@ exit:
define void @iv_start_is_addrec(ptr %p, ptr noalias %q) {
; CHECK-LABEL: define void @iv_start_is_addrec(
; CHECK-SAME: ptr [[P:%.*]], ptr noalias [[Q:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: br label %[[PH:.*]]
-; CHECK: [[PH]]:
-; CHECK-NEXT: [[IND_INCOMING:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IND_INCOMING_NEXT:%.*]], %[[EXIT:.*]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[IND_INCOMING]], 2
-; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP0]]
+; CHECK-NEXT: [[PH:.*]]:
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[IND_INCOMING:%.*]] = phi i64 [ 0, %[[PH]] ], [ [[IND_INCOMING_NEXT:%.*]], %[[EXIT:.*]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[IND_INCOMING]], 2
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP0]]
+; CHECK-NEXT: br label %[[VECTOR_PH1:.*]]
+; CHECK: [[VECTOR_PH1]]:
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 8 x ptr> poison, ptr [[Q]], i64 0
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 8 x ptr> [[BROADCAST_SPLATINSERT]], <vscale x 8 x ptr> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 129, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH1]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 129, %[[VECTOR_PH1]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 8, i1 true)
; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[INDEX]], -8
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[TMP4]]
@@ -2107,7 +2107,7 @@ define void @iv_start_is_addrec(ptr %p, ptr noalias %q) {
; CHECK-NEXT: br label %[[EXIT]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: [[IND_INCOMING_NEXT]] = add i64 [[IND_INCOMING]], 1
-; CHECK-NEXT: br label %[[PH]]
+; CHECK-NEXT: br label %[[VECTOR_PH]]
;
; CHECK-UF2-LABEL: define void @iv_start_is_addrec(
; CHECK-UF2-SAME: ptr [[P:%.*]], ptr noalias [[Q:%.*]]) #[[ATTR0]] {
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll b/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
index 137eebf488c80..b87023b881a1b 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
@@ -321,14 +321,13 @@ exit:
define void @scev_addrec_expanded(ptr %dst) {
; CHECK-LABEL: VPlan for loop in 'scev_addrec_expanded'
; CHECK: VPlan 'Final VPlan for VF={4},UF={1}' {
-; CHECK-NEXT: Live-in ir<%2> = original trip-count
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<outer>:
; CHECK-NEXT: IR %outer.iv = phi i64 [ 0, %entry ], [ %outer.iv.next, %outer.latch ]
-; CHECK-NEXT: IR %0 = add i64 %outer.iv, 4
-; CHECK-NEXT: IR %1 = udiv i64 %0, 3
-; CHECK-NEXT: IR %2 = add nuw nsw i64 %1, 1
-; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult ir<%2>, ir<4>
+; CHECK-NEXT: EMIT vp<[[VP2:%[0-9]+]]> = add nuw ir<4>, ir<%outer.iv>
+; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = udiv vp<[[VP2]]>, ir<3>
+; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = add nuw nsw vp<[[VP3]]>, ir<1>
+; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult vp<[[VP4]]>, ir<4>
; CHECK-NEXT: EMIT branch-on-cond vp<%min.iters.check>
; CHECK-NEXT: Successor(s): ir-bb<scalar.ph>, vector.ph
;
@@ -525,17 +524,16 @@ exit:
define void @addrec_nuw_flags(ptr %dst) {
; CHECK-LABEL: VPlan for loop in 'addrec_nuw_flags'
; CHECK: VPlan 'Final VPlan for VF={4},UF={1}' {
-; CHECK-NEXT: Live-in ir<%3> = original trip-count
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<outer>:
; CHECK-NEXT: IR %outer.iv = phi i64 [ 0, %entry ], [ %outer.iv.next, %outer.latch ]
-; CHECK-NEXT: IR %0 = shl nuw nsw i64 %outer.iv, 2
-; CHECK-NEXT: IR %1 = add i64 %0, 4
-; CHECK-NEXT: IR %2 = udiv i64 %1, 3
-; CHECK-NEXT: IR %3 = add nuw nsw i64 %2, 1
; CHECK-NEXT: IR %m = mul nuw i64 %outer.iv, 4
; CHECK-NEXT: IR %bound = add nuw i64 %m, 5
-; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult ir<%3>, ir<4>
+; CHECK-NEXT: EMIT vp<[[VP2:%[0-9]+]]> = shl nuw ir<%outer.iv>, ir<2>
+; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = add nuw ir<4>, vp<[[VP2]]>
+; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = udiv vp<[[VP3]]>, ir<3>
+; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = add nuw nsw vp<[[VP4]]>, ir<1>
+; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult vp<[[VP5]]>, ir<4>
; CHECK-NEXT: EMIT branch-on-cond vp<%min.iters.check>
; CHECK-NEXT: Successor(s): ir-bb<scalar.ph>, vector.ph
;
@@ -692,15 +690,14 @@ exit:
define void @addrec_nonscevable(ptr %dst) {
; CHECK-LABEL: VPlan for loop in 'addrec_nonscevable'
; CHECK: VPlan 'Final VPlan for VF={4},UF={1}' {
-; CHECK-NEXT: Live-in ir<%2> = original trip-count
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<outer>:
; CHECK-NEXT: IR %fp.phi = phi float [ 0.000000e+00, %entry ], [ %fp.next, %outer.latch ]
; CHECK-NEXT: IR %outer.iv = phi i64 [ 0, %entry ], [ %outer.iv.next, %outer.latch ]
-; CHECK-NEXT: IR %0 = add i64 %outer.iv, 4
-; CHECK-NEXT: IR %1 = udiv i64 %0, 3
-; CHECK-NEXT: IR %2 = add nuw nsw i64 %1, 1
-; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult ir<%2>, ir<4>
+; CHECK-NEXT: EMIT vp<[[VP2:%[0-9]+]]> = add nuw ir<4>, ir<%outer.iv>
+; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = udiv vp<[[VP2]]>, ir<3>
+; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = add nuw nsw vp<[[VP3]]>, ir<1>
+; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult vp<[[VP4]]>, ir<4>
; CHECK-NEXT: EMIT branch-on-cond vp<%min.iters.check>
; CHECK-NEXT: Successor(s): ir-bb<scalar.ph>, vector.ph
;
diff --git a/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll b/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
index 9014cc606ad78..8bde71d0c318d 100644
--- a/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
+++ b/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
@@ -335,9 +335,8 @@ define void @test_expand_secv_in_entry_before_gep(ptr %dst) {
; CHECK-NEXT: br label %[[OUTER_HEADER:.*]]
; CHECK: [[OUTER_HEADER]]:
; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[OUTER_IV_NEXT:%.*]], %[[OUTER_LATCH:.*]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = mul i64 [[OUTER_IV]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 112
; CHECK-NEXT: [[GEP_M:%.*]] = getelementptr [36 x [36 x double]], ptr [[DST]], i64 0, i64 [[OUTER_IV]]
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 112, [[OUTER_IV]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
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