[llvm] 2678a67 - [RISCV] Merge RISCVISD::PMUL_H_B01 and RISCVISD::PMUL_W_H01. (#218046)

[via llvm-commits]

Author: Craig Topper
Date: 2026-08-22T20:52:08-07:00
New Revision: 2678a67b21a455c336a9cd42b5ce72483ac56f9b

URL: https://github.com/llvm/llvm-project/commit/2678a67b21a455c336a9cd42b5ce72483ac56f9b
DIFF: https://github.com/llvm/llvm-project/commit/2678a67b21a455c336a9cd42b5ce72483ac56f9b.diff

LOG: [RISCV] Merge RISCVISD::PMUL_H_B01 and RISCVISD::PMUL_W_H01. (#218046)

Same for RISCVISD::PMULU_H_B01/PMULU_W_H01 and
RISCVISD::PMULSU_H_B00/PMULSU_W_H00.

We can distquish by types, we don't need different nodes for each type.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/lib/Target/RISCV/RISCVInstrInfoP.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index c6b859da32b5a..194aad22775cf 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -18989,15 +18989,14 @@ static SDValue combinePExtWideningMul(SDNode *N, SelectionDAG &DAG,
   bool IsSignedUnsigned = false;
   if (N0IsSExt && N1IsSExt) {
     RV32Opc = RISCVISD::PWMUL;
-    RV64Opc = VT == MVT::v4i16 ? RISCVISD::PMUL_H_B01 : RISCVISD::PMUL_W_H01;
+    RV64Opc = RISCVISD::PMUL_HALVES_01;
   } else if (N0IsZExt && N1IsZExt) {
     RV32Opc = RISCVISD::PWMULU;
-    RV64Opc = VT == MVT::v4i16 ? RISCVISD::PMULU_H_B01 : RISCVISD::PMULU_W_H01;
+    RV64Opc = RISCVISD::PMULU_HALVES_01;
   } else {
     IsSignedUnsigned = true;
     RV32Opc = RISCVISD::PWMULSU;
-    RV64Opc =
-        VT == MVT::v4i16 ? RISCVISD::PMULSU_H_B00 : RISCVISD::PMULSU_W_H00;
+    RV64Opc = RISCVISD::PMULSU_HALVES_00;
     if (N0IsZExt && N1IsSExt)
       std::swap(A, B);
   }

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index a68a589c0f964..9b72141ef9bcd 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -1858,19 +1858,14 @@ def riscv_pwmulsu : RVSDNode<"PWMULSU", SDT_RISCVPackedWideningMul>;
 def SDT_RISCVPackedWideningMulByHalves
     : SDTypeProfile<1, 2, [SDTCisVec<0>,
                            SDTCisSameAs<1, 2>,
+                           SDTCisSameSizeAs<0, 1>,
                            SDTCisOpSmallerThanOp<1, 0>]>;
-def riscv_pmul_h_b01
-    : RVSDNode<"PMUL_H_B01", SDT_RISCVPackedWideningMulByHalves>;
-def riscv_pmul_w_h01
-    : RVSDNode<"PMUL_W_H01", SDT_RISCVPackedWideningMulByHalves>;
-def riscv_pmulu_h_b01
-    : RVSDNode<"PMULU_H_B01", SDT_RISCVPackedWideningMulByHalves>;
-def riscv_pmulu_w_h01
-    : RVSDNode<"PMULU_W_H01", SDT_RISCVPackedWideningMulByHalves>;
-def riscv_pmulsu_h_b00
-    : RVSDNode<"PMULSU_H_B00", SDT_RISCVPackedWideningMulByHalves>;
-def riscv_pmulsu_w_h00
-    : RVSDNode<"PMULSU_W_H00", SDT_RISCVPackedWideningMulByHalves>;
+def riscv_pmul_halves_01
+    : RVSDNode<"PMUL_HALVES_01", SDT_RISCVPackedWideningMulByHalves>;
+def riscv_pmulu_halves_01
+    : RVSDNode<"PMULU_HALVES_01", SDT_RISCVPackedWideningMulByHalves>;
+def riscv_pmulsu_halves_00
+    : RVSDNode<"PMULSU_HALVES_00", SDT_RISCVPackedWideningMulByHalves>;
 
 def SDT_RISCVWideningShiftLeft : SDTypeProfile<2, 2, [SDTCisVT<0, i32>,
                                                       SDTCisSameAs<0, 1>,
@@ -2866,17 +2861,17 @@ let append Predicates = [IsRV64] in {
             (PACK (MUL_W00 GPR:$rs1, GPR:$rs2), (MUL_W11 GPR:$rs1, GPR:$rs2))>;
 
   // Packed widening multiply patterns.
-  def : Pat<(v4i16 (riscv_pmul_h_b01 (v8i8 GPR:$rs1), (v8i8 GPR:$rs2))),
+  def : Pat<(v4i16 (riscv_pmul_halves_01 (v8i8 GPR:$rs1), (v8i8 GPR:$rs2))),
             (PMUL_H_B01 GPR:$rs1, GPR:$rs2)>;
-  def : Pat<(v2i32 (riscv_pmul_w_h01 (v4i16 GPR:$rs1), (v4i16 GPR:$rs2))),
+  def : Pat<(v2i32 (riscv_pmul_halves_01 (v4i16 GPR:$rs1), (v4i16 GPR:$rs2))),
             (PMUL_W_H01 GPR:$rs1, GPR:$rs2)>;
-  def : Pat<(v4i16 (riscv_pmulu_h_b01 (v8i8 GPR:$rs1), (v8i8 GPR:$rs2))),
+  def : Pat<(v4i16 (riscv_pmulu_halves_01 (v8i8 GPR:$rs1), (v8i8 GPR:$rs2))),
             (PMULU_H_B01 GPR:$rs1, GPR:$rs2)>;
-  def : Pat<(v2i32 (riscv_pmulu_w_h01 (v4i16 GPR:$rs1), (v4i16 GPR:$rs2))),
+  def : Pat<(v2i32 (riscv_pmulu_halves_01 (v4i16 GPR:$rs1), (v4i16 GPR:$rs2))),
             (PMULU_W_H01 GPR:$rs1, GPR:$rs2)>;
-  def : Pat<(v4i16 (riscv_pmulsu_h_b00 (v8i8 GPR:$rs1), (v8i8 GPR:$rs2))),
+  def : Pat<(v4i16 (riscv_pmulsu_halves_00 (v8i8 GPR:$rs1), (v8i8 GPR:$rs2))),
             (PMULSU_H_B00 GPR:$rs1, GPR:$rs2)>;
-  def : Pat<(v2i32 (riscv_pmulsu_w_h00 (v4i16 GPR:$rs1), (v4i16 GPR:$rs2))),
+  def : Pat<(v2i32 (riscv_pmulsu_halves_00 (v4i16 GPR:$rs1), (v4i16 GPR:$rs2))),
             (PMULSU_W_H00 GPR:$rs1, GPR:$rs2)>;
 
   // 8-bit multiply high patterns