[llvm] ada2299 - [RISCV] Fix size of PseudoMERGE (#218171)

[via llvm-commits]

Author: Sam Elliott
Date: 2026-08-23T00:52:37Z
New Revision: ada22991220fe96130d7d5d69f16cb17b53e3e27

URL: https://github.com/llvm/llvm-project/commit/ada22991220fe96130d7d5d69f16cb17b53e3e27
DIFF: https://github.com/llvm/llvm-project/commit/ada22991220fe96130d7d5d69f16cb17b53e3e27.diff

LOG: [RISCV] Fix size of PseudoMERGE (#218171)

This can expand to two 4-byte instructions, so mark it as size 8.
Usually it will expand to just one 4-byte instruction.

This was found in #218170.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoP.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index ac893d83cf3ac..a68a589c0f964 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -2062,6 +2062,7 @@ let Predicates = [HasStdExtP] in {
   // Pseudo version of MERGE without the tied constraint. Will be expanded to
   // MERGE, MVM, or MVMN after register allocation.
   // dst = (~rd & rs1) | (rd & rs2)
+  let Size = 8 in
   def PseudoMERGE : Pseudo<(outs GPR:$dst), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
                            []>;
   def : Pat<(XLenVT (or (and GPR:$rd, GPR:$rs2), (and (not GPR:$rd), GPR:$rs1))),