[llvm] [RISCV][NFCI] Introduce Base for Pseudo Expansion Passes (PR #218170)
Sam Elliott via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 22 17:38:38 PDT 2026
https://github.com/lenary updated https://github.com/llvm/llvm-project/pull/218170
>From cfb58c728ebf1f2f6ce4d9e521b28e72c0320592 Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Sat, 22 Aug 2026 16:10:12 -0700
Subject: [PATCH 1/3] [RISCV][NFCI] Introduce Base for Pseudo Expansion Passes
This introduces a base class for the Pseudo Instruction Expansion Pass
Implementations, which shares the boiler plate that ensures the function
size estimate does not grow during expansion.
This also makes many of those methods `const`, to more clearly
illustrate how the Impl class works.
This is used to simplify all four of the Pseudo Instruction Expansion
passes. Additionally, many static functions in the Atomic Expand pass
are moved onto the Impl class, so they can directly access the
subtarget and instruction info.
Assisted-by: AI
---
llvm/lib/Target/RISCV/CMakeLists.txt | 1 +
.../RISCV/RISCVExpandAtomicPseudoInsts.cpp | 282 ++++++++----------
.../Target/RISCV/RISCVExpandPseudoBase.cpp | 59 ++++
llvm/lib/Target/RISCV/RISCVExpandPseudoBase.h | 41 +++
.../Target/RISCV/RISCVExpandPseudoInsts.cpp | 125 +++-----
.../RISCV/RISCVPostRAExpandPseudoInsts.cpp | 73 ++---
.../RISCV/RISCVPreRAExpandPseudoInsts.cpp | 137 +++------
7 files changed, 333 insertions(+), 385 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVExpandPseudoBase.cpp
create mode 100644 llvm/lib/Target/RISCV/RISCVExpandPseudoBase.h
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt
index dab90facab836..b26a2deb89ef4 100644
--- a/llvm/lib/Target/RISCV/CMakeLists.txt
+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -38,6 +38,7 @@ add_llvm_target(RISCVCodeGen
RISCVConstantPoolValue.cpp
RISCVDeadRegisterDefinitions.cpp
RISCVExpandAtomicPseudoInsts.cpp
+ RISCVExpandPseudoBase.cpp
RISCVExpandPseudoInsts.cpp
RISCVFoldMemOffset.cpp
RISCVFrameLowering.cpp
diff --git a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
index 0dc72aca76ed7..02fc4f7147ee8 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
@@ -14,9 +14,9 @@
//===----------------------------------------------------------------------===//
#include "RISCV.h"
+#include "RISCVExpandPseudoBase.h"
#include "RISCVInstrInfo.h"
#include "RISCVSubtarget.h"
-
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -28,36 +28,59 @@ using namespace llvm;
namespace {
-class RISCVExpandAtomicPseudoImpl {
-public:
- const RISCVSubtarget *STI;
- const RISCVInstrInfo *TII;
- bool run(MachineFunction &MF);
-
-private:
- bool expandMBB(MachineBasicBlock &MBB);
+class RISCVExpandAtomicPseudoImpl final : public RISCVExpandPseudoImplBase {
bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI);
+ MachineBasicBlock::iterator &NextMBBI) const override;
+
bool expandAtomicBinOp(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, AtomicRMWInst::BinOp,
bool IsMasked, int Width,
- MachineBasicBlock::iterator &NextMBBI);
+ MachineBasicBlock::iterator &NextMBBI) const;
+
bool expandAtomicMinMaxOp(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
AtomicRMWInst::BinOp, bool IsMasked, int Width,
- MachineBasicBlock::iterator &NextMBBI);
+ MachineBasicBlock::iterator &NextMBBI) const;
+
bool expandAtomicCmpXchg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, bool IsMasked,
- int Width, MachineBasicBlock::iterator &NextMBBI);
-#ifndef NDEBUG
- unsigned getInstSizeInBytes(const MachineFunction &MF) const {
- unsigned Size = 0;
- for (auto &MBB : MF)
- for (auto &MI : MBB)
- Size += TII->getInstSizeInBytes(MI);
- return Size;
- }
-#endif
+ int Width,
+ MachineBasicBlock::iterator &NextMBBI) const;
+
+ unsigned getLRForRMW32(AtomicOrdering Ordering) const;
+ unsigned getSCForRMW32(AtomicOrdering Ordering) const;
+ unsigned getLRForRMW64(AtomicOrdering Ordering) const;
+ unsigned getSCForRMW64(AtomicOrdering Ordering) const;
+ unsigned getLRForRMW(AtomicOrdering Ordering, int Width) const;
+ unsigned getSCForRMW(AtomicOrdering Ordering, int Width) const;
+
+ void doAtomicBinOpExpansion(MachineInstr &MI, MachineBasicBlock *LoopMBB,
+ AtomicRMWInst::BinOp BinOp, int Width) const;
+ void insertMaskedMerge(DebugLoc DL, MachineBasicBlock *MBB, Register DestReg,
+ Register OldValReg, Register NewValReg,
+ Register MaskReg, Register ScratchReg) const;
+ void doMaskedAtomicBinOpExpansion(MachineInstr &MI,
+ MachineBasicBlock *LoopMBB,
+ AtomicRMWInst::BinOp BinOp,
+ int Width) const;
+ void insertSext(DebugLoc DL, MachineBasicBlock *MBB, Register ValReg,
+ Register ShamtReg) const;
+ void doAtomicMinMaxOpExpansion(MachineInstr &MI,
+ MachineBasicBlock *LoopHeadMBB,
+ MachineBasicBlock *LoopIfBodyMBB,
+ MachineBasicBlock *LoopTailMBB,
+ AtomicRMWInst::BinOp BinOp, int Width) const;
+ void doMaskedAtomicMinMaxOpExpansion(MachineInstr &MI,
+ MachineBasicBlock *LoopHeadMBB,
+ MachineBasicBlock *LoopIfBodyMBB,
+ MachineBasicBlock *LoopTailMBB,
+ AtomicRMWInst::BinOp BinOp,
+ int Width) const;
+ bool tryToFoldBNEOnCmpXchgResult(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ Register DestReg, Register CmpValReg,
+ Register MaskReg,
+ MachineBasicBlock *&LoopHeadBNETarget) const;
};
class RISCVExpandAtomicPseudoLegacy : public MachineFunctionPass {
@@ -75,43 +98,11 @@ class RISCVExpandAtomicPseudoLegacy : public MachineFunctionPass {
}
};
-char RISCVExpandAtomicPseudoLegacy::ID = 0;
-
-bool RISCVExpandAtomicPseudoImpl::run(MachineFunction &MF) {
- STI = &MF.getSubtarget<RISCVSubtarget>();
- TII = STI->getInstrInfo();
-
-#ifndef NDEBUG
- const unsigned OldSize = getInstSizeInBytes(MF);
-#endif
-
- bool Modified = false;
- for (auto &MBB : MF)
- Modified |= expandMBB(MBB);
-
-#ifndef NDEBUG
- const unsigned NewSize = getInstSizeInBytes(MF);
- assert(OldSize >= NewSize);
-#endif
- return Modified;
-}
-
-bool RISCVExpandAtomicPseudoImpl::expandMBB(MachineBasicBlock &MBB) {
- bool Modified = false;
-
- MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
- while (MBBI != E) {
- MachineBasicBlock::iterator NMBBI = std::next(MBBI);
- Modified |= expandMI(MBB, MBBI, NMBBI);
- MBBI = NMBBI;
- }
-
- return Modified;
-}
+} // anonymous namespace
bool RISCVExpandAtomicPseudoImpl::expandMI(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
+ MachineBasicBlock::iterator &NextMBBI) const {
// RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
// expanded instructions for each pseudo is correct in the Size field of the
// tablegen definition for the pseudo.
@@ -213,21 +204,21 @@ bool RISCVExpandAtomicPseudoImpl::expandMI(
return false;
}
-static unsigned getLRForRMW32(AtomicOrdering Ordering,
- const RISCVSubtarget *Subtarget) {
+unsigned
+RISCVExpandAtomicPseudoImpl::getLRForRMW32(AtomicOrdering Ordering) const {
switch (Ordering) {
default:
llvm_unreachable("Unexpected AtomicOrdering");
case AtomicOrdering::Monotonic:
return RISCV::LR_W;
case AtomicOrdering::Acquire:
- if (Subtarget->hasStdExtZtso())
+ if (STI->hasStdExtZtso())
return RISCV::LR_W;
return RISCV::LR_W_AQ;
case AtomicOrdering::Release:
return RISCV::LR_W;
case AtomicOrdering::AcquireRelease:
- if (Subtarget->hasStdExtZtso())
+ if (STI->hasStdExtZtso())
return RISCV::LR_W;
return RISCV::LR_W_AQ;
case AtomicOrdering::SequentiallyConsistent:
@@ -235,8 +226,8 @@ static unsigned getLRForRMW32(AtomicOrdering Ordering,
}
}
-static unsigned getSCForRMW32(AtomicOrdering Ordering,
- const RISCVSubtarget *Subtarget) {
+unsigned
+RISCVExpandAtomicPseudoImpl::getSCForRMW32(AtomicOrdering Ordering) const {
switch (Ordering) {
default:
llvm_unreachable("Unexpected AtomicOrdering");
@@ -245,11 +236,11 @@ static unsigned getSCForRMW32(AtomicOrdering Ordering,
case AtomicOrdering::Acquire:
return RISCV::SC_W;
case AtomicOrdering::Release:
- if (Subtarget->hasStdExtZtso())
+ if (STI->hasStdExtZtso())
return RISCV::SC_W;
return RISCV::SC_W_RL;
case AtomicOrdering::AcquireRelease:
- if (Subtarget->hasStdExtZtso())
+ if (STI->hasStdExtZtso())
return RISCV::SC_W;
return RISCV::SC_W_RL;
case AtomicOrdering::SequentiallyConsistent:
@@ -257,21 +248,21 @@ static unsigned getSCForRMW32(AtomicOrdering Ordering,
}
}
-static unsigned getLRForRMW64(AtomicOrdering Ordering,
- const RISCVSubtarget *Subtarget) {
+unsigned
+RISCVExpandAtomicPseudoImpl::getLRForRMW64(AtomicOrdering Ordering) const {
switch (Ordering) {
default:
llvm_unreachable("Unexpected AtomicOrdering");
case AtomicOrdering::Monotonic:
return RISCV::LR_D;
case AtomicOrdering::Acquire:
- if (Subtarget->hasStdExtZtso())
+ if (STI->hasStdExtZtso())
return RISCV::LR_D;
return RISCV::LR_D_AQ;
case AtomicOrdering::Release:
return RISCV::LR_D;
case AtomicOrdering::AcquireRelease:
- if (Subtarget->hasStdExtZtso())
+ if (STI->hasStdExtZtso())
return RISCV::LR_D;
return RISCV::LR_D_AQ;
case AtomicOrdering::SequentiallyConsistent:
@@ -279,8 +270,8 @@ static unsigned getLRForRMW64(AtomicOrdering Ordering,
}
}
-static unsigned getSCForRMW64(AtomicOrdering Ordering,
- const RISCVSubtarget *Subtarget) {
+unsigned
+RISCVExpandAtomicPseudoImpl::getSCForRMW64(AtomicOrdering Ordering) const {
switch (Ordering) {
default:
llvm_unreachable("Unexpected AtomicOrdering");
@@ -289,11 +280,11 @@ static unsigned getSCForRMW64(AtomicOrdering Ordering,
case AtomicOrdering::Acquire:
return RISCV::SC_D;
case AtomicOrdering::Release:
- if (Subtarget->hasStdExtZtso())
+ if (STI->hasStdExtZtso())
return RISCV::SC_D;
return RISCV::SC_D_RL;
case AtomicOrdering::AcquireRelease:
- if (Subtarget->hasStdExtZtso())
+ if (STI->hasStdExtZtso())
return RISCV::SC_D;
return RISCV::SC_D_RL;
case AtomicOrdering::SequentiallyConsistent:
@@ -301,30 +292,28 @@ static unsigned getSCForRMW64(AtomicOrdering Ordering,
}
}
-static unsigned getLRForRMW(AtomicOrdering Ordering, int Width,
- const RISCVSubtarget *Subtarget) {
+unsigned RISCVExpandAtomicPseudoImpl::getLRForRMW(AtomicOrdering Ordering,
+ int Width) const {
if (Width == 32)
- return getLRForRMW32(Ordering, Subtarget);
+ return getLRForRMW32(Ordering);
if (Width == 64)
- return getLRForRMW64(Ordering, Subtarget);
+ return getLRForRMW64(Ordering);
llvm_unreachable("Unexpected LR width\n");
}
-static unsigned getSCForRMW(AtomicOrdering Ordering, int Width,
- const RISCVSubtarget *Subtarget) {
+unsigned RISCVExpandAtomicPseudoImpl::getSCForRMW(AtomicOrdering Ordering,
+ int Width) const {
if (Width == 32)
- return getSCForRMW32(Ordering, Subtarget);
+ return getSCForRMW32(Ordering);
if (Width == 64)
- return getSCForRMW64(Ordering, Subtarget);
+ return getSCForRMW64(Ordering);
llvm_unreachable("Unexpected SC width\n");
}
-static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI,
- DebugLoc DL, MachineBasicBlock *ThisMBB,
- MachineBasicBlock *LoopMBB,
- MachineBasicBlock *DoneMBB,
- AtomicRMWInst::BinOp BinOp, int Width,
- const RISCVSubtarget *STI) {
+void RISCVExpandAtomicPseudoImpl::doAtomicBinOpExpansion(
+ MachineInstr &MI, MachineBasicBlock *LoopMBB, AtomicRMWInst::BinOp BinOp,
+ int Width) const {
+ DebugLoc DL = MI.getDebugLoc();
Register DestReg = MI.getOperand(0).getReg();
Register ScratchReg = MI.getOperand(1).getReg();
Register AddrReg = MI.getOperand(2).getReg();
@@ -337,7 +326,7 @@ static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI,
// binop scratch, dest, val
// sc.[w|d] scratch, scratch, (addr)
// bnez scratch, loop
- BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width, STI)), DestReg)
+ BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg)
.addReg(AddrReg);
switch (BinOp) {
default:
@@ -401,7 +390,7 @@ static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI,
.addReg(IncrReg);
break;
}
- BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width, STI)), ScratchReg)
+ BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg)
.addReg(ScratchReg)
.addReg(AddrReg);
BuildMI(LoopMBB, DL, TII->get(RISCV::BNE))
@@ -410,10 +399,9 @@ static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI,
.addMBB(LoopMBB);
}
-static void insertMaskedMerge(const RISCVInstrInfo *TII, DebugLoc DL,
- MachineBasicBlock *MBB, Register DestReg,
- Register OldValReg, Register NewValReg,
- Register MaskReg, Register ScratchReg) {
+void RISCVExpandAtomicPseudoImpl::insertMaskedMerge(
+ DebugLoc DL, MachineBasicBlock *MBB, Register DestReg, Register OldValReg,
+ Register NewValReg, Register MaskReg, Register ScratchReg) const {
assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique");
assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique");
assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique");
@@ -432,13 +420,10 @@ static void insertMaskedMerge(const RISCVInstrInfo *TII, DebugLoc DL,
.addReg(ScratchReg);
}
-static void doMaskedAtomicBinOpExpansion(const RISCVInstrInfo *TII,
- MachineInstr &MI, DebugLoc DL,
- MachineBasicBlock *ThisMBB,
- MachineBasicBlock *LoopMBB,
- MachineBasicBlock *DoneMBB,
- AtomicRMWInst::BinOp BinOp, int Width,
- const RISCVSubtarget *STI) {
+void RISCVExpandAtomicPseudoImpl::doMaskedAtomicBinOpExpansion(
+ MachineInstr &MI, MachineBasicBlock *LoopMBB, AtomicRMWInst::BinOp BinOp,
+ int Width) const {
+ DebugLoc DL = MI.getDebugLoc();
assert(Width == 32 && "Should never need to expand masked 64-bit operations");
Register DestReg = MI.getOperand(0).getReg();
Register ScratchReg = MI.getOperand(1).getReg();
@@ -456,7 +441,7 @@ static void doMaskedAtomicBinOpExpansion(const RISCVInstrInfo *TII,
// xor scratch, destreg, scratch
// sc.w scratch, scratch, (alignedaddr)
// bnez scratch, loop
- BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering, STI)), DestReg)
+ BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg)
.addReg(AddrReg);
switch (BinOp) {
default:
@@ -486,10 +471,10 @@ static void doMaskedAtomicBinOpExpansion(const RISCVInstrInfo *TII,
break;
}
- insertMaskedMerge(TII, DL, LoopMBB, ScratchReg, DestReg, ScratchReg, MaskReg,
+ insertMaskedMerge(DL, LoopMBB, ScratchReg, DestReg, ScratchReg, MaskReg,
ScratchReg);
- BuildMI(LoopMBB, DL, TII->get(getSCForRMW32(Ordering, STI)), ScratchReg)
+ BuildMI(LoopMBB, DL, TII->get(getSCForRMW32(Ordering)), ScratchReg)
.addReg(ScratchReg)
.addReg(AddrReg);
BuildMI(LoopMBB, DL, TII->get(RISCV::BNE))
@@ -501,10 +486,8 @@ static void doMaskedAtomicBinOpExpansion(const RISCVInstrInfo *TII,
bool RISCVExpandAtomicPseudoImpl::expandAtomicBinOp(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
AtomicRMWInst::BinOp BinOp, bool IsMasked, int Width,
- MachineBasicBlock::iterator &NextMBBI) {
+ MachineBasicBlock::iterator &NextMBBI) const {
MachineInstr &MI = *MBBI;
- DebugLoc DL = MI.getDebugLoc();
-
MachineFunction *MF = MBB.getParent();
auto LoopMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
@@ -521,11 +504,9 @@ bool RISCVExpandAtomicPseudoImpl::expandAtomicBinOp(
MBB.addSuccessor(LoopMBB);
if (!IsMasked)
- doAtomicBinOpExpansion(TII, MI, DL, &MBB, LoopMBB, DoneMBB, BinOp, Width,
- STI);
+ doAtomicBinOpExpansion(MI, LoopMBB, BinOp, Width);
else
- doMaskedAtomicBinOpExpansion(TII, MI, DL, &MBB, LoopMBB, DoneMBB, BinOp,
- Width, STI);
+ doMaskedAtomicBinOpExpansion(MI, LoopMBB, BinOp, Width);
NextMBBI = MBB.end();
MI.eraseFromParent();
@@ -537,9 +518,10 @@ bool RISCVExpandAtomicPseudoImpl::expandAtomicBinOp(
return true;
}
-static void insertSext(const RISCVInstrInfo *TII, DebugLoc DL,
- MachineBasicBlock *MBB, Register ValReg,
- Register ShamtReg) {
+void RISCVExpandAtomicPseudoImpl::insertSext(DebugLoc DL,
+ MachineBasicBlock *MBB,
+ Register ValReg,
+ Register ShamtReg) const {
BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg)
.addReg(ValReg)
.addReg(ShamtReg);
@@ -548,12 +530,11 @@ static void insertSext(const RISCVInstrInfo *TII, DebugLoc DL,
.addReg(ShamtReg);
}
-static void doAtomicMinMaxOpExpansion(
- const RISCVInstrInfo *TII, MachineInstr &MI, DebugLoc DL,
- MachineBasicBlock *ThisMBB, MachineBasicBlock *LoopHeadMBB,
+void RISCVExpandAtomicPseudoImpl::doAtomicMinMaxOpExpansion(
+ MachineInstr &MI, MachineBasicBlock *LoopHeadMBB,
MachineBasicBlock *LoopIfBodyMBB, MachineBasicBlock *LoopTailMBB,
- MachineBasicBlock *DoneMBB, AtomicRMWInst::BinOp BinOp, int Width,
- const RISCVSubtarget *STI) {
+ AtomicRMWInst::BinOp BinOp, int Width) const {
+ DebugLoc DL = MI.getDebugLoc();
Register DestReg = MI.getOperand(0).getReg();
Register ScratchReg = MI.getOperand(1).getReg();
Register AddrReg = MI.getOperand(2).getReg();
@@ -565,7 +546,7 @@ static void doAtomicMinMaxOpExpansion(
// lr.[w|d] dest, (addr)
// mv scratch, dest
// ifnochangeneeded scratch, incr, .looptail
- BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width, STI)), DestReg)
+ BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg)
.addReg(AddrReg);
BuildMI(LoopHeadMBB, DL, TII->get(RISCV::ADDI), ScratchReg)
.addReg(DestReg)
@@ -610,8 +591,7 @@ static void doAtomicMinMaxOpExpansion(
// .looptail:
// sc.[w|d] scratch, scratch, (addr)
// bnez scratch, loop
- BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width, STI)),
- ScratchReg)
+ BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg)
.addReg(ScratchReg)
.addReg(AddrReg);
BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE))
@@ -620,12 +600,11 @@ static void doAtomicMinMaxOpExpansion(
.addMBB(LoopHeadMBB);
}
-static void doMaskedAtomicMinMaxOpExpansion(
- const RISCVInstrInfo *TII, MachineInstr &MI, DebugLoc DL,
- MachineBasicBlock *ThisMBB, MachineBasicBlock *LoopHeadMBB,
+void RISCVExpandAtomicPseudoImpl::doMaskedAtomicMinMaxOpExpansion(
+ MachineInstr &MI, MachineBasicBlock *LoopHeadMBB,
MachineBasicBlock *LoopIfBodyMBB, MachineBasicBlock *LoopTailMBB,
- MachineBasicBlock *DoneMBB, AtomicRMWInst::BinOp BinOp, int Width,
- const RISCVSubtarget *STI) {
+ AtomicRMWInst::BinOp BinOp, int Width) const {
+ DebugLoc DL = MI.getDebugLoc();
assert(Width == 32 && "Should never need to expand masked 64-bit operations");
Register DestReg = MI.getOperand(0).getReg();
Register Scratch1Reg = MI.getOperand(1).getReg();
@@ -644,7 +623,7 @@ static void doMaskedAtomicMinMaxOpExpansion(
// mv scratch1, destreg
// [sext scratch2 if signed min/max]
// ifnochangeneeded scratch2, incr, .looptail
- BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW32(Ordering, STI)), DestReg)
+ BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg)
.addReg(AddrReg);
BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), Scratch2Reg)
.addReg(DestReg)
@@ -657,7 +636,7 @@ static void doMaskedAtomicMinMaxOpExpansion(
default:
llvm_unreachable("Unexpected AtomicRMW BinOp");
case AtomicRMWInst::Max: {
- insertSext(TII, DL, LoopHeadMBB, Scratch2Reg, MI.getOperand(6).getReg());
+ insertSext(DL, LoopHeadMBB, Scratch2Reg, MI.getOperand(6).getReg());
BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE))
.addReg(Scratch2Reg)
.addReg(IncrReg)
@@ -665,7 +644,7 @@ static void doMaskedAtomicMinMaxOpExpansion(
break;
}
case AtomicRMWInst::Min: {
- insertSext(TII, DL, LoopHeadMBB, Scratch2Reg, MI.getOperand(6).getReg());
+ insertSext(DL, LoopHeadMBB, Scratch2Reg, MI.getOperand(6).getReg());
BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE))
.addReg(IncrReg)
.addReg(Scratch2Reg)
@@ -690,13 +669,13 @@ static void doMaskedAtomicMinMaxOpExpansion(
// xor scratch1, destreg, incr
// and scratch1, scratch1, mask
// xor scratch1, destreg, scratch1
- insertMaskedMerge(TII, DL, LoopIfBodyMBB, Scratch1Reg, DestReg, IncrReg,
- MaskReg, Scratch1Reg);
+ insertMaskedMerge(DL, LoopIfBodyMBB, Scratch1Reg, DestReg, IncrReg, MaskReg,
+ Scratch1Reg);
// .looptail:
// sc.w scratch1, scratch1, (addr)
// bnez scratch1, loop
- BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW32(Ordering, STI)), Scratch1Reg)
+ BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW32(Ordering)), Scratch1Reg)
.addReg(Scratch1Reg)
.addReg(AddrReg);
BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE))
@@ -708,13 +687,12 @@ static void doMaskedAtomicMinMaxOpExpansion(
bool RISCVExpandAtomicPseudoImpl::expandAtomicMinMaxOp(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
AtomicRMWInst::BinOp BinOp, bool IsMasked, int Width,
- MachineBasicBlock::iterator &NextMBBI) {
+ MachineBasicBlock::iterator &NextMBBI) const {
// Using MIN(U)/MAX(U) is preferrable if permitted
if (STI->hasPermissiveZalrsc() && STI->hasStdExtZbb() && !IsMasked)
return expandAtomicBinOp(MBB, MBBI, BinOp, IsMasked, Width, NextMBBI);
MachineInstr &MI = *MBBI;
- DebugLoc DL = MI.getDebugLoc();
MachineFunction *MF = MBB.getParent();
auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
auto LoopIfBodyMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
@@ -738,12 +716,11 @@ bool RISCVExpandAtomicPseudoImpl::expandAtomicMinMaxOp(
MBB.addSuccessor(LoopHeadMBB);
if (!IsMasked)
- doAtomicMinMaxOpExpansion(TII, MI, DL, &MBB, LoopHeadMBB, LoopIfBodyMBB,
- LoopTailMBB, DoneMBB, BinOp, Width, STI);
+ doAtomicMinMaxOpExpansion(MI, LoopHeadMBB, LoopIfBodyMBB, LoopTailMBB,
+ BinOp, Width);
else
- doMaskedAtomicMinMaxOpExpansion(TII, MI, DL, &MBB, LoopHeadMBB,
- LoopIfBodyMBB, LoopTailMBB, DoneMBB, BinOp,
- Width, STI);
+ doMaskedAtomicMinMaxOpExpansion(MI, LoopHeadMBB, LoopIfBodyMBB, LoopTailMBB,
+ BinOp, Width);
NextMBBI = MBB.end();
MI.eraseFromParent();
@@ -768,11 +745,10 @@ bool RISCVExpandAtomicPseudoImpl::expandAtomicMinMaxOp(
// On success, returns true and deletes the matching BNE or AND+BNE, sets the
// LoopHeadBNETarget argument to the target that should be used within the
// loop head, and removes that block as a successor to MBB.
-bool tryToFoldBNEOnCmpXchgResult(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- Register DestReg, Register CmpValReg,
- Register MaskReg,
- MachineBasicBlock *&LoopHeadBNETarget) {
+bool RISCVExpandAtomicPseudoImpl::tryToFoldBNEOnCmpXchgResult(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg,
+ Register CmpValReg, Register MaskReg,
+ MachineBasicBlock *&LoopHeadBNETarget) const {
SmallVector<MachineInstr *> ToErase;
auto E = MBB.end();
if (MBBI == E)
@@ -825,7 +801,7 @@ bool tryToFoldBNEOnCmpXchgResult(MachineBasicBlock &MBB,
bool RISCVExpandAtomicPseudoImpl::expandAtomicCmpXchg(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, bool IsMasked,
- int Width, MachineBasicBlock::iterator &NextMBBI) {
+ int Width, MachineBasicBlock::iterator &NextMBBI) const {
MachineInstr &MI = *MBBI;
DebugLoc DL = MI.getDebugLoc();
MachineFunction *MF = MBB.getParent();
@@ -865,8 +841,7 @@ bool RISCVExpandAtomicPseudoImpl::expandAtomicCmpXchg(
// .loophead:
// lr.[w|d] dest, (addr)
// bne dest, cmpval, done
- BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width, STI)),
- DestReg)
+ BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg)
.addReg(AddrReg);
BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE))
.addReg(DestReg)
@@ -875,8 +850,7 @@ bool RISCVExpandAtomicPseudoImpl::expandAtomicCmpXchg(
// .looptail:
// sc.[w|d] scratch, newval, (addr)
// bnez scratch, loophead
- BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width, STI)),
- ScratchReg)
+ BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg)
.addReg(NewValReg)
.addReg(AddrReg);
BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE))
@@ -889,8 +863,7 @@ bool RISCVExpandAtomicPseudoImpl::expandAtomicCmpXchg(
// and scratch, dest, mask
// bne scratch, cmpval, done
Register MaskReg = MI.getOperand(5).getReg();
- BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width, STI)),
- DestReg)
+ BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg)
.addReg(AddrReg);
BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), ScratchReg)
.addReg(DestReg)
@@ -906,10 +879,9 @@ bool RISCVExpandAtomicPseudoImpl::expandAtomicCmpXchg(
// xor scratch, dest, scratch
// sc.w scratch, scratch, (adrr)
// bnez scratch, loophead
- insertMaskedMerge(TII, DL, LoopTailMBB, ScratchReg, DestReg, NewValReg,
- MaskReg, ScratchReg);
- BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width, STI)),
- ScratchReg)
+ insertMaskedMerge(DL, LoopTailMBB, ScratchReg, DestReg, NewValReg, MaskReg,
+ ScratchReg);
+ BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg)
.addReg(ScratchReg)
.addReg(AddrReg);
BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE))
@@ -929,7 +901,7 @@ bool RISCVExpandAtomicPseudoImpl::expandAtomicCmpXchg(
return true;
}
-} // end of anonymous namespace
+char RISCVExpandAtomicPseudoLegacy::ID = 0;
INITIALIZE_PASS(RISCVExpandAtomicPseudoLegacy, "riscv-expand-atomic-pseudo",
RISCV_EXPAND_ATOMIC_PSEUDO_NAME, false, false)
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoBase.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoBase.cpp
new file mode 100644
index 0000000000000..deef2059927ec
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoBase.cpp
@@ -0,0 +1,59 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+//===----------------------------------------------------------------------===//
+
+#include "RISCVExpandPseudoBase.h"
+#include "RISCVInstrInfo.h"
+#include "RISCVSubtarget.h"
+
+using namespace llvm;
+
+#ifndef NDEBUG
+static unsigned getFuncSizeFromInsts(const MachineFunction &MF,
+ const RISCVInstrInfo *TII) {
+ unsigned Size = 0;
+ for (auto &MBB : MF)
+ for (auto &MI : MBB)
+ Size += TII->getInstSizeInBytes(MI);
+ return Size;
+}
+#endif
+
+bool RISCVExpandPseudoImplBase::run(MachineFunction &MF) {
+ STI = &MF.getSubtarget<RISCVSubtarget>();
+ TII = STI->getInstrInfo();
+
+#ifndef NDEBUG
+ const unsigned OldSize = getFuncSizeFromInsts(MF, TII);
+#endif
+
+ bool Modified = false;
+ for (auto &MBB : MF)
+ Modified |= expandMBB(MBB);
+
+#ifndef NDEBUG
+ const unsigned NewSize = getFuncSizeFromInsts(MF, TII);
+ assert(OldSize >= NewSize &&
+ "Expanding Pseudos should not increase function size estimate");
+#endif
+ return Modified;
+}
+
+bool RISCVExpandPseudoImplBase::expandMBB(MachineBasicBlock &MBB) const {
+ bool Modified = false;
+
+ MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
+ while (MBBI != E) {
+ MachineBasicBlock::iterator NMBBI = std::next(MBBI);
+ Modified |= expandMI(MBB, MBBI, NMBBI);
+ MBBI = NMBBI;
+ }
+
+ return Modified;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoBase.h b/llvm/lib/Target/RISCV/RISCVExpandPseudoBase.h
new file mode 100644
index 0000000000000..03ebe8e7d6087
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoBase.h
@@ -0,0 +1,41 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the base class used by the several RISC-V Pseudo
+// Instruction Expansion passes. This avoids having to re-implement some of the
+// boilerplate needed in these passes.
+//
+//===----------------------------------------------------------------------===//
+
+#include "RISCV.h"
+#include "llvm/CodeGen/MachineFunction.h"
+
+namespace llvm {
+
+class RISCVSubtarget;
+class RISCVInstrInfo;
+
+class RISCVExpandPseudoImplBase {
+public:
+ bool run(MachineFunction &MF);
+
+ virtual ~RISCVExpandPseudoImplBase() = default;
+
+protected:
+ const RISCVSubtarget *STI;
+ const RISCVInstrInfo *TII;
+
+ virtual bool expandMI(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) const;
+
+private:
+ bool expandMBB(MachineBasicBlock &MBB) const;
+};
+
+} // namespace llvm
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
index 113298f63b174..1c6d12494e2aa 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -13,9 +13,9 @@
//===----------------------------------------------------------------------===//
#include "RISCV.h"
+#include "RISCVExpandPseudoBase.h"
#include "RISCVInstrInfo.h"
#include "RISCVSubtarget.h"
-
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -26,43 +26,38 @@ using namespace llvm;
namespace {
-class RISCVExpandPseudoImpl {
-public:
- const RISCVSubtarget *STI;
- const RISCVInstrInfo *TII;
- bool run(MachineFunction &MF);
-
-private:
- bool expandMBB(MachineBasicBlock &MBB);
+class RISCVExpandPseudoImpl final : public RISCVExpandPseudoImplBase {
bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI);
+ MachineBasicBlock::iterator &NextMBBI) const override;
+
bool expandCCOp(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI);
+ MachineBasicBlock::iterator &NextMBBI) const;
+
bool expandCCOpToCMov(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI);
+ MachineBasicBlock::iterator MBBI) const;
+
bool expandVMSET_VMCLR(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, unsigned Opcode);
+ MachineBasicBlock::iterator MBBI,
+ unsigned Opcode) const;
+
bool expandMV_FPR16INX(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI);
+ MachineBasicBlock::iterator MBBI) const;
+
bool expandMV_FPR32INX(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI);
+ MachineBasicBlock::iterator MBBI) const;
+
bool expandRV32ZdinxStore(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI);
+ MachineBasicBlock::iterator MBBI) const;
+
bool expandRV32ZdinxLoad(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI);
- bool expandPseudoReadVLENBViaVSETVLIX0(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI);
+ MachineBasicBlock::iterator MBBI) const;
+
+ bool
+ expandPseudoReadVLENBViaVSETVLIX0(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI) const;
+
bool expandPseudoClearFPR64(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI);
-#ifndef NDEBUG
- unsigned getInstSizeInBytes(const MachineFunction &MF) const {
- unsigned Size = 0;
- for (auto &MBB : MF)
- for (auto &MI : MBB)
- Size += TII->getInstSizeInBytes(MI);
- return Size;
- }
-#endif
+ MachineBasicBlock::iterator MBBI) const;
};
class RISCVExpandPseudoLegacy : public MachineFunctionPass {
@@ -78,43 +73,11 @@ class RISCVExpandPseudoLegacy : public MachineFunctionPass {
StringRef getPassName() const override { return RISCV_EXPAND_PSEUDO_NAME; }
};
-char RISCVExpandPseudoLegacy::ID = 0;
+} // anonymous namespace
-bool RISCVExpandPseudoImpl::run(MachineFunction &MF) {
- STI = &MF.getSubtarget<RISCVSubtarget>();
- TII = STI->getInstrInfo();
-
-#ifndef NDEBUG
- const unsigned OldSize = getInstSizeInBytes(MF);
-#endif
-
- bool Modified = false;
- for (auto &MBB : MF)
- Modified |= expandMBB(MBB);
-
-#ifndef NDEBUG
- const unsigned NewSize = getInstSizeInBytes(MF);
- assert(OldSize >= NewSize);
-#endif
- return Modified;
-}
-
-bool RISCVExpandPseudoImpl::expandMBB(MachineBasicBlock &MBB) {
- bool Modified = false;
-
- MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
- while (MBBI != E) {
- MachineBasicBlock::iterator NMBBI = std::next(MBBI);
- Modified |= expandMI(MBB, MBBI, NMBBI);
- MBBI = NMBBI;
- }
-
- return Modified;
-}
-
-bool RISCVExpandPseudoImpl::expandMI(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
+bool RISCVExpandPseudoImpl::expandMI(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) const {
// RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
// expanded instructions for each pseudo is correct in the Size field of the
// tablegen definition for the pseudo.
@@ -206,9 +169,9 @@ bool RISCVExpandPseudoImpl::expandMI(MachineBasicBlock &MBB,
return false;
}
-bool RISCVExpandPseudoImpl::expandCCOp(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
+bool RISCVExpandPseudoImpl::expandCCOp(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) const {
// First try expanding to a Conditional Move rather than a branch+mv
if (expandCCOpToCMov(MBB, MBBI))
return true;
@@ -335,8 +298,8 @@ bool RISCVExpandPseudoImpl::expandCCOp(MachineBasicBlock &MBB,
return true;
}
-bool RISCVExpandPseudoImpl::expandCCOpToCMov(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI) {
+bool RISCVExpandPseudoImpl::expandCCOpToCMov(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
MachineInstr &MI = *MBBI;
DebugLoc DL = MI.getDebugLoc();
@@ -464,7 +427,7 @@ bool RISCVExpandPseudoImpl::expandCCOpToCMov(MachineBasicBlock &MBB,
bool RISCVExpandPseudoImpl::expandVMSET_VMCLR(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
- unsigned Opcode) {
+ unsigned Opcode) const {
DebugLoc DL = MBBI->getDebugLoc();
Register DstReg = MBBI->getOperand(0).getReg();
const MCInstrDesc &Desc = TII->get(Opcode);
@@ -476,7 +439,7 @@ bool RISCVExpandPseudoImpl::expandVMSET_VMCLR(MachineBasicBlock &MBB,
}
bool RISCVExpandPseudoImpl::expandMV_FPR16INX(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
DebugLoc DL = MBBI->getDebugLoc();
const TargetRegisterInfo *TRI = STI->getRegisterInfo();
Register DstReg = TRI->getMatchingSuperReg(
@@ -493,7 +456,7 @@ bool RISCVExpandPseudoImpl::expandMV_FPR16INX(
}
bool RISCVExpandPseudoImpl::expandMV_FPR32INX(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
DebugLoc DL = MBBI->getDebugLoc();
const TargetRegisterInfo *TRI = STI->getRegisterInfo();
Register DstReg = TRI->getMatchingSuperReg(
@@ -513,7 +476,7 @@ bool RISCVExpandPseudoImpl::expandMV_FPR32INX(
// floating-point value into memory by generating an equivalent instruction
// sequence for RV32.
bool RISCVExpandPseudoImpl::expandRV32ZdinxStore(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
DebugLoc DL = MBBI->getDebugLoc();
const TargetRegisterInfo *TRI = STI->getRegisterInfo();
Register Lo =
@@ -562,7 +525,7 @@ bool RISCVExpandPseudoImpl::expandRV32ZdinxStore(
// floating-point value from memory into an equivalent instruction sequence for
// RV32.
bool RISCVExpandPseudoImpl::expandRV32ZdinxLoad(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
DebugLoc DL = MBBI->getDebugLoc();
const TargetRegisterInfo *TRI = STI->getRegisterInfo();
Register Lo =
@@ -620,7 +583,7 @@ bool RISCVExpandPseudoImpl::expandRV32ZdinxLoad(
}
bool RISCVExpandPseudoImpl::expandPseudoReadVLENBViaVSETVLIX0(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
DebugLoc DL = MBBI->getDebugLoc();
Register Dst = MBBI->getOperand(0).getReg();
unsigned Mul = MBBI->getOperand(1).getImm();
@@ -638,7 +601,7 @@ bool RISCVExpandPseudoImpl::expandPseudoReadVLENBViaVSETVLIX0(
}
bool RISCVExpandPseudoImpl::expandPseudoClearFPR64(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
const DebugLoc &DL = MBBI->getDebugLoc();
Register Dst = MBBI->getOperand(0).getReg();
@@ -654,14 +617,12 @@ bool RISCVExpandPseudoImpl::expandPseudoClearFPR64(
return true;
}
-} // end of anonymous namespace
+char RISCVExpandPseudoLegacy::ID = 0;
INITIALIZE_PASS(RISCVExpandPseudoLegacy, "riscv-expand-pseudo",
RISCV_EXPAND_PSEUDO_NAME, false, false)
-namespace llvm {
-
-FunctionPass *createRISCVExpandPseudoLegacyPass() {
+FunctionPass *llvm::createRISCVExpandPseudoLegacyPass() {
return new RISCVExpandPseudoLegacy();
}
@@ -673,5 +634,3 @@ RISCVExpandPseudoPass::run(MachineFunction &MF,
return PreservedAnalyses::all();
return getMachineFunctionPassPreservedAnalyses();
}
-
-} // end of namespace llvm
diff --git a/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
index b81d57bc38f3c..f3ade17e4fdb9 100644
--- a/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
@@ -13,7 +13,9 @@
//===----------------------------------------------------------------------===//
#include "RISCV.h"
+#include "RISCVExpandPseudoBase.h"
#include "RISCVInstrInfo.h"
+#include "RISCVSubtarget.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -24,20 +26,21 @@ using namespace llvm;
namespace {
-class RISCVPostRAExpandPseudoImpl {
-public:
- const RISCVInstrInfo *TII;
- bool run(MachineFunction &MF);
-
-private:
- bool expandMBB(MachineBasicBlock &MBB);
+class RISCVPostRAExpandPseudoImpl final : public RISCVExpandPseudoImplBase {
bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI);
- bool expandMovImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
- bool expandMovAddr(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
- bool expandMERGE(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
+ MachineBasicBlock::iterator &NextMBBI) const override;
+
+ bool expandMovImm(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI) const;
+
+ bool expandMovAddr(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI) const;
+
+ bool expandMERGE(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI) const;
+
bool expandAddUpperImm(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI);
+ MachineBasicBlock::iterator MBBI) const;
};
class RISCVPostRAExpandPseudoLegacy : public MachineFunctionPass {
@@ -60,32 +63,11 @@ class RISCVPostRAExpandPseudoLegacy : public MachineFunctionPass {
}
};
-char RISCVPostRAExpandPseudoLegacy::ID = 0;
-
-bool RISCVPostRAExpandPseudoImpl::run(MachineFunction &MF) {
- TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo());
- bool Modified = false;
- for (auto &MBB : MF)
- Modified |= expandMBB(MBB);
- return Modified;
-}
-
-bool RISCVPostRAExpandPseudoImpl::expandMBB(MachineBasicBlock &MBB) {
- bool Modified = false;
-
- MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
- while (MBBI != E) {
- MachineBasicBlock::iterator NMBBI = std::next(MBBI);
- Modified |= expandMI(MBB, MBBI, NMBBI);
- MBBI = NMBBI;
- }
-
- return Modified;
-}
+} // anonymous namespace
bool RISCVPostRAExpandPseudoImpl::expandMI(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
+ MachineBasicBlock::iterator &NextMBBI) const {
switch (MBBI->getOpcode()) {
case RISCV::PseudoMovImm:
return expandMovImm(MBB, MBBI);
@@ -95,13 +77,13 @@ bool RISCVPostRAExpandPseudoImpl::expandMI(
return expandAddUpperImm(MBB, MBBI);
case RISCV::PseudoMERGE:
return expandMERGE(MBB, MBBI);
- default:
- return false;
}
+
+ return false;
}
bool RISCVPostRAExpandPseudoImpl::expandMovImm(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
DebugLoc DL = MBBI->getDebugLoc();
int64_t Val = MBBI->getOperand(1).getImm();
@@ -118,7 +100,7 @@ bool RISCVPostRAExpandPseudoImpl::expandMovImm(
}
bool RISCVPostRAExpandPseudoImpl::expandMovAddr(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
DebugLoc DL = MBBI->getDebugLoc();
Register DstReg = MBBI->getOperand(0).getReg();
@@ -138,7 +120,7 @@ bool RISCVPostRAExpandPseudoImpl::expandMovAddr(
}
bool RISCVPostRAExpandPseudoImpl::expandAddUpperImm(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
DebugLoc DL = MBBI->getDebugLoc();
Register DstReg = MBBI->getOperand(0).getReg();
@@ -163,7 +145,7 @@ bool RISCVPostRAExpandPseudoImpl::expandAddUpperImm(
/// Transfer implicit operands on the pseudo instruction to the
/// instructions created from the expansion.
-static void transferImpOps(MachineInstr &OldMI, MachineInstrBuilder &MI) {
+static void transferImpOps(const MachineInstr &OldMI, MachineInstrBuilder &MI) {
const MCInstrDesc &Desc = OldMI.getDesc();
for (const MachineOperand &MO :
llvm::drop_begin(OldMI.operands(), Desc.getNumOperands())) {
@@ -174,7 +156,7 @@ static void transferImpOps(MachineInstr &OldMI, MachineInstrBuilder &MI) {
// Expand PseudoMERGE to MERGE, MVM, or MVMN.
bool RISCVPostRAExpandPseudoImpl::expandMERGE(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
MachineInstr &MI = *MBBI;
DebugLoc DL = MI.getDebugLoc();
@@ -228,13 +210,12 @@ bool RISCVPostRAExpandPseudoImpl::expandMERGE(
return true;
}
-} // end of anonymous namespace
+char RISCVPostRAExpandPseudoLegacy::ID = 0;
INITIALIZE_PASS(RISCVPostRAExpandPseudoLegacy, "riscv-post-ra-expand-pseudo",
RISCV_POST_RA_EXPAND_PSEUDO_NAME, false, false)
-namespace llvm {
-FunctionPass *createRISCVPostRAExpandPseudoLegacyPass() {
+FunctionPass *llvm::createRISCVPostRAExpandPseudoLegacyPass() {
return new RISCVPostRAExpandPseudoLegacy();
}
@@ -249,5 +230,3 @@ RISCVPostRAExpandPseudoPass::run(MachineFunction &MF,
PA.preserveSet<CFGAnalyses>();
return PA;
}
-
-} // end of namespace llvm
diff --git a/llvm/lib/Target/RISCV/RISCVPreRAExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVPreRAExpandPseudoInsts.cpp
index 03994ac43aa2f..e6da34192b8ca 100644
--- a/llvm/lib/Target/RISCV/RISCVPreRAExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVPreRAExpandPseudoInsts.cpp
@@ -12,10 +12,9 @@
//===----------------------------------------------------------------------===//
#include "RISCV.h"
+#include "RISCVExpandPseudoBase.h"
#include "RISCVInstrInfo.h"
#include "RISCVSubtarget.h"
-
-#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/MC/MCContext.h"
@@ -27,45 +26,28 @@ using namespace llvm;
namespace {
-class RISCVPreRAExpandPseudoImpl {
-public:
- const RISCVSubtarget *STI;
- const RISCVInstrInfo *TII;
- bool run(MachineFunction &MF);
-
-private:
- bool expandMBB(MachineBasicBlock &MBB);
+class RISCVPreRAExpandPseudoImpl final : public RISCVExpandPseudoImplBase {
bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI);
+ MachineBasicBlock::iterator &NextMBBI) const override;
+
bool expandAuipcInstPair(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI,
- unsigned FlagsHi, unsigned SecondOpcode);
+ MachineBasicBlock::iterator MBBI, unsigned FlagsHi,
+ unsigned SecondOpcode) const;
+
bool expandLoadLocalAddress(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI);
+ MachineBasicBlock::iterator MBBI) const;
+
bool expandLoadGlobalAddress(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI);
+ MachineBasicBlock::iterator MBBI) const;
+
bool expandLoadTLSIEAddress(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI);
+ MachineBasicBlock::iterator MBBI) const;
+
bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI);
+ MachineBasicBlock::iterator MBBI) const;
+
bool expandLoadTLSDescAddress(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI);
-
-#ifndef NDEBUG
- unsigned getInstSizeInBytes(const MachineFunction &MF) const {
- unsigned Size = 0;
- for (auto &MBB : MF)
- for (auto &MI : MBB)
- Size += TII->getInstSizeInBytes(MI);
- return Size;
- }
-#endif
+ MachineBasicBlock::iterator MBBI) const;
};
class RISCVPreRAExpandPseudoLegacy : public MachineFunctionPass {
@@ -91,63 +73,31 @@ class RISCVPreRAExpandPseudoLegacy : public MachineFunctionPass {
}
};
-char RISCVPreRAExpandPseudoLegacy::ID = 0;
-
-bool RISCVPreRAExpandPseudoImpl::run(MachineFunction &MF) {
- STI = &MF.getSubtarget<RISCVSubtarget>();
- TII = STI->getInstrInfo();
-
-#ifndef NDEBUG
- const unsigned OldSize = getInstSizeInBytes(MF);
-#endif
-
- bool Modified = false;
- for (auto &MBB : MF)
- Modified |= expandMBB(MBB);
-
-#ifndef NDEBUG
- const unsigned NewSize = getInstSizeInBytes(MF);
- assert(OldSize >= NewSize);
-#endif
- return Modified;
-}
-
-bool RISCVPreRAExpandPseudoImpl::expandMBB(MachineBasicBlock &MBB) {
- bool Modified = false;
-
- MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
- while (MBBI != E) {
- MachineBasicBlock::iterator NMBBI = std::next(MBBI);
- Modified |= expandMI(MBB, MBBI, NMBBI);
- MBBI = NMBBI;
- }
-
- return Modified;
-}
+} // anonymous namespace
bool RISCVPreRAExpandPseudoImpl::expandMI(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
+ MachineBasicBlock::iterator &NextMBBI) const {
switch (MBBI->getOpcode()) {
case RISCV::PseudoLLA:
- return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
+ return expandLoadLocalAddress(MBB, MBBI);
case RISCV::PseudoLGA:
- return expandLoadGlobalAddress(MBB, MBBI, NextMBBI);
+ return expandLoadGlobalAddress(MBB, MBBI);
case RISCV::PseudoLA_TLS_IE:
- return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
+ return expandLoadTLSIEAddress(MBB, MBBI);
case RISCV::PseudoLA_TLS_GD:
- return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
+ return expandLoadTLSGDAddress(MBB, MBBI);
case RISCV::PseudoLA_TLSDESC:
- return expandLoadTLSDescAddress(MBB, MBBI, NextMBBI);
+ return expandLoadTLSDescAddress(MBB, MBBI);
}
+
return false;
}
bool RISCVPreRAExpandPseudoImpl::expandAuipcInstPair(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
- unsigned SecondOpcode) {
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned FlagsHi,
+ unsigned SecondOpcode) const {
MachineFunction *MF = MBB.getParent();
MachineInstr &MI = *MBBI;
DebugLoc DL = MI.getDebugLoc();
@@ -177,38 +127,29 @@ bool RISCVPreRAExpandPseudoImpl::expandAuipcInstPair(
}
bool RISCVPreRAExpandPseudoImpl::expandLoadLocalAddress(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
- return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
- RISCV::ADDI);
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
+ return expandAuipcInstPair(MBB, MBBI, RISCVII::MO_PCREL_HI, RISCV::ADDI);
}
bool RISCVPreRAExpandPseudoImpl::expandLoadGlobalAddress(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
- return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI,
- SecondOpcode);
+ return expandAuipcInstPair(MBB, MBBI, RISCVII::MO_GOT_HI, SecondOpcode);
}
bool RISCVPreRAExpandPseudoImpl::expandLoadTLSIEAddress(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
- return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
- SecondOpcode);
+ return expandAuipcInstPair(MBB, MBBI, RISCVII::MO_TLS_GOT_HI, SecondOpcode);
}
bool RISCVPreRAExpandPseudoImpl::expandLoadTLSGDAddress(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
- return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
- RISCV::ADDI);
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
+ return expandAuipcInstPair(MBB, MBBI, RISCVII::MO_TLS_GD_HI, RISCV::ADDI);
}
bool RISCVPreRAExpandPseudoImpl::expandLoadTLSDescAddress(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
MachineFunction *MF = MBB.getParent();
MachineInstr &MI = *MBBI;
DebugLoc DL = MI.getDebugLoc();
@@ -251,14 +192,12 @@ bool RISCVPreRAExpandPseudoImpl::expandLoadTLSDescAddress(
return true;
}
-} // end of anonymous namespace
+char RISCVPreRAExpandPseudoLegacy::ID = 0;
INITIALIZE_PASS(RISCVPreRAExpandPseudoLegacy, "riscv-pre-ra-expand-pseudo",
RISCV_PRERA_EXPAND_PSEUDO_NAME, false, false)
-namespace llvm {
-
-FunctionPass *createRISCVPreRAExpandPseudoLegacyPass() {
+FunctionPass *llvm::createRISCVPreRAExpandPseudoLegacyPass() {
return new RISCVPreRAExpandPseudoLegacy();
}
@@ -274,5 +213,3 @@ RISCVPreRAExpandPseudoPass::run(MachineFunction &MF,
PA.preserveSet<CFGAnalyses>();
return PA;
}
-
-} // end of namespace llvm
>From e32c859bae4830a73c220d7dab47b6404a8287a9 Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Sat, 22 Aug 2026 17:28:48 -0700
Subject: [PATCH 2/3] Header Guard
---
llvm/lib/Target/RISCV/RISCVExpandPseudoBase.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoBase.h b/llvm/lib/Target/RISCV/RISCVExpandPseudoBase.h
index 03ebe8e7d6087..f40a66fb9cfcc 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoBase.h
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoBase.h
@@ -12,6 +12,9 @@
//
//===----------------------------------------------------------------------===//
+#ifndef LLVM_LIB_TARGET_RISCV_RISCVEXPANDPSEUDOBASE_H
+#define LLVM_LIB_TARGET_RISCV_RISCVEXPANDPSEUDOBASE_H
+
#include "RISCV.h"
#include "llvm/CodeGen/MachineFunction.h"
@@ -39,3 +42,5 @@ class RISCVExpandPseudoImplBase {
};
} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_RISCV_RISCVEXPANDPSEUDOBASE_H
>From 2065e19f3737cefe9bfb12398a46eb9d0d7b9ef9 Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Sat, 22 Aug 2026 17:37:46 -0700
Subject: [PATCH 3/3] Docs, NYI implementation of expandMI
---
llvm/lib/Target/RISCV/RISCVExpandPseudoBase.h | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoBase.h b/llvm/lib/Target/RISCV/RISCVExpandPseudoBase.h
index f40a66fb9cfcc..d6e491a7e8877 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoBase.h
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoBase.h
@@ -25,17 +25,32 @@ class RISCVInstrInfo;
class RISCVExpandPseudoImplBase {
public:
+ /// Expand a subset of pseudos in the current function. Returns whether the
+ /// function was modified.
+ ///
+ /// This will assert if expansion increased the estimated size of the
+ /// function.
bool run(MachineFunction &MF);
virtual ~RISCVExpandPseudoImplBase() = default;
protected:
+ /// The Subtarget for the current function.
const RISCVSubtarget *STI;
+
+ /// The derived TargetInstrInfo for the current function.
const RISCVInstrInfo *TII;
+ /// This method should be implemented to expand the instruction at `*MBBI`.
+ /// The iteration over the current basic block will continue at `NextMBBI`.
+ /// This method should return `true` if it replaced the instruction at
+ /// `*MBBI`.
virtual bool expandMI(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) const;
+ MachineBasicBlock::iterator &NextMBBI) const {
+ reportFatalInternalError("Expand Pseudos not yet implemented.");
+ return false;
+ }
private:
bool expandMBB(MachineBasicBlock &MBB) const;
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