[llvm] [RISCV] Fix size of PseudoMERGE (PR #218171)

[Sam Elliott via llvm-commits]

https://github.com/lenary created https://github.com/llvm/llvm-project/pull/218171

This can expand to two 4-byte instructions, so mark it as size 8. Usually it will expand to just one 4-byte instruction.

This was found in #218170.

>From 8aeebb7277b49ce3b853c493e2e354408d8db0b9 Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Sat, 22 Aug 2026 17:07:43 -0700
Subject: [PATCH] [RISCV] Fix size of PseudoMERGE

This can expand to two 4-byte instructions, so mark it as size 8.
Usually it will expand to just one 4-byte instruction.

This was found in #218170.
---
 llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 1 +
 1 file changed, 1 insertion(+)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index ac893d83cf3ac..a68a589c0f964 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -2062,6 +2062,7 @@ let Predicates = [HasStdExtP] in {
   // Pseudo version of MERGE without the tied constraint. Will be expanded to
   // MERGE, MVM, or MVMN after register allocation.
   // dst = (~rd & rs1) | (rd & rs2)
+  let Size = 8 in
   def PseudoMERGE : Pseudo<(outs GPR:$dst), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
                            []>;
   def : Pat<(XLenVT (or (and GPR:$rd, GPR:$rs2), (and (not GPR:$rd), GPR:$rs1))),