[llvm] 0f9791c - [AArch64][GlobalISel] Use integer types for scalable vector insert / extract index. (#218150)

[via llvm-commits]

Author: David Green
Date: 2026-08-22T22:45:06Z
New Revision: 0f9791c9aa9e040a20e50bcd10aa07f21c272825

URL: https://github.com/llvm/llvm-project/commit/0f9791c9aa9e040a20e50bcd10aa07f21c272825
DIFF: https://github.com/llvm/llvm-project/commit/0f9791c9aa9e040a20e50bcd10aa07f21c272825.diff

LOG: [AArch64][GlobalISel] Use integer types for scalable vector insert / extract index. (#218150)

Added: 
    

Modified: 
    llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
    llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-subvector.ll

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 8777c8f51dd7b..baac98561f25b 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -4154,7 +4154,7 @@ bool IRTranslatorImpl::translateInsertVector(const User &U,
     if (isa<ScalableVectorType>(U.getOperand(0)->getType())) {
       // We are inserting an illegal fixed vector into a scalable
       // vector, use a scalar element insert.
-      LLT VecIdxTy = LLT::scalar(PreferredVecIdxWidth);
+      LLT VecIdxTy = LLT::integer(PreferredVecIdxWidth);
       Register Idx = getOrCreateVReg(*CI);
       auto ScaledIndex = MIRBuilder.buildMul(
           VecIdxTy, MIRBuilder.buildVScale(VecIdxTy, 1), Idx);
@@ -4233,7 +4233,7 @@ bool IRTranslatorImpl::translateExtractVector(const User &U,
     if (isa<ScalableVectorType>(U.getOperand(0)->getType())) {
       // We are extracting an illegal fixed vector from a scalable
       // vector, use a scalar element extract.
-      LLT VecIdxTy = LLT::scalar(PreferredVecIdxWidth);
+      LLT VecIdxTy = LLT::integer(PreferredVecIdxWidth);
       Register Idx = getOrCreateVReg(*CI);
       auto ScaledIndex = MIRBuilder.buildMul(
           VecIdxTy, MIRBuilder.buildVScale(VecIdxTy, 1), Idx);

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-subvector.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-subvector.ll
index 546aa0f874e64..1144466e677ec 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-subvector.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-subvector.ll
@@ -189,9 +189,9 @@ define i32 @extract_v4i32_vector_extract_const_illegal_scalable(<vscale x 4 x i3
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
   ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
-  ; CHECK-NEXT:   [[VSCALE:%[0-9]+]]:_(s64) = G_VSCALE i64 1
-  ; CHECK-NEXT:   [[MUL:%[0-9]+]]:_(s64) = G_MUL [[VSCALE]], [[C]]
-  ; CHECK-NEXT:   [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 4 x i32>), [[MUL]](s64)
+  ; CHECK-NEXT:   [[VSCALE:%[0-9]+]]:_(i64) = G_VSCALE i64 1
+  ; CHECK-NEXT:   [[MUL:%[0-9]+]]:_(i64) = G_MUL [[VSCALE]], [[C]]
+  ; CHECK-NEXT:   [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 4 x i32>), [[MUL]](i64)
   ; CHECK-NEXT:   G_STORE [[EVEC]](i32), [[COPY1]](p0) :: (store (i32) into %ir.p, align 16)
   ; CHECK-NEXT:   $w0 = COPY [[C1]](i32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
@@ -213,9 +213,9 @@ define i32 @extract_v4i32_vector_insert_const_illegal_scalable(<vscale x 4 x i32
   ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(p0) = COPY $x1
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
   ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
-  ; CHECK-NEXT:   [[VSCALE:%[0-9]+]]:_(s64) = G_VSCALE i64 1
-  ; CHECK-NEXT:   [[MUL:%[0-9]+]]:_(s64) = G_MUL [[VSCALE]], [[C]]
-  ; CHECK-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x i32>) = G_INSERT_VECTOR_ELT [[COPY]], [[UV]](i32), [[MUL]](s64)
+  ; CHECK-NEXT:   [[VSCALE:%[0-9]+]]:_(i64) = G_VSCALE i64 1
+  ; CHECK-NEXT:   [[MUL:%[0-9]+]]:_(i64) = G_MUL [[VSCALE]], [[C]]
+  ; CHECK-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x i32>) = G_INSERT_VECTOR_ELT [[COPY]], [[UV]](i32), [[MUL]](i64)
   ; CHECK-NEXT:   G_STORE [[IVEC]](<vscale x 4 x i32>), [[COPY3]](p0) :: (store (<vscale x 4 x i32>) into %ir.p)
   ; CHECK-NEXT:   $w0 = COPY [[C1]](i32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0