[llvm] [RISCV][NFC] Split PreRAExpandPseudo to new file (PR #218167)
Sam Elliott via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 22 15:17:44 PDT 2026
https://github.com/lenary created https://github.com/llvm/llvm-project/pull/218167
Also update the comments on all the other ExpandPseudo passes, to clarify where they are run in the pipeline, and that there are many target-specific pseudo expansion passes, in addition to the generic passes.
>From 5c6dc2fc7a5c8d71aaabfe77e880fc1c86e69b70 Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Sat, 22 Aug 2026 11:30:21 -0700
Subject: [PATCH] [RISCV][NFC] Split PreRAExpandPseudo to new file
Also update the comments on all the other ExpandPseudo passes, to
clarify where they are run in the pipeline, and that there are many
target-specific pseudo expansion passes, in addition to the generic
passes.
---
llvm/lib/Target/RISCV/CMakeLists.txt | 1 +
.../RISCV/RISCVExpandAtomicPseudoInsts.cpp | 6 +-
.../Target/RISCV/RISCVExpandPseudoInsts.cpp | 254 +---------------
.../RISCV/RISCVPostRAExpandPseudoInsts.cpp | 6 +-
.../RISCV/RISCVPreRAExpandPseudoInsts.cpp | 278 ++++++++++++++++++
5 files changed, 289 insertions(+), 256 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVPreRAExpandPseudoInsts.cpp
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt
index 27879c1dd1085..dab90facab836 100644
--- a/llvm/lib/Target/RISCV/CMakeLists.txt
+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -60,6 +60,7 @@ add_llvm_target(RISCVCodeGen
RISCVMoveMerger.cpp
RISCVOptWInstrs.cpp
RISCVPostRAExpandPseudoInsts.cpp
+ RISCVPreRAExpandPseudoInsts.cpp
RISCVPromoteConstant.cpp
RISCVPushPopOptimizer.cpp
RISCVQCRelaxMarking.cpp
diff --git a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
index 9bd66a43717e7..5348bdbb2d84b 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
//
-// This file contains a pass that expands atomic pseudo instructions into
-// target instructions. This pass should be run at the last possible moment,
+// This file contains one of the several passes that expand pseudo instructions
+// into target instructions. This pass is run at the last possible moment,
// avoiding the possibility for other passes to break the requirements for
// forward progress in the LR/SC block.
//
@@ -15,7 +15,7 @@
#include "RISCV.h"
#include "RISCVInstrInfo.h"
-#include "RISCVTargetMachine.h"
+#include "RISCVSubtarget.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
index fa9990f3ea0bc..113298f63b174 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -6,25 +6,23 @@
//
//===----------------------------------------------------------------------===//
//
-// This file contains a pass that expands pseudo instructions into target
-// instructions. This pass should be run after register allocation but before
-// the post-regalloc scheduling pass.
+// This file contains one of the four passes that expand pseudo instructions
+// into target instructions. This pass is run very late, but before atomic
+// instructions are expanded.
//
//===----------------------------------------------------------------------===//
#include "RISCV.h"
#include "RISCVInstrInfo.h"
-#include "RISCVTargetMachine.h"
+#include "RISCVSubtarget.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/MC/MCContext.h"
using namespace llvm;
#define RISCV_EXPAND_PSEUDO_NAME "RISC-V pseudo instruction expansion pass"
-#define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISC-V Pre-RA pseudo instruction expansion pass"
namespace {
@@ -656,238 +654,11 @@ bool RISCVExpandPseudoImpl::expandPseudoClearFPR64(
return true;
}
-class RISCVPreRAExpandPseudoImpl {
-public:
- const RISCVSubtarget *STI;
- const RISCVInstrInfo *TII;
- bool run(MachineFunction &MF);
-
-private:
- bool expandMBB(MachineBasicBlock &MBB);
- bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI);
- bool expandAuipcInstPair(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI,
- unsigned FlagsHi, unsigned SecondOpcode);
- bool expandLoadLocalAddress(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI);
- bool expandLoadGlobalAddress(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI);
- bool expandLoadTLSIEAddress(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI);
- bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI);
- bool expandLoadTLSDescAddress(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI);
-
-#ifndef NDEBUG
- unsigned getInstSizeInBytes(const MachineFunction &MF) const {
- unsigned Size = 0;
- for (auto &MBB : MF)
- for (auto &MI : MBB)
- Size += TII->getInstSizeInBytes(MI);
- return Size;
- }
-#endif
-};
-
-class RISCVPreRAExpandPseudoLegacy : public MachineFunctionPass {
-public:
- static char ID;
-
- RISCVPreRAExpandPseudoLegacy() : MachineFunctionPass(ID) {}
-
- bool runOnMachineFunction(MachineFunction &MF) override {
- return RISCVPreRAExpandPseudoImpl().run(MF);
- }
-
- MachineFunctionProperties getRequiredProperties() const override {
- return MachineFunctionProperties().setIsSSA();
- }
-
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.setPreservesCFG();
- MachineFunctionPass::getAnalysisUsage(AU);
- }
- StringRef getPassName() const override {
- return RISCV_PRERA_EXPAND_PSEUDO_NAME;
- }
-};
-
-char RISCVPreRAExpandPseudoLegacy::ID = 0;
-
-bool RISCVPreRAExpandPseudoImpl::run(MachineFunction &MF) {
- STI = &MF.getSubtarget<RISCVSubtarget>();
- TII = STI->getInstrInfo();
-
-#ifndef NDEBUG
- const unsigned OldSize = getInstSizeInBytes(MF);
-#endif
-
- bool Modified = false;
- for (auto &MBB : MF)
- Modified |= expandMBB(MBB);
-
-#ifndef NDEBUG
- const unsigned NewSize = getInstSizeInBytes(MF);
- assert(OldSize >= NewSize);
-#endif
- return Modified;
-}
-
-bool RISCVPreRAExpandPseudoImpl::expandMBB(MachineBasicBlock &MBB) {
- bool Modified = false;
-
- MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
- while (MBBI != E) {
- MachineBasicBlock::iterator NMBBI = std::next(MBBI);
- Modified |= expandMI(MBB, MBBI, NMBBI);
- MBBI = NMBBI;
- }
-
- return Modified;
-}
-
-bool RISCVPreRAExpandPseudoImpl::expandMI(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
-
- switch (MBBI->getOpcode()) {
- case RISCV::PseudoLLA:
- return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
- case RISCV::PseudoLGA:
- return expandLoadGlobalAddress(MBB, MBBI, NextMBBI);
- case RISCV::PseudoLA_TLS_IE:
- return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
- case RISCV::PseudoLA_TLS_GD:
- return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
- case RISCV::PseudoLA_TLSDESC:
- return expandLoadTLSDescAddress(MBB, MBBI, NextMBBI);
- }
- return false;
-}
-
-bool RISCVPreRAExpandPseudoImpl::expandAuipcInstPair(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
- unsigned SecondOpcode) {
- MachineFunction *MF = MBB.getParent();
- MachineInstr &MI = *MBBI;
- DebugLoc DL = MI.getDebugLoc();
-
- Register DestReg = MI.getOperand(0).getReg();
- Register ScratchReg =
- MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
-
- MachineOperand &Symbol = MI.getOperand(1);
- Symbol.setTargetFlags(FlagsHi);
- MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("pcrel_hi");
-
- MachineInstr *MIAUIPC =
- BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
- MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
-
- MachineInstr *SecondMI =
- BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
- .addReg(ScratchReg)
- .addSym(AUIPCSymbol, RISCVII::MO_PCREL_LO);
-
- if (MI.hasOneMemOperand())
- SecondMI->addMemOperand(*MF, *MI.memoperands_begin());
-
- MI.eraseFromParent();
- return true;
-}
-
-bool RISCVPreRAExpandPseudoImpl::expandLoadLocalAddress(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
- return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
- RISCV::ADDI);
-}
-
-bool RISCVPreRAExpandPseudoImpl::expandLoadGlobalAddress(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
- unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
- return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI,
- SecondOpcode);
-}
-
-bool RISCVPreRAExpandPseudoImpl::expandLoadTLSIEAddress(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
- unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
- return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
- SecondOpcode);
-}
-
-bool RISCVPreRAExpandPseudoImpl::expandLoadTLSGDAddress(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
- return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
- RISCV::ADDI);
-}
-
-bool RISCVPreRAExpandPseudoImpl::expandLoadTLSDescAddress(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
- MachineFunction *MF = MBB.getParent();
- MachineInstr &MI = *MBBI;
- DebugLoc DL = MI.getDebugLoc();
-
- const auto &STI = MF->getSubtarget<RISCVSubtarget>();
- unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
-
- Register FinalReg = MI.getOperand(0).getReg();
- Register DestReg =
- MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
- Register ScratchReg =
- MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
-
- MachineOperand &Symbol = MI.getOperand(1);
- Symbol.setTargetFlags(RISCVII::MO_TLSDESC_HI);
- MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("tlsdesc_hi");
-
- MachineInstr *MIAUIPC =
- BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
- MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
-
- BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
- .addReg(ScratchReg)
- .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_LOAD_LO);
-
- BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), RISCV::X10)
- .addReg(ScratchReg)
- .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_ADD_LO);
-
- BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoTLSDESCCall), RISCV::X5)
- .addReg(DestReg)
- .addImm(0)
- .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_CALL);
-
- BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), FinalReg)
- .addReg(RISCV::X10)
- .addReg(RISCV::X4);
-
- MI.eraseFromParent();
- return true;
-}
-
} // end of anonymous namespace
INITIALIZE_PASS(RISCVExpandPseudoLegacy, "riscv-expand-pseudo",
RISCV_EXPAND_PSEUDO_NAME, false, false)
-INITIALIZE_PASS(RISCVPreRAExpandPseudoLegacy, "riscv-pre-ra-expand-pseudo",
- RISCV_PRERA_EXPAND_PSEUDO_NAME, false, false)
-
namespace llvm {
FunctionPass *createRISCVExpandPseudoLegacyPass() {
@@ -903,21 +674,4 @@ RISCVExpandPseudoPass::run(MachineFunction &MF,
return getMachineFunctionPassPreservedAnalyses();
}
-FunctionPass *createRISCVPreRAExpandPseudoLegacyPass() {
- return new RISCVPreRAExpandPseudoLegacy();
-}
-
-PreservedAnalyses
-RISCVPreRAExpandPseudoPass::run(MachineFunction &MF,
- MachineFunctionAnalysisManager &MFAM) {
- MFPropsModifier _(*this, MF);
- bool Changed = RISCVPreRAExpandPseudoImpl().run(MF);
- if (!Changed)
- return PreservedAnalyses::all();
-
- PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
- PA.preserveSet<CFGAnalyses>();
- return PA;
-}
-
} // end of namespace llvm
diff --git a/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
index 1f9bed2ba147b..037f3789f5361 100644
--- a/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
@@ -6,9 +6,9 @@
//
//===----------------------------------------------------------------------===//
//
-// This file contains a pass that expands the pseudo instruction pseudolisimm32
-// into target instructions. This pass should be run during the post-regalloc
-// passes, before post RA scheduling.
+// This file contains one of the several passes that expand pseudo instructions
+// into target instructions. This pass is run after register allocation and
+// before post RA scheduling.
//
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVPreRAExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVPreRAExpandPseudoInsts.cpp
new file mode 100644
index 0000000000000..03994ac43aa2f
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVPreRAExpandPseudoInsts.cpp
@@ -0,0 +1,278 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains one of the several passes that expand pseudo instructions
+// into target instructions. This pass is run before register allocation.
+//
+//===----------------------------------------------------------------------===//
+
+#include "RISCV.h"
+#include "RISCVInstrInfo.h"
+#include "RISCVSubtarget.h"
+
+#include "llvm/CodeGen/LivePhysRegs.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/MC/MCContext.h"
+
+using namespace llvm;
+
+#define RISCV_PRERA_EXPAND_PSEUDO_NAME \
+ "RISC-V Pre-RA pseudo instruction expansion pass"
+
+namespace {
+
+class RISCVPreRAExpandPseudoImpl {
+public:
+ const RISCVSubtarget *STI;
+ const RISCVInstrInfo *TII;
+ bool run(MachineFunction &MF);
+
+private:
+ bool expandMBB(MachineBasicBlock &MBB);
+ bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI);
+ bool expandAuipcInstPair(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI,
+ unsigned FlagsHi, unsigned SecondOpcode);
+ bool expandLoadLocalAddress(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI);
+ bool expandLoadGlobalAddress(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI);
+ bool expandLoadTLSIEAddress(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI);
+ bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI);
+ bool expandLoadTLSDescAddress(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI);
+
+#ifndef NDEBUG
+ unsigned getInstSizeInBytes(const MachineFunction &MF) const {
+ unsigned Size = 0;
+ for (auto &MBB : MF)
+ for (auto &MI : MBB)
+ Size += TII->getInstSizeInBytes(MI);
+ return Size;
+ }
+#endif
+};
+
+class RISCVPreRAExpandPseudoLegacy : public MachineFunctionPass {
+public:
+ static char ID;
+
+ RISCVPreRAExpandPseudoLegacy() : MachineFunctionPass(ID) {}
+
+ bool runOnMachineFunction(MachineFunction &MF) override {
+ return RISCVPreRAExpandPseudoImpl().run(MF);
+ }
+
+ MachineFunctionProperties getRequiredProperties() const override {
+ return MachineFunctionProperties().setIsSSA();
+ }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.setPreservesCFG();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+ StringRef getPassName() const override {
+ return RISCV_PRERA_EXPAND_PSEUDO_NAME;
+ }
+};
+
+char RISCVPreRAExpandPseudoLegacy::ID = 0;
+
+bool RISCVPreRAExpandPseudoImpl::run(MachineFunction &MF) {
+ STI = &MF.getSubtarget<RISCVSubtarget>();
+ TII = STI->getInstrInfo();
+
+#ifndef NDEBUG
+ const unsigned OldSize = getInstSizeInBytes(MF);
+#endif
+
+ bool Modified = false;
+ for (auto &MBB : MF)
+ Modified |= expandMBB(MBB);
+
+#ifndef NDEBUG
+ const unsigned NewSize = getInstSizeInBytes(MF);
+ assert(OldSize >= NewSize);
+#endif
+ return Modified;
+}
+
+bool RISCVPreRAExpandPseudoImpl::expandMBB(MachineBasicBlock &MBB) {
+ bool Modified = false;
+
+ MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
+ while (MBBI != E) {
+ MachineBasicBlock::iterator NMBBI = std::next(MBBI);
+ Modified |= expandMI(MBB, MBBI, NMBBI);
+ MBBI = NMBBI;
+ }
+
+ return Modified;
+}
+
+bool RISCVPreRAExpandPseudoImpl::expandMI(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) {
+
+ switch (MBBI->getOpcode()) {
+ case RISCV::PseudoLLA:
+ return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
+ case RISCV::PseudoLGA:
+ return expandLoadGlobalAddress(MBB, MBBI, NextMBBI);
+ case RISCV::PseudoLA_TLS_IE:
+ return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
+ case RISCV::PseudoLA_TLS_GD:
+ return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
+ case RISCV::PseudoLA_TLSDESC:
+ return expandLoadTLSDescAddress(MBB, MBBI, NextMBBI);
+ }
+ return false;
+}
+
+bool RISCVPreRAExpandPseudoImpl::expandAuipcInstPair(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
+ unsigned SecondOpcode) {
+ MachineFunction *MF = MBB.getParent();
+ MachineInstr &MI = *MBBI;
+ DebugLoc DL = MI.getDebugLoc();
+
+ Register DestReg = MI.getOperand(0).getReg();
+ Register ScratchReg =
+ MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
+
+ MachineOperand &Symbol = MI.getOperand(1);
+ Symbol.setTargetFlags(FlagsHi);
+ MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("pcrel_hi");
+
+ MachineInstr *MIAUIPC =
+ BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
+ MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
+
+ MachineInstr *SecondMI =
+ BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
+ .addReg(ScratchReg)
+ .addSym(AUIPCSymbol, RISCVII::MO_PCREL_LO);
+
+ if (MI.hasOneMemOperand())
+ SecondMI->addMemOperand(*MF, *MI.memoperands_begin());
+
+ MI.eraseFromParent();
+ return true;
+}
+
+bool RISCVPreRAExpandPseudoImpl::expandLoadLocalAddress(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) {
+ return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
+ RISCV::ADDI);
+}
+
+bool RISCVPreRAExpandPseudoImpl::expandLoadGlobalAddress(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) {
+ unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
+ return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI,
+ SecondOpcode);
+}
+
+bool RISCVPreRAExpandPseudoImpl::expandLoadTLSIEAddress(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) {
+ unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
+ return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
+ SecondOpcode);
+}
+
+bool RISCVPreRAExpandPseudoImpl::expandLoadTLSGDAddress(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) {
+ return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
+ RISCV::ADDI);
+}
+
+bool RISCVPreRAExpandPseudoImpl::expandLoadTLSDescAddress(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) {
+ MachineFunction *MF = MBB.getParent();
+ MachineInstr &MI = *MBBI;
+ DebugLoc DL = MI.getDebugLoc();
+
+ const auto &STI = MF->getSubtarget<RISCVSubtarget>();
+ unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
+
+ Register FinalReg = MI.getOperand(0).getReg();
+ Register DestReg =
+ MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
+ Register ScratchReg =
+ MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
+
+ MachineOperand &Symbol = MI.getOperand(1);
+ Symbol.setTargetFlags(RISCVII::MO_TLSDESC_HI);
+ MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("tlsdesc_hi");
+
+ MachineInstr *MIAUIPC =
+ BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
+ MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
+
+ BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
+ .addReg(ScratchReg)
+ .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_LOAD_LO);
+
+ BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), RISCV::X10)
+ .addReg(ScratchReg)
+ .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_ADD_LO);
+
+ BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoTLSDESCCall), RISCV::X5)
+ .addReg(DestReg)
+ .addImm(0)
+ .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_CALL);
+
+ BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), FinalReg)
+ .addReg(RISCV::X10)
+ .addReg(RISCV::X4);
+
+ MI.eraseFromParent();
+ return true;
+}
+
+} // end of anonymous namespace
+
+INITIALIZE_PASS(RISCVPreRAExpandPseudoLegacy, "riscv-pre-ra-expand-pseudo",
+ RISCV_PRERA_EXPAND_PSEUDO_NAME, false, false)
+
+namespace llvm {
+
+FunctionPass *createRISCVPreRAExpandPseudoLegacyPass() {
+ return new RISCVPreRAExpandPseudoLegacy();
+}
+
+PreservedAnalyses
+RISCVPreRAExpandPseudoPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ MFPropsModifier _(*this, MF);
+ bool Changed = RISCVPreRAExpandPseudoImpl().run(MF);
+ if (!Changed)
+ return PreservedAnalyses::all();
+
+ PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ return PA;
+}
+
+} // end of namespace llvm
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