[llvm] [RISCV] Port Post-RA Expand Pseudos to NewPM (PR #218080)
Sam Elliott via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 22 11:14:49 PDT 2026
https://github.com/lenary updated https://github.com/llvm/llvm-project/pull/218080
>From cbbd86c99d9ebccb6e86769997b9766f2f89c3f6 Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Fri, 21 Aug 2026 17:56:43 -0700
Subject: [PATCH 1/2] [RISCV] Port Post-RA Expand Pseudos to NewPM
Assisted-by: AI
---
llvm/lib/Target/RISCV/RISCV.h | 11 ++-
.../Target/RISCV/RISCVCodeGenPassBuilder.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVPassRegistry.def | 2 +
.../RISCV/RISCVPostRAExpandPseudoInsts.cpp | 76 ++++++++++++-------
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 4 +-
llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll | 1 +
llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll | 1 +
.../CodeGen/RISCV/postra-expand-pseudo.mir | 27 +++++++
llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp | 2 +-
9 files changed, 94 insertions(+), 32 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/postra-expand-pseudo.mir
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index 504c268a57ffb..7d2e721362dca 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -123,8 +123,15 @@ FunctionPass *createRISCVInsertVSETVLIPass();
void initializeRISCVInsertVSETVLIPass(PassRegistry &);
extern char &RISCVInsertVSETVLIID;
-FunctionPass *createRISCVPostRAExpandPseudoPass();
-void initializeRISCVPostRAExpandPseudoPass(PassRegistry &);
+class RISCVPostRAExpandPseudoPass
+ : public OptionalPassInfoMixin<RISCVPostRAExpandPseudoPass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
+
+FunctionPass *createRISCVPostRAExpandPseudoLegacyPass();
+void initializeRISCVPostRAExpandPseudoLegacyPass(PassRegistry &);
FunctionPass *createRISCVInsertReadWriteCSRPass();
void initializeRISCVInsertReadWriteCSRPass(PassRegistry &);
diff --git a/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp b/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
index f51b44776e916..a60c6ea848e94 100644
--- a/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+++ b/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
@@ -145,7 +145,7 @@ void RISCVCodeGenPassBuilder::addPostRegAlloc(PassManagerWrapper &PMW) {
}
void RISCVCodeGenPassBuilder::addPreSched2(PassManagerWrapper &PMW) {
- // TODO: RISCVPostRAExpandPseudoPass
+ addMachineFunctionPass(RISCVPostRAExpandPseudoPass(), PMW);
addMachineFunctionPass(MachineKCFIPass(), PMW);
if (getOptLevel() != CodeGenOptLevel::None) {
diff --git a/llvm/lib/Target/RISCV/RISCVPassRegistry.def b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
index b62d195982ecb..288f8af833f52 100644
--- a/llvm/lib/Target/RISCV/RISCVPassRegistry.def
+++ b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
@@ -36,6 +36,8 @@ MACHINE_FUNCTION_PASS("riscv-asm-printer", RISCVAsmPrinterPass())
MACHINE_FUNCTION_PASS("riscv-fold-mem-offset", RISCVFoldMemOffsetPass())
MACHINE_FUNCTION_PASS("riscv-isel", RISCVISelDAGToDAGPass(*this, getOptLevel()))
MACHINE_FUNCTION_PASS("riscv-opt-w-instrs", RISCVOptWInstrsPass())
+MACHINE_FUNCTION_PASS("riscv-post-ra-expand-pseudo",
+ RISCVPostRAExpandPseudoPass())
MACHINE_FUNCTION_PASS("riscv-vector-peephole", RISCVVectorPeepholePass())
MACHINE_FUNCTION_PASS("riscv-vl-optimizer", RISCVVLOptimizerPass())
#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
index 1f9bed2ba147b..4b2c55cc49a5c 100644
--- a/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
@@ -24,18 +24,10 @@ using namespace llvm;
namespace {
-class RISCVPostRAExpandPseudo : public MachineFunctionPass {
+class RISCVPostRAExpandPseudoImpl {
public:
const RISCVInstrInfo *TII;
- static char ID;
-
- RISCVPostRAExpandPseudo() : MachineFunctionPass(ID) {}
-
- bool runOnMachineFunction(MachineFunction &MF) override;
-
- StringRef getPassName() const override {
- return RISCV_POST_RA_EXPAND_PSEUDO_NAME;
- }
+ bool run(MachineFunction &MF);
private:
bool expandMBB(MachineBasicBlock &MBB);
@@ -48,9 +40,29 @@ class RISCVPostRAExpandPseudo : public MachineFunctionPass {
MachineBasicBlock::iterator MBBI);
};
-char RISCVPostRAExpandPseudo::ID = 0;
+class RISCVPostRAExpandPseudoLegacy : public MachineFunctionPass {
+public:
+ static char ID;
+
+ RISCVPostRAExpandPseudoLegacy() : MachineFunctionPass(ID) {}
+
+ bool runOnMachineFunction(MachineFunction &MF) override {
+ return RISCVPostRAExpandPseudoImpl().run(MF);
+ }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.setPreservesCFG();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+
+ StringRef getPassName() const override {
+ return RISCV_POST_RA_EXPAND_PSEUDO_NAME;
+ }
+};
+
+char RISCVPostRAExpandPseudoLegacy::ID = 0;
-bool RISCVPostRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
+bool RISCVPostRAExpandPseudoImpl::run(MachineFunction &MF) {
TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo());
bool Modified = false;
for (auto &MBB : MF)
@@ -58,7 +70,7 @@ bool RISCVPostRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
return Modified;
}
-bool RISCVPostRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
+bool RISCVPostRAExpandPseudoImpl::expandMBB(MachineBasicBlock &MBB) {
bool Modified = false;
MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
@@ -71,9 +83,9 @@ bool RISCVPostRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
return Modified;
}
-bool RISCVPostRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
+bool RISCVPostRAExpandPseudoImpl::expandMI(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) {
switch (MBBI->getOpcode()) {
case RISCV::PseudoMovImm:
return expandMovImm(MBB, MBBI);
@@ -88,8 +100,8 @@ bool RISCVPostRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
}
}
-bool RISCVPostRAExpandPseudo::expandMovImm(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI) {
+bool RISCVPostRAExpandPseudoImpl::expandMovImm(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
DebugLoc DL = MBBI->getDebugLoc();
int64_t Val = MBBI->getOperand(1).getImm();
@@ -105,8 +117,8 @@ bool RISCVPostRAExpandPseudo::expandMovImm(MachineBasicBlock &MBB,
return true;
}
-bool RISCVPostRAExpandPseudo::expandMovAddr(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI) {
+bool RISCVPostRAExpandPseudoImpl::expandMovAddr(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
DebugLoc DL = MBBI->getDebugLoc();
Register DstReg = MBBI->getOperand(0).getReg();
@@ -125,7 +137,7 @@ bool RISCVPostRAExpandPseudo::expandMovAddr(MachineBasicBlock &MBB,
return true;
}
-bool RISCVPostRAExpandPseudo::expandAddUpperImm(
+bool RISCVPostRAExpandPseudoImpl::expandAddUpperImm(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
DebugLoc DL = MBBI->getDebugLoc();
@@ -161,8 +173,8 @@ static void transferImpOps(MachineInstr &OldMI, MachineInstrBuilder &MI) {
}
// Expand PseudoMERGE to MERGE, MVM, or MVMN.
-bool RISCVPostRAExpandPseudo::expandMERGE(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI) {
+bool RISCVPostRAExpandPseudoImpl::expandMERGE(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
MachineInstr &MI = *MBBI;
DebugLoc DL = MI.getDebugLoc();
@@ -218,12 +230,24 @@ bool RISCVPostRAExpandPseudo::expandMERGE(MachineBasicBlock &MBB,
} // end of anonymous namespace
-INITIALIZE_PASS(RISCVPostRAExpandPseudo, "riscv-post-ra-expand-pseudo",
+INITIALIZE_PASS(RISCVPostRAExpandPseudoLegacy, "riscv-post-ra-expand-pseudo",
RISCV_POST_RA_EXPAND_PSEUDO_NAME, false, false)
namespace llvm {
-FunctionPass *createRISCVPostRAExpandPseudoPass() {
- return new RISCVPostRAExpandPseudo();
+FunctionPass *createRISCVPostRAExpandPseudoLegacyPass() {
+ return new RISCVPostRAExpandPseudoLegacy();
+}
+
+PreservedAnalyses
+RISCVPostRAExpandPseudoPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ bool Changed = RISCVPostRAExpandPseudoImpl().run(MF);
+ if (!Changed)
+ return PreservedAnalyses::all();
+
+ PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ return PA;
}
} // end of namespace llvm
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 5d891fcd998cc..44f0d1e8e0fd7 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -130,7 +130,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
initializeRISCVGatherScatterLoweringLegacyPass(*PR);
initializeRISCVCodeGenPrepareLegacyPassPass(*PR);
initializeRISCVZacasABIFixLegacyPass(*PR);
- initializeRISCVPostRAExpandPseudoPass(*PR);
+ initializeRISCVPostRAExpandPseudoLegacyPass(*PR);
initializeRISCVMergeBaseOffsetOptPass(*PR);
initializeRISCVOptWInstrsLegacyPass(*PR);
initializeRISCVFoldMemOffsetLegacyPass(*PR);
@@ -555,7 +555,7 @@ bool RISCVPassConfig::addGlobalInstructionSelect() {
}
void RISCVPassConfig::addPreSched2() {
- addPass(createRISCVPostRAExpandPseudoPass());
+ addPass(createRISCVPostRAExpandPseudoLegacyPass());
// Emit KCFI checks for indirect calls.
addPass(createKCFIPass());
diff --git a/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll b/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
index eb054e64e32ff..018455daab499 100644
--- a/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
@@ -86,6 +86,7 @@
; CHECK-NEXT: tailduplication
; CHECK-NEXT: machine-cp
; CHECK-NEXT: post-ra-pseudos
+; CHECK-NEXT: riscv-post-ra-expand-pseudo
; CHECK-NEXT: kcfi
; CHECK-NEXT: post-RA-sched
; CHECK-NEXT: block-placement
diff --git a/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
index 593912c130e19..81247e956209b 100644
--- a/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
@@ -86,6 +86,7 @@
; CHECK-NEXT: tailduplication
; CHECK-NEXT: machine-cp
; CHECK-NEXT: post-ra-pseudos
+; CHECK-NEXT: riscv-post-ra-expand-pseudo
; CHECK-NEXT: kcfi
; CHECK-NEXT: post-RA-sched
; CHECK-NEXT: block-placement
diff --git a/llvm/test/CodeGen/RISCV/postra-expand-pseudo.mir b/llvm/test/CodeGen/RISCV/postra-expand-pseudo.mir
new file mode 100644
index 0000000000000..07905a3214fcd
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/postra-expand-pseudo.mir
@@ -0,0 +1,27 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=riscv32 -run-pass=riscv-post-ra-expand-pseudo %s -o - \
+# RUN: | FileCheck %s
+# RUN: llc -mtriple=riscv64 -run-pass=riscv-post-ra-expand-pseudo %s -o - \
+# RUN: | FileCheck %s
+# RUN: llc -mtriple=riscv32 -passes=riscv-post-ra-expand-pseudo %s -o - \
+# RUN: | FileCheck %s
+# RUN: llc -mtriple=riscv64 -passes=riscv-post-ra-expand-pseudo %s -o - \
+# RUN: | FileCheck %s
+
+--- |
+ define void @test() {
+ ret void
+ }
+...
+---
+name: test
+noVRegs: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test
+ ; CHECK: $x10 = LUI 4
+ ; CHECK-NEXT: $x10 = ADD $x2, killed $x10
+ ; CHECK-NEXT: PseudoRET
+ $x10 = PseudoAddUpperImm $x2, 4
+ PseudoRET
+...
diff --git a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
index 887df7ac7b393..326a66f536f91 100644
--- a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
@@ -748,7 +748,7 @@ class ExegesisRISCVTarget : public ExegesisTarget {
PM.add(exegesis::createRISCVPostprocessingPass());
// PseudoRET will be expanded by RISCVAsmPrinter; we have to expand
// PseudoMovImm with RISCVPostRAExpandPseudoPass though.
- PM.add(createRISCVPostRAExpandPseudoPass());
+ PM.add(createRISCVPostRAExpandPseudoLegacyPass());
}
};
>From ebac545d19d6614cbfded6ef01efd028788ab7c4 Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Fri, 21 Aug 2026 23:23:52 -0700
Subject: [PATCH 2/2] Required Pass
---
llvm/lib/Target/RISCV/RISCV.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index 209e2ca1bee49..b10389e3839fd 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -134,7 +134,7 @@ void initializeRISCVInsertVSETVLIPass(PassRegistry &);
extern char &RISCVInsertVSETVLIID;
class RISCVPostRAExpandPseudoPass
- : public OptionalPassInfoMixin<RISCVPostRAExpandPseudoPass> {
+ : public RequiredPassInfoMixin<RISCVPostRAExpandPseudoPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
More information about the llvm-commits
mailing list