[llvm] [AMDGPU] Custom lower get_fpmode for demanded-bits based read narrowing (PR #218137)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/lib/Target/AMDGPU/SIISelLowering.cpp llvm/lib/Target/AMDGPU/SIISelLowering.h --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index a274648e5..18623a2ac 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5106,13 +5106,12 @@ SDValue SITargetLowering::lowerGET_FPMODE(SDValue Op, SelectionDAG &DAG) const {
   SDValue IntrinID =
       DAG.getTargetConstant(Intrinsic::amdgcn_s_getreg, SL, MVT::i32);
   SDValue GetModeReg = DAG.getNode(ISD::INTRINSIC_W_CHAIN, SL, VTList,
-                                  Op.getOperand(0), IntrinID, ModeHwRegImm);
+                                   Op.getOperand(0), IntrinID, ModeHwRegImm);
 
   SDValue Mask = DAG.getConstant(FPMask, SL, MVT::i32);
   SDValue Result = DAG.getNode(ISD::AND, SL, MVT::i32, GetModeReg, Mask);
 
   return DAG.getMergeValues({Result, GetModeReg.getValue(1)}, SL);
-
 }
 
 Register SITargetLowering::getRegisterByName(const char *RegName, LLT VT,
@@ -14967,8 +14966,7 @@ SDValue SITargetLowering::performAndCombine(SDNode *N,
       }
     }
 
-    if (CRHS && LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
-       LHS.hasOneUse()) {
+    if (CRHS && LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN && LHS.hasOneUse()) {
       unsigned IntrinID = LHS.getConstantOperandVal(1);
       if (IntrinID == Intrinsic::amdgcn_s_getreg) {
         uint32_t Simm16 = LHS.getConstantOperandVal(2);
@@ -14982,29 +14980,25 @@ SDValue SITargetLowering::performAndCombine(SDNode *N,
           unsigned Lo = NeededInRead.countr_zero();
           unsigned Hi = 32 - NeededInRead.countLeadingZeros() - 1;
 
-          APInt Contiguous =
-              APInt::getBitsSet(32, Lo, Hi+1);
+          APInt Contiguous = APInt::getBitsSet(32, Lo, Hi + 1);
           if (NeededInRead == Contiguous) {
             unsigned NewWidth = Hi + 1;
 
             if (NewWidth < RegSize) {
               SDLoc DL(N);
-              uint32_t NewSimm16 =
-                  AMDGPU::Hwreg::HwregEncoding::encode(
-                      AMDGPU::Hwreg::ID_MODE, RegOffset, NewWidth);
+              uint32_t NewSimm16 = AMDGPU::Hwreg::HwregEncoding::encode(
+                  AMDGPU::Hwreg::ID_MODE, RegOffset, NewWidth);
               SDValue NewImm = DAG.getTargetConstant(NewSimm16, DL, MVT::i32);
 
               SDValue NewIntrin = SDValue(
-                  DAG.UpdateNodeOperands(
-                      LHS.getNode(),
-                      LHS.getOperand(0),
-                      LHS.getOperand(1),
-                      NewImm), 0);
+                  DAG.UpdateNodeOperands(LHS.getNode(), LHS.getOperand(0),
+                                         LHS.getOperand(1), NewImm),
+                  0);
 
               if (Lo == 0)
                 return NewIntrin;
               return DAG.getNode(ISD::AND, DL, VT, NewIntrin,
-                                  DAG.getConstant(Mask, DL, VT));
+                                 DAG.getConstant(Mask, DL, VT));
             }
           }
         }

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https://github.com/llvm/llvm-project/pull/218137