[llvm] [AArch64][GlobalISel] Use integer types in udot zero lanes. (PR #218115)

[David Green via llvm-commits]

https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/218115

None

>From 80ad345d4afe26fa5b4984d2c8bdabb4daae59f0 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Sat, 22 Aug 2026 09:48:52 +0100
Subject: [PATCH] [AArch64][GlobalISel] Use integer types in udot zero lanes.

---
 .../GISel/AArch64PreLegalizerCombiner.cpp     | 19 ++++++++-----------
 .../prelegalizer-combiner-scalar.mir          |  8 ++++----
 2 files changed, 12 insertions(+), 15 deletions(-)

diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
index 8d25f56fc5226..e7ecdce8caba7 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
@@ -349,19 +349,16 @@ void applyExtAddvToDotAddv(MachineInstr &MI, MachineRegisterInfo &MRI,
       // Split the elements into v16i8 and v8i8
       LLT MainTy = LLT::fixed_vector(16, LLT::integer(8));
       LLT LeftoverTy1, LeftoverTy2;
-      if ((!extractParts(Ext1SrcReg, MRI.getType(Ext1SrcReg), MainTy,
-                         LeftoverTy1, Ext1UnmergeReg, Leftover1, Builder,
-                         MRI)) ||
-          (!extractParts(Ext2SrcReg, MRI.getType(Ext2SrcReg), MainTy,
-                         LeftoverTy2, Ext2UnmergeReg, Leftover2, Builder,
-                         MRI))) {
+      if (!extractParts(Ext1SrcReg, MRI.getType(Ext1SrcReg), MainTy,
+                        LeftoverTy1, Ext1UnmergeReg, Leftover1, Builder, MRI) ||
+          !extractParts(Ext2SrcReg, MRI.getType(Ext2SrcReg), MainTy,
+                        LeftoverTy2, Ext2UnmergeReg, Leftover2, Builder, MRI)) {
         llvm_unreachable("Unable to split this vector properly");
       }
 
       // Pad the leftover v8i8 vector with register of 0s of type v8i8
-      Register v8Zeroes = Builder.buildConstant(LLT::fixed_vector(8, 8), 0)
-                              ->getOperand(0)
-                              .getReg();
+      auto v8Zeroes =
+          Builder.buildConstant(LLT::fixed_vector(8, LLT::integer(8)), 0);
 
       Ext1UnmergeReg.push_back(
           Builder
@@ -396,10 +393,10 @@ void applyExtAddvToDotAddv(MachineInstr &MI, MachineRegisterInfo &MRI,
         ZeroesLLT = LLT::fixed_vector(2, LLT::integer(32));
         NumElements += 2;
       }
-      auto Zeroes = Builder.buildConstant(ZeroesLLT, 0)->getOperand(0).getReg();
+      auto Zeroes = Builder.buildConstant(ZeroesLLT, 0);
       DotReg.push_back(
           Builder
-              .buildInstr(DotOpcode, {MRI.getType(Zeroes)},
+              .buildInstr(DotOpcode, {ZeroesLLT},
                           {Zeroes, Ext1UnmergeReg[i], Ext2UnmergeReg[i]})
               .getReg(0));
     }
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-scalar.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-scalar.mir
index eacb7cacbb7e8..c3d7caddd5e87 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-scalar.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-scalar.mir
@@ -18,10 +18,10 @@ body:             |
     ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x i8>) = G_CONCAT_VECTORS [[UV]](<8 x i8>), [[UV1]](<8 x i8>)
     ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(<8 x i8>), [[UV4:%[0-9]+]]:_(<8 x i8>), [[UV5:%[0-9]+]]:_(<8 x i8>) = G_UNMERGE_VALUES [[LOAD]](<24 x i8>)
     ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<16 x i8>) = G_CONCAT_VECTORS [[UV3]](<8 x i8>), [[UV4]](<8 x i8>)
-    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
-    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8)
-    ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<16 x i8>) = G_CONCAT_VECTORS [[UV2]](<8 x i8>), [[BUILD_VECTOR]](<8 x s8>)
-    ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<16 x i8>) = G_CONCAT_VECTORS [[UV5]](<8 x i8>), [[BUILD_VECTOR]](<8 x s8>)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(i8) = G_CONSTANT i8 0
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i8>) = G_BUILD_VECTOR [[C]](i8), [[C]](i8), [[C]](i8), [[C]](i8), [[C]](i8), [[C]](i8), [[C]](i8), [[C]](i8)
+    ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<16 x i8>) = G_CONCAT_VECTORS [[UV2]](<8 x i8>), [[BUILD_VECTOR]](<8 x i8>)
+    ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<16 x i8>) = G_CONCAT_VECTORS [[UV5]](<8 x i8>), [[BUILD_VECTOR]](<8 x i8>)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
     ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[C1]](i32), [[C1]](i32), [[C1]](i32), [[C1]](i32)
     ; CHECK-NEXT: [[UDOT:%[0-9]+]]:_(<4 x i32>) = G_UDOT [[BUILD_VECTOR1]], [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]