[llvm] [RISCV] Rename riscv-pre-ra-expand-pseudo (PR #218106)

[Aiden Grossman via llvm-commits]

https://github.com/boomanaiden154 created https://github.com/llvm/llvm-project/pull/218106

>From riscv-prera-expand-psuedo. Makes the name more consistent with other targets (e.g., AMDGPU uses pre-ra) and with our hyphenation in general.

>From 3d5340df65229a0a07cd272e585c5371298e83ec Mon Sep 17 00:00:00 2001
From: Aiden Grossman <aidengrossman at google.com>
Date: Sat, 22 Aug 2026 06:20:42 +0000
Subject: [PATCH] [RISCV] Rename riscv-pre-ra-expand-pseudo

>From riscv-prera-expand-psuedo. Makes the name more consistent with
other targets (e.g., AMDGPU uses pre-ra) and with our hyphenation in
general.
---
 llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp | 2 +-
 llvm/lib/Target/RISCV/RISCVPassRegistry.def      | 2 +-
 llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll     | 2 +-
 llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll     | 2 +-
 llvm/test/CodeGen/RISCV/mir-target-flags.ll      | 4 ++--
 llvm/test/CodeGen/RISCV/prera-expand-pseudo.mir  | 8 ++++----
 6 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
index b9cbc77249ca3..2f4ca7e428385 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -878,7 +878,7 @@ bool RISCVPreRAExpandPseudoImpl::expandLoadTLSDescAddress(
 INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo",
                 RISCV_EXPAND_PSEUDO_NAME, false, false)
 
-INITIALIZE_PASS(RISCVPreRAExpandPseudoLegacy, "riscv-prera-expand-pseudo",
+INITIALIZE_PASS(RISCVPreRAExpandPseudoLegacy, "riscv-pre-ra-expand-pseudo",
                 RISCV_PRERA_EXPAND_PSEUDO_NAME, false, false)
 
 namespace llvm {
diff --git a/llvm/lib/Target/RISCV/RISCVPassRegistry.def b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
index 0b303aa256edc..cd3ebfe58894f 100644
--- a/llvm/lib/Target/RISCV/RISCVPassRegistry.def
+++ b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
@@ -36,7 +36,7 @@ MACHINE_FUNCTION_PASS("riscv-asm-printer", RISCVAsmPrinterPass())
 MACHINE_FUNCTION_PASS("riscv-fold-mem-offset", RISCVFoldMemOffsetPass())
 MACHINE_FUNCTION_PASS("riscv-isel", RISCVISelDAGToDAGPass(*this, getOptLevel()))
 MACHINE_FUNCTION_PASS("riscv-opt-w-instrs", RISCVOptWInstrsPass())
-MACHINE_FUNCTION_PASS("riscv-prera-expand-pseudo",
+MACHINE_FUNCTION_PASS("riscv-pre-ra-expand-pseudo",
                       RISCVPreRAExpandPseudoPass())
 MACHINE_FUNCTION_PASS("riscv-vector-peephole", RISCVVectorPeepholePass())
 MACHINE_FUNCTION_PASS("riscv-vl-optimizer", RISCVVLOptimizerPass())
diff --git a/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll b/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
index f5f67d996f0b5..60efb06dd120e 100644
--- a/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
@@ -60,7 +60,7 @@
 ; CHECK-NEXT:     peephole-opt
 ; CHECK-NEXT:     dead-mi-elimination
 ; RV64-NEXT:      riscv-opt-w-instrs
-; CHECK-NEXT:     riscv-prera-expand-pseudo
+; CHECK-NEXT:     riscv-pre-ra-expand-pseudo
 ; CHECK-NEXT:     detect-dead-lanes
 ; CHECK-NEXT:     init-undef
 ; CHECK-NEXT:     process-imp-defs
diff --git a/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
index 7873d1db04108..e4c7c06e73796 100644
--- a/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
@@ -60,7 +60,7 @@
 ; CHECK-NEXT:     peephole-opt
 ; CHECK-NEXT:     dead-mi-elimination
 ; RV64-NEXT:      riscv-opt-w-instrs
-; CHECK-NEXT:     riscv-prera-expand-pseudo
+; CHECK-NEXT:     riscv-pre-ra-expand-pseudo
 ; CHECK-NEXT:     detect-dead-lanes
 ; CHECK-NEXT:     init-undef
 ; CHECK-NEXT:     process-imp-defs
diff --git a/llvm/test/CodeGen/RISCV/mir-target-flags.ll b/llvm/test/CodeGen/RISCV/mir-target-flags.ll
index fdc0d894b2cae..d311f09a996ec 100644
--- a/llvm/test/CodeGen/RISCV/mir-target-flags.ll
+++ b/llvm/test/CodeGen/RISCV/mir-target-flags.ll
@@ -1,10 +1,10 @@
 ; RUN: llc -mtriple=riscv32 --code-model=small \
-; RUN:    -stop-after riscv-prera-expand-pseudo %s -o %t.mir
+; RUN:    -stop-after riscv-pre-ra-expand-pseudo %s -o %t.mir
 ; RUN: llc -mtriple=riscv32 -run-pass riscv-expand-pseudo %t.mir -o - | \
 ; RUN:   FileCheck %s -check-prefix=RV32-SMALL
 ;
 ; RUN: llc -mtriple=riscv32 --code-model=medium --relocation-model=pic \
-; RUN:   -stop-after riscv-prera-expand-pseudo %s -o %t.mir
+; RUN:   -stop-after riscv-pre-ra-expand-pseudo %s -o %t.mir
 ; RUN: llc -mtriple=riscv32 -run-pass riscv-expand-pseudo %t.mir -o - | \
 ; RUN:   FileCheck %s -check-prefix=RV32-MED
 
diff --git a/llvm/test/CodeGen/RISCV/prera-expand-pseudo.mir b/llvm/test/CodeGen/RISCV/prera-expand-pseudo.mir
index a5b0798022933..dc239a41373a4 100644
--- a/llvm/test/CodeGen/RISCV/prera-expand-pseudo.mir
+++ b/llvm/test/CodeGen/RISCV/prera-expand-pseudo.mir
@@ -1,11 +1,11 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=riscv32 -run-pass=riscv-prera-expand-pseudo %s -o - \
+# RUN: llc -mtriple=riscv32 -run-pass=riscv-pre-ra-expand-pseudo %s -o - \
 # RUN:   | FileCheck %s --check-prefixes=RV32
-# RUN: llc -mtriple=riscv64 -run-pass=riscv-prera-expand-pseudo %s -o - \
+# RUN: llc -mtriple=riscv64 -run-pass=riscv-pre-ra-expand-pseudo %s -o - \
 # RUN:   | FileCheck %s --check-prefixes=RV64
-# RUN: llc -mtriple=riscv32 -passes=riscv-prera-expand-pseudo %s -o - \
+# RUN: llc -mtriple=riscv32 -passes=riscv-pre-ra-expand-pseudo %s -o - \
 # RUN:   | FileCheck %s --check-prefixes=RV32
-# RUN: llc -mtriple=riscv64 -passes=riscv-prera-expand-pseudo %s -o - \
+# RUN: llc -mtriple=riscv64 -passes=riscv-pre-ra-expand-pseudo %s -o - \
 # RUN:   | FileCheck %s --check-prefixes=RV64
 
 --- |