[llvm] [SDAG][ComputeNumSignBits] Look through undefined high bits for EXTRACT_VECTOR_ELT in a BUILD_VECTOR (PR #218099)
Usman Nadeem via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 21 21:51:57 PDT 2026
https://github.com/UsmanNadeem created https://github.com/llvm/llvm-project/pull/218099
If we have a `BUILD_VECTOR(EXTRACT_VECTOR_ELT()...)` where the `EXTRACT_VECTOR_ELT` is adding undefined high bits by extending but the `BUILD_VECTOR` is again truncating those bits, then we can just look through the extract and call `ComputeNumSignBits` directly on the parent vector.
Ideally, when the caller is truncating the value, it would be nice for `ComputeNumSignBits` to have the ability to ignore high bits we don't care about.
>From 4c2292fc4afd8bd68377406ccdc632c2d712745b Mon Sep 17 00:00:00 2001
From: Usman Nadeem <mnadeem at qti.qualcomm.com>
Date: Tue, 21 Jul 2026 18:57:56 -0700
Subject: [PATCH 1/2] Precommit tests
Change-Id: Ic9ab60dee5aceb5c958e2fbaf569705460d1b4d1
---
...fold-sext-in-reg-predicate-fixed-length.ll | 100 ++++++++++++++++++
1 file changed, 100 insertions(+)
diff --git a/llvm/test/CodeGen/AArch64/fold-sext-in-reg-predicate-fixed-length.ll b/llvm/test/CodeGen/AArch64/fold-sext-in-reg-predicate-fixed-length.ll
index 84ecea6664716..d9dbcdb8558b8 100644
--- a/llvm/test/CodeGen/AArch64/fold-sext-in-reg-predicate-fixed-length.ll
+++ b/llvm/test/CodeGen/AArch64/fold-sext-in-reg-predicate-fixed-length.ll
@@ -31,6 +31,106 @@ entry:
ret void
}
+define void @active_lane_mask_doubleLenVector_i8_mstore_vscaleX2(ptr %p, i64 %n) vscale_range(2,2) {
+; CHECK-LABEL: active_lane_mask_doubleLenVector_i8_mstore_vscaleX2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov z0.b, #123 // =0x7b
+; CHECK-NEXT: mov w8, #32 // =0x20
+; CHECK-NEXT: whilelo p0.b, xzr, x1
+; CHECK-NEXT: whilelo p1.b, x8, x1
+; CHECK-NEXT: st1b { z0.b }, p0, [x0]
+; CHECK-NEXT: st1b { z0.b }, p1, [x0, #1, mul vl]
+; CHECK-NEXT: ret
+entry:
+ %mask = call <64 x i1> @llvm.get.active.lane.mask.v64i1(i64 0, i64 %n)
+ call void @llvm.masked.store.v64i8.p0(<64 x i8> splat(i8 123), ptr %p, <64 x i1> %mask)
+ ret void
+}
+
+define void @active_lane_mask_doubleLenVector_i16_mstore_vscaleX2(ptr %p, i64 %n) vscale_range(2,2) {
+; CHECK-LABEL: active_lane_mask_doubleLenVector_i16_mstore_vscaleX2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #16 // =0x10
+; CHECK-NEXT: whilelo p0.b, xzr, x1
+; CHECK-NEXT: whilelo p1.b, x8, x1
+; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: mov z1.b, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: uunpklo z0.h, z0.b
+; CHECK-NEXT: uunpklo z1.h, z1.b
+; CHECK-NEXT: lsl z0.h, z0.h, #15
+; CHECK-NEXT: lsl z1.h, z1.h, #15
+; CHECK-NEXT: asr z0.h, z0.h, #15
+; CHECK-NEXT: asr z1.h, z1.h, #15
+; CHECK-NEXT: cmpne p1.h, p0/z, z0.h, #0
+; CHECK-NEXT: mov z0.h, #123 // =0x7b
+; CHECK-NEXT: cmpne p2.h, p0/z, z1.h, #0
+; CHECK-NEXT: st1h { z0.h }, p1, [x0]
+; CHECK-NEXT: st1h { z0.h }, p2, [x0, #1, mul vl]
+; CHECK-NEXT: ret
+entry:
+ %mask = call <32 x i1> @llvm.get.active.lane.mask.v32i1(i64 0, i64 %n)
+ call void @llvm.masked.store.v32i16.p0(<32 x i16> splat(i16 123), ptr %p, <32 x i1> %mask)
+ ret void
+}
+
+define void @active_lane_mask_doubleLenVector_i32_mstore_vscaleX2(ptr %p, i64 %n) vscale_range(2,2) {
+; CHECK-LABEL: active_lane_mask_doubleLenVector_i32_mstore_vscaleX2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #8 // =0x8
+; CHECK-NEXT: whilelo p0.b, xzr, x1
+; CHECK-NEXT: whilelo p1.b, x8, x1
+; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: mov z1.b, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: uunpklo z0.h, z0.b
+; CHECK-NEXT: uunpklo z1.h, z1.b
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpklo z1.s, z1.h
+; CHECK-NEXT: lsl z0.s, z0.s, #31
+; CHECK-NEXT: lsl z1.s, z1.s, #31
+; CHECK-NEXT: asr z0.s, z0.s, #31
+; CHECK-NEXT: asr z1.s, z1.s, #31
+; CHECK-NEXT: cmpne p1.s, p0/z, z0.s, #0
+; CHECK-NEXT: mov z0.s, #123 // =0x7b
+; CHECK-NEXT: cmpne p2.s, p0/z, z1.s, #0
+; CHECK-NEXT: st1w { z0.s }, p1, [x0]
+; CHECK-NEXT: st1w { z0.s }, p2, [x0, #1, mul vl]
+; CHECK-NEXT: ret
+entry:
+ %mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1(i64 0, i64 %n)
+ call void @llvm.masked.store.v16i32.p0(<16 x i32> splat(i32 123), ptr %p, <16 x i1> %mask)
+ ret void
+}
+
+define void @active_lane_mask_doubleLenVector_i64_mstore_vscaleX2(ptr %p, i64 %n) vscale_range(2,2) {
+; CHECK-LABEL: active_lane_mask_doubleLenVector_i64_mstore_vscaleX2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: whilelo p1.b, xzr, x1
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: mov z0.b, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: zip2 v1.8b, v0.8b, v0.8b
+; CHECK-NEXT: zip1 v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: uunpklo z1.s, z1.h
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpklo z1.d, z1.s
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: lsl z1.d, z1.d, #63
+; CHECK-NEXT: lsl z0.d, z0.d, #63
+; CHECK-NEXT: asr z1.d, z1.d, #63
+; CHECK-NEXT: asr z0.d, z0.d, #63
+; CHECK-NEXT: cmpne p1.d, p0/z, z1.d, #0
+; CHECK-NEXT: cmpne p2.d, p0/z, z0.d, #0
+; CHECK-NEXT: mov z1.d, #123 // =0x7b
+; CHECK-NEXT: st1d { z1.d }, p1, [x0, #1, mul vl]
+; CHECK-NEXT: st1d { z1.d }, p2, [x0]
+; CHECK-NEXT: ret
+entry:
+ %mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1(i64 0, i64 %n)
+ call void @llvm.masked.store.v8i64.p0(<8 x i64> splat(i64 123), ptr %p, <8 x i1> %mask)
+ ret void
+}
+
define void @active_lane_mask_mstore_vscaleX4(ptr %p, i64 %n) vscale_range(4,4) {
; CHECK-LABEL: active_lane_mask_mstore_vscaleX4:
; CHECK: // %bb.0:
>From 28a2443e200f4360258b1083ceb6500155b14a6b Mon Sep 17 00:00:00 2001
From: Usman Nadeem <mnadeem at qti.qualcomm.com>
Date: Fri, 21 Aug 2026 21:34:52 -0700
Subject: [PATCH 2/2] [SDAG][ComputeNumSignBits] Look through undefined high
bits for EXTRACT_VECTOR_ELT in a BUILD_VECTOR
If we have a BUILD_VECTOR(EXTRACT_VECTOR_ELT()...) where the EXTRACT_VECTOR_ELT is adding undefined high bits by extending but the BUILD_VECTOR is again truncating those bits, then we can just look through the extract and call ComputeNumSignBits directly on the parent vector.
Ideally it would be nice for ComputeNumSignBits to have the ability to ignore high bits we dont care about when the caller is truncating the value.
Change-Id: I6e0d50899c23c0e8dc5081bcef73c27822bdbba3
---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 22 +++
...fold-sext-in-reg-predicate-fixed-length.ll | 44 +----
.../illegal-floating-point-vector-compares.ll | 2 -
llvm/test/CodeGen/ARM/vtrn.ll | 6 +-
.../WebAssembly/simd-setcc-reductions.ll | 184 +++++++-----------
5 files changed, 102 insertions(+), 156 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 00cef99069347..2294e1624d6a3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4999,6 +4999,28 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SrcOp)) {
APInt T = C->getAPIntValue().trunc(VTBits);
Tmp2 = T.getNumSignBits();
+ } else if (SrcOp.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
+ SrcOp.getOperand(0).getScalarValueSizeInBits() >= VTBits) {
+ // EXTRACT_VECTOR_ELT can extend the value with high bits undefined. If
+ // this BUILD_VECTOR truncates those undefined bits we can just look
+ // through the SrcOp and query the vector directly.
+ SDValue InVec = SrcOp.getOperand(0);
+ EVT InVecVT = InVec.getValueType();
+ // Not yet implemented for scalable vectors.
+ if (InVecVT.isScalableVector())
+ return 1;
+
+ const unsigned NumSrcElts = InVecVT.getVectorNumElements();
+ APInt DemandedSrcElts = APInt::getAllOnes(NumSrcElts);
+ auto *ConstEltNo = dyn_cast<ConstantSDNode>(SrcOp.getOperand(1));
+ if (ConstEltNo && ConstEltNo->getAPIntValue().ult(NumSrcElts))
+ DemandedSrcElts =
+ APInt::getOneBitSet(NumSrcElts, ConstEltNo->getZExtValue());
+
+ Tmp2 = ComputeNumSignBits(InVec, DemandedSrcElts, Depth + 1);
+ unsigned ExtraBits = InVec.getScalarValueSizeInBits() - VTBits;
+ if (ExtraBits)
+ Tmp2 = (Tmp2 > ExtraBits ? Tmp2 - ExtraBits : 1);
} else {
Tmp2 = ComputeNumSignBits(SrcOp, Depth + 1);
diff --git a/llvm/test/CodeGen/AArch64/fold-sext-in-reg-predicate-fixed-length.ll b/llvm/test/CodeGen/AArch64/fold-sext-in-reg-predicate-fixed-length.ll
index d9dbcdb8558b8..6aa8daff88e5f 100644
--- a/llvm/test/CodeGen/AArch64/fold-sext-in-reg-predicate-fixed-length.ll
+++ b/llvm/test/CodeGen/AArch64/fold-sext-in-reg-predicate-fixed-length.ll
@@ -50,23 +50,12 @@ entry:
define void @active_lane_mask_doubleLenVector_i16_mstore_vscaleX2(ptr %p, i64 %n) vscale_range(2,2) {
; CHECK-LABEL: active_lane_mask_doubleLenVector_i16_mstore_vscaleX2:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov w8, #16 // =0x10
-; CHECK-NEXT: whilelo p0.b, xzr, x1
-; CHECK-NEXT: whilelo p1.b, x8, x1
-; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: mov z1.b, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: uunpklo z0.h, z0.b
-; CHECK-NEXT: uunpklo z1.h, z1.b
-; CHECK-NEXT: lsl z0.h, z0.h, #15
-; CHECK-NEXT: lsl z1.h, z1.h, #15
-; CHECK-NEXT: asr z0.h, z0.h, #15
-; CHECK-NEXT: asr z1.h, z1.h, #15
-; CHECK-NEXT: cmpne p1.h, p0/z, z0.h, #0
; CHECK-NEXT: mov z0.h, #123 // =0x7b
-; CHECK-NEXT: cmpne p2.h, p0/z, z1.h, #0
-; CHECK-NEXT: st1h { z0.h }, p1, [x0]
-; CHECK-NEXT: st1h { z0.h }, p2, [x0, #1, mul vl]
+; CHECK-NEXT: mov w8, #16 // =0x10
+; CHECK-NEXT: whilelo p0.h, xzr, x1
+; CHECK-NEXT: whilelo p1.h, x8, x1
+; CHECK-NEXT: st1h { z0.h }, p0, [x0]
+; CHECK-NEXT: st1h { z0.h }, p1, [x0, #1, mul vl]
; CHECK-NEXT: ret
entry:
%mask = call <32 x i1> @llvm.get.active.lane.mask.v32i1(i64 0, i64 %n)
@@ -77,25 +66,12 @@ entry:
define void @active_lane_mask_doubleLenVector_i32_mstore_vscaleX2(ptr %p, i64 %n) vscale_range(2,2) {
; CHECK-LABEL: active_lane_mask_doubleLenVector_i32_mstore_vscaleX2:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov w8, #8 // =0x8
-; CHECK-NEXT: whilelo p0.b, xzr, x1
-; CHECK-NEXT: whilelo p1.b, x8, x1
-; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov z1.b, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: uunpklo z0.h, z0.b
-; CHECK-NEXT: uunpklo z1.h, z1.b
-; CHECK-NEXT: uunpklo z0.s, z0.h
-; CHECK-NEXT: uunpklo z1.s, z1.h
-; CHECK-NEXT: lsl z0.s, z0.s, #31
-; CHECK-NEXT: lsl z1.s, z1.s, #31
-; CHECK-NEXT: asr z0.s, z0.s, #31
-; CHECK-NEXT: asr z1.s, z1.s, #31
-; CHECK-NEXT: cmpne p1.s, p0/z, z0.s, #0
; CHECK-NEXT: mov z0.s, #123 // =0x7b
-; CHECK-NEXT: cmpne p2.s, p0/z, z1.s, #0
-; CHECK-NEXT: st1w { z0.s }, p1, [x0]
-; CHECK-NEXT: st1w { z0.s }, p2, [x0, #1, mul vl]
+; CHECK-NEXT: mov w8, #8 // =0x8
+; CHECK-NEXT: whilelo p0.s, xzr, x1
+; CHECK-NEXT: whilelo p1.s, x8, x1
+; CHECK-NEXT: st1w { z0.s }, p0, [x0]
+; CHECK-NEXT: st1w { z0.s }, p1, [x0, #1, mul vl]
; CHECK-NEXT: ret
entry:
%mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1(i64 0, i64 %n)
diff --git a/llvm/test/CodeGen/AArch64/illegal-floating-point-vector-compares.ll b/llvm/test/CodeGen/AArch64/illegal-floating-point-vector-compares.ll
index 140e2a99bb4b2..ecd3741b6e183 100644
--- a/llvm/test/CodeGen/AArch64/illegal-floating-point-vector-compares.ll
+++ b/llvm/test/CodeGen/AArch64/illegal-floating-point-vector-compares.ll
@@ -64,8 +64,6 @@ define i1 @unordered_floating_point_compare_on_v32f32(<32 x float> %a_vec) {
; CHECK-NEXT: uzp1 v1.16b, v3.16b, v1.16b
; CHECK-NEXT: mvn v0.16b, v0.16b
; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: shl v0.16b, v0.16b, #7
-; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
; CHECK-NEXT: umaxv b0, v0.16b
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: bic w0, w9, w8
diff --git a/llvm/test/CodeGen/ARM/vtrn.ll b/llvm/test/CodeGen/ARM/vtrn.ll
index 218e11aef5501..fbe5e1b991d13 100644
--- a/llvm/test/CodeGen/ARM/vtrn.ll
+++ b/llvm/test/CodeGen/ARM/vtrn.ll
@@ -356,15 +356,13 @@ define <8 x i8> @vtrn_mismatched_builvector0(<8 x i8> %tr0, <8 x i8> %tr1, <4 x
; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
; CHECK-NEXT: vcgt.u32 q8, q9, q8
; CHECK-NEXT: vldr d20, [sp, #32]
+; CHECK-NEXT: vmov d19, r0, r1
; CHECK-NEXT: vldr d18, [sp, #40]
; CHECK-NEXT: vcgt.u16 d18, d18, d20
; CHECK-NEXT: vmovn.i32 d16, q8
; CHECK-NEXT: vmov d17, r2, r3
; CHECK-NEXT: vtrn.8 d16, d18
-; CHECK-NEXT: vmov d18, r0, r1
-; CHECK-NEXT: vshl.i8 d16, d16, #7
-; CHECK-NEXT: vshr.s8 d16, d16, #7
-; CHECK-NEXT: vbsl d16, d18, d17
+; CHECK-NEXT: vbsl d16, d19, d17
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
%c0 = icmp ult <4 x i32> %cmp0, %cmp1
diff --git a/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll b/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll
index b645fc57478f3..b5465195c76a6 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll
@@ -148,30 +148,22 @@ define i32 @all_true_big_v32i16(<32 x i16> %v) {
; CHECK-LABEL: all_true_big_v32i16:
; CHECK: .functype all_true_big_v32i16 (v128, v128, v128, v128) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: v128.const $push22=, 0, 0, 0, 0, 0, 0, 0, 0
-; CHECK-NEXT: local.tee $push21=, $4=, $pop22
-; CHECK-NEXT: i16x8.eq $push8=, $0, $pop21
-; CHECK-NEXT: i16x8.eq $push7=, $1, $4
-; CHECK-NEXT: i8x16.shuffle $push9=, $pop8, $pop7, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
-; CHECK-NEXT: i32.const $push3=, 7
-; CHECK-NEXT: i8x16.shl $push10=, $pop9, $pop3
-; CHECK-NEXT: i32.const $push20=, 7
-; CHECK-NEXT: i8x16.shr_s $push11=, $pop10, $pop20
-; CHECK-NEXT: i8x16.all_true $push12=, $pop11
+; CHECK-NEXT: v128.const $push14=, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT: local.tee $push13=, $4=, $pop14
+; CHECK-NEXT: i16x8.eq $push5=, $0, $pop13
+; CHECK-NEXT: i16x8.eq $push4=, $1, $4
+; CHECK-NEXT: i8x16.shuffle $push6=, $pop5, $pop4, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
+; CHECK-NEXT: i8x16.all_true $push7=, $pop6
; CHECK-NEXT: i16x8.eq $push1=, $2, $4
; CHECK-NEXT: i16x8.eq $push0=, $3, $4
; CHECK-NEXT: i8x16.shuffle $push2=, $pop1, $pop0, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
-; CHECK-NEXT: i32.const $push19=, 7
-; CHECK-NEXT: i8x16.shl $push4=, $pop2, $pop19
-; CHECK-NEXT: i32.const $push18=, 7
-; CHECK-NEXT: i8x16.shr_s $push5=, $pop4, $pop18
-; CHECK-NEXT: i8x16.all_true $push6=, $pop5
-; CHECK-NEXT: i32.and $push13=, $pop12, $pop6
-; CHECK-NEXT: i32.const $push14=, -1
-; CHECK-NEXT: i32.xor $push15=, $pop13, $pop14
-; CHECK-NEXT: i32.const $push16=, 1
-; CHECK-NEXT: i32.and $push17=, $pop15, $pop16
-; CHECK-NEXT: return $pop17
+; CHECK-NEXT: i8x16.all_true $push3=, $pop2
+; CHECK-NEXT: i32.and $push8=, $pop7, $pop3
+; CHECK-NEXT: i32.const $push9=, -1
+; CHECK-NEXT: i32.xor $push10=, $pop8, $pop9
+; CHECK-NEXT: i32.const $push11=, 1
+; CHECK-NEXT: i32.and $push12=, $pop10, $pop11
+; CHECK-NEXT: return $pop12
%1 = icmp eq <32 x i16> %v, zeroinitializer
%2 = bitcast <32 x i1> %1 to i32
%3 = icmp ne i32 %2, -1
@@ -183,49 +175,33 @@ define i64 @all_true_big_v64i16(<64 x i16> %v) {
; CHECK-LABEL: all_true_big_v64i16:
; CHECK: .functype all_true_big_v64i16 (v128, v128, v128, v128, v128, v128, v128, v128) -> (i64)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: v128.const $push41=, 0, 0, 0, 0, 0, 0, 0, 0
-; CHECK-NEXT: local.tee $push40=, $8=, $pop41
-; CHECK-NEXT: i16x8.eq $push8=, $0, $pop40
-; CHECK-NEXT: i16x8.eq $push7=, $1, $8
-; CHECK-NEXT: i8x16.shuffle $push9=, $pop8, $pop7, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
-; CHECK-NEXT: i32.const $push3=, 7
-; CHECK-NEXT: i8x16.shl $push10=, $pop9, $pop3
-; CHECK-NEXT: i32.const $push39=, 7
-; CHECK-NEXT: i8x16.shr_s $push11=, $pop10, $pop39
-; CHECK-NEXT: i8x16.all_true $push12=, $pop11
+; CHECK-NEXT: v128.const $push25=, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT: local.tee $push24=, $8=, $pop25
+; CHECK-NEXT: i16x8.eq $push5=, $0, $pop24
+; CHECK-NEXT: i16x8.eq $push4=, $1, $8
+; CHECK-NEXT: i8x16.shuffle $push6=, $pop5, $pop4, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
+; CHECK-NEXT: i8x16.all_true $push7=, $pop6
; CHECK-NEXT: i16x8.eq $push1=, $2, $8
; CHECK-NEXT: i16x8.eq $push0=, $3, $8
; CHECK-NEXT: i8x16.shuffle $push2=, $pop1, $pop0, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
-; CHECK-NEXT: i32.const $push38=, 7
-; CHECK-NEXT: i8x16.shl $push4=, $pop2, $pop38
-; CHECK-NEXT: i32.const $push37=, 7
-; CHECK-NEXT: i8x16.shr_s $push5=, $pop4, $pop37
-; CHECK-NEXT: i8x16.all_true $push6=, $pop5
-; CHECK-NEXT: i32.and $push13=, $pop12, $pop6
-; CHECK-NEXT: i16x8.eq $push15=, $4, $8
-; CHECK-NEXT: i16x8.eq $push14=, $5, $8
+; CHECK-NEXT: i8x16.all_true $push3=, $pop2
+; CHECK-NEXT: i32.and $push8=, $pop7, $pop3
+; CHECK-NEXT: i16x8.eq $push10=, $4, $8
+; CHECK-NEXT: i16x8.eq $push9=, $5, $8
+; CHECK-NEXT: i8x16.shuffle $push11=, $pop10, $pop9, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
+; CHECK-NEXT: i8x16.all_true $push12=, $pop11
+; CHECK-NEXT: i32.and $push13=, $pop8, $pop12
+; CHECK-NEXT: i16x8.eq $push15=, $6, $8
+; CHECK-NEXT: i16x8.eq $push14=, $7, $8
; CHECK-NEXT: i8x16.shuffle $push16=, $pop15, $pop14, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
-; CHECK-NEXT: i32.const $push36=, 7
-; CHECK-NEXT: i8x16.shl $push17=, $pop16, $pop36
-; CHECK-NEXT: i32.const $push35=, 7
-; CHECK-NEXT: i8x16.shr_s $push18=, $pop17, $pop35
-; CHECK-NEXT: i8x16.all_true $push19=, $pop18
-; CHECK-NEXT: i32.and $push20=, $pop13, $pop19
-; CHECK-NEXT: i16x8.eq $push22=, $6, $8
-; CHECK-NEXT: i16x8.eq $push21=, $7, $8
-; CHECK-NEXT: i8x16.shuffle $push23=, $pop22, $pop21, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
-; CHECK-NEXT: i32.const $push34=, 7
-; CHECK-NEXT: i8x16.shl $push24=, $pop23, $pop34
-; CHECK-NEXT: i32.const $push33=, 7
-; CHECK-NEXT: i8x16.shr_s $push25=, $pop24, $pop33
-; CHECK-NEXT: i8x16.all_true $push26=, $pop25
-; CHECK-NEXT: i32.and $push27=, $pop20, $pop26
-; CHECK-NEXT: i32.const $push28=, -1
-; CHECK-NEXT: i32.xor $push29=, $pop27, $pop28
-; CHECK-NEXT: i64.extend_i32_u $push30=, $pop29
-; CHECK-NEXT: i64.const $push31=, 1
-; CHECK-NEXT: i64.and $push32=, $pop30, $pop31
-; CHECK-NEXT: return $pop32
+; CHECK-NEXT: i8x16.all_true $push17=, $pop16
+; CHECK-NEXT: i32.and $push18=, $pop13, $pop17
+; CHECK-NEXT: i32.const $push19=, -1
+; CHECK-NEXT: i32.xor $push20=, $pop18, $pop19
+; CHECK-NEXT: i64.extend_i32_u $push21=, $pop20
+; CHECK-NEXT: i64.const $push22=, 1
+; CHECK-NEXT: i64.and $push23=, $pop21, $pop22
+; CHECK-NEXT: return $pop23
%1 = icmp eq <64 x i16> %v, zeroinitializer
%2 = bitcast <64 x i1> %1 to i64
%3 = icmp ne i64 %2, -1
@@ -703,28 +679,20 @@ define i32 @any_true_big_v32i16(<32 x i16> %v) {
; CHECK-LABEL: any_true_big_v32i16:
; CHECK: .functype any_true_big_v32i16 (v128, v128, v128, v128) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: v128.const $push20=, 0, 0, 0, 0, 0, 0, 0, 0
-; CHECK-NEXT: local.tee $push19=, $4=, $pop20
-; CHECK-NEXT: i16x8.eq $push8=, $0, $pop19
-; CHECK-NEXT: i16x8.eq $push7=, $1, $4
-; CHECK-NEXT: i8x16.shuffle $push9=, $pop8, $pop7, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
-; CHECK-NEXT: i32.const $push3=, 7
-; CHECK-NEXT: i8x16.shl $push10=, $pop9, $pop3
-; CHECK-NEXT: i32.const $push18=, 7
-; CHECK-NEXT: i8x16.shr_s $push11=, $pop10, $pop18
-; CHECK-NEXT: v128.any_true $push12=, $pop11
+; CHECK-NEXT: v128.const $push12=, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT: local.tee $push11=, $4=, $pop12
+; CHECK-NEXT: i16x8.eq $push5=, $0, $pop11
+; CHECK-NEXT: i16x8.eq $push4=, $1, $4
+; CHECK-NEXT: i8x16.shuffle $push6=, $pop5, $pop4, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
+; CHECK-NEXT: v128.any_true $push7=, $pop6
; CHECK-NEXT: i16x8.eq $push1=, $2, $4
; CHECK-NEXT: i16x8.eq $push0=, $3, $4
; CHECK-NEXT: i8x16.shuffle $push2=, $pop1, $pop0, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
-; CHECK-NEXT: i32.const $push17=, 7
-; CHECK-NEXT: i8x16.shl $push4=, $pop2, $pop17
-; CHECK-NEXT: i32.const $push16=, 7
-; CHECK-NEXT: i8x16.shr_s $push5=, $pop4, $pop16
-; CHECK-NEXT: v128.any_true $push6=, $pop5
-; CHECK-NEXT: i32.or $push13=, $pop12, $pop6
-; CHECK-NEXT: i32.const $push14=, 1
-; CHECK-NEXT: i32.and $push15=, $pop13, $pop14
-; CHECK-NEXT: return $pop15
+; CHECK-NEXT: v128.any_true $push3=, $pop2
+; CHECK-NEXT: i32.or $push8=, $pop7, $pop3
+; CHECK-NEXT: i32.const $push9=, 1
+; CHECK-NEXT: i32.and $push10=, $pop8, $pop9
+; CHECK-NEXT: return $pop10
%1 = icmp eq <32 x i16> %v, zeroinitializer
%2 = bitcast <32 x i1> %1 to i32
%3 = icmp ne i32 %2, 0
@@ -736,47 +704,31 @@ define i64 @any_true_big_v64i16(<64 x i16> %v) {
; CHECK-LABEL: any_true_big_v64i16:
; CHECK: .functype any_true_big_v64i16 (v128, v128, v128, v128, v128, v128, v128, v128) -> (i64)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: v128.const $push39=, 0, 0, 0, 0, 0, 0, 0, 0
-; CHECK-NEXT: local.tee $push38=, $8=, $pop39
-; CHECK-NEXT: i16x8.eq $push8=, $0, $pop38
-; CHECK-NEXT: i16x8.eq $push7=, $1, $8
-; CHECK-NEXT: i8x16.shuffle $push9=, $pop8, $pop7, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
-; CHECK-NEXT: i32.const $push3=, 7
-; CHECK-NEXT: i8x16.shl $push10=, $pop9, $pop3
-; CHECK-NEXT: i32.const $push37=, 7
-; CHECK-NEXT: i8x16.shr_s $push11=, $pop10, $pop37
-; CHECK-NEXT: v128.any_true $push12=, $pop11
+; CHECK-NEXT: v128.const $push23=, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT: local.tee $push22=, $8=, $pop23
+; CHECK-NEXT: i16x8.eq $push5=, $0, $pop22
+; CHECK-NEXT: i16x8.eq $push4=, $1, $8
+; CHECK-NEXT: i8x16.shuffle $push6=, $pop5, $pop4, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
+; CHECK-NEXT: v128.any_true $push7=, $pop6
; CHECK-NEXT: i16x8.eq $push1=, $2, $8
; CHECK-NEXT: i16x8.eq $push0=, $3, $8
; CHECK-NEXT: i8x16.shuffle $push2=, $pop1, $pop0, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
-; CHECK-NEXT: i32.const $push36=, 7
-; CHECK-NEXT: i8x16.shl $push4=, $pop2, $pop36
-; CHECK-NEXT: i32.const $push35=, 7
-; CHECK-NEXT: i8x16.shr_s $push5=, $pop4, $pop35
-; CHECK-NEXT: v128.any_true $push6=, $pop5
-; CHECK-NEXT: i32.or $push13=, $pop12, $pop6
-; CHECK-NEXT: i16x8.eq $push15=, $4, $8
-; CHECK-NEXT: i16x8.eq $push14=, $5, $8
+; CHECK-NEXT: v128.any_true $push3=, $pop2
+; CHECK-NEXT: i32.or $push8=, $pop7, $pop3
+; CHECK-NEXT: i16x8.eq $push10=, $4, $8
+; CHECK-NEXT: i16x8.eq $push9=, $5, $8
+; CHECK-NEXT: i8x16.shuffle $push11=, $pop10, $pop9, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
+; CHECK-NEXT: v128.any_true $push12=, $pop11
+; CHECK-NEXT: i32.or $push13=, $pop8, $pop12
+; CHECK-NEXT: i16x8.eq $push15=, $6, $8
+; CHECK-NEXT: i16x8.eq $push14=, $7, $8
; CHECK-NEXT: i8x16.shuffle $push16=, $pop15, $pop14, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
-; CHECK-NEXT: i32.const $push34=, 7
-; CHECK-NEXT: i8x16.shl $push17=, $pop16, $pop34
-; CHECK-NEXT: i32.const $push33=, 7
-; CHECK-NEXT: i8x16.shr_s $push18=, $pop17, $pop33
-; CHECK-NEXT: v128.any_true $push19=, $pop18
-; CHECK-NEXT: i32.or $push20=, $pop13, $pop19
-; CHECK-NEXT: i16x8.eq $push22=, $6, $8
-; CHECK-NEXT: i16x8.eq $push21=, $7, $8
-; CHECK-NEXT: i8x16.shuffle $push23=, $pop22, $pop21, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
-; CHECK-NEXT: i32.const $push32=, 7
-; CHECK-NEXT: i8x16.shl $push24=, $pop23, $pop32
-; CHECK-NEXT: i32.const $push31=, 7
-; CHECK-NEXT: i8x16.shr_s $push25=, $pop24, $pop31
-; CHECK-NEXT: v128.any_true $push26=, $pop25
-; CHECK-NEXT: i32.or $push27=, $pop20, $pop26
-; CHECK-NEXT: i64.extend_i32_u $push28=, $pop27
-; CHECK-NEXT: i64.const $push29=, 1
-; CHECK-NEXT: i64.and $push30=, $pop28, $pop29
-; CHECK-NEXT: return $pop30
+; CHECK-NEXT: v128.any_true $push17=, $pop16
+; CHECK-NEXT: i32.or $push18=, $pop13, $pop17
+; CHECK-NEXT: i64.extend_i32_u $push19=, $pop18
+; CHECK-NEXT: i64.const $push20=, 1
+; CHECK-NEXT: i64.and $push21=, $pop19, $pop20
+; CHECK-NEXT: return $pop21
%1 = icmp eq <64 x i16> %v, zeroinitializer
%2 = bitcast <64 x i1> %1 to i64
%3 = icmp ne i64 %2, 0
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