[llvm] [MachinePipeliner] Use VirtRegOrUnit instead of Register appropriately (PR #177535)

[via llvm-commits]

hjagasiaAMD wrote:

Thanks for the ping. The changes look correct to me. An existing AArch64 test may work as a regression test. 

diff --git a/llvm/test/CodeGen/AArch64/sms-regpress.mir b/llvm/test/CodeGen/A\
Arch64/sms-regpress.mir
index 0e126ccf87cb..b6129db1a3ea 100644
--- a/llvm/test/CodeGen/AArch64/sms-regpress.mir
+++ b/llvm/test/CodeGen/AArch64/sms-regpress.mir
@@ -5,7 +5,12 @@
 # Check that if the register pressure is too high, the schedule is rejected,\
 II is incremented, and scheduling continues.
 # The specific value of II is not important.

+# Check that an allocatable physical register unit is not mistaken for a
+# reserved physical register when their numeric IDs coincide.
 # CHECK: {{^ *}}Try to schedule with {{[0-9]+$}}
+# W2's register-unit ID is 237, the same numeric value as the reserved W29
+# physical-register ID. Ensure the unit is not mistaken for W29 and skipped.
+# CHECK: insert W2
 # CHECK: {{^ *}}Rejected the schedule because of too high register pressure{\
{$}}
 # CHECK: {{^ *}}Try to schedule with {{[0-9]+$}}
 # CHECK: {{^ *}}Schedule Found? 1 (II={{[0-9]+}}){{$}}
@@ -118,7 +123,7 @@ body:             |
     %5:gpr64sp = PHI %11, %bb.1, %8, %bb.3
     %6:fpr64 = PHI %15, %bb.1, %7, %bb.3
     early-clobber %17:gpr64sp, %18:fpr64 = LDRDpost %5, 8 :: (load (s64) fro\
m %ir.lsr.iv)
-    %19:fpr64 = nofpexcept FMADDDrrr %0, %18, %0, implicit $fpcr
+    %19:fpr64 = nofpexcept FMADDDrrr %0, %18, %0, implicit $fpcr, implicit-d\
ef $x2
     %20:fpr64 = nofpexcept FMADDDrrr %19, %18, %19, implicit $fpcr
     %21:fpr64 = nofpexcept FMADDDrrr %20, %18, %20, implicit $fpcr
     %22:fpr64 = nofpexcept FMADDDrrr %21, %18, %21, implicit $fpcr


https://github.com/llvm/llvm-project/pull/177535