[llvm] [RISCV] Port Expand Pseudos to NewPM (PR #218078)
Sam Elliott via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 21 17:47:09 PDT 2026
https://github.com/lenary created https://github.com/llvm/llvm-project/pull/218078
Assisted-by: AI
>From 8f8279ee167fc270ec9fe1c5a7716b3bc39ce71a Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Fri, 21 Aug 2026 17:45:47 -0700
Subject: [PATCH] [RISCV] Port Expand Pseudos to NewPM
Assisted-by: AI
---
llvm/lib/Target/RISCV/RISCV.h | 11 ++-
.../Target/RISCV/RISCVCodeGenPassBuilder.cpp | 2 +-
.../Target/RISCV/RISCVExpandPseudoInsts.cpp | 87 +++++++++++--------
llvm/lib/Target/RISCV/RISCVPassRegistry.def | 1 +
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 4 +-
llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll | 1 +
llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll | 1 +
llvm/test/CodeGen/RISCV/expand-pseudo.mir | 30 +++++++
8 files changed, 98 insertions(+), 39 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/expand-pseudo.mir
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index 504c268a57ffb..6986793599b31 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -110,8 +110,15 @@ void initializeRISCVFoldMemOffsetLegacyPass(PassRegistry &);
FunctionPass *createRISCVMergeBaseOffsetOptPass();
void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &);
-FunctionPass *createRISCVExpandPseudoPass();
-void initializeRISCVExpandPseudoPass(PassRegistry &);
+class RISCVExpandPseudoPass
+ : public OptionalPassInfoMixin<RISCVExpandPseudoPass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
+
+FunctionPass *createRISCVExpandPseudoLegacyPass();
+void initializeRISCVExpandPseudoLegacyPass(PassRegistry &);
FunctionPass *createRISCVPreRAExpandPseudoPass();
void initializeRISCVPreRAExpandPseudoPass(PassRegistry &);
diff --git a/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp b/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
index f51b44776e916..596b55c7bc25e 100644
--- a/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+++ b/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
@@ -176,7 +176,7 @@ void RISCVCodeGenPassBuilder::addPreEmitPass2(PassManagerWrapper &PMW) {
// TODO: RISCVMoveMergePass
// TODO: RISCVPushPopOptimizationPass
}
- // TODO: RISCVExpandPseudoPass
+ addMachineFunctionPass(RISCVExpandPseudoPass(), PMW);
// Add QC Relaxation Markers as late as possible, and only for RV32
if (getOptLevel() != CodeGenOptLevel::None &&
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
index cf86dbcc8908e..649e40e58f3fc 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -28,17 +28,11 @@ using namespace llvm;
namespace {
-class RISCVExpandPseudo : public MachineFunctionPass {
+class RISCVExpandPseudoImpl {
public:
const RISCVSubtarget *STI;
const RISCVInstrInfo *TII;
- static char ID;
-
- RISCVExpandPseudo() : MachineFunctionPass(ID) {}
-
- bool runOnMachineFunction(MachineFunction &MF) override;
-
- StringRef getPassName() const override { return RISCV_EXPAND_PSEUDO_NAME; }
+ bool run(MachineFunction &MF);
private:
bool expandMBB(MachineBasicBlock &MBB);
@@ -73,9 +67,22 @@ class RISCVExpandPseudo : public MachineFunctionPass {
#endif
};
-char RISCVExpandPseudo::ID = 0;
+class RISCVExpandPseudoLegacy : public MachineFunctionPass {
+public:
+ static char ID;
+
+ RISCVExpandPseudoLegacy() : MachineFunctionPass(ID) {}
+
+ bool runOnMachineFunction(MachineFunction &MF) override {
+ return RISCVExpandPseudoImpl().run(MF);
+ }
-bool RISCVExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
+ StringRef getPassName() const override { return RISCV_EXPAND_PSEUDO_NAME; }
+};
+
+char RISCVExpandPseudoLegacy::ID = 0;
+
+bool RISCVExpandPseudoImpl::run(MachineFunction &MF) {
STI = &MF.getSubtarget<RISCVSubtarget>();
TII = STI->getInstrInfo();
@@ -94,7 +101,7 @@ bool RISCVExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
return Modified;
}
-bool RISCVExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
+bool RISCVExpandPseudoImpl::expandMBB(MachineBasicBlock &MBB) {
bool Modified = false;
MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
@@ -107,9 +114,9 @@ bool RISCVExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
return Modified;
}
-bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
+bool RISCVExpandPseudoImpl::expandMI(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) {
// RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
// expanded instructions for each pseudo is correct in the Size field of the
// tablegen definition for the pseudo.
@@ -201,9 +208,9 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
return false;
}
-bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
+bool RISCVExpandPseudoImpl::expandCCOp(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) {
// First try expanding to a Conditional Move rather than a branch+mv
if (expandCCOpToCMov(MBB, MBBI))
return true;
@@ -330,8 +337,8 @@ bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
return true;
}
-bool RISCVExpandPseudo::expandCCOpToCMov(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI) {
+bool RISCVExpandPseudoImpl::expandCCOpToCMov(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI) {
MachineInstr &MI = *MBBI;
DebugLoc DL = MI.getDebugLoc();
@@ -457,9 +464,9 @@ bool RISCVExpandPseudo::expandCCOpToCMov(MachineBasicBlock &MBB,
return true;
}
-bool RISCVExpandPseudo::expandVMSET_VMCLR(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- unsigned Opcode) {
+bool RISCVExpandPseudoImpl::expandVMSET_VMCLR(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned Opcode) {
DebugLoc DL = MBBI->getDebugLoc();
Register DstReg = MBBI->getOperand(0).getReg();
const MCInstrDesc &Desc = TII->get(Opcode);
@@ -470,8 +477,8 @@ bool RISCVExpandPseudo::expandVMSET_VMCLR(MachineBasicBlock &MBB,
return true;
}
-bool RISCVExpandPseudo::expandMV_FPR16INX(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI) {
+bool RISCVExpandPseudoImpl::expandMV_FPR16INX(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
DebugLoc DL = MBBI->getDebugLoc();
const TargetRegisterInfo *TRI = STI->getRegisterInfo();
Register DstReg = TRI->getMatchingSuperReg(
@@ -487,8 +494,8 @@ bool RISCVExpandPseudo::expandMV_FPR16INX(MachineBasicBlock &MBB,
return true;
}
-bool RISCVExpandPseudo::expandMV_FPR32INX(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI) {
+bool RISCVExpandPseudoImpl::expandMV_FPR32INX(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
DebugLoc DL = MBBI->getDebugLoc();
const TargetRegisterInfo *TRI = STI->getRegisterInfo();
Register DstReg = TRI->getMatchingSuperReg(
@@ -507,8 +514,8 @@ bool RISCVExpandPseudo::expandMV_FPR32INX(MachineBasicBlock &MBB,
// This function expands the PseudoRV32ZdinxSD for storing a double-precision
// floating-point value into memory by generating an equivalent instruction
// sequence for RV32.
-bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI) {
+bool RISCVExpandPseudoImpl::expandRV32ZdinxStore(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
DebugLoc DL = MBBI->getDebugLoc();
const TargetRegisterInfo *TRI = STI->getRegisterInfo();
Register Lo =
@@ -556,8 +563,8 @@ bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
// This function expands PseudoRV32ZdinxLoad for loading a double-precision
// floating-point value from memory into an equivalent instruction sequence for
// RV32.
-bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI) {
+bool RISCVExpandPseudoImpl::expandRV32ZdinxLoad(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
DebugLoc DL = MBBI->getDebugLoc();
const TargetRegisterInfo *TRI = STI->getRegisterInfo();
Register Lo =
@@ -614,7 +621,7 @@ bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
return true;
}
-bool RISCVExpandPseudo::expandPseudoReadVLENBViaVSETVLIX0(
+bool RISCVExpandPseudoImpl::expandPseudoReadVLENBViaVSETVLIX0(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
DebugLoc DL = MBBI->getDebugLoc();
Register Dst = MBBI->getOperand(0).getReg();
@@ -632,7 +639,7 @@ bool RISCVExpandPseudo::expandPseudoReadVLENBViaVSETVLIX0(
return true;
}
-bool RISCVExpandPseudo::expandPseudoClearFPR64(
+bool RISCVExpandPseudoImpl::expandPseudoClearFPR64(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
const DebugLoc &DL = MBBI->getDebugLoc();
Register Dst = MBBI->getOperand(0).getReg();
@@ -864,7 +871,7 @@ bool RISCVPreRAExpandPseudo::expandLoadTLSDescAddress(
} // end of anonymous namespace
-INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo",
+INITIALIZE_PASS(RISCVExpandPseudoLegacy, "riscv-expand-pseudo",
RISCV_EXPAND_PSEUDO_NAME, false, false)
INITIALIZE_PASS(RISCVPreRAExpandPseudo, "riscv-prera-expand-pseudo",
@@ -872,7 +879,19 @@ INITIALIZE_PASS(RISCVPreRAExpandPseudo, "riscv-prera-expand-pseudo",
namespace llvm {
-FunctionPass *createRISCVExpandPseudoPass() { return new RISCVExpandPseudo(); }
+FunctionPass *createRISCVExpandPseudoLegacyPass() {
+ return new RISCVExpandPseudoLegacy();
+}
+
+PreservedAnalyses
+RISCVExpandPseudoPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ bool Changed = RISCVExpandPseudoImpl().run(MF);
+ if (!Changed)
+ return PreservedAnalyses::all();
+ return getMachineFunctionPassPreservedAnalyses();
+}
+
FunctionPass *createRISCVPreRAExpandPseudoPass() { return new RISCVPreRAExpandPseudo(); }
} // end of namespace llvm
diff --git a/llvm/lib/Target/RISCV/RISCVPassRegistry.def b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
index b62d195982ecb..e68ec3e6fc37e 100644
--- a/llvm/lib/Target/RISCV/RISCVPassRegistry.def
+++ b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
@@ -33,6 +33,7 @@ FUNCTION_PASS("riscv-zacas-abi-fix", RISCVZacasABIFixPass(this))
#define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS)
#endif
MACHINE_FUNCTION_PASS("riscv-asm-printer", RISCVAsmPrinterPass())
+MACHINE_FUNCTION_PASS("riscv-expand-pseudo", RISCVExpandPseudoPass())
MACHINE_FUNCTION_PASS("riscv-fold-mem-offset", RISCVFoldMemOffsetPass())
MACHINE_FUNCTION_PASS("riscv-isel", RISCVISelDAGToDAGPass(*this, getOptLevel()))
MACHINE_FUNCTION_PASS("riscv-opt-w-instrs", RISCVOptWInstrsPass())
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 5d891fcd998cc..c21e420ed1ea9 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -135,7 +135,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
initializeRISCVOptWInstrsLegacyPass(*PR);
initializeRISCVFoldMemOffsetLegacyPass(*PR);
initializeRISCVPreRAExpandPseudoPass(*PR);
- initializeRISCVExpandPseudoPass(*PR);
+ initializeRISCVExpandPseudoLegacyPass(*PR);
initializeRISCVVectorPeepholeLegacyPass(*PR);
initializeRISCVVLOptimizerLegacyPass(*PR);
initializeRISCVVMV0EliminationPass(*PR);
@@ -589,7 +589,7 @@ void RISCVPassConfig::addPreEmitPass2() {
// ensuring return instruction is detected correctly.
addPass(createRISCVPushPopOptimizationPass());
}
- addPass(createRISCVExpandPseudoPass());
+ addPass(createRISCVExpandPseudoLegacyPass());
// Add QC Relaxation Markers as late as possible, and only for RV32
if (TM->getOptLevel() != CodeGenOptLevel::None &&
diff --git a/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll b/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
index eb054e64e32ff..2949919af41af 100644
--- a/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
@@ -102,6 +102,7 @@
; CHECK-NEXT: function
; CHECK-NEXT: machine-function
; CHECK-NEXT: stack-frame-layout
+; CHECK-NEXT: riscv-expand-pseudo
; CHECK-NEXT: unpack-mi-bundles
; CHECK-NEXT: verify
; CHECK-NEXT: riscv-asm-printer
diff --git a/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
index 593912c130e19..6109a3da11020 100644
--- a/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
@@ -103,6 +103,7 @@
; CHECK-NEXT: function
; CHECK-NEXT: machine-function
; CHECK-NEXT: stack-frame-layout
+; CHECK-NEXT: riscv-expand-pseudo
; CHECK-NEXT: unpack-mi-bundles
; CHECK-NEXT: verify
; CHECK-NEXT: riscv-asm-printer
diff --git a/llvm/test/CodeGen/RISCV/expand-pseudo.mir b/llvm/test/CodeGen/RISCV/expand-pseudo.mir
new file mode 100644
index 0000000000000..82c265224edd4
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/expand-pseudo.mir
@@ -0,0 +1,30 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=riscv-expand-pseudo %s -o - \
+# RUN: | FileCheck %s --check-prefixes=RV32
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=riscv-expand-pseudo %s -o - \
+# RUN: | FileCheck %s --check-prefixes=RV64
+# RUN: llc -mtriple=riscv32 -mattr=+d -passes=riscv-expand-pseudo %s -o - \
+# RUN: | FileCheck %s --check-prefixes=RV32
+# RUN: llc -mtriple=riscv64 -mattr=+d -passes=riscv-expand-pseudo %s -o - \
+# RUN: | FileCheck %s --check-prefixes=RV64
+
+--- |
+ define void @test() {
+ ret void
+ }
+...
+---
+name: test
+noVRegs: true
+body: |
+ bb.0:
+ ; RV32-LABEL: name: test
+ ; RV32: $f10_d = FCVT_D_W $x0, 0
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test
+ ; RV64: $f10_d = FMV_D_X $x0
+ ; RV64-NEXT: PseudoRET
+ $f10_d = PseudoClearFPR64
+ PseudoRET
+...
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