[llvm] [RISCV] Port PreRA Pseudo Expansion to NewPM (PR #218069)
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Fri Aug 21 17:04:33 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Sam Elliott (lenary)
<details>
<summary>Changes</summary>
Assisted-by: AI
---
Full diff: https://github.com/llvm/llvm-project/pull/218069.diff
8 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCV.h (+12-2)
- (modified) llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp (+1-1)
- (modified) llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp (+53-28)
- (modified) llvm/lib/Target/RISCV/RISCVPassRegistry.def (+2)
- (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+2-2)
- (modified) llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll (+1)
- (modified) llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll (+1)
- (added) llvm/test/CodeGen/RISCV/prera-expand-pseudo.mir (+50)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index 504c268a57ffb..ecc459eb02a7e 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -113,8 +113,18 @@ void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &);
FunctionPass *createRISCVExpandPseudoPass();
void initializeRISCVExpandPseudoPass(PassRegistry &);
-FunctionPass *createRISCVPreRAExpandPseudoPass();
-void initializeRISCVPreRAExpandPseudoPass(PassRegistry &);
+class RISCVPreRAExpandPseudoPass
+ : public OptionalPassInfoMixin<RISCVPreRAExpandPseudoPass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+ MachineFunctionProperties getRequiredProperties() const {
+ return MachineFunctionProperties().setIsSSA();
+ }
+};
+
+FunctionPass *createRISCVPreRAExpandPseudoLegacyPass();
+void initializeRISCVPreRAExpandPseudoLegacyPass(PassRegistry &);
FunctionPass *createRISCVExpandAtomicPseudoPass();
void initializeRISCVExpandAtomicPseudoPass(PassRegistry &);
diff --git a/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp b/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
index f51b44776e916..cbf204ae3b322 100644
--- a/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+++ b/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
@@ -123,7 +123,7 @@ void RISCVCodeGenPassBuilder::addMachineSSAOptimization(
}
void RISCVCodeGenPassBuilder::addPreRegAlloc(PassManagerWrapper &PMW) {
- // TODO: RISCVPreRAExpandPseudoPass
+ addMachineFunctionPass(RISCVPreRAExpandPseudoPass(), PMW);
if (getOptLevel() != CodeGenOptLevel::None) {
// TODO: RISCVMergeBaseOffsetOptPass
// TODO: RISCVPreAllocZilsdOptPass
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
index cf86dbcc8908e..b9cbc77249ca3 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -649,23 +649,11 @@ bool RISCVExpandPseudo::expandPseudoClearFPR64(
return true;
}
-class RISCVPreRAExpandPseudo : public MachineFunctionPass {
+class RISCVPreRAExpandPseudoImpl {
public:
const RISCVSubtarget *STI;
const RISCVInstrInfo *TII;
- static char ID;
-
- RISCVPreRAExpandPseudo() : MachineFunctionPass(ID) {}
-
- bool runOnMachineFunction(MachineFunction &MF) override;
-
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.setPreservesCFG();
- MachineFunctionPass::getAnalysisUsage(AU);
- }
- StringRef getPassName() const override {
- return RISCV_PRERA_EXPAND_PSEUDO_NAME;
- }
+ bool run(MachineFunction &MF);
private:
bool expandMBB(MachineBasicBlock &MBB);
@@ -702,9 +690,32 @@ class RISCVPreRAExpandPseudo : public MachineFunctionPass {
#endif
};
-char RISCVPreRAExpandPseudo::ID = 0;
+class RISCVPreRAExpandPseudoLegacy : public MachineFunctionPass {
+public:
+ static char ID;
-bool RISCVPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
+ RISCVPreRAExpandPseudoLegacy() : MachineFunctionPass(ID) {}
+
+ bool runOnMachineFunction(MachineFunction &MF) override {
+ return RISCVPreRAExpandPseudoImpl().run(MF);
+ }
+
+ MachineFunctionProperties getRequiredProperties() const override {
+ return MachineFunctionProperties().setIsSSA();
+ }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.setPreservesCFG();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+ StringRef getPassName() const override {
+ return RISCV_PRERA_EXPAND_PSEUDO_NAME;
+ }
+};
+
+char RISCVPreRAExpandPseudoLegacy::ID = 0;
+
+bool RISCVPreRAExpandPseudoImpl::run(MachineFunction &MF) {
STI = &MF.getSubtarget<RISCVSubtarget>();
TII = STI->getInstrInfo();
@@ -723,7 +734,7 @@ bool RISCVPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
return Modified;
}
-bool RISCVPreRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
+bool RISCVPreRAExpandPseudoImpl::expandMBB(MachineBasicBlock &MBB) {
bool Modified = false;
MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
@@ -736,9 +747,9 @@ bool RISCVPreRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
return Modified;
}
-bool RISCVPreRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
+bool RISCVPreRAExpandPseudoImpl::expandMI(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) {
switch (MBBI->getOpcode()) {
case RISCV::PseudoLLA:
@@ -755,7 +766,7 @@ bool RISCVPreRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
return false;
}
-bool RISCVPreRAExpandPseudo::expandAuipcInstPair(
+bool RISCVPreRAExpandPseudoImpl::expandAuipcInstPair(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
unsigned SecondOpcode) {
@@ -787,14 +798,14 @@ bool RISCVPreRAExpandPseudo::expandAuipcInstPair(
return true;
}
-bool RISCVPreRAExpandPseudo::expandLoadLocalAddress(
+bool RISCVPreRAExpandPseudoImpl::expandLoadLocalAddress(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) {
return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
RISCV::ADDI);
}
-bool RISCVPreRAExpandPseudo::expandLoadGlobalAddress(
+bool RISCVPreRAExpandPseudoImpl::expandLoadGlobalAddress(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) {
unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
@@ -802,7 +813,7 @@ bool RISCVPreRAExpandPseudo::expandLoadGlobalAddress(
SecondOpcode);
}
-bool RISCVPreRAExpandPseudo::expandLoadTLSIEAddress(
+bool RISCVPreRAExpandPseudoImpl::expandLoadTLSIEAddress(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) {
unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
@@ -810,14 +821,14 @@ bool RISCVPreRAExpandPseudo::expandLoadTLSIEAddress(
SecondOpcode);
}
-bool RISCVPreRAExpandPseudo::expandLoadTLSGDAddress(
+bool RISCVPreRAExpandPseudoImpl::expandLoadTLSGDAddress(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) {
return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
RISCV::ADDI);
}
-bool RISCVPreRAExpandPseudo::expandLoadTLSDescAddress(
+bool RISCVPreRAExpandPseudoImpl::expandLoadTLSDescAddress(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) {
MachineFunction *MF = MBB.getParent();
@@ -867,12 +878,26 @@ bool RISCVPreRAExpandPseudo::expandLoadTLSDescAddress(
INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo",
RISCV_EXPAND_PSEUDO_NAME, false, false)
-INITIALIZE_PASS(RISCVPreRAExpandPseudo, "riscv-prera-expand-pseudo",
+INITIALIZE_PASS(RISCVPreRAExpandPseudoLegacy, "riscv-prera-expand-pseudo",
RISCV_PRERA_EXPAND_PSEUDO_NAME, false, false)
namespace llvm {
FunctionPass *createRISCVExpandPseudoPass() { return new RISCVExpandPseudo(); }
-FunctionPass *createRISCVPreRAExpandPseudoPass() { return new RISCVPreRAExpandPseudo(); }
+FunctionPass *createRISCVPreRAExpandPseudoLegacyPass() {
+ return new RISCVPreRAExpandPseudoLegacy();
+}
+
+PreservedAnalyses
+RISCVPreRAExpandPseudoPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ bool Changed = RISCVPreRAExpandPseudoImpl().run(MF);
+ if (!Changed)
+ return PreservedAnalyses::all();
+
+ PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ return PA;
+}
} // end of namespace llvm
diff --git a/llvm/lib/Target/RISCV/RISCVPassRegistry.def b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
index b62d195982ecb..0b303aa256edc 100644
--- a/llvm/lib/Target/RISCV/RISCVPassRegistry.def
+++ b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
@@ -36,6 +36,8 @@ MACHINE_FUNCTION_PASS("riscv-asm-printer", RISCVAsmPrinterPass())
MACHINE_FUNCTION_PASS("riscv-fold-mem-offset", RISCVFoldMemOffsetPass())
MACHINE_FUNCTION_PASS("riscv-isel", RISCVISelDAGToDAGPass(*this, getOptLevel()))
MACHINE_FUNCTION_PASS("riscv-opt-w-instrs", RISCVOptWInstrsPass())
+MACHINE_FUNCTION_PASS("riscv-prera-expand-pseudo",
+ RISCVPreRAExpandPseudoPass())
MACHINE_FUNCTION_PASS("riscv-vector-peephole", RISCVVectorPeepholePass())
MACHINE_FUNCTION_PASS("riscv-vl-optimizer", RISCVVLOptimizerPass())
#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 5d891fcd998cc..369086a08b785 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -134,7 +134,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
initializeRISCVMergeBaseOffsetOptPass(*PR);
initializeRISCVOptWInstrsLegacyPass(*PR);
initializeRISCVFoldMemOffsetLegacyPass(*PR);
- initializeRISCVPreRAExpandPseudoPass(*PR);
+ initializeRISCVPreRAExpandPseudoLegacyPass(*PR);
initializeRISCVExpandPseudoPass(*PR);
initializeRISCVVectorPeepholeLegacyPass(*PR);
initializeRISCVVLOptimizerLegacyPass(*PR);
@@ -635,7 +635,7 @@ void RISCVPassConfig::addMachineSSAOptimization() {
}
void RISCVPassConfig::addPreRegAlloc() {
- addPass(createRISCVPreRAExpandPseudoPass());
+ addPass(createRISCVPreRAExpandPseudoLegacyPass());
if (TM->getOptLevel() != CodeGenOptLevel::None) {
addPass(createRISCVMergeBaseOffsetOptPass());
// Add Zilsd pre-allocation load/store optimization
diff --git a/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll b/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
index eb054e64e32ff..f5f67d996f0b5 100644
--- a/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
@@ -60,6 +60,7 @@
; CHECK-NEXT: peephole-opt
; CHECK-NEXT: dead-mi-elimination
; RV64-NEXT: riscv-opt-w-instrs
+; CHECK-NEXT: riscv-prera-expand-pseudo
; CHECK-NEXT: detect-dead-lanes
; CHECK-NEXT: init-undef
; CHECK-NEXT: process-imp-defs
diff --git a/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
index 593912c130e19..7873d1db04108 100644
--- a/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
@@ -60,6 +60,7 @@
; CHECK-NEXT: peephole-opt
; CHECK-NEXT: dead-mi-elimination
; RV64-NEXT: riscv-opt-w-instrs
+; CHECK-NEXT: riscv-prera-expand-pseudo
; CHECK-NEXT: detect-dead-lanes
; CHECK-NEXT: init-undef
; CHECK-NEXT: process-imp-defs
diff --git a/llvm/test/CodeGen/RISCV/prera-expand-pseudo.mir b/llvm/test/CodeGen/RISCV/prera-expand-pseudo.mir
new file mode 100644
index 0000000000000..cbe929bdf43ee
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/prera-expand-pseudo.mir
@@ -0,0 +1,50 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=riscv32 -run-pass=riscv-prera-expand-pseudo %s -o - \
+# RUN: | FileCheck %s --check-prefixes=CHECK,RV32
+# RUN: llc -mtriple=riscv64 -run-pass=riscv-prera-expand-pseudo %s -o - \
+# RUN: | FileCheck %s --check-prefixes=CHECK,RV64
+# RUN: llc -mtriple=riscv32 -passes=riscv-prera-expand-pseudo %s -o - \
+# RUN: | FileCheck %s --check-prefixes=CHECK,RV32
+# RUN: llc -mtriple=riscv64 -passes=riscv-prera-expand-pseudo %s -o - \
+# RUN: | FileCheck %s --check-prefixes=CHECK,RV64
+
+--- |
+ @global = external global i32
+ @tls = external thread_local global i32
+
+ define void @test() {
+ ret void
+ }
+...
+---
+name: test
+isSSA: true
+body: |
+ bb.0:
+ ; RV32-LABEL: name: test
+ ; RV32: [[AUIPC:%[0-9]+]]:gpr = AUIPC target-flags(riscv-pcrel-hi) @global, pre-instr-symbol <mcsymbol .Lpcrel_hi0>
+ ; RV32-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[AUIPC]], target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi0>
+ ; RV32-NEXT: [[AUIPC1:%[0-9]+]]:gpr = AUIPC target-flags(riscv-got-hi) @global, pre-instr-symbol <mcsymbol .Lpcrel_hi1>
+ ; RV32-NEXT: [[LW:%[0-9]+]]:gpr = LW [[AUIPC1]], target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable invariant load (s32) from got)
+ ; RV32-NEXT: [[AUIPC2:%[0-9]+]]:gpr = AUIPC target-flags(riscv-tls-got-hi) @tls, pre-instr-symbol <mcsymbol .Lpcrel_hi2>
+ ; RV32-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[AUIPC2]], target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi2> :: (dereferenceable invariant load (s32) from got)
+ ; RV32-NEXT: [[AUIPC3:%[0-9]+]]:gpr = AUIPC target-flags(riscv-tls-gd-hi) @tls, pre-instr-symbol <mcsymbol .Lpcrel_hi3>
+ ; RV32-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI [[AUIPC3]], target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi3>
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test
+ ; RV64: [[AUIPC:%[0-9]+]]:gpr = AUIPC target-flags(riscv-pcrel-hi) @global, pre-instr-symbol <mcsymbol .Lpcrel_hi0>
+ ; RV64-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[AUIPC]], target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi0>
+ ; RV64-NEXT: [[AUIPC1:%[0-9]+]]:gpr = AUIPC target-flags(riscv-got-hi) @global, pre-instr-symbol <mcsymbol .Lpcrel_hi1>
+ ; RV64-NEXT: [[LD:%[0-9]+]]:gpr = LD [[AUIPC1]], target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable invariant load (s32) from got)
+ ; RV64-NEXT: [[AUIPC2:%[0-9]+]]:gpr = AUIPC target-flags(riscv-tls-got-hi) @tls, pre-instr-symbol <mcsymbol .Lpcrel_hi2>
+ ; RV64-NEXT: [[LD1:%[0-9]+]]:gpr = LD [[AUIPC2]], target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi2> :: (dereferenceable invariant load (s32) from got)
+ ; RV64-NEXT: [[AUIPC3:%[0-9]+]]:gpr = AUIPC target-flags(riscv-tls-gd-hi) @tls, pre-instr-symbol <mcsymbol .Lpcrel_hi3>
+ ; RV64-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI [[AUIPC3]], target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi3>
+ ; RV64-NEXT: PseudoRET
+ %0:gpr = PseudoLLA @global
+ %1:gpr = PseudoLGA @global :: (dereferenceable invariant load (s32) from got)
+ %2:gpr = PseudoLA_TLS_IE @tls :: (dereferenceable invariant load (s32) from got)
+ %3:gpr = PseudoLA_TLS_GD @tls
+ PseudoRET
+...
``````````
</details>
https://github.com/llvm/llvm-project/pull/218069
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