[llvm] [AArch64][GlobalISel] Add tests for scalar types. NFC (PR #218006)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 21 12:10:39 PDT 2026
https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/218006
None
>From 6519131128968011fe4078a674e2d6f6c7e82cbf Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Fri, 21 Aug 2026 20:10:27 +0100
Subject: [PATCH] [AArch64][GlobalISel] Add tests for scalar types. NFC
---
.../AArch64/GlobalISel/irtranslator-vararg.ll | 70 +++++++++++++++++++
.../prelegalizer-combiner-scalar.mir | 43 ++++++++++++
2 files changed, 113 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vararg.ll
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-scalar.mir
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vararg.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vararg.ll
new file mode 100644
index 0000000000000..a9d7b540c502b
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vararg.ll
@@ -0,0 +1,70 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
+
+define i64 @vararg(...) #0 {
+ ; CHECK-LABEL: name: vararg
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: liveins: $q0, $q1, $q2, $q3, $q4, $q5, $q6, $q7, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: G_STORE [[COPY]](i64), [[FRAME_INDEX]](p0) :: (store (i64) into stack, align 1)
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](i64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: G_STORE [[COPY1]](i64), [[PTR_ADD]](p0) :: (store (i64) into stack + 8, align 1)
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](i64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: G_STORE [[COPY2]](i64), [[PTR_ADD1]](p0) :: (store (i64) into stack + 16, align 1)
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](i64)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: G_STORE [[COPY3]](i64), [[PTR_ADD2]](p0) :: (store (i64) into stack + 24, align 1)
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](i64)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: G_STORE [[COPY4]](i64), [[PTR_ADD3]](p0) :: (store (i64) into stack + 32, align 1)
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](i64)
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: G_STORE [[COPY5]](i64), [[PTR_ADD4]](p0) :: (store (i64) into stack + 40, align 1)
+ ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](i64)
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i64) = COPY $x6
+ ; CHECK-NEXT: G_STORE [[COPY6]](i64), [[PTR_ADD5]](p0) :: (store (i64) into stack + 48, align 1)
+ ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](i64)
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i64) = COPY $x7
+ ; CHECK-NEXT: G_STORE [[COPY7]](i64), [[PTR_ADD6]](p0) :: (store (i64) into stack + 56, align 1)
+ ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD6]], [[C]](i64)
+ ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s128) = COPY $q0
+ ; CHECK-NEXT: G_STORE [[COPY8]](s128), [[FRAME_INDEX1]](p0) :: (store (s128) into stack, align 1)
+ ; CHECK-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX1]], [[C1]](i64)
+ ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s128) = COPY $q1
+ ; CHECK-NEXT: G_STORE [[COPY9]](s128), [[PTR_ADD8]](p0) :: (store (s128) into stack + 16, align 1)
+ ; CHECK-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD8]], [[C1]](i64)
+ ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s128) = COPY $q2
+ ; CHECK-NEXT: G_STORE [[COPY10]](s128), [[PTR_ADD9]](p0) :: (store (s128) into stack + 32, align 1)
+ ; CHECK-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD9]], [[C1]](i64)
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(s128) = COPY $q3
+ ; CHECK-NEXT: G_STORE [[COPY11]](s128), [[PTR_ADD10]](p0) :: (store (s128) into stack + 48, align 1)
+ ; CHECK-NEXT: [[PTR_ADD11:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD10]], [[C1]](i64)
+ ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s128) = COPY $q4
+ ; CHECK-NEXT: G_STORE [[COPY12]](s128), [[PTR_ADD11]](p0) :: (store (s128) into stack + 64, align 1)
+ ; CHECK-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD11]], [[C1]](i64)
+ ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s128) = COPY $q5
+ ; CHECK-NEXT: G_STORE [[COPY13]](s128), [[PTR_ADD12]](p0) :: (store (s128) into stack + 80, align 1)
+ ; CHECK-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD12]], [[C1]](i64)
+ ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s128) = COPY $q6
+ ; CHECK-NEXT: G_STORE [[COPY14]](s128), [[PTR_ADD13]](p0) :: (store (s128) into stack + 96, align 1)
+ ; CHECK-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD13]], [[C1]](i64)
+ ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s128) = COPY $q7
+ ; CHECK-NEXT: G_STORE [[COPY15]](s128), [[PTR_ADD14]](p0) :: (store (s128) into stack + 112, align 1)
+ ; CHECK-NEXT: [[PTR_ADD15:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD14]], [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.2.g
+ ; CHECK-NEXT: G_VASTART [[FRAME_INDEX2]](p0) :: (store (s256) into %ir.g, align 4)
+ ; CHECK-NEXT: $x0 = COPY [[C2]](i64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+entry:
+ %g = alloca ptr, align 4
+ call void @llvm.va_start(ptr %g)
+ ret i64 1
+}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-scalar.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-scalar.mir
new file mode 100644
index 0000000000000..eacb7cacbb7e8
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-scalar.mir
@@ -0,0 +1,43 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64 -mattr=+dotprod -run-pass=aarch64-prelegalizer-combiner %s -o - | FileCheck %s
+
+---
+name: udot
+liveins:
+body: |
+ bb.0:
+ liveins: $x0, $x1
+ ; CHECK-LABEL: name: udot
+ ; CHECK: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<24 x i8>) = G_LOAD [[COPY]](p0) :: (load (<24 x i8>), align 32)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<24 x i8>) = G_LOAD [[COPY1]](p0) :: (load (<24 x i8>), align 32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<8 x i8>), [[UV1:%[0-9]+]]:_(<8 x i8>), [[UV2:%[0-9]+]]:_(<8 x i8>) = G_UNMERGE_VALUES [[LOAD1]](<24 x i8>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x i8>) = G_CONCAT_VECTORS [[UV]](<8 x i8>), [[UV1]](<8 x i8>)
+ ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(<8 x i8>), [[UV4:%[0-9]+]]:_(<8 x i8>), [[UV5:%[0-9]+]]:_(<8 x i8>) = G_UNMERGE_VALUES [[LOAD]](<24 x i8>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<16 x i8>) = G_CONCAT_VECTORS [[UV3]](<8 x i8>), [[UV4]](<8 x i8>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8)
+ ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<16 x i8>) = G_CONCAT_VECTORS [[UV2]](<8 x i8>), [[BUILD_VECTOR]](<8 x s8>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<16 x i8>) = G_CONCAT_VECTORS [[UV5]](<8 x i8>), [[BUILD_VECTOR]](<8 x s8>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[C1]](i32), [[C1]](i32), [[C1]](i32), [[C1]](i32)
+ ; CHECK-NEXT: [[UDOT:%[0-9]+]]:_(<4 x i32>) = G_UDOT [[BUILD_VECTOR1]], [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]
+ ; CHECK-NEXT: [[UDOT1:%[0-9]+]]:_(<4 x i32>) = G_UDOT [[BUILD_VECTOR1]], [[CONCAT_VECTORS2]], [[CONCAT_VECTORS3]]
+ ; CHECK-NEXT: [[CONCAT_VECTORS4:%[0-9]+]]:_(<8 x i32>) = G_CONCAT_VECTORS [[UDOT]](<4 x i32>), [[UDOT1]](<4 x i32>)
+ ; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(i32) = G_VECREDUCE_ADD [[CONCAT_VECTORS4]](<8 x i32>)
+ ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_ADD]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
+ %0:_(p0) = COPY $x0
+ %1:_(p0) = COPY $x1
+ %2:_(<24 x i8>) = G_LOAD %0:_(p0) :: (load (<24 x i8>))
+ %3:_(<24 x i8>) = G_LOAD %1:_(p0) :: (load (<24 x i8>))
+ %4:_(<24 x i32>) = G_ZEXT %2:_(<24 x i8>)
+ %5:_(<24 x i32>) = G_ZEXT %3:_(<24 x i8>)
+ %6:_(<24 x i32>) = nuw nsw G_MUL %5:_, %4:_
+ %7:_(i32) = G_VECREDUCE_ADD %6:_(<24 x i32>)
+ $w0 = COPY %7:_(i32)
+ RET_ReallyLR implicit $w0
+...
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