[llvm] [AMDGPU] Improve codegen for copysign(x, fneg(y)) (PR #207178)

[Madhur Kumar via llvm-commits]

================
@@ -2932,11 +2948,31 @@ def : AMDGPUPat <
   (S_AND_B32 (S_MOV_B32 (i32 0x80000000)), $src1)
 >;
 
+def : AMDGPUPat <
+  (DivergentBinFrag<fcopysign> (f32 fpimm_zero), (fneg f32:$src1)),
+  (V_BFI_B32_e64 VGPR_32:$src1, (i32 0), (S_MOV_B32 (i32 0x80000000)))
+>;
+
 def : AMDGPUPat <
   (fcopysign (f32 fpimm_pos_zero), (f32 VGPR_32:$src1)),
   (V_AND_B32_e32 (S_MOV_B32 (i32 0x80000000)), $src1)
 >;
 
+def : AMDGPUPat <
----------------
MadhurKumar004 wrote:

Yes they both fire.  As i showed with an example above :

```
Optimized legalized selection DAG: %bb.0 'v_copysign_v2f64_0_fneg:'
SelectionDAG has 35 nodes:
  t0: ch,glue = EntryToken
  t26: ch,glue = CopyToReg t0, Register:i32 $vgpr0, Constant:i32<0>
                  t2: i32,ch = CopyFromReg # D:1 t0, Register:i32 %8
                  t4: i32,ch = CopyFromReg # D:1 t0, Register:i32 %9
                t68: v2i32 = BUILD_VECTOR # D:1 t2, t4
              t69: f64 = bitcast # D:1 t68
            t60: f64 = fneg # D:1 t69
          t53: v2f32 = bitcast # D:1 t60
        t54: f32 = extract_vector_elt # D:1 t53, Constant:i32<1>
      t85: i32 = bitcast # D:1 t54
    t86: i32 = and # D:1 t85, Constant:i32<-2147483648>
  t28: ch,glue = CopyToReg # D:1 t26, Register:i32 $vgpr1, t86, t26:1
  t30: ch,glue = CopyToReg t28, Register:i32 $vgpr2, Constant:i32<0>, t28:1
                  t6: i32,ch = CopyFromReg # D:1 t0, Register:i32 %10
                  t8: i32,ch = CopyFromReg # D:1 t0, Register:i32 %11
                t70: v2i32 = BUILD_VECTOR # D:1 t6, t8
              t71: f64 = bitcast # D:1 t70
            t62: f64 = fneg # D:1 t71
          t56: v2f32 = bitcast # D:1 t62
        t57: f32 = extract_vector_elt # D:1 t56, Constant:i32<1>
      t79: i32 = bitcast # D:1 t57
    t81: i32 = and # D:1 t79, Constant:i32<-2147483648>
  t32: ch,glue = CopyToReg # D:1 t30, Register:i32 $vgpr3, t81, t30:1
  t33: ch = AMDGPUISD::RET_GLUE t32, Register:i32 $vgpr0, Register:i32 $vgpr1, Register:i32 $vgpr2, Register:i32 $vgpr3, t32:1
  ```
(extractelt (v2i32 (bitconvert (f64 $src1))), (i32 1))  :  for f64 case 
(i32 (bitconvert (extractelt (v2f32 (bitconvert (f64 $src1))), (i32 1))))  :   for v2f64 test case 

https://github.com/llvm/llvm-project/pull/207178