[llvm] [SCEV] Rework wrap-flag-inference for sext-addrec (PR #217362)
Ramkumar Ramachandra via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 21 10:55:00 PDT 2026
https://github.com/artagnon updated https://github.com/llvm/llvm-project/pull/217362
>From 2da4c8eb787c38e2dfeb5979b03ee86b5cdc85fd Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: Wed, 19 Aug 2026 18:36:12 +0100
Subject: [PATCH 1/2] [SCEV] Rework wrap-flag-inferrence for sext-addrec
Rewrite getSignExtendExprImpl to avoid the roundabout method of creating
sign-extend expressions to check no-wrap, by computing the no-wrap
information using induction and reading it off the expression directly.
The new code has much better compile-time, while not being exactly
equivalent to the old code.
---
llvm/lib/Analysis/ScalarEvolution.cpp | 95 ++-----------------
.../Analysis/ScalarEvolution/incorrect-nsw.ll | 6 +-
2 files changed, 10 insertions(+), 91 deletions(-)
diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp
index 6095f59ec1413..0d50747d4205c 100644
--- a/llvm/lib/Analysis/ScalarEvolution.cpp
+++ b/llvm/lib/Analysis/ScalarEvolution.cpp
@@ -2044,91 +2044,17 @@ const SCEV *ScalarEvolution::getSignExtendExprImpl(SCEVUse Op, Type *Ty,
// operands (often constants). This allows analysis of something like
// this: for (signed char X = 0; X < 100; ++X) { int Y = X; }
if (match(Op, m_scev_AffineAddRec(m_SCEV(Start), m_SCEV(Step), m_Loop(L)))) {
+ // Redo the AddRec check, computing nsw this time.
const auto *AR = cast<SCEVAddRecExpr>(Op);
- unsigned BitWidth = getTypeSizeInBits(AR->getType());
-
- // The no-signed-wrap case is handled before the uniquing lookup above.
-
- // Check whether the backedge-taken count is SCEVCouldNotCompute.
- // Note that this serves two purposes: It filters out loops that are
- // simply not analyzable, and it covers the case where this code is
- // being called from within backedge-taken count analysis, such that
- // attempting to ask for the backedge-taken count would likely result
- // in infinite recursion. In the later case, the analysis code will
- // cope with a conservative value, and it will take care to purge
- // that value once it has finished.
- const SCEV *MaxBECount = getConstantMaxBackedgeTakenCount(L);
- if (!isa<SCEVCouldNotCompute>(MaxBECount)) {
- // Manually compute the final value for AR, checking for
- // overflow.
-
- // Check whether the backedge-taken count can be losslessly casted to
- // the addrec's type. The count is always unsigned.
- const SCEV *CastedMaxBECount =
- getTruncateOrZeroExtend(MaxBECount, Start->getType(), Depth);
- const SCEV *RecastedMaxBECount = getTruncateOrZeroExtend(
- CastedMaxBECount, MaxBECount->getType(), Depth);
- if (MaxBECount == RecastedMaxBECount) {
- Type *WideTy = IntegerType::get(getContext(), BitWidth * 2);
- // Check whether Start+Step*MaxBECount has no signed overflow.
- const SCEV *SMul =
- getMulExpr(CastedMaxBECount, Step, SCEV::FlagAnyWrap, Depth + 1);
- const SCEV *SAdd = getSignExtendExpr(
- getAddExpr(Start, SMul, SCEV::FlagAnyWrap, Depth + 1), WideTy,
- Depth + 1);
- const SCEV *WideStart = getSignExtendExpr(Start, WideTy, Depth + 1);
- const SCEV *WideMaxBECount =
- getZeroExtendExpr(CastedMaxBECount, WideTy, Depth + 1);
- const SCEV *OperandExtendedAdd =
- getAddExpr(WideStart,
- getMulExpr(WideMaxBECount,
- getSignExtendExpr(Step, WideTy, Depth + 1),
- SCEV::FlagAnyWrap, Depth + 1),
- SCEV::FlagAnyWrap, Depth + 1);
- if (SAdd == OperandExtendedAdd) {
- // Cache knowledge of AR NSW, which is propagated to this AddRec.
- setNoWrapFlags(const_cast<SCEVAddRecExpr *>(AR), SCEV::FlagNSW);
- // Return the expression with the addrec on the outside.
- Start =
- getExtendAddRecStart<SCEVSignExtendExpr>(AR, Ty, this, Depth + 1);
- Step = getSignExtendExpr(Step, Ty, Depth + 1);
- return getAddRecExpr(Start, Step, L, AR->getNoWrapFlags());
- }
- // Similar to above, only this time treat the step value as unsigned.
- // This covers loops that count up with an unsigned step.
- OperandExtendedAdd =
- getAddExpr(WideStart,
- getMulExpr(WideMaxBECount,
- getZeroExtendExpr(Step, WideTy, Depth + 1),
- SCEV::FlagAnyWrap, Depth + 1),
- SCEV::FlagAnyWrap, Depth + 1);
- if (SAdd == OperandExtendedAdd) {
- // If AR wraps around then
- //
- // abs(Step) * MaxBECount > unsigned-max(AR->getType())
- // => SAdd != OperandExtendedAdd
- //
- // Thus (AR is not NW => SAdd != OperandExtendedAdd) <=>
- // (SAdd == OperandExtendedAdd => AR is NW)
-
- setNoWrapFlags(const_cast<SCEVAddRecExpr *>(AR), SCEV::FlagNW);
-
- // Return the expression with the addrec on the outside.
- Start =
- getExtendAddRecStart<SCEVSignExtendExpr>(AR, Ty, this, Depth + 1);
- Step = getZeroExtendExpr(Step, Ty, Depth + 1);
- return getAddRecExpr(Start, Step, L, AR->getNoWrapFlags());
- }
- }
- }
-
+ inferNoWrapViaConstantRanges(AR);
auto NewFlags = proveNoSignedWrapViaInduction(AR);
+ if (!hasFlags(NewFlags, SCEV::FlagNSW) &&
+ proveNoWrapByVaryingStart<SCEVSignExtendExpr>(Start, Step, L))
+ NewFlags |= SCEV::FlagNSW;
setNoWrapFlags(const_cast<SCEVAddRecExpr *>(AR), NewFlags);
+
+ // If we have nsw, the sign-extend distributes over the recurrence.
if (AR->hasNoSignedWrap()) {
- // Same as nsw case above - duplicated here to avoid a compile time
- // issue. It's not clear that the order of checks does matter, but
- // it's one of two issue possible causes for a change which was
- // reverted. Be conservative for the moment.
Start = getExtendAddRecStart<SCEVSignExtendExpr>(AR, Ty, this, Depth + 1);
Step = getSignExtendExpr(Step, Ty, Depth + 1);
return getAddRecExpr(Start, Step, L, AR->getNoWrapFlags());
@@ -2149,13 +2075,6 @@ const SCEV *ScalarEvolution::getSignExtendExprImpl(SCEVUse Op, Type *Ty,
Depth + 1);
}
}
-
- if (proveNoWrapByVaryingStart<SCEVSignExtendExpr>(Start, Step, L)) {
- setNoWrapFlags(const_cast<SCEVAddRecExpr *>(AR), SCEV::FlagNSW);
- Start = getExtendAddRecStart<SCEVSignExtendExpr>(AR, Ty, this, Depth + 1);
- Step = getSignExtendExpr(Step, Ty, Depth + 1);
- return getAddRecExpr(Start, Step, L, AR->getNoWrapFlags());
- }
}
// If the input value is provably positive and we could not simplify
diff --git a/llvm/test/Analysis/ScalarEvolution/incorrect-nsw.ll b/llvm/test/Analysis/ScalarEvolution/incorrect-nsw.ll
index f7edf493c64c4..1490c6710bced 100644
--- a/llvm/test/Analysis/ScalarEvolution/incorrect-nsw.ll
+++ b/llvm/test/Analysis/ScalarEvolution/incorrect-nsw.ll
@@ -3,13 +3,13 @@
define void @bad.nsw() {
; CHECK-LABEL: Classifying expressions for: @bad.nsw
; CHECK-LABEL: Classifying expressions for: @bad.nsw
- entry:
+ entry:
br label %loop
loop:
%i = phi i8 [ -1, %entry ], [ %i.inc, %loop ]
; CHECK: %i = phi i8 [ -1, %entry ], [ %i.inc, %loop ]
-; CHECK-NEXT: --> {-1,+,-128}<nw><%loop>
+; CHECK-NEXT: --> {-1,+,-128}<%loop>
; CHECK-NOT: --> {-1,+,-128}<nsw><%loop>
%counter = phi i8 [ 0, %entry ], [ %counter.inc, %loop ]
@@ -22,5 +22,5 @@ define void @bad.nsw() {
br i1 %continue, label %exit, label %loop
exit:
- ret void
+ ret void
}
>From ef2b8d29418c187b9f547a47a7b461ee74607fb6 Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: Fri, 21 Aug 2026 17:28:51 +0100
Subject: [PATCH 2/2] [SCEV] Learning from closed incorrect-nw patch
---
llvm/lib/Analysis/ScalarEvolution.cpp | 9 +-
.../Delinearization/gcd_multiply_expr.ll | 18 +-
llvm/test/Analysis/DependenceAnalysis/AA.ll | 4 +-
.../DependenceAnalysis/banerjee-overflow.ll | 2 +-
...invariant-dep-with-backedge-taken-count.ll | 10 -
.../nssw-predicate-implied.ll | 5 +-
.../LoopAccessAnalysis/symbolic-stride.ll | 20 +-
.../ScalarEvolution/2012-05-29-MulAddRec.ll | 56 +-
.../ScalarEvolution/flags-from-poison.ll | 32 +-
.../ScalarEvolution/infer-prestart-no-wrap.ll | 2 +-
.../Analysis/ScalarEvolution/min-max-exprs.ll | 6 +-
llvm/test/Analysis/ScalarEvolution/pr27315.ll | 31 +-
.../ptrtoint-constantexpr-loop.ll | 12 +-
.../Analysis/ScalarEvolution/range_nw_flag.ll | 4 +-
.../Analysis/ScalarEvolution/sext-iv-2.ll | 40 +-
.../test/Analysis/ScalarEvolution/sext-mul.ll | 8 +-
.../CanonicalizeFreezeInLoops/aarch64.ll | 4 +-
.../IndVarSimplify/AArch64/widen-loop-comp.ll | 26 +-
.../IndVarSimplify/ARM/code-size.ll | 24 +-
.../ARM/indvar-unroll-imm-cost.ll | 4 +-
.../IndVarSimplify/X86/eliminate-trunc.ll | 12 +-
.../IndVarSimplify/X86/overflow-intrinsics.ll | 4 +-
.../IndVarSimplify/add-nsw-zext-fold.ll | 2 +-
.../IndVarSimplify/backedge-on-min-max.ll | 4 +-
.../IndVarSimplify/eliminate-exit.ll | 8 +-
.../eliminate-max-from-min-exit.ll | 2 +-
.../IndVarSimplify/floating-point-iv.ll | 2 +-
.../IndVarSimplify/infer-poison-flags.ll | 8 +-
.../IndVarSimplify/iv-widen-elim-ext.ll | 2 +-
.../Transforms/IndVarSimplify/lftr-pr41998.ll | 4 +-
.../IndVarSimplify/loop-guard-order.ll | 4 +-
.../IndVarSimplify/loop-predication.ll | 20 +-
.../IndVarSimplify/monotonic_checks.ll | 2 +-
.../IndVarSimplify/pointer-loop-guards.ll | 4 +-
.../test/Transforms/IndVarSimplify/pr55925.ll | 4 +-
.../test/Transforms/IndVarSimplify/pr57247.ll | 2 +-
.../test/Transforms/IndVarSimplify/pr79861.ll | 4 +-
.../scev-expander-preserve-lcssa.ll | 14 +-
.../simplify-icmp-operands-order.ll | 2 +-
.../IndVarSimplify/strengthen-overflow.ll | 8 +-
.../IndVarSimplify/turn-to-invariant.ll | 6 +-
.../IndVarSimplify/widen-nonnegative.ll | 21 +-
llvm/test/Transforms/LoopFlatten/widen-iv.ll | 20 +-
.../ARM/illegal-addr-modes.ll | 2 +-
.../X86/2008-08-14-ShadowIV.ll | 268 ++++++---
.../X86/2012-01-13-phielim.ll | 2 +-
.../LoopStrengthReduce/X86/pr17473.ll | 38 +-
.../two-combinations-bug.ll | 36 +-
.../LoopUnroll/AArch64/apple-unrolling.ll | 22 +-
.../AArch64/runtime-unroll-generic.ll | 2 +-
.../Transforms/LoopUnroll/AArch64/vector.ll | 4 +-
.../unroll-convergent-uniform-tripcount.ll | 4 +-
.../LoopUnroll/ARM/loop-unrolling.ll | 557 +++++++++++++++---
.../Transforms/LoopUnroll/ARM/multi-blocks.ll | 10 +-
.../unroll-convergent-uniform-tripcount.ll | 4 +-
...unrolling-legalize-vectors-inseltpoison.ll | 2 +-
.../PowerPC/p8-unrolling-legalize-vectors.ll | 2 +-
.../Transforms/LoopUnroll/RISCV/vector.ll | 2 +-
.../LoopUnroll/WebAssembly/basic-unrolling.ll | 16 +-
.../LoopUnroll/convergent.controlled.ll | 2 +-
.../LoopUnroll/expensive-tripcount.ll | 2 +-
.../peel-last-iteration-with-guards.ll | 4 +-
...last-iteration-with-variable-trip-count.ll | 8 +-
.../peel-loop-min-max-intrinsics.ll | 4 +-
.../peel-loop-noalias-scope-decl.ll | 82 +--
.../runtime-exit-phi-scev-invalidation.ll | 8 +-
.../Transforms/LoopUnroll/runtime-i128.ll | 4 +-
.../runtime-loop-at-most-two-exits.ll | 4 +-
.../LoopUnroll/runtime-loop-multiple-exits.ll | 146 ++---
.../LoopUnroll/runtime-multiexit-heuristic.ll | 80 +--
.../runtime-unroll-assume-no-remainder.ll | 2 +-
.../runtime-unroll-reductions-min-max.ll | 48 +-
.../LoopUnroll/runtime-unroll-reductions.ll | 18 +-
.../LoopUnroll/runtime-unroll-remainder.ll | 2 +-
.../LoopUnroll/scev-invalidation-lcssa.ll | 4 +-
.../LoopUnroll/shifted-tripcount.ll | 4 +-
.../LoopUnroll/tripcount-overflow.ll | 4 +-
.../Transforms/LoopUnroll/unroll-loads-cse.ll | 10 +-
.../dependencies_visit_order.ll | 5 +-
.../LoopUnrollAndJam/unroll-and-jam.ll | 34 +-
.../LoopVectorize/AArch64/bounded-load.ll | 8 +-
.../PowerPC/optimal-epilog-vectorization.ll | 22 +-
.../RISCV/strided-accesses-narrow-iv.ll | 33 +-
.../RISCV/tail-folding-iv-outside-user.ll | 23 +-
.../X86/replicating-load-store-costs.ll | 5 +-
.../alias-mask-data-tail-folding-style.ll | 6 +-
.../Transforms/LoopVectorize/alias-mask.ll | 9 +-
.../Transforms/LoopVectorize/div-exact.ll | 16 +-
.../first-order-recurrence-complex.ll | 20 +-
...irst-order-recurrence-dead-instructions.ll | 29 +-
.../interleaved-accesses-dead-member.ll | 12 +-
.../LoopVectorize/iv_outside_user.ll | 8 +-
.../optimal-epilog-vectorization.ll | 16 +-
.../LoopVectorize/pointer-induction.ll | 20 +-
.../LoopVectorize/reverse_induction.ll | 79 +--
.../LoopVectorize/simplify-logic.ll | 48 +-
.../widen-intrinsic-tail-fold.ll | 44 +-
.../LoopVersioningLICM/loopversioningLICM1.ll | 6 +-
.../constraint-elimination-placement.ll | 3 +-
.../AArch64/extra-unroll-simplifications.ll | 4 +-
.../AArch64/hoist-runtime-checks.ll | 8 +-
...ple-unreachable-exits-for-vectorization.ll | 4 +-
.../PhaseOrdering/X86/spurious-peeling.ll | 4 +-
.../PhaseOrdering/loop-access-checks.ll | 8 +-
.../PhaseOrdering/swap-promotion.ll | 2 +-
105 files changed, 1395 insertions(+), 964 deletions(-)
diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp
index 0d50747d4205c..015f4b2db493b 100644
--- a/llvm/lib/Analysis/ScalarEvolution.cpp
+++ b/llvm/lib/Analysis/ScalarEvolution.cpp
@@ -2044,7 +2044,7 @@ const SCEV *ScalarEvolution::getSignExtendExprImpl(SCEVUse Op, Type *Ty,
// operands (often constants). This allows analysis of something like
// this: for (signed char X = 0; X < 100; ++X) { int Y = X; }
if (match(Op, m_scev_AffineAddRec(m_SCEV(Start), m_SCEV(Step), m_Loop(L)))) {
- // Redo the AddRec check, computing nsw this time.
+ // Redo the AddRec check, computing wrap-flags this time.
const auto *AR = cast<SCEVAddRecExpr>(Op);
inferNoWrapViaConstantRanges(AR);
auto NewFlags = proveNoSignedWrapViaInduction(AR);
@@ -2060,6 +2060,13 @@ const SCEV *ScalarEvolution::getSignExtendExprImpl(SCEVUse Op, Type *Ty,
return getAddRecExpr(Start, Step, L, AR->getNoWrapFlags());
}
+ // We can zero-extend the step if no-self-wrap is present.
+ if (AR->hasNoSelfWrap()) {
+ Start = getExtendAddRecStart<SCEVSignExtendExpr>(AR, Ty, this, Depth + 1);
+ Step = getZeroExtendExpr(Step, Ty, Depth + 1);
+ return getAddRecExpr(Start, Step, L, AR->getNoWrapFlags());
+ }
+
// sext({C,+,Step}) --> (sext(D) + sext({C-D,+,Step}))<nuw><nsw>
// if D + (C - D + Step * n) could be proven to not signed wrap
// where D maximizes the number of trailing zeros of (C - D + Step * n)
diff --git a/llvm/test/Analysis/Delinearization/gcd_multiply_expr.ll b/llvm/test/Analysis/Delinearization/gcd_multiply_expr.ll
index a5af30011f487..4c16c66a4c040 100644
--- a/llvm/test/Analysis/Delinearization/gcd_multiply_expr.ll
+++ b/llvm/test/Analysis/Delinearization/gcd_multiply_expr.ll
@@ -33,7 +33,7 @@ define i32 @fn2() {
; CHECK-NEXT: failed to delinearize
; CHECK-EMPTY:
; CHECK-NEXT: Inst: %9 = load i8, ptr %arrayidx.i, align 1
-; CHECK-NEXT: AccessFunction: (sext i32 {({(%1 * %2),+,1}<nw><%for.cond2thread-pre-split.i> + %.pr.i),+,8}<nw><%for.body4.i> to i64)
+; CHECK-NEXT: AccessFunction: {(sext i32 ({(%1 * %2),+,1}<nw><%for.cond2thread-pre-split.i> + %.pr.i) to i64),+,8}<nsw><%for.body4.i>
; CHECK-NEXT: failed to delinearize
; CHECK-EMPTY:
; CHECK-NEXT: Inst: store i32 %conv.i, ptr @c, align 4
@@ -45,7 +45,7 @@ define i32 @fn2() {
; CHECK-NEXT: failed to delinearize
; CHECK-EMPTY:
; CHECK-NEXT: Inst: %10 = load i8, ptr %arrayidx.1.i, align 1
-; CHECK-NEXT: AccessFunction: (sext i32 {({(1 + (%1 * %2)),+,1}<nw><%for.cond2thread-pre-split.i> + %.pr.i),+,8}<nw><%for.body4.i> to i64)
+; CHECK-NEXT: AccessFunction: {(sext i32 ({(1 + (%1 * %2)),+,1}<nw><%for.cond2thread-pre-split.i> + %.pr.i) to i64),+,8}<nsw><%for.body4.i>
; CHECK-NEXT: failed to delinearize
; CHECK-EMPTY:
; CHECK-NEXT: Inst: store i32 %conv.1.i, ptr @c, align 4
@@ -57,7 +57,7 @@ define i32 @fn2() {
; CHECK-NEXT: failed to delinearize
; CHECK-EMPTY:
; CHECK-NEXT: Inst: %11 = load i8, ptr %arrayidx.2.i, align 1
-; CHECK-NEXT: AccessFunction: (sext i32 {({(2 + (%1 * %2)),+,1}<nw><%for.cond2thread-pre-split.i> + %.pr.i),+,8}<nw><%for.body4.i> to i64)
+; CHECK-NEXT: AccessFunction: {(sext i32 ({(2 + (%1 * %2)),+,1}<nw><%for.cond2thread-pre-split.i> + %.pr.i) to i64),+,8}<nsw><%for.body4.i>
; CHECK-NEXT: failed to delinearize
; CHECK-EMPTY:
; CHECK-NEXT: Inst: store i32 %conv.2.i, ptr @c, align 4
@@ -69,7 +69,7 @@ define i32 @fn2() {
; CHECK-NEXT: failed to delinearize
; CHECK-EMPTY:
; CHECK-NEXT: Inst: %12 = load i8, ptr %arrayidx.3.i, align 1
-; CHECK-NEXT: AccessFunction: (sext i32 {({(3 + (%1 * %2)),+,1}<nw><%for.cond2thread-pre-split.i> + %.pr.i),+,8}<nw><%for.body4.i> to i64)
+; CHECK-NEXT: AccessFunction: {(sext i32 ({(3 + (%1 * %2)),+,1}<nw><%for.cond2thread-pre-split.i> + %.pr.i) to i64),+,8}<nsw><%for.body4.i>
; CHECK-NEXT: failed to delinearize
; CHECK-EMPTY:
; CHECK-NEXT: Inst: store i32 %conv.3.i, ptr @c, align 4
@@ -81,7 +81,7 @@ define i32 @fn2() {
; CHECK-NEXT: failed to delinearize
; CHECK-EMPTY:
; CHECK-NEXT: Inst: %13 = load i8, ptr %arrayidx.4.i, align 1
-; CHECK-NEXT: AccessFunction: (sext i32 {({(4 + (%1 * %2)),+,1}<nw><%for.cond2thread-pre-split.i> + %.pr.i),+,8}<nw><%for.body4.i> to i64)
+; CHECK-NEXT: AccessFunction: {(sext i32 ({(4 + (%1 * %2)),+,1}<nw><%for.cond2thread-pre-split.i> + %.pr.i) to i64),+,8}<nsw><%for.body4.i>
; CHECK-NEXT: failed to delinearize
; CHECK-EMPTY:
; CHECK-NEXT: Inst: store i32 %conv.4.i, ptr @c, align 4
@@ -93,7 +93,7 @@ define i32 @fn2() {
; CHECK-NEXT: failed to delinearize
; CHECK-EMPTY:
; CHECK-NEXT: Inst: %14 = load i8, ptr %arrayidx.5.i, align 1
-; CHECK-NEXT: AccessFunction: (sext i32 {({(5 + (%1 * %2)),+,1}<nw><%for.cond2thread-pre-split.i> + %.pr.i),+,8}<nw><%for.body4.i> to i64)
+; CHECK-NEXT: AccessFunction: {(sext i32 ({(5 + (%1 * %2)),+,1}<nw><%for.cond2thread-pre-split.i> + %.pr.i) to i64),+,8}<nw><%for.body4.i>
; CHECK-NEXT: failed to delinearize
; CHECK-EMPTY:
; CHECK-NEXT: Inst: store i32 %conv.5.i, ptr @c, align 4
@@ -105,7 +105,7 @@ define i32 @fn2() {
; CHECK-NEXT: failed to delinearize
; CHECK-EMPTY:
; CHECK-NEXT: Inst: %15 = load i8, ptr %arrayidx.6.i, align 1
-; CHECK-NEXT: AccessFunction: (sext i32 {({(6 + (%1 * %2)),+,1}<nw><%for.cond2thread-pre-split.i> + %.pr.i),+,8}<nw><%for.body4.i> to i64)
+; CHECK-NEXT: AccessFunction: {(sext i32 ({(6 + (%1 * %2)),+,1}<nw><%for.cond2thread-pre-split.i> + %.pr.i) to i64),+,8}<nw><%for.body4.i>
; CHECK-NEXT: failed to delinearize
; CHECK-EMPTY:
; CHECK-NEXT: Inst: store i32 %conv.6.i, ptr @c, align 4
@@ -117,7 +117,7 @@ define i32 @fn2() {
; CHECK-NEXT: failed to delinearize
; CHECK-EMPTY:
; CHECK-NEXT: Inst: %16 = load i8, ptr %arrayidx.7.i, align 1
-; CHECK-NEXT: AccessFunction: (sext i32 {({(7 + (%1 * %2)),+,1}<nw><%for.cond2thread-pre-split.i> + %.pr.i),+,8}<nw><%for.body4.i> to i64)
+; CHECK-NEXT: AccessFunction: {(sext i32 ({(7 + (%1 * %2)),+,1}<nw><%for.cond2thread-pre-split.i> + %.pr.i) to i64),+,8}<nw><%for.body4.i>
; CHECK-NEXT: failed to delinearize
; CHECK-EMPTY:
; CHECK-NEXT: Inst: store i32 %conv.7.i, ptr @c, align 4
@@ -129,7 +129,7 @@ define i32 @fn2() {
; CHECK-NEXT: failed to delinearize
; CHECK-EMPTY:
; CHECK-NEXT: Inst: %21 = load i8, ptr %arrayidx.ur.i, align 1
-; CHECK-NEXT: AccessFunction: (sext i32 {({(%1 * %2),+,1}<nw><%for.cond2thread-pre-split.i> + %.ph),+,1}<nw><%for.body4.ur.i> to i64)
+; CHECK-NEXT: AccessFunction: {(sext i32 ({(%1 * %2),+,1}<nw><%for.cond2thread-pre-split.i> + %.ph) to i64),+,1}<nsw><%for.body4.ur.i>
; CHECK-NEXT: failed to delinearize
; CHECK-EMPTY:
; CHECK-NEXT: Inst: store i32 %conv.ur.i, ptr @c, align 4
diff --git a/llvm/test/Analysis/DependenceAnalysis/AA.ll b/llvm/test/Analysis/DependenceAnalysis/AA.ll
index 173744a07ef96..6090cdc854467 100644
--- a/llvm/test/Analysis/DependenceAnalysis/AA.ll
+++ b/llvm/test/Analysis/DependenceAnalysis/AA.ll
@@ -128,11 +128,11 @@ define void @test_tbaa_diff(ptr %A, ptr %B) {
define void @tbaa_loop(i32 %I, i32 %J, ptr nocapture %A, ptr nocapture readonly %B) {
; CHECK-LABEL: 'tbaa_loop'
; CHECK-NEXT: Src: %0 = load i16, ptr %arrayidx.us, align 4, !tbaa !0 --> Dst: %0 = load i16, ptr %arrayidx.us, align 4, !tbaa !0
-; CHECK-NEXT: da analyze - input [* *]!
+; CHECK-NEXT: da analyze - input [S 0]!
; CHECK-NEXT: Src: %0 = load i16, ptr %arrayidx.us, align 4, !tbaa !0 --> Dst: store i32 %add.us.lcssa, ptr %arrayidx6.us, align 4, !tbaa !4
; CHECK-NEXT: da analyze - none!
; CHECK-NEXT: Src: store i32 %add.us.lcssa, ptr %arrayidx6.us, align 4, !tbaa !4 --> Dst: store i32 %add.us.lcssa, ptr %arrayidx6.us, align 4, !tbaa !4
-; CHECK-NEXT: da analyze - output [*]!
+; CHECK-NEXT: da analyze - none!
;
entry:
%cmp = icmp ne i32 %J, 0
diff --git a/llvm/test/Analysis/DependenceAnalysis/banerjee-overflow.ll b/llvm/test/Analysis/DependenceAnalysis/banerjee-overflow.ll
index e74bbb3f033c6..fdea58c621a2f 100644
--- a/llvm/test/Analysis/DependenceAnalysis/banerjee-overflow.ll
+++ b/llvm/test/Analysis/DependenceAnalysis/banerjee-overflow.ll
@@ -84,7 +84,7 @@ define void @banerjee_no_nsw(ptr %A) {
; CHECK-NEXT: Src: store i8 0, ptr %gep.0, align 1 --> Dst: store i8 0, ptr %gep.0, align 1
; CHECK-NEXT: da analyze - output [* *]!
; CHECK-NEXT: Src: store i8 0, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.1, align 1
-; CHECK-NEXT: da analyze - output [* *|<]!
+; CHECK-NEXT: da analyze - none!
; CHECK-NEXT: Src: store i8 1, ptr %gep.1, align 1 --> Dst: store i8 1, ptr %gep.1, align 1
; CHECK-NEXT: da analyze - output [* *]!
;
diff --git a/llvm/test/Analysis/LoopAccessAnalysis/loop-invariant-dep-with-backedge-taken-count.ll b/llvm/test/Analysis/LoopAccessAnalysis/loop-invariant-dep-with-backedge-taken-count.ll
index 8328591a3c7f4..b66b4f9044207 100644
--- a/llvm/test/Analysis/LoopAccessAnalysis/loop-invariant-dep-with-backedge-taken-count.ll
+++ b/llvm/test/Analysis/LoopAccessAnalysis/loop-invariant-dep-with-backedge-taken-count.ll
@@ -181,21 +181,11 @@ define void @test_btc_is_unknown_value(ptr %a, i32 %N) {
; CHECK-EMPTY:
; CHECK-NEXT: Run-time memory checks:
; CHECK-NEXT: Grouped accesses:
-; CHECK-NEXT: Group GRP0:
-; CHECK-NEXT: (Low: (400 + %a) High: (404 + %a))
-; CHECK-NEXT: Member: (400 + %a)
-; CHECK-NEXT: Group GRP1:
-; CHECK-NEXT: (Low: %a High: (4 + (4 * (zext i32 (-1 + %N) to i64))<nuw><nsw> + %a))
-; CHECK-NEXT: Member: {%a,+,4}<nw><%loop>
; CHECK-EMPTY:
; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
; CHECK-NEXT: SCEV assumptions:
-; CHECK-NEXT: {0,+,1}<nuw><%loop> Added Flags: <nssw>
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
-; CHECK-NEXT: [PSE] %gep = getelementptr i32, ptr %a, i32 %iv:
-; CHECK-NEXT: ((4 * (sext i32 {0,+,1}<nuw><%loop> to i64))<nsw> + %a)
-; CHECK-NEXT: --> {%a,+,4}<nw><%loop>
;
entry:
%gep.x = getelementptr i32, ptr %a, i32 100
diff --git a/llvm/test/Analysis/LoopAccessAnalysis/nssw-predicate-implied.ll b/llvm/test/Analysis/LoopAccessAnalysis/nssw-predicate-implied.ll
index 2cd487f71f068..5e24040886823 100644
--- a/llvm/test/Analysis/LoopAccessAnalysis/nssw-predicate-implied.ll
+++ b/llvm/test/Analysis/LoopAccessAnalysis/nssw-predicate-implied.ll
@@ -404,7 +404,7 @@ define void @narrower_i8_nssw_implies_wider_i32_nssw(ptr %dst, ptr %src, i32 %N)
; CHECK-NEXT: Grouped accesses:
; CHECK-NEXT: Group GRP0:
; CHECK-NEXT: (Low: %dst High: (4 + (4 * (zext i32 (-1 + %N) to i64))<nuw><nsw> + %dst))
-; CHECK-NEXT: Member: {%dst,+,4}<nw><%loop>
+; CHECK-NEXT: Member: {%dst,+,4}<nuw><%loop>
; CHECK-NEXT: Group GRP1:
; CHECK-NEXT: (Low: %src High: (4 + (8 * (zext i32 (-1 + %N) to i64))<nuw><nsw> + %src))
; CHECK-NEXT: Member: {%src,+,8}<nw><%loop>
@@ -414,9 +414,6 @@ define void @narrower_i8_nssw_implies_wider_i32_nssw(ptr %dst, ptr %src, i32 %N)
; CHECK-NEXT: {0,+,2}<%loop> Added Flags: <nssw>
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
-; CHECK-NEXT: [PSE] %gep.dst = getelementptr inbounds i32, ptr %dst, i64 %ext.iv.1:
-; CHECK-NEXT: ((4 * (sext i32 {0,+,1}<nuw><%loop> to i64))<nsw> + %dst)
-; CHECK-NEXT: --> {%dst,+,4}<nw><%loop>
; CHECK-NEXT: [PSE] %gep.src = getelementptr inbounds i32, ptr %src, i64 %ext.iv.2:
; CHECK-NEXT: ((4 * (sext i8 {0,+,2}<%loop> to i64))<nsw> + %src)
; CHECK-NEXT: --> {%src,+,8}<nw><%loop>
diff --git a/llvm/test/Analysis/LoopAccessAnalysis/symbolic-stride.ll b/llvm/test/Analysis/LoopAccessAnalysis/symbolic-stride.ll
index c6ce3fbdf678f..79b2934908daa 100644
--- a/llvm/test/Analysis/LoopAccessAnalysis/symbolic-stride.ll
+++ b/llvm/test/Analysis/LoopAccessAnalysis/symbolic-stride.ll
@@ -526,12 +526,8 @@ define void @unknown_stride_equalto_zext_tc(i16 zeroext %N, ptr %A, ptr %B, i32
; CHECK-EMPTY:
; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
; CHECK-NEXT: SCEV assumptions:
-; CHECK-NEXT: {%j,+,(zext i16 %N to i32)}<nw><%loop> Added Flags: <nssw>
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
-; CHECK-NEXT: [PSE] %arrayidx = getelementptr inbounds i16, ptr %B, i32 %add:
-; CHECK-NEXT: ((2 * (sext i32 {%j,+,(zext i16 %N to i32)}<nw><%loop> to i64))<nsw> + %B)
-; CHECK-NEXT: --> {((2 * (sext i32 %j to i64))<nsw> + %B),+,(2 * (zext i16 %N to i64))<nuw><nsw>}<nw><%loop>
;
entry:
%N.ext = zext i16 %N to i32
@@ -572,17 +568,13 @@ define void @unknown_stride_equalto_sext_tc(i16 %N, ptr %A, ptr %B, i32 %j) {
; CHECK-NEXT: (Low: %A High: (4 + %A))
; CHECK-NEXT: Member: %A
; CHECK-NEXT: Group GRP1:
-; CHECK-NEXT: (Low: (((2 * (sext i32 %j to i64))<nsw> + %B) umin ((2 * (sext i32 %j to i64))<nsw> + (2 * (zext i32 (-1 + (sext i16 %N to i32))<nsw> to i64) * (sext i16 %N to i64)) + %B)) High: (2 + (((2 * (sext i32 %j to i64))<nsw> + %B) umax ((2 * (sext i32 %j to i64))<nsw> + (2 * (zext i32 (-1 + (sext i16 %N to i32))<nsw> to i64) * (sext i16 %N to i64)) + %B))))
-; CHECK-NEXT: Member: {((2 * (sext i32 %j to i64))<nsw> + %B),+,(2 * (sext i16 %N to i64))<nsw>}<nw><%loop>
+; CHECK-NEXT: (Low: (((2 * (sext i32 %j to i64))<nsw> + %B) umin ((2 * (sext i32 %j to i64))<nsw> + (2 * (zext i32 (sext i16 %N to i32) to i64) * (zext i32 (-1 + (sext i16 %N to i32))<nsw> to i64)) + %B)) High: (2 + (((2 * (sext i32 %j to i64))<nsw> + %B) umax ((2 * (sext i32 %j to i64))<nsw> + (2 * (zext i32 (sext i16 %N to i32) to i64) * (zext i32 (-1 + (sext i16 %N to i32))<nsw> to i64)) + %B))))
+; CHECK-NEXT: Member: {((2 * (sext i32 %j to i64))<nsw> + %B),+,(2 * (zext i32 (sext i16 %N to i32) to i64))<nuw><nsw>}<%loop>
; CHECK-EMPTY:
; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
; CHECK-NEXT: SCEV assumptions:
-; CHECK-NEXT: {%j,+,(sext i16 %N to i32)}<nw><%loop> Added Flags: <nssw>
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
-; CHECK-NEXT: [PSE] %arrayidx = getelementptr inbounds i16, ptr %B, i32 %add:
-; CHECK-NEXT: ((2 * (sext i32 {%j,+,(sext i16 %N to i32)}<nw><%loop> to i64))<nsw> + %B)
-; CHECK-NEXT: --> {((2 * (sext i32 %j to i64))<nsw> + %B),+,(2 * (sext i16 %N to i64))<nsw>}<nw><%loop>
;
entry:
%N.ext = sext i16 %N to i32
@@ -623,17 +615,13 @@ define void @unknown_stride_equalto_trunc_tc(i64 %N, ptr %A, ptr %B, i32 %j) {
; CHECK-NEXT: (Low: %A High: (4 + %A))
; CHECK-NEXT: Member: %A
; CHECK-NEXT: Group GRP1:
-; CHECK-NEXT: (Low: (((2 * (sext i32 %j to i64))<nsw> + %B) umin ((2 * (sext i32 %j to i64))<nsw> + (2 * (zext i32 (-1 + (trunc i64 %N to i32)) to i64) * (sext i32 (trunc i64 %N to i32) to i64)) + %B)) High: (2 + (((2 * (sext i32 %j to i64))<nsw> + %B) umax ((2 * (sext i32 %j to i64))<nsw> + (2 * (zext i32 (-1 + (trunc i64 %N to i32)) to i64) * (sext i32 (trunc i64 %N to i32) to i64)) + %B))))
-; CHECK-NEXT: Member: {((2 * (sext i32 %j to i64))<nsw> + %B),+,(2 * (sext i32 (trunc i64 %N to i32) to i64))<nsw>}<%loop>
+; CHECK-NEXT: (Low: (((2 * (sext i32 %j to i64))<nsw> + %B) umin ((2 * (sext i32 %j to i64))<nsw> + (2 * (zext i32 (trunc i64 %N to i32) to i64) * (zext i32 (-1 + (trunc i64 %N to i32)) to i64)) + %B)) High: (2 + (((2 * (sext i32 %j to i64))<nsw> + %B) umax ((2 * (sext i32 %j to i64))<nsw> + (2 * (zext i32 (trunc i64 %N to i32) to i64) * (zext i32 (-1 + (trunc i64 %N to i32)) to i64)) + %B))))
+; CHECK-NEXT: Member: {((2 * (sext i32 %j to i64))<nsw> + %B),+,(2 * (zext i32 (trunc i64 %N to i32) to i64))<nuw><nsw>}<%loop>
; CHECK-EMPTY:
; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
; CHECK-NEXT: SCEV assumptions:
-; CHECK-NEXT: {%j,+,(trunc i64 %N to i32)}<nw><%loop> Added Flags: <nssw>
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
-; CHECK-NEXT: [PSE] %arrayidx = getelementptr inbounds i16, ptr %B, i32 %add:
-; CHECK-NEXT: ((2 * (sext i32 {%j,+,(trunc i64 %N to i32)}<nw><%loop> to i64))<nsw> + %B)
-; CHECK-NEXT: --> {((2 * (sext i32 %j to i64))<nsw> + %B),+,(2 * (sext i32 (trunc i64 %N to i32) to i64))<nsw>}<%loop>
;
entry:
%N.trunc = trunc i64 %N to i32
diff --git a/llvm/test/Analysis/ScalarEvolution/2012-05-29-MulAddRec.ll b/llvm/test/Analysis/ScalarEvolution/2012-05-29-MulAddRec.ll
index 1d735d9d3dccc..e2079cf63a686 100644
--- a/llvm/test/Analysis/ScalarEvolution/2012-05-29-MulAddRec.ll
+++ b/llvm/test/Analysis/ScalarEvolution/2012-05-29-MulAddRec.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt < %s -S -passes='loop(indvars),loop-unroll' | FileCheck %s
;
; loop-unroll fully unrolls the inner loop, creating an interesting
@@ -12,17 +13,52 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
declare void @use(i8 %x)
-; CHECK: @func
-; CHECK: for.cond:
-; CHECK: %inc1 = phi i8 [ 0, %entry ], [ %0, %for.body ]
-; CHECK: br label %for.body
-
-; CHECK: for.body:
-; CHECK: %inc.9 = add i8 %inc1, 10
-; CHECK: %0 = add i8 %inc1, 10
-; CHECK: br label %for.cond
-
define void @func() noreturn nounwind uwtable ssp {
+; CHECK-LABEL: define void @func(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: br label %[[FOR_COND:.*]]
+; CHECK: [[FOR_COND]]:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i8 [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY:.*]] ], [ 10, %[[ENTRY]] ]
+; CHECK-NEXT: [[MUL3:%.*]] = phi i8 [ undef, %[[ENTRY]] ], [ [[MUL_9:%.*]], %[[FOR_BODY]] ]
+; CHECK-NEXT: [[INC1:%.*]] = phi i8 [ 0, %[[ENTRY]] ], [ [[TMP0:%.*]], %[[FOR_BODY]] ]
+; CHECK-NEXT: call void @use(i8 [[INC1]])
+; CHECK-NEXT: br label %[[FOR_BODY]]
+; CHECK: [[FOR_BODY]]:
+; CHECK-NEXT: [[INC:%.*]] = add nsw i8 [[INC1]], 1
+; CHECK-NEXT: [[MUL:%.*]] = mul i8 [[INC1]], [[MUL3]]
+; CHECK-NEXT: call void @use(i8 [[INC]])
+; CHECK-NEXT: [[INC_1:%.*]] = add nsw i8 [[INC1]], 2
+; CHECK-NEXT: [[MUL_1:%.*]] = mul i8 [[INC]], [[MUL]]
+; CHECK-NEXT: call void @use(i8 [[INC_1]])
+; CHECK-NEXT: [[INC_2:%.*]] = add nsw i8 [[INC1]], 3
+; CHECK-NEXT: [[MUL_2:%.*]] = mul i8 [[INC_1]], [[MUL_1]]
+; CHECK-NEXT: call void @use(i8 [[INC_2]])
+; CHECK-NEXT: [[INC_3:%.*]] = add nsw i8 [[INC1]], 4
+; CHECK-NEXT: [[MUL_3:%.*]] = mul i8 [[INC_2]], [[MUL_2]]
+; CHECK-NEXT: call void @use(i8 [[INC_3]])
+; CHECK-NEXT: [[INC_4:%.*]] = add nsw i8 [[INC1]], 5
+; CHECK-NEXT: [[MUL_4:%.*]] = mul i8 [[INC_3]], [[MUL_3]]
+; CHECK-NEXT: call void @use(i8 [[INC_4]])
+; CHECK-NEXT: [[INC_5:%.*]] = add nsw i8 [[INC1]], 6
+; CHECK-NEXT: [[MUL_5:%.*]] = mul i8 [[INC_4]], [[MUL_4]]
+; CHECK-NEXT: call void @use(i8 [[INC_5]])
+; CHECK-NEXT: [[INC_6:%.*]] = add nsw i8 [[INC1]], 7
+; CHECK-NEXT: [[MUL_6:%.*]] = mul i8 [[INC_5]], [[MUL_5]]
+; CHECK-NEXT: call void @use(i8 [[INC_6]])
+; CHECK-NEXT: [[INC_7:%.*]] = add nsw i8 [[INC1]], 8
+; CHECK-NEXT: [[MUL_7:%.*]] = mul i8 [[INC_6]], [[MUL_6]]
+; CHECK-NEXT: call void @use(i8 [[INC_7]])
+; CHECK-NEXT: [[INC_8:%.*]] = add nsw i8 [[INC1]], 9
+; CHECK-NEXT: [[MUL_8:%.*]] = mul i8 [[INC_7]], [[MUL_7]]
+; CHECK-NEXT: call void @use(i8 [[INC_8]])
+; CHECK-NEXT: [[INC_9:%.*]] = add nsw i8 [[INC1]], 10
+; CHECK-NEXT: [[MUL_9]] = mul i8 [[INC_8]], [[MUL_8]]
+; CHECK-NEXT: call void @use(i8 [[INC_9]])
+; CHECK-NEXT: [[TMP0]] = add i8 [[INC1]], 10
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i8 [[INDVARS_IV]], 10
+; CHECK-NEXT: br label %[[FOR_COND]]
+;
entry:
br label %for.cond
diff --git a/llvm/test/Analysis/ScalarEvolution/flags-from-poison.ll b/llvm/test/Analysis/ScalarEvolution/flags-from-poison.ll
index ce899726d44cd..9acee61f0bfc7 100644
--- a/llvm/test/Analysis/ScalarEvolution/flags-from-poison.ll
+++ b/llvm/test/Analysis/ScalarEvolution/flags-from-poison.ll
@@ -62,7 +62,7 @@ define void @test-add-nuw(ptr %input, i32 %offset, i32 %numIterations) {
; CHECK-NEXT: %index32 = add nuw i32 %i, %offset
; CHECK-NEXT: --> {%offset,+,1}<nuw><%loop> U: full-set S: full-set Exits: (-1 + %offset + %numIterations) LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %ptr = getelementptr inbounds float, ptr %input, i32 %index32
-; CHECK-NEXT: --> ((4 * (sext i32 {%offset,+,1}<nuw><%loop> to i64))<nsw> + %input) U: full-set S: full-set Exits: ((4 * (sext i32 (-1 + %offset + %numIterations) to i64))<nsw> + %input) LoopDispositions: { %loop: Computable }
+; CHECK-NEXT: --> {((4 * (sext i32 %offset to i64))<nsw> + %input),+,4}<nw><%loop> U: full-set S: full-set Exits: ((4 * (zext i32 (-1 + %numIterations) to i64))<nuw><nsw> + (4 * (sext i32 %offset to i64))<nsw> + %input) LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %nexti = add nuw i32 %i, 1
; CHECK-NEXT: --> {1,+,1}<nuw><%loop> U: [1,0) S: [1,0) Exits: %numIterations LoopDispositions: { %loop: Computable }
; CHECK-NEXT: Determining loop execution counts for: @test-add-nuw
@@ -102,7 +102,7 @@ define void @test-add-scope-invariant(ptr %input, i32 %needle) {
; CHECK-NEXT: %of_interest = add nuw nsw i32 %i.next, %offset
; CHECK-NEXT: --> {(1 + %offset)<nuw><nsw>,+,1}<nuw><%loop> U: [1,0) S: [1,0) Exits: %needle LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %gep2 = getelementptr i32, ptr %input, i32 %of_interest
-; CHECK-NEXT: --> ((4 * (sext i32 {(1 + %offset)<nuw><nsw>,+,1}<nuw><%loop> to i64))<nsw> + %input) U: full-set S: full-set Exits: ((4 * (sext i32 %needle to i64))<nsw> + %input) LoopDispositions: { %loop: Computable }
+; CHECK-NEXT: --> {(4 + (4 * (sext i32 %offset to i64))<nsw> + %input),+,4}<nw><%loop> U: full-set S: full-set Exits: (4 + (4 * (zext i32 (-1 + (-1 * %offset) + %needle) to i64))<nuw><nsw> + (4 * (sext i32 %offset to i64))<nsw> + %input) LoopDispositions: { %loop: Computable }
; CHECK-NEXT: Determining loop execution counts for: @test-add-scope-invariant
; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + (-1 * %offset) + %needle)
; CHECK-NEXT: Loop %loop: constant max backedge-taken count is i32 -1
@@ -133,7 +133,7 @@ define void @test-add-scope-bound(ptr %input, i32 %needle) {
; CHECK-NEXT: %i = phi i32 [ %i.next, %loop ], [ 0, %entry ]
; CHECK-NEXT: --> {0,+,1}<nuw><%loop> U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %gep = getelementptr i32, ptr %input, i32 %i
-; CHECK-NEXT: --> ((4 * (sext i32 {0,+,1}<nuw><%loop> to i64))<nsw> + %input) U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
+; CHECK-NEXT: --> {%input,+,4}<%loop> U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %offset = load i32, ptr %gep, align 4
; CHECK-NEXT: --> %offset U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Variant }
; CHECK-NEXT: %i.next = add nuw i32 %i, 1
@@ -141,7 +141,7 @@ define void @test-add-scope-bound(ptr %input, i32 %needle) {
; CHECK-NEXT: %of_interest = add nuw nsw i32 %i.next, %offset
; CHECK-NEXT: --> ({1,+,1}<nuw><%loop> + %offset)<nuw><nsw> U: [1,0) S: [1,0) Exits: <<Unknown>> LoopDispositions: { %loop: Variant }
; CHECK-NEXT: %gep2 = getelementptr i32, ptr %input, i32 %of_interest
-; CHECK-NEXT: --> ((4 * ((sext i32 {1,+,1}<nuw><%loop> to i64) + (sext i32 %offset to i64))<nsw>)<nsw> + %input) U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Variant }
+; CHECK-NEXT: --> ((4 * ((sext i32 %offset to i64) + {1,+,1}<nuw><%loop>)<nsw>) + %input) U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Variant }
; CHECK-NEXT: Determining loop execution counts for: @test-add-scope-bound
; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count.
; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count.
@@ -174,7 +174,7 @@ define void @test-add-scope-bound-unkn-preheader(ptr %input, i32 %needle) {
; CHECK-NEXT: %i.next = add nuw i32 %i, %offset
; CHECK-NEXT: --> {%offset,+,%offset}<nuw><%loop> U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %gep2 = getelementptr i32, ptr %input, i32 %i.next
-; CHECK-NEXT: --> ((4 * (sext i32 {%offset,+,%offset}<nuw><%loop> to i64))<nsw> + %input) U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
+; CHECK-NEXT: --> {((4 * (sext i32 %offset to i64))<nsw> + %input),+,(4 * (zext i32 %offset to i64))<nuw><nsw>}<%loop> U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
; CHECK-NEXT: Determining loop execution counts for: @test-add-scope-bound-unkn-preheader
; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count.
; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count.
@@ -205,7 +205,7 @@ define void @test-add-scope-bound-unkn-preheader-neg1(ptr %input, i32 %needle) {
; CHECK-NEXT: %i.next = add nuw i32 %i, %offset
; CHECK-NEXT: --> {%offset,+,%offset}<nuw><%loop> U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %gep2 = getelementptr i32, ptr %input, i32 %i.next
-; CHECK-NEXT: --> ((4 * (sext i32 {%offset,+,%offset}<nuw><%loop> to i64))<nsw> + %input) U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
+; CHECK-NEXT: --> {((4 * (sext i32 %offset to i64))<nsw> + %input),+,(4 * (zext i32 %offset to i64))<nuw><nsw>}<%loop> U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
; CHECK-NEXT: Determining loop execution counts for: @test-add-scope-bound-unkn-preheader-neg1
; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count.
; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count.
@@ -237,7 +237,7 @@ define void @test-add-scope-bound-unkn-preheader-neg2(ptr %input, i32 %needle) {
; CHECK-NEXT: %i.next = add nuw i32 %i, %offset
; CHECK-NEXT: --> {%offset,+,%offset}<nw><%loop> U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %gep2 = getelementptr i32, ptr %input, i32 %i.next
-; CHECK-NEXT: --> ((4 * (sext i32 {%offset,+,%offset}<nw><%loop> to i64))<nsw> + %input) U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
+; CHECK-NEXT: --> {((4 * (sext i32 %offset to i64))<nsw> + %input),+,(4 * (zext i32 %offset to i64))<nuw><nsw>}<%loop> U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
; CHECK-NEXT: Determining loop execution counts for: @test-add-scope-bound-unkn-preheader-neg2
; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count.
; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count.
@@ -412,7 +412,7 @@ define void @test-add-no-load(ptr %input, i32 %offset, i32 %numIterations) {
; CHECK-NEXT: %index32 = add nsw i32 %i, %offset
; CHECK-NEXT: --> {%offset,+,1}<nw><%loop> U: full-set S: full-set Exits: (-1 + %offset + %numIterations) LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %ptr = getelementptr inbounds float, ptr %input, i32 %index32
-; CHECK-NEXT: --> ((4 * (sext i32 {%offset,+,1}<nw><%loop> to i64))<nsw> + %input) U: full-set S: full-set Exits: ((4 * (sext i32 (-1 + %offset + %numIterations) to i64))<nsw> + %input) LoopDispositions: { %loop: Computable }
+; CHECK-NEXT: --> {((4 * (sext i32 %offset to i64))<nsw> + %input),+,4}<nw><%loop> U: full-set S: full-set Exits: ((4 * (zext i32 (-1 + %numIterations) to i64))<nuw><nsw> + (4 * (sext i32 %offset to i64))<nsw> + %input) LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %nexti = add nuw i32 %i, 1
; CHECK-NEXT: --> {1,+,1}<nuw><%loop> U: [1,0) S: [1,0) Exits: %numIterations LoopDispositions: { %loop: Computable }
; CHECK-NEXT: Determining loop execution counts for: @test-add-no-load
@@ -448,7 +448,7 @@ define void @test-add-not-header(ptr %input, i32 %offset, i32 %numIterations) {
; CHECK-NEXT: %index32 = add nsw i32 %i, %offset
; CHECK-NEXT: --> {%offset,+,1}<nw><%loop> U: full-set S: full-set Exits: (-1 + %offset + %numIterations) LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %ptr = getelementptr inbounds float, ptr %input, i32 %index32
-; CHECK-NEXT: --> ((4 * (sext i32 {%offset,+,1}<nw><%loop> to i64))<nsw> + %input) U: full-set S: full-set Exits: ((4 * (sext i32 (-1 + %offset + %numIterations) to i64))<nsw> + %input) LoopDispositions: { %loop: Computable }
+; CHECK-NEXT: --> {((4 * (sext i32 %offset to i64))<nsw> + %input),+,4}<nw><%loop> U: full-set S: full-set Exits: ((4 * (zext i32 (-1 + %numIterations) to i64))<nuw><nsw> + (4 * (sext i32 %offset to i64))<nsw> + %input) LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %nexti = add nsw i32 %i, 1
; CHECK-NEXT: --> {1,+,1}<nuw><nsw><%loop> U: [1,-2147483648) S: [1,-2147483648) Exits: %numIterations LoopDispositions: { %loop: Computable }
; CHECK-NEXT: Determining loop execution counts for: @test-add-not-header
@@ -522,7 +522,7 @@ define void @test-add-not-header3(ptr %input, i32 %offset, i32 %numIterations,
; CHECK-NEXT: %index32 = add nsw i32 %i, %offset
; CHECK-NEXT: --> {%offset,+,1}<nw><%loop> U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %ptr = getelementptr inbounds float, ptr %input, i32 %index32
-; CHECK-NEXT: --> ((4 * (sext i32 {%offset,+,1}<nw><%loop> to i64))<nsw> + %input) U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
+; CHECK-NEXT: --> {((4 * (sext i32 %offset to i64))<nsw> + %input),+,4}<nw><%loop> U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %nexti = add nsw i32 %i, 1
; CHECK-NEXT: --> {1,+,1}<nuw><%loop> U: [1,0) S: [1,0) Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %cond = load volatile i1, ptr %cond_buf, align 1
@@ -606,7 +606,7 @@ define void @test-add-not-header5(ptr %input, i32 %offset) {
; CHECK-NEXT: %index32 = add nsw i32 %i, %offset
; CHECK-NEXT: --> {%offset,+,1}<nw><%loop> U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %ptr = getelementptr inbounds float, ptr %input, i32 %index32
-; CHECK-NEXT: --> ((4 * (sext i32 {%offset,+,1}<nw><%loop> to i64))<nsw> + %input) U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
+; CHECK-NEXT: --> {((4 * (sext i32 %offset to i64))<nsw> + %input),+,4}<%loop> U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %nexti = add nsw i32 %i, 1
; CHECK-NEXT: --> {1,+,1}<nuw><%loop> U: [1,0) S: [1,0) Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
; CHECK-NEXT: Determining loop execution counts for: @test-add-not-header5
@@ -718,7 +718,7 @@ define void @test-add-not-header8(ptr %input, i32 %offset, i32 %numIterations) {
; CHECK-NEXT: %nexti2 = add nsw i32 %i2, 1
; CHECK-NEXT: --> {(1 + %offset),+,1}<nw><%loop> U: full-set S: full-set Exits: (%offset + %numIterations) LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %ptr = getelementptr inbounds float, ptr %input, i32 %nexti2
-; CHECK-NEXT: --> ((4 * (sext i32 {(1 + %offset),+,1}<nw><%loop> to i64))<nsw> + %input) U: full-set S: full-set Exits: ((4 * (sext i32 (%offset + %numIterations) to i64))<nsw> + %input) LoopDispositions: { %loop: Computable }
+; CHECK-NEXT: --> {((4 * (sext i32 (1 + %offset) to i64))<nsw> + %input),+,4}<nw><%loop> U: full-set S: full-set Exits: ((4 * (zext i32 (-1 + %numIterations) to i64))<nuw><nsw> + (4 * (sext i32 (1 + %offset) to i64))<nsw> + %input) LoopDispositions: { %loop: Computable }
; CHECK-NEXT: Determining loop execution counts for: @test-add-not-header8
; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations)
; CHECK-NEXT: Loop %loop: constant max backedge-taken count is i32 -1
@@ -755,7 +755,7 @@ define void @test-add-call(ptr %input, i32 %offset, i32 %numIterations) {
; CHECK-NEXT: %index32 = add nsw i32 %i, %offset
; CHECK-NEXT: --> {%offset,+,1}<nw><%loop> U: full-set S: full-set Exits: (-1 + %offset + %numIterations) LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %ptr = getelementptr inbounds float, ptr %input, i32 %index32
-; CHECK-NEXT: --> ((4 * (sext i32 {%offset,+,1}<nw><%loop> to i64))<nsw> + %input) U: full-set S: full-set Exits: ((4 * (sext i32 (-1 + %offset + %numIterations) to i64))<nsw> + %input) LoopDispositions: { %loop: Computable }
+; CHECK-NEXT: --> {((4 * (sext i32 %offset to i64))<nsw> + %input),+,4}<nw><%loop> U: full-set S: full-set Exits: ((4 * (zext i32 (-1 + %numIterations) to i64))<nuw><nsw> + (4 * (sext i32 %offset to i64))<nsw> + %input) LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %nexti = add nsw i32 %i, 1
; CHECK-NEXT: --> {1,+,1}<nuw><%loop> U: [1,0) S: [1,0) Exits: %numIterations LoopDispositions: { %loop: Computable }
; CHECK-NEXT: Determining loop execution counts for: @test-add-call
@@ -791,7 +791,7 @@ define void @test-add-call2(ptr %input, i32 %offset, i32 %numIterations) {
; CHECK-NEXT: %index32 = add nsw i32 %i, %offset
; CHECK-NEXT: --> {%offset,+,1}<nw><%loop> U: full-set S: full-set Exits: (-1 + %offset + %numIterations) LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %ptr = getelementptr inbounds float, ptr %input, i32 %index32
-; CHECK-NEXT: --> ((4 * (sext i32 {%offset,+,1}<nw><%loop> to i64))<nsw> + %input) U: full-set S: full-set Exits: ((4 * (sext i32 (-1 + %offset + %numIterations) to i64))<nsw> + %input) LoopDispositions: { %loop: Computable }
+; CHECK-NEXT: --> {((4 * (sext i32 %offset to i64))<nsw> + %input),+,4}<nw><%loop> U: full-set S: full-set Exits: ((4 * (zext i32 (-1 + %numIterations) to i64))<nuw><nsw> + (4 * (sext i32 %offset to i64))<nsw> + %input) LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %nexti = add nsw i32 %i, 1
; CHECK-NEXT: --> {1,+,1}<nuw><%loop> U: [1,0) S: [1,0) Exits: %numIterations LoopDispositions: { %loop: Computable }
; CHECK-NEXT: Determining loop execution counts for: @test-add-call2
@@ -1156,7 +1156,7 @@ define void @test-mul-nuw(ptr %input, i32 %stride, i32 %numIterations) {
; CHECK-NEXT: %index32 = mul nuw i32 %i, %stride
; CHECK-NEXT: --> {0,+,%stride}<nuw><%loop> U: full-set S: full-set Exits: ((-1 + %numIterations) * %stride) LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %ptr = getelementptr inbounds float, ptr %input, i32 %index32
-; CHECK-NEXT: --> ((4 * (sext i32 {0,+,%stride}<nuw><%loop> to i64))<nsw> + %input) U: full-set S: full-set Exits: ((4 * (sext i32 ((-1 + %numIterations) * %stride) to i64))<nsw> + %input) LoopDispositions: { %loop: Computable }
+; CHECK-NEXT: --> {%input,+,(4 * (zext i32 %stride to i64))<nuw><nsw>}<%loop> U: full-set S: full-set Exits: ((4 * (zext i32 (-1 + %numIterations) to i64) * (zext i32 %stride to i64)) + %input) LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %nexti = add nuw i32 %i, 1
; CHECK-NEXT: --> {1,+,1}<nuw><%loop> U: [1,0) S: [1,0) Exits: %numIterations LoopDispositions: { %loop: Computable }
; CHECK-NEXT: Determining loop execution counts for: @test-mul-nuw
@@ -1382,7 +1382,7 @@ define void @test-shl-nuw(ptr %input, i32 %numIterations) {
; CHECK-NEXT: %index32 = shl nuw i32 %i, 9
; CHECK-NEXT: --> {0,+,512}<nuw><%loop> U: [0,-511) S: [-2147483648,2147483137) Exits: (-512 + (512 * %numIterations)) LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %ptr = getelementptr inbounds float, ptr %input, i32 %index32
-; CHECK-NEXT: --> ((4 * (sext i32 {0,+,512}<nuw><%loop> to i64))<nsw> + %input) U: full-set S: full-set Exits: ((4 * (sext i32 (-512 + (512 * %numIterations)) to i64))<nsw> + %input) LoopDispositions: { %loop: Computable }
+; CHECK-NEXT: --> {%input,+,2048}<nuw><%loop> U: full-set S: full-set Exits: ((2048 * (zext i32 (-1 + %numIterations) to i64))<nuw><nsw> + %input) LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %nexti = add nuw i32 %i, 1
; CHECK-NEXT: --> {1,+,1}<nuw><%loop> U: [1,0) S: [1,0) Exits: %numIterations LoopDispositions: { %loop: Computable }
; CHECK-NEXT: Determining loop execution counts for: @test-shl-nuw
diff --git a/llvm/test/Analysis/ScalarEvolution/infer-prestart-no-wrap.ll b/llvm/test/Analysis/ScalarEvolution/infer-prestart-no-wrap.ll
index 677463ee63225..6b04863eb58a5 100644
--- a/llvm/test/Analysis/ScalarEvolution/infer-prestart-no-wrap.ll
+++ b/llvm/test/Analysis/ScalarEvolution/infer-prestart-no-wrap.ll
@@ -56,7 +56,7 @@ define void @infer.zext.0(ptr %c, i32 %start, ptr %buf) {
; CHECK-NEXT: %idx.inc.sext = zext i32 %idx.inc to i64
; CHECK-NEXT: --> {(1 + (zext i32 %start to i64))<nuw><nsw>,+,1}<nuw><%loop> U: [1,4294967298) S: [1,4294967298) Exits: (2 + (zext i32 %start to i64))<nuw><nsw> LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %buf.gep = getelementptr inbounds i32, ptr %buf, i32 %idx.inc
-; CHECK-NEXT: --> ((4 * (sext i32 {(1 + %start)<nuw>,+,1}<nuw><%loop> to i64))<nsw> + %buf) U: full-set S: full-set Exits: ((4 * (sext i32 (2 + %start) to i64))<nsw> + %buf) LoopDispositions: { %loop: Computable }
+; CHECK-NEXT: --> {((4 * (sext i32 (1 + %start)<nuw> to i64))<nsw> + %buf),+,4}<nw><%loop> U: full-set S: full-set Exits: (4 + (4 * (sext i32 (1 + %start)<nuw> to i64))<nsw> + %buf) LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %val = load i32, ptr %buf.gep, align 4
; CHECK-NEXT: --> %val U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Variant }
; CHECK-NEXT: %counter.inc = add i32 %counter, 1
diff --git a/llvm/test/Analysis/ScalarEvolution/min-max-exprs.ll b/llvm/test/Analysis/ScalarEvolution/min-max-exprs.ll
index 6ededf2477711..73a20f03548ba 100644
--- a/llvm/test/Analysis/ScalarEvolution/min-max-exprs.ll
+++ b/llvm/test/Analysis/ScalarEvolution/min-max-exprs.ll
@@ -26,13 +26,13 @@ define void @f(ptr %A, i32 %N) {
; CHECK-NEXT: %tmp3 = add nuw nsw i32 %i.0, 3
; CHECK-NEXT: --> {3,+,1}<nuw><%bb1> U: [3,-2147483645) S: [3,-2147483645) Exits: (3 + (0 smax %N))<nuw> LoopDispositions: { %bb1: Computable }
; CHECK-NEXT: %tmp5 = sext i32 %tmp3 to i64
-; CHECK-NEXT: --> (sext i32 {3,+,1}<nuw><%bb1> to i64) U: [-2147483648,2147483648) S: [-2147483648,2147483648) Exits: (sext i32 (3 + (0 smax %N))<nuw> to i64) LoopDispositions: { %bb1: Computable }
+; CHECK-NEXT: --> {3,+,1}<nuw><%bb1> U: [3,2147483651) S: [3,2147483651) Exits: (3 + (zext i32 (0 smax %N) to i64))<nuw><nsw> LoopDispositions: { %bb1: Computable }
; CHECK-NEXT: %tmp6 = sext i32 %N to i64
; CHECK-NEXT: --> (sext i32 %N to i64) U: [-2147483648,2147483648) S: [-2147483648,2147483648) Exits: (sext i32 %N to i64) LoopDispositions: { %bb1: Invariant }
; CHECK-NEXT: %tmp9 = select i1 %tmp4, i64 %tmp5, i64 %tmp6
-; CHECK-NEXT: --> ((sext i32 {3,+,1}<nuw><%bb1> to i64) smin (sext i32 %N to i64)) U: [-2147483648,2147483648) S: [-2147483648,2147483648) Exits: ((sext i32 (3 + (0 smax %N))<nuw> to i64) smin (sext i32 %N to i64)) LoopDispositions: { %bb1: Computable }
+; CHECK-NEXT: --> ((sext i32 %N to i64) smin {3,+,1}<nuw><nsw><%bb1>) U: [-2147483648,2147483648) S: [-2147483648,2147483648) Exits: ((sext i32 %N to i64) smin (3 + (zext i32 (0 smax %N) to i64))<nuw><nsw>) LoopDispositions: { %bb1: Computable }
; CHECK-NEXT: %tmp11 = getelementptr inbounds i32, ptr %A, i64 %tmp9
-; CHECK-NEXT: --> ((4 * ((sext i32 {3,+,1}<nuw><%bb1> to i64) smin (sext i32 %N to i64)))<nsw> + %A) U: full-set S: full-set Exits: ((4 * ((sext i32 (3 + (0 smax %N))<nuw> to i64) smin (sext i32 %N to i64)))<nsw> + %A) LoopDispositions: { %bb1: Computable }
+; CHECK-NEXT: --> ((4 * ((sext i32 %N to i64) smin {3,+,1}<nuw><nsw><%bb1>))<nsw> + %A) U: full-set S: full-set Exits: ((4 * ((sext i32 %N to i64) smin (3 + (zext i32 (0 smax %N) to i64))<nuw><nsw>))<nsw> + %A) LoopDispositions: { %bb1: Computable }
; CHECK-NEXT: %tmp12 = load i32, ptr %tmp11, align 4
; CHECK-NEXT: --> %tmp12 U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %bb1: Variant }
; CHECK-NEXT: %tmp13 = shl nsw i32 %tmp12, 1
diff --git a/llvm/test/Analysis/ScalarEvolution/pr27315.ll b/llvm/test/Analysis/ScalarEvolution/pr27315.ll
index 1c99075f5f1b4..405d2f62e5268 100644
--- a/llvm/test/Analysis/ScalarEvolution/pr27315.ll
+++ b/llvm/test/Analysis/ScalarEvolution/pr27315.ll
@@ -1,16 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
; RUN: opt -disable-output "-passes=print<scalar-evolution>" < %s 2>&1 | FileCheck %s
declare i1 @use(i64)
define void @f_0() {
-; CHECK-LABEL: Classifying expressions for: @f_0
+; CHECK-LABEL: 'f_0'
+; CHECK-NEXT: Classifying expressions for: @f_0
+; CHECK-NEXT: %iv = phi i32 [ 0, %entry ], [ %iv.inc.nowrap, %be ]
+; CHECK-NEXT: --> {0,+,1}<nuw><nsw><%loop> U: [0,-2147483648) S: [0,-2147483648) Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
+; CHECK-NEXT: %iv.inc.maywrap = add i32 %iv, 1
+; CHECK-NEXT: --> {1,+,1}<nuw><%loop> U: [1,0) S: [1,0) Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
+; CHECK-NEXT: %iv.inc.maywrap.sext = sext i32 %iv.inc.maywrap to i64
+; CHECK-NEXT: --> {1,+,1}<nuw><%loop> U: [1,0) S: [1,0) Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
+; CHECK-NEXT: %cond0 = call i1 @use(i64 %iv.inc.maywrap.sext)
+; CHECK-NEXT: --> %cond0 U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Variant }
+; CHECK-NEXT: %iv.inc.nowrap = add nsw i32 %iv, 1
+; CHECK-NEXT: --> {1,+,1}<nuw><%loop> U: [1,0) S: [1,0) Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
+; CHECK-NEXT: %be.cond = call i1 @use(i64 0)
+; CHECK-NEXT: --> %be.cond U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Variant }
+; CHECK-NEXT: Determining loop execution counts for: @f_0
+; CHECK-NEXT: Loop %loop: <multiple exits> Unpredictable backedge-taken count.
+; CHECK-NEXT: exit count for loop: ***COULDNOTCOMPUTE***
+; CHECK-NEXT: exit count for be: ***COULDNOTCOMPUTE***
+; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count.
+; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count.
+; CHECK-NEXT: symbolic max exit count for loop: ***COULDNOTCOMPUTE***
+; CHECK-NEXT: symbolic max exit count for be: ***COULDNOTCOMPUTE***
+;
-; CHECK: %iv = phi i32 [ 0, %entry ], [ %iv.inc.nowrap, %be ]
-; CHECK-NEXT: --> {0,+,1}<nuw><nsw><%loop>
-; CHECK: %iv.inc.maywrap = add i32 %iv, 1
-; CHECK-NEXT: --> {1,+,1}<nuw><%loop>
-; CHECK: %iv.inc.maywrap.sext = sext i32 %iv.inc.maywrap to i64
-; CHECK-NEXT: --> (sext i32 {1,+,1}<nuw><%loop> to i64)
entry:
br label %loop
diff --git a/llvm/test/Analysis/ScalarEvolution/ptrtoint-constantexpr-loop.ll b/llvm/test/Analysis/ScalarEvolution/ptrtoint-constantexpr-loop.ll
index 99ecb3c9a7cb9..daa0bd3e3cbc5 100644
--- a/llvm/test/Analysis/ScalarEvolution/ptrtoint-constantexpr-loop.ll
+++ b/llvm/test/Analysis/ScalarEvolution/ptrtoint-constantexpr-loop.ll
@@ -325,9 +325,9 @@ define i64 @sext_like_noop(i32 %n) {
; PTR64_IDX64-LABEL: 'sext_like_noop'
; PTR64_IDX64-NEXT: Classifying expressions for: @sext_like_noop
; PTR64_IDX64-NEXT: %ii = sext i32 %i to i64
-; PTR64_IDX64-NEXT: --> (sext i32 {1,+,1}<nuw><%for.body> to i64) U: [-2147483648,2147483648) S: [-2147483648,2147483648) --> (sext i32 (-1 + ptrtoint (ptr @sext_like_noop to i32)) to i64) U: [-2147483648,2147483648) S: [-2147483648,2147483648)
+; PTR64_IDX64-NEXT: --> {1,+,1}<nuw><%for.body> U: [1,4294967297) S: [1,4294967297) --> (1 + (zext i32 (-2 + ptrtoint (ptr @sext_like_noop to i32)) to i64))<nuw><nsw> U: [1,4294967297) S: [1,4294967297)
; PTR64_IDX64-NEXT: %div = sdiv i64 55555, %ii
-; PTR64_IDX64-NEXT: --> %div U: full-set S: full-set
+; PTR64_IDX64-NEXT: --> (55555 /u {1,+,1}<nuw><nsw><%for.body>) U: [0,55556) S: [0,55556) --> (55555 /u (1 + (zext i32 (-2 + ptrtoint (ptr @sext_like_noop to i32)) to i64))<nuw><nsw>) U: [0,55556) S: [0,55556)
; PTR64_IDX64-NEXT: %i = phi i32 [ %inc, %for.body ], [ 1, %entry ]
; PTR64_IDX64-NEXT: --> {1,+,1}<nuw><%for.body> U: [1,0) S: [1,0) Exits: (-1 + ptrtoint (ptr @sext_like_noop to i32)) LoopDispositions: { %for.body: Computable }
; PTR64_IDX64-NEXT: %inc = add nuw i32 %i, 1
@@ -341,9 +341,9 @@ define i64 @sext_like_noop(i32 %n) {
; PTR64_IDX32-LABEL: 'sext_like_noop'
; PTR64_IDX32-NEXT: Classifying expressions for: @sext_like_noop
; PTR64_IDX32-NEXT: %ii = sext i32 %i to i64
-; PTR64_IDX32-NEXT: --> (sext i32 {1,+,1}<nuw><%for.body> to i64) U: [-2147483648,2147483648) S: [-2147483648,2147483648) --> (sext i32 (-1 + ptrtoint (ptr @sext_like_noop to i32)) to i64) U: [-2147483648,2147483648) S: [-2147483648,2147483648)
+; PTR64_IDX32-NEXT: --> {1,+,1}<nuw><%for.body> U: [1,4294967297) S: [1,4294967297) --> (1 + (zext i32 (-2 + ptrtoint (ptr @sext_like_noop to i32)) to i64))<nuw><nsw> U: [1,4294967297) S: [1,4294967297)
; PTR64_IDX32-NEXT: %div = sdiv i64 55555, %ii
-; PTR64_IDX32-NEXT: --> %div U: full-set S: full-set
+; PTR64_IDX32-NEXT: --> (55555 /u {1,+,1}<nuw><nsw><%for.body>) U: [0,55556) S: [0,55556) --> (55555 /u (1 + (zext i32 (-2 + ptrtoint (ptr @sext_like_noop to i32)) to i64))<nuw><nsw>) U: [0,55556) S: [0,55556)
; PTR64_IDX32-NEXT: %i = phi i32 [ %inc, %for.body ], [ 1, %entry ]
; PTR64_IDX32-NEXT: --> {1,+,1}<nuw><%for.body> U: [1,0) S: [1,0) Exits: (-1 + ptrtoint (ptr @sext_like_noop to i32)) LoopDispositions: { %for.body: Computable }
; PTR64_IDX32-NEXT: %inc = add nuw i32 %i, 1
@@ -357,9 +357,9 @@ define i64 @sext_like_noop(i32 %n) {
; PTR16_IDX16-LABEL: 'sext_like_noop'
; PTR16_IDX16-NEXT: Classifying expressions for: @sext_like_noop
; PTR16_IDX16-NEXT: %ii = sext i32 %i to i64
-; PTR16_IDX16-NEXT: --> (sext i32 {1,+,1}<nuw><%for.body> to i64) U: [-2147483648,2147483648) S: [-2147483648,2147483648) --> (-1 + (zext i32 ptrtoint (ptr @sext_like_noop to i32) to i64))<nsw> U: [-1,65535) S: [-1,65535)
+; PTR16_IDX16-NEXT: --> {1,+,1}<nuw><%for.body> U: [1,4294967297) S: [1,4294967297) --> (1 + (zext i32 (-2 + ptrtoint (ptr @sext_like_noop to i32))<nsw> to i64))<nuw><nsw> U: [1,4294967297) S: [1,4294967297)
; PTR16_IDX16-NEXT: %div = sdiv i64 55555, %ii
-; PTR16_IDX16-NEXT: --> %div U: full-set S: full-set
+; PTR16_IDX16-NEXT: --> (55555 /u {1,+,1}<nuw><nsw><%for.body>) U: [0,55556) S: [0,55556) --> (55555 /u (1 + (zext i32 (-2 + ptrtoint (ptr @sext_like_noop to i32))<nsw> to i64))<nuw><nsw>) U: [0,55556) S: [0,55556)
; PTR16_IDX16-NEXT: %i = phi i32 [ %inc, %for.body ], [ 1, %entry ]
; PTR16_IDX16-NEXT: --> {1,+,1}<nuw><%for.body> U: [1,0) S: [1,0) Exits: (-1 + ptrtoint (ptr @sext_like_noop to i32))<nsw> LoopDispositions: { %for.body: Computable }
; PTR16_IDX16-NEXT: %inc = add nuw i32 %i, 1
diff --git a/llvm/test/Analysis/ScalarEvolution/range_nw_flag.ll b/llvm/test/Analysis/ScalarEvolution/range_nw_flag.ll
index 02168e9b81953..846c7457053cd 100644
--- a/llvm/test/Analysis/ScalarEvolution/range_nw_flag.ll
+++ b/llvm/test/Analysis/ScalarEvolution/range_nw_flag.ll
@@ -12,7 +12,7 @@ define void @test-add-nuw(ptr %input, i32 %offset, i32 %numIterations) {
; CHECK-NEXT: %index32 = add nuw i32 %nexti, %offset
; CHECK-NEXT: --> {(1 + %offset)<nuw>,+,1}<nuw><%loop> U: [1,0) S: [1,0) Exits: (%offset + %numIterations) LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %ptr = getelementptr inbounds float, ptr %input, i32 %index32
-; CHECK-NEXT: --> ((4 * (sext i32 {(1 + %offset)<nuw>,+,1}<nuw><%loop> to i64))<nsw> + %input) U: full-set S: full-set Exits: ((4 * (sext i32 (%offset + %numIterations) to i64))<nsw> + %input) LoopDispositions: { %loop: Computable }
+; CHECK-NEXT: --> {((4 * (sext i32 (1 + %offset)<nuw> to i64))<nsw> + %input),+,4}<nw><%loop> U: full-set S: full-set Exits: ((4 * (zext i32 (-1 + %numIterations) to i64))<nuw><nsw> + (4 * (sext i32 (1 + %offset)<nuw> to i64))<nsw> + %input) LoopDispositions: { %loop: Computable }
; CHECK-NEXT: Determining loop execution counts for: @test-add-nuw
; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations)
; CHECK-NEXT: Loop %loop: constant max backedge-taken count is i32 -1
@@ -46,7 +46,7 @@ define void @test-addrec-nuw(ptr %input, i32 %offset, i32 %numIterations) {
; CHECK-NEXT: %index32 = add nuw i32 %nexti, %min.10
; CHECK-NEXT: --> {(1 + (10 smax %offset))<nuw>,+,1}<nuw><%loop> U: [11,0) S: [11,0) Exits: ((10 smax %offset) + %numIterations) LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %ptr = getelementptr inbounds float, ptr %input, i32 %index32
-; CHECK-NEXT: --> ((4 * (sext i32 {(1 + (10 smax %offset))<nuw>,+,1}<nuw><%loop> to i64))<nsw> + %input) U: full-set S: full-set Exits: ((4 * (sext i32 ((10 smax %offset) + %numIterations) to i64))<nsw> + %input) LoopDispositions: { %loop: Computable }
+; CHECK-NEXT: --> {((4 * (sext i32 (1 + (10 smax %offset))<nuw> to i64))<nsw> + %input),+,4}<nw><%loop> U: full-set S: full-set Exits: ((4 * (zext i32 (-1 + %numIterations) to i64))<nuw><nsw> + (4 * (sext i32 (1 + (10 smax %offset))<nuw> to i64))<nsw> + %input) LoopDispositions: { %loop: Computable }
; CHECK-NEXT: Determining loop execution counts for: @test-addrec-nuw
; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations)
; CHECK-NEXT: Loop %loop: constant max backedge-taken count is i32 -1
diff --git a/llvm/test/Analysis/ScalarEvolution/sext-iv-2.ll b/llvm/test/Analysis/ScalarEvolution/sext-iv-2.ll
index 572b3f7271b88..275d35e968a42 100644
--- a/llvm/test/Analysis/ScalarEvolution/sext-iv-2.ll
+++ b/llvm/test/Analysis/ScalarEvolution/sext-iv-2.ll
@@ -1,10 +1,6 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
; RUN: opt < %s -disable-output "-passes=print<scalar-evolution>" 2>&1 | FileCheck %s
-; CHECK: %tmp3 = sext i8 %tmp2 to i32
-; CHECK: --> (sext i8 {0,+,1}<nuw><%bb1> to i32) U: [-128,128) S: [-128,128) Exits: -1
-; CHECK: %tmp4 = mul i32 %tmp3, %i.02
-; CHECK: --> ((sext i8 {0,+,1}<nuw><%bb1> to i32) * {0,+,1}<nuw><nsw><%bb>) U: [-3968,3938) S: [-3968,3938) Exits: {0,+,-1}<nsw><%bb>
-
; These sexts are not foldable.
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64"
@@ -12,6 +8,40 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64"
@table = common global [32 x [256 x i32]] zeroinitializer, align 32 ; <ptr> [#uses=2]
define i32 @main() nounwind {
+; CHECK-LABEL: 'main'
+; CHECK-NEXT: Classifying expressions for: @main
+; CHECK-NEXT: %i.02 = phi i32 [ %tmp10, %bb4 ], [ 0, %bb.nph3 ]
+; CHECK-NEXT: --> {0,+,1}<nuw><nsw><%bb> U: [0,32) S: [0,32) Exits: 31 LoopDispositions: { %bb: Computable, %bb1: Invariant }
+; CHECK-NEXT: %j.01 = phi i32 [ %tmp8, %bb2 ], [ 0, %bb.nph ]
+; CHECK-NEXT: --> {0,+,1}<nuw><nsw><%bb1> U: [0,256) S: [0,256) Exits: 255 LoopDispositions: { %bb1: Computable, %bb: Uniform }
+; CHECK-NEXT: %tmp2 = trunc i32 %j.01 to i8
+; CHECK-NEXT: --> {0,+,1}<%bb1> U: full-set S: full-set Exits: -1 LoopDispositions: { %bb1: Computable, %bb: Uniform }
+; CHECK-NEXT: %tmp3 = sext i8 %tmp2 to i32
+; CHECK-NEXT: --> {0,+,1}<nuw><nsw><%bb1> U: [0,256) S: [0,256) Exits: 255 LoopDispositions: { %bb1: Computable, %bb: Uniform }
+; CHECK-NEXT: %tmp4 = mul i32 %tmp3, %i.02
+; CHECK-NEXT: --> {0,+,{0,+,1}<nuw><nsw><%bb>}<%bb1> U: [0,7906) S: [0,7906) Exits: {0,+,255}<nuw><nsw><%bb> LoopDispositions: { %bb1: Computable, %bb: Variant }
+; CHECK-NEXT: %tmp5 = sext i32 %i.02 to i64
+; CHECK-NEXT: --> {0,+,1}<nuw><nsw><%bb> U: [0,32) S: [0,32) Exits: {0,+,1}<nuw><nsw><%bb> LoopDispositions: { %bb1: Invariant, %bb: Computable }
+; CHECK-NEXT: %tmp6 = sext i32 %j.01 to i64
+; CHECK-NEXT: --> {0,+,1}<nuw><nsw><%bb1> U: [0,256) S: [0,256) Exits: 255 LoopDispositions: { %bb1: Computable, %bb: Uniform }
+; CHECK-NEXT: %tmp7 = getelementptr [32 x [256 x i32]], ptr @table, i64 0, i64 %tmp5, i64 %tmp6
+; CHECK-NEXT: --> {{\{\{}}@table,+,1024}<nw><%bb>,+,4}<nw><%bb1> U: [32,-35) S: [-9223372036854775808,9223372036854775805) Exits: {(1020 + @table)<nuw>,+,1024}<nuw><%bb> LoopDispositions: { %bb1: Computable, %bb: Variant }
+; CHECK-NEXT: %tmp8 = add i32 %j.01, 1
+; CHECK-NEXT: --> {1,+,1}<nuw><nsw><%bb1> U: [1,257) S: [1,257) Exits: 256 LoopDispositions: { %bb1: Computable, %bb: Uniform }
+; CHECK-NEXT: %tmp10 = add i32 %i.02, 1
+; CHECK-NEXT: --> {1,+,1}<nuw><nsw><%bb> U: [1,33) S: [1,33) Exits: 32 LoopDispositions: { %bb: Computable, %bb1: Invariant }
+; CHECK-NEXT: %tmp12 = load i32, ptr getelementptr ([32 x [256 x i32]], ptr @table, i64 0, i64 9, i64 132), align 16
+; CHECK-NEXT: --> %tmp12 U: full-set S: full-set
+; CHECK-NEXT: Determining loop execution counts for: @main
+; CHECK-NEXT: Loop %bb1: backedge-taken count is i32 255
+; CHECK-NEXT: Loop %bb1: constant max backedge-taken count is i32 255
+; CHECK-NEXT: Loop %bb1: symbolic max backedge-taken count is i32 255
+; CHECK-NEXT: Loop %bb1: Trip multiple is 256
+; CHECK-NEXT: Loop %bb: backedge-taken count is i32 31
+; CHECK-NEXT: Loop %bb: constant max backedge-taken count is i32 31
+; CHECK-NEXT: Loop %bb: symbolic max backedge-taken count is i32 31
+; CHECK-NEXT: Loop %bb: Trip multiple is 32
+;
entry:
br i1 false, label %bb5, label %bb.nph3
diff --git a/llvm/test/Analysis/ScalarEvolution/sext-mul.ll b/llvm/test/Analysis/ScalarEvolution/sext-mul.ll
index 5d6a1dec72e13..41bab08a9ae82 100644
--- a/llvm/test/Analysis/ScalarEvolution/sext-mul.ll
+++ b/llvm/test/Analysis/ScalarEvolution/sext-mul.ll
@@ -11,17 +11,17 @@ define void @foo(ptr nocapture %arg, i32 %arg1, i32 %arg2) {
; CHECK-NEXT: %tmp9 = shl i64 %tmp8, 33
; CHECK-NEXT: --> {0,+,8589934592}<nuw><%bb7> U: [0,-17179869183) S: [-9223372036854775808,9223372028264841217) Exits: (-8589934592 + (8589934592 * (zext i32 %arg2 to i64))) LoopDispositions: { %bb7: Computable }
; CHECK-NEXT: %tmp10 = ashr exact i64 %tmp9, 32
-; CHECK-NEXT: --> (sext i32 {0,+,2}<nuw><%bb7> to i64) U: [0,-1) S: [-2147483648,2147483647) Exits: (sext i32 (-2 + (2 * %arg2)) to i64) LoopDispositions: { %bb7: Computable }
+; CHECK-NEXT: --> {0,+,2}<nuw><nsw><%bb7> U: [0,4294967293) S: [0,4294967293) Exits: (-2 + (2 * (zext i32 %arg2 to i64))<nuw><nsw>)<nsw> LoopDispositions: { %bb7: Computable }
; CHECK-NEXT: %tmp11 = getelementptr inbounds i32, ptr %arg, i64 %tmp10
-; CHECK-NEXT: --> ((4 * (sext i32 {0,+,2}<nuw><%bb7> to i64))<nsw> + %arg) U: full-set S: full-set Exits: ((4 * (sext i32 (-2 + (2 * %arg2)) to i64))<nsw> + %arg) LoopDispositions: { %bb7: Computable }
+; CHECK-NEXT: --> {%arg,+,8}<nuw><%bb7> U: full-set S: full-set Exits: (-8 + (8 * (zext i32 %arg2 to i64))<nuw><nsw> + %arg) LoopDispositions: { %bb7: Computable }
; CHECK-NEXT: %tmp12 = load i32, ptr %tmp11, align 4
; CHECK-NEXT: --> %tmp12 U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %bb7: Variant }
; CHECK-NEXT: %tmp13 = sub nsw i32 %tmp12, %arg1
; CHECK-NEXT: --> ((-1 * %arg1) + %tmp12) U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %bb7: Variant }
; CHECK-NEXT: %tmp14 = or disjoint i64 %tmp10, 1
-; CHECK-NEXT: --> (1 + (sext i32 {0,+,2}<nuw><%bb7> to i64))<nuw><nsw> U: [1,0) S: [-2147483647,2147483648) Exits: (1 + (sext i32 (-2 + (2 * %arg2)) to i64))<nuw><nsw> LoopDispositions: { %bb7: Computable }
+; CHECK-NEXT: --> {1,+,2}<nuw><nsw><%bb7> U: [1,4294967294) S: [1,4294967294) Exits: (-1 + (2 * (zext i32 %arg2 to i64))<nuw><nsw>)<nsw> LoopDispositions: { %bb7: Computable }
; CHECK-NEXT: %tmp15 = getelementptr inbounds i32, ptr %arg, i64 %tmp14
-; CHECK-NEXT: --> (4 + (4 * (sext i32 {0,+,2}<nuw><%bb7> to i64))<nsw> + %arg) U: full-set S: full-set Exits: (4 + (4 * (sext i32 (-2 + (2 * %arg2)) to i64))<nsw> + %arg) LoopDispositions: { %bb7: Computable }
+; CHECK-NEXT: --> {(4 + %arg),+,8}<nuw><%bb7> U: full-set S: full-set Exits: (-4 + (8 * (zext i32 %arg2 to i64))<nuw><nsw> + %arg) LoopDispositions: { %bb7: Computable }
; CHECK-NEXT: %tmp16 = load i32, ptr %tmp15, align 4
; CHECK-NEXT: --> %tmp16 U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %bb7: Variant }
; CHECK-NEXT: %tmp17 = mul nsw i32 %tmp16, %arg1
diff --git a/llvm/test/Transforms/CanonicalizeFreezeInLoops/aarch64.ll b/llvm/test/Transforms/CanonicalizeFreezeInLoops/aarch64.ll
index 165aec4fce207..a7d490e93fb59 100644
--- a/llvm/test/Transforms/CanonicalizeFreezeInLoops/aarch64.ll
+++ b/llvm/test/Transforms/CanonicalizeFreezeInLoops/aarch64.ll
@@ -35,11 +35,11 @@ define void @f_without_freeze(ptr %p, i32 %n, i32 %m) {
; CHECK-LABEL: f_without_freeze:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: add w8, w2, #1
+; CHECK-NEXT: add x8, x0, w8, sxtw
; CHECK-NEXT: .LBB1_1: // %loop
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: subs w1, w1, #1
-; CHECK-NEXT: strb wzr, [x0, w8, sxtw]
-; CHECK-NEXT: add w8, w8, #1
+; CHECK-NEXT: strb wzr, [x8], #1
; CHECK-NEXT: b.ne .LBB1_1
; CHECK-NEXT: // %bb.2: // %exit
; CHECK-NEXT: ret
diff --git a/llvm/test/Transforms/IndVarSimplify/AArch64/widen-loop-comp.ll b/llvm/test/Transforms/IndVarSimplify/AArch64/widen-loop-comp.ll
index d4498baf0577a..495a173f3ccb1 100644
--- a/llvm/test/Transforms/IndVarSimplify/AArch64/widen-loop-comp.ll
+++ b/llvm/test/Transforms/IndVarSimplify/AArch64/widen-loop-comp.ll
@@ -1062,10 +1062,12 @@ side_exit:
define i32 @test16_signed_pos1(i32 %start, ptr %p, ptr %q, i32 %x) {
; CHECK-LABEL: @test16_signed_pos1(
; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[START:%.*]] to i64
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
-; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT_1:%.*]], [[BACKEDGE:%.*]] ]
-; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV]], 0
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[TMP0]], [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[INDVARS_IV]], 0
+; CHECK-NEXT: [[IV:%.*]] = trunc nsw i64 [[INDVARS_IV]] to i32
; CHECK-NEXT: [[FOO:%.*]] = add i32 [[IV]], -1
; CHECK-NEXT: br i1 [[COND]], label [[EXIT:%.*]], label [[GUARDED:%.*]]
; CHECK: guarded:
@@ -1078,7 +1080,7 @@ define i32 @test16_signed_pos1(i32 %start, ptr %p, ptr %q, i32 %x) {
; CHECK-NEXT: [[LOAD_ADDR:%.*]] = getelementptr i32, ptr [[Q:%.*]], i64 [[INDEX]]
; CHECK-NEXT: [[STOP:%.*]] = load i32, ptr [[Q]], align 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp eq i32 [[STOP]], 0
-; CHECK-NEXT: [[IV_NEXT_1]] = add i32 [[IV]], -1
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 4294967295
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[FAILURE:%.*]]
; CHECK: exit:
; CHECK-NEXT: call void @use(i32 -1)
@@ -1129,10 +1131,12 @@ side_exit:
define i32 @test16_signed_pos2(i32 %start, ptr %p, ptr %q, i32 %x) {
; CHECK-LABEL: @test16_signed_pos2(
; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[START:%.*]] to i64
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
-; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT_1:%.*]], [[BACKEDGE:%.*]] ]
-; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV]], 0
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[TMP0]], [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[INDVARS_IV]], 0
+; CHECK-NEXT: [[IV:%.*]] = trunc nsw i64 [[INDVARS_IV]] to i32
; CHECK-NEXT: [[FOO:%.*]] = add i32 [[IV]], -1
; CHECK-NEXT: br i1 [[COND]], label [[EXIT:%.*]], label [[GUARDED:%.*]]
; CHECK: guarded:
@@ -1145,7 +1149,7 @@ define i32 @test16_signed_pos2(i32 %start, ptr %p, ptr %q, i32 %x) {
; CHECK-NEXT: [[LOAD_ADDR:%.*]] = getelementptr i32, ptr [[Q:%.*]], i64 [[INDEX]]
; CHECK-NEXT: [[STOP:%.*]] = load i32, ptr [[Q]], align 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp eq i32 [[STOP]], 0
-; CHECK-NEXT: [[IV_NEXT_1]] = add i32 [[IV]], -1
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 4294967295
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[FAILURE:%.*]]
; CHECK: exit:
; CHECK-NEXT: call void @use(i32 -1)
@@ -1196,12 +1200,14 @@ side_exit:
define i32 @test16_signed_neg(i32 %start, ptr %p, ptr %q, i32 %x) {
; CHECK-LABEL: @test16_signed_neg(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[START:%.*]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[START:%.*]] to i64
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[START]], -1
; CHECK-NEXT: [[ICMP_USER_FIRST_ITER:%.*]] = icmp ult i32 [[TMP0]], [[X:%.*]]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
-; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START]], [[ENTRY:%.*]] ], [ [[IV_NEXT_1:%.*]], [[BACKEDGE:%.*]] ]
-; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV]], 0
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[TMP1]], [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[INDVARS_IV]], 0
+; CHECK-NEXT: [[IV:%.*]] = trunc nsw i64 [[INDVARS_IV]] to i32
; CHECK-NEXT: [[FOO:%.*]] = add i32 [[IV]], -1
; CHECK-NEXT: br i1 [[COND]], label [[EXIT:%.*]], label [[GUARDED:%.*]]
; CHECK: guarded:
@@ -1213,7 +1219,7 @@ define i32 @test16_signed_neg(i32 %start, ptr %p, ptr %q, i32 %x) {
; CHECK-NEXT: [[LOAD_ADDR:%.*]] = getelementptr i32, ptr [[Q:%.*]], i64 [[INDEX]]
; CHECK-NEXT: [[STOP:%.*]] = load i32, ptr [[Q]], align 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp eq i32 [[STOP]], 0
-; CHECK-NEXT: [[IV_NEXT_1]] = add i32 [[IV]], -1
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 4294967295
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[FAILURE:%.*]]
; CHECK: exit:
; CHECK-NEXT: call void @use(i32 -1)
diff --git a/llvm/test/Transforms/IndVarSimplify/ARM/code-size.ll b/llvm/test/Transforms/IndVarSimplify/ARM/code-size.ll
index 61ca1d4f016f6..60345210ac562 100644
--- a/llvm/test/Transforms/IndVarSimplify/ARM/code-size.ll
+++ b/llvm/test/Transforms/IndVarSimplify/ARM/code-size.ll
@@ -148,7 +148,7 @@ define i32 @test1(ptr %array, i32 %length, i32 %n) #0 {
; CHECK-V8M-NEXT: [[ARRAY_I_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAY:%.*]], i64 [[I_I64]]
; CHECK-V8M-NEXT: [[ARRAY_I:%.*]] = load i32, ptr [[ARRAY_I_PTR]], align 4
; CHECK-V8M-NEXT: [[LOOP_ACC_NEXT]] = add i32 [[LOOP_ACC]], [[ARRAY_I]]
-; CHECK-V8M-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-V8M-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-V8M-NEXT: [[CONTINUE:%.*]] = icmp ult i32 [[I_NEXT]], [[N]]
; CHECK-V8M-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK-V8M: exit:
@@ -174,7 +174,7 @@ define i32 @test1(ptr %array, i32 %length, i32 %n) #0 {
; CHECK-V8A-NEXT: [[ARRAY_I_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAY:%.*]], i64 [[I_I64]]
; CHECK-V8A-NEXT: [[ARRAY_I:%.*]] = load i32, ptr [[ARRAY_I_PTR]], align 4
; CHECK-V8A-NEXT: [[LOOP_ACC_NEXT]] = add i32 [[LOOP_ACC]], [[ARRAY_I]]
-; CHECK-V8A-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-V8A-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-V8A-NEXT: [[CONTINUE:%.*]] = icmp ult i32 [[I_NEXT]], [[N]]
; CHECK-V8A-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK-V8A: exit:
@@ -230,7 +230,7 @@ define i32 @test2(ptr %array, i32 %length, i32 %n) #0 {
; CHECK-V8M-NEXT: [[ARRAY_I_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAY:%.*]], i64 [[I_I64]]
; CHECK-V8M-NEXT: [[ARRAY_I:%.*]] = load i32, ptr [[ARRAY_I_PTR]], align 4
; CHECK-V8M-NEXT: [[LOOP_ACC_NEXT]] = add i32 [[LOOP_ACC]], [[ARRAY_I]]
-; CHECK-V8M-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-V8M-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-V8M-NEXT: [[CONTINUE:%.*]] = icmp ne i32 [[I_NEXT]], [[N]]
; CHECK-V8M-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK-V8M: exit:
@@ -256,7 +256,7 @@ define i32 @test2(ptr %array, i32 %length, i32 %n) #0 {
; CHECK-V8A-NEXT: [[ARRAY_I_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAY:%.*]], i64 [[I_I64]]
; CHECK-V8A-NEXT: [[ARRAY_I:%.*]] = load i32, ptr [[ARRAY_I_PTR]], align 4
; CHECK-V8A-NEXT: [[LOOP_ACC_NEXT]] = add i32 [[LOOP_ACC]], [[ARRAY_I]]
-; CHECK-V8A-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-V8A-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-V8A-NEXT: [[CONTINUE:%.*]] = icmp ne i32 [[I_NEXT]], [[N]]
; CHECK-V8A-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK-V8A: exit:
@@ -314,7 +314,7 @@ define i32 @two_range_checks(ptr %array.1, i32 %length.1, ptr %array.2, i32 %len
; CHECK-V8M-NEXT: [[ARRAY_2_I_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAY_2:%.*]], i64 [[I_I64]]
; CHECK-V8M-NEXT: [[ARRAY_2_I:%.*]] = load i32, ptr [[ARRAY_2_I_PTR]], align 4
; CHECK-V8M-NEXT: [[LOOP_ACC_NEXT]] = add i32 [[LOOP_ACC_1]], [[ARRAY_2_I]]
-; CHECK-V8M-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-V8M-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-V8M-NEXT: [[CONTINUE:%.*]] = icmp ult i32 [[I_NEXT]], [[N]]
; CHECK-V8M-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK-V8M: exit:
@@ -344,7 +344,7 @@ define i32 @two_range_checks(ptr %array.1, i32 %length.1, ptr %array.2, i32 %len
; CHECK-V8A-NEXT: [[ARRAY_2_I_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAY_2:%.*]], i64 [[I_I64]]
; CHECK-V8A-NEXT: [[ARRAY_2_I:%.*]] = load i32, ptr [[ARRAY_2_I_PTR]], align 4
; CHECK-V8A-NEXT: [[LOOP_ACC_NEXT]] = add i32 [[LOOP_ACC_1]], [[ARRAY_2_I]]
-; CHECK-V8A-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-V8A-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-V8A-NEXT: [[CONTINUE:%.*]] = icmp ult i32 [[I_NEXT]], [[N]]
; CHECK-V8A-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK-V8A: exit:
@@ -411,7 +411,7 @@ define i32 @three_range_checks(ptr %array.1, i32 %length.1, ptr %array.2, i32 %l
; CHECK-V8M-NEXT: [[ARRAY_3_I_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAY_3:%.*]], i64 [[I_I64]]
; CHECK-V8M-NEXT: [[ARRAY_3_I:%.*]] = load i32, ptr [[ARRAY_3_I_PTR]], align 4
; CHECK-V8M-NEXT: [[LOOP_ACC_NEXT]] = add i32 [[LOOP_ACC_2]], [[ARRAY_3_I]]
-; CHECK-V8M-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-V8M-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-V8M-NEXT: [[CONTINUE:%.*]] = icmp ult i32 [[I_NEXT]], [[N]]
; CHECK-V8M-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK-V8M: exit:
@@ -445,7 +445,7 @@ define i32 @three_range_checks(ptr %array.1, i32 %length.1, ptr %array.2, i32 %l
; CHECK-V8A-NEXT: [[ARRAY_3_I_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAY_3:%.*]], i64 [[I_I64]]
; CHECK-V8A-NEXT: [[ARRAY_3_I:%.*]] = load i32, ptr [[ARRAY_3_I_PTR]], align 4
; CHECK-V8A-NEXT: [[LOOP_ACC_NEXT]] = add i32 [[LOOP_ACC_2]], [[ARRAY_3_I]]
-; CHECK-V8A-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-V8A-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-V8A-NEXT: [[CONTINUE:%.*]] = icmp ult i32 [[I_NEXT]], [[N]]
; CHECK-V8A-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK-V8A: exit:
@@ -521,7 +521,7 @@ define i32 @distinct_checks(ptr %array.1, i32 %length.1, ptr %array.2, i32 %leng
; CHECK-V8M-NEXT: [[ARRAY_3_I_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAY_3:%.*]], i64 [[I_I64]]
; CHECK-V8M-NEXT: [[ARRAY_3_I:%.*]] = load i32, ptr [[ARRAY_3_I_PTR]], align 4
; CHECK-V8M-NEXT: [[LOOP_ACC_NEXT]] = add i32 [[LOOP_ACC_1]], [[ARRAY_3_I]]
-; CHECK-V8M-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-V8M-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-V8M-NEXT: [[CONTINUE:%.*]] = icmp ult i32 [[I_NEXT]], [[N]]
; CHECK-V8M-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK-V8M: exit:
@@ -558,7 +558,7 @@ define i32 @distinct_checks(ptr %array.1, i32 %length.1, ptr %array.2, i32 %leng
; CHECK-V8A-NEXT: [[ARRAY_3_I_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAY_3:%.*]], i64 [[I_I64]]
; CHECK-V8A-NEXT: [[ARRAY_3_I:%.*]] = load i32, ptr [[ARRAY_3_I_PTR]], align 4
; CHECK-V8A-NEXT: [[LOOP_ACC_NEXT]] = add i32 [[LOOP_ACC_1]], [[ARRAY_3_I]]
-; CHECK-V8A-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-V8A-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-V8A-NEXT: [[CONTINUE:%.*]] = icmp ult i32 [[I_NEXT]], [[N]]
; CHECK-V8A-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK-V8A: exit:
@@ -631,7 +631,7 @@ define i32 @duplicate_checks(ptr %array.1, ptr %array.2, ptr %array.3, i32 %leng
; CHECK-V8M-NEXT: [[ARRAY_3_I_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAY_3:%.*]], i64 [[I_I64]]
; CHECK-V8M-NEXT: [[ARRAY_3_I:%.*]] = load i32, ptr [[ARRAY_3_I_PTR]], align 4
; CHECK-V8M-NEXT: [[LOOP_ACC_NEXT]] = add i32 [[LOOP_ACC_1]], [[ARRAY_3_I]]
-; CHECK-V8M-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-V8M-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-V8M-NEXT: [[CONTINUE:%.*]] = icmp ult i32 [[I_NEXT]], [[N]]
; CHECK-V8M-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK-V8M: exit:
@@ -665,7 +665,7 @@ define i32 @duplicate_checks(ptr %array.1, ptr %array.2, ptr %array.3, i32 %leng
; CHECK-V8A-NEXT: [[ARRAY_3_I_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAY_3:%.*]], i64 [[I_I64]]
; CHECK-V8A-NEXT: [[ARRAY_3_I:%.*]] = load i32, ptr [[ARRAY_3_I_PTR]], align 4
; CHECK-V8A-NEXT: [[LOOP_ACC_NEXT]] = add i32 [[LOOP_ACC_1]], [[ARRAY_3_I]]
-; CHECK-V8A-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-V8A-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-V8A-NEXT: [[CONTINUE:%.*]] = icmp ult i32 [[I_NEXT]], [[N]]
; CHECK-V8A-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK-V8A: exit:
diff --git a/llvm/test/Transforms/IndVarSimplify/ARM/indvar-unroll-imm-cost.ll b/llvm/test/Transforms/IndVarSimplify/ARM/indvar-unroll-imm-cost.ll
index 1cec2dd83988b..870ecc4bc96a7 100644
--- a/llvm/test/Transforms/IndVarSimplify/ARM/indvar-unroll-imm-cost.ll
+++ b/llvm/test/Transforms/IndVarSimplify/ARM/indvar-unroll-imm-cost.ll
@@ -96,7 +96,7 @@ define dso_local arm_aapcscc void @test(ptr nocapture %pDest, ptr nocapture read
; CHECK-NEXT: [[INCDEC_PTR36]] = getelementptr inbounds i16, ptr [[PSRCA_ADDR_282]], i32 1
; CHECK-NEXT: [[INCDEC_PTR37]] = getelementptr inbounds i16, ptr [[PSRCB_ADDR_281]], i32 1
; CHECK-NEXT: [[INCDEC_PTR38]] = getelementptr inbounds i32, ptr [[PDEST_ADDR_283]], i32 1
-; CHECK-NEXT: [[INC]] = add nuw i32 [[J_184]], 1
+; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[J_184]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[ADD25]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END40_LOOPEXIT:%.*]], label [[FOR_BODY29]]
; CHECK: for.end40.loopexit:
@@ -109,7 +109,7 @@ define dso_local arm_aapcscc void @test(ptr nocapture %pDest, ptr nocapture read
; CHECK-NEXT: [[PSRCB_ADDR_2_LCSSA]] = phi ptr [ [[PSRCB_ADDR_1_LCSSA]], [[FOR_END]] ], [ [[SCEVGEP93]], [[FOR_END40_LOOPEXIT]] ]
; CHECK-NEXT: [[PSRCA_ADDR_2_LCSSA]] = phi ptr [ [[PSRCA_ADDR_1_LCSSA]], [[FOR_END]] ], [ [[SCEVGEP]], [[FOR_END40_LOOPEXIT]] ]
; CHECK-NEXT: [[PDEST_ADDR_2_LCSSA]] = phi ptr [ [[PDEST_ADDR_1_LCSSA]], [[FOR_END]] ], [ [[SCEVGEP94]], [[FOR_END40_LOOPEXIT]] ]
-; CHECK-NEXT: [[INC42]] = add nuw i32 [[I_092]], 1
+; CHECK-NEXT: [[INC42]] = add nuw nsw i32 [[I_092]], 1
; CHECK-NEXT: [[EXITCOND95:%.*]] = icmp eq i32 [[INC42]], [[BLKCNT]]
; CHECK-NEXT: br i1 [[EXITCOND95]], label [[FOR_COND_CLEANUP_LOOPEXIT:%.*]], label [[FOR_BODY]]
;
diff --git a/llvm/test/Transforms/IndVarSimplify/X86/eliminate-trunc.ll b/llvm/test/Transforms/IndVarSimplify/X86/eliminate-trunc.ll
index a506739ad6cc8..1153c583d75f5 100644
--- a/llvm/test/Transforms/IndVarSimplify/X86/eliminate-trunc.ll
+++ b/llvm/test/Transforms/IndVarSimplify/X86/eliminate-trunc.ll
@@ -223,12 +223,12 @@ define void @test_01_unsigned(i32 %n) {
; CHECK-LABEL: @test_01_unsigned(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N:%.*]], 1
+; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = sext i32 [[TMP0]] to i64
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
-; CHECK-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i64 [[IV_NEXT]] to i32
-; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[LFTR_WIDEIV]], [[TMP0]]
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[IV_NEXT]], [[WIDE_TRIP_COUNT]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: ret void
@@ -300,12 +300,12 @@ define void @test_04_unsigned(i32 %n) {
; CHECK-LABEL: @test_04_unsigned(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N:%.*]], 1
+; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = sext i32 [[TMP0]] to i64
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
-; CHECK-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i64 [[IV_NEXT]] to i32
-; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[LFTR_WIDEIV]], [[TMP0]]
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[IV_NEXT]], [[WIDE_TRIP_COUNT]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: ret void
@@ -328,12 +328,12 @@ define void @test_05_unsigned(i32 %n) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[UMAX:%.*]] = call i32 @llvm.umax.i32(i32 [[N:%.*]], i32 1)
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[UMAX]], 1
+; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = sext i32 [[TMP0]] to i64
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 1, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
-; CHECK-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i64 [[IV_NEXT]] to i32
-; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[LFTR_WIDEIV]], [[TMP0]]
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[IV_NEXT]], [[WIDE_TRIP_COUNT]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/IndVarSimplify/X86/overflow-intrinsics.ll b/llvm/test/Transforms/IndVarSimplify/X86/overflow-intrinsics.ll
index 9b9bc68ba7ad8..f3fe59a31fbbf 100644
--- a/llvm/test/Transforms/IndVarSimplify/X86/overflow-intrinsics.ll
+++ b/llvm/test/Transforms/IndVarSimplify/X86/overflow-intrinsics.ll
@@ -60,12 +60,12 @@ define void @f_sadd_overflow(ptr %a) {
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], %[[CONT:.*]] ], [ 2147483645, %[[ENTRY]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[INDVARS_IV]]
; CHECK-NEXT: store i8 0, ptr [[ARRAYIDX]], align 1
-; CHECK-NEXT: br i1 true, label %[[TRAP:.*]], label %[[CONT]], !nosanitize [[META0]]
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
+; CHECK-NEXT: br i1 false, label %[[TRAP:.*]], label %[[CONT]], !nosanitize [[META0]]
; CHECK: [[TRAP]]:
; CHECK-NEXT: tail call void @llvm.trap(), !nosanitize [[META0]]
; CHECK-NEXT: unreachable, !nosanitize [[META0]]
; CHECK: [[CONT]]:
-; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: br i1 true, label %[[FOR_BODY]], label %[[FOR_COND_CLEANUP]]
;
entry:
diff --git a/llvm/test/Transforms/IndVarSimplify/add-nsw-zext-fold.ll b/llvm/test/Transforms/IndVarSimplify/add-nsw-zext-fold.ll
index 1de41e47a8569..5d989edf0d741 100644
--- a/llvm/test/Transforms/IndVarSimplify/add-nsw-zext-fold.ll
+++ b/llvm/test/Transforms/IndVarSimplify/add-nsw-zext-fold.ll
@@ -21,7 +21,7 @@ define void @add_nsw_zext_fold_results_in_sext(i64 %len) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[TMP1]], %[[LOOP_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[IV:%.*]] = trunc nuw i64 [[INDVARS_IV]] to i32
-; CHECK-NEXT: [[IV_NEXT:%.*]] = add i32 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT:%.*]] = add nsw i32 [[IV]], 1
; CHECK-NEXT: [[SH_PROM:%.*]] = zext nneg i32 [[IV_NEXT]] to i64
; CHECK-NEXT: [[SHR:%.*]] = lshr i64 1, [[SH_PROM]]
; CHECK-NEXT: [[TMP0:%.*]] = trunc nuw nsw i64 [[SHR]] to i32
diff --git a/llvm/test/Transforms/IndVarSimplify/backedge-on-min-max.ll b/llvm/test/Transforms/IndVarSimplify/backedge-on-min-max.ll
index 577edc3650d90..6917ae1a86db8 100644
--- a/llvm/test/Transforms/IndVarSimplify/backedge-on-min-max.ll
+++ b/llvm/test/Transforms/IndVarSimplify/backedge-on-min-max.ll
@@ -426,7 +426,7 @@ define void @min.unsigned.1(ptr %a, i32 %a_len, i32 %n) {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IDX:%.*]] = phi i32 [ [[IDX_INC:%.*]], [[LATCH:%.*]] ], [ 5, [[LOOP_PREHEADER]] ]
-; CHECK-NEXT: [[IDX_INC]] = add nuw i32 [[IDX]], 1
+; CHECK-NEXT: [[IDX_INC]] = add nuw nsw i32 [[IDX]], 1
; CHECK-NEXT: br i1 true, label [[OK:%.*]], label [[LATCH]]
; CHECK: ok:
; CHECK-NEXT: [[ADDR:%.*]] = getelementptr i32, ptr [[A]], i32 [[IDX]]
@@ -477,7 +477,7 @@ define void @min.unsigned.2(ptr %a, i32 %a_len, i32 %n) {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IDX:%.*]] = phi i32 [ [[IDX_INC:%.*]], [[LATCH:%.*]] ], [ 5, [[LOOP_PREHEADER]] ]
-; CHECK-NEXT: [[IDX_INC]] = add nuw i32 [[IDX]], 1
+; CHECK-NEXT: [[IDX_INC]] = add nuw nsw i32 [[IDX]], 1
; CHECK-NEXT: br i1 true, label [[OK:%.*]], label [[LATCH]]
; CHECK: ok:
; CHECK-NEXT: [[ADDR:%.*]] = getelementptr i32, ptr [[A]], i32 [[IDX]]
diff --git a/llvm/test/Transforms/IndVarSimplify/eliminate-exit.ll b/llvm/test/Transforms/IndVarSimplify/eliminate-exit.ll
index b20891d2f9ed8..7d9a4836bb3a1 100644
--- a/llvm/test/Transforms/IndVarSimplify/eliminate-exit.ll
+++ b/llvm/test/Transforms/IndVarSimplify/eliminate-exit.ll
@@ -10,7 +10,7 @@ define void @ult(i64 %n, i64 %m) {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
-; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1
; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i64 [[IV]], [[N]]
; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH]], label [[EXIT_LOOPEXIT:%.*]]
; CHECK: latch:
@@ -46,7 +46,7 @@ define void @ugt(i64 %n, i64 %m) {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
-; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1
; CHECK-NEXT: br i1 true, label [[LATCH]], label [[EXIT_LOOPEXIT:%.*]]
; CHECK: latch:
; CHECK-NEXT: call void @side_effect()
@@ -82,7 +82,7 @@ define void @ule(i64 %n, i64 %m) {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
-; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1
; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i64 [[IV]], [[N]]
; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH]], label [[EXIT_LOOPEXIT:%.*]]
; CHECK: latch:
@@ -119,7 +119,7 @@ define void @uge(i64 %n, i64 %m) {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
-; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1
; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i64 [[IV]], [[N]]
; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH]], label [[EXIT_LOOPEXIT:%.*]]
; CHECK: latch:
diff --git a/llvm/test/Transforms/IndVarSimplify/eliminate-max-from-min-exit.ll b/llvm/test/Transforms/IndVarSimplify/eliminate-max-from-min-exit.ll
index 0c24716d6aaaf..009047ab9059b 100644
--- a/llvm/test/Transforms/IndVarSimplify/eliminate-max-from-min-exit.ll
+++ b/llvm/test/Transforms/IndVarSimplify/eliminate-max-from-min-exit.ll
@@ -71,7 +71,7 @@ define i8 @umax_exit_from_umin(i32 %start, i32 %limit) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[K:%.*]] = phi i32 [ [[INC:%.*]], %[[LOOP]] ], [ [[START]], %[[PH2]] ]
; CHECK-NEXT: call void @use()
-; CHECK-NEXT: [[INC]] = add i32 [[K]], 1
+; CHECK-NEXT: [[INC]] = add nsw i32 [[K]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[K]], [[UMIN]]
; CHECK-NEXT: br i1 [[COND]], label %[[LOOP]], label %[[LOOP_EXIT:.*]]
; CHECK: [[LOOP_EXIT]]:
diff --git a/llvm/test/Transforms/IndVarSimplify/floating-point-iv.ll b/llvm/test/Transforms/IndVarSimplify/floating-point-iv.ll
index d45785b7818cf..17ee92354ecdd 100644
--- a/llvm/test/Transforms/IndVarSimplify/floating-point-iv.ll
+++ b/llvm/test/Transforms/IndVarSimplify/floating-point-iv.ll
@@ -340,7 +340,7 @@ define void @fcmp_neg1() nounwind {
; CHECK: backedge:
; CHECK-NEXT: [[IV_FP:%.*]] = sitofp i64 [[IV]] to double
; CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @foo(double [[IV_FP]]) #[[ATTR0]]
-; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[CMP2:%.*]] = fcmp olt double [[IV_FP]], 1.000000e+04
; CHECK-NEXT: br i1 [[CMP2]], label [[BB]], label [[RETURN]]
; CHECK: return:
diff --git a/llvm/test/Transforms/IndVarSimplify/infer-poison-flags.ll b/llvm/test/Transforms/IndVarSimplify/infer-poison-flags.ll
index 6b28b933687e4..ccd5c673e58ac 100644
--- a/llvm/test/Transforms/IndVarSimplify/infer-poison-flags.ll
+++ b/llvm/test/Transforms/IndVarSimplify/infer-poison-flags.ll
@@ -36,7 +36,7 @@ define void @add_cr_nuw() {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP]] ]
-; CHECK-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-NEXT: store i32 [[I]], ptr @A, align 4
; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[I_NEXT]], -1
; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[LOOPEXIT:%.*]]
@@ -90,7 +90,7 @@ define void @add_cr_none() {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[I:%.*]] = phi i32 [ 10, [[ENTRY:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP]] ]
-; CHECK-NEXT: [[I_NEXT]] = add i32 [[I]], 1
+; CHECK-NEXT: [[I_NEXT]] = add nsw i32 [[I]], 1
; CHECK-NEXT: store i32 [[I]], ptr @A, align 4
; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[I_NEXT]], 0
; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[LOOPEXIT:%.*]]
@@ -117,7 +117,7 @@ define void @add_unknown_none(i32 %n) {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP]] ]
-; CHECK-NEXT: [[I_NEXT]] = add i32 [[I]], 1
+; CHECK-NEXT: [[I_NEXT]] = add nsw i32 [[I]], 1
; CHECK-NEXT: store i32 [[I]], ptr @A, align 4
; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[I_NEXT]], [[N:%.*]]
; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[LOOPEXIT:%.*]]
@@ -172,7 +172,7 @@ define void @sub_unknown_none(i32 %n) {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP]] ]
-; CHECK-NEXT: [[I_NEXT]] = sub i32 [[I]], -1
+; CHECK-NEXT: [[I_NEXT]] = sub nsw i32 [[I]], -1
; CHECK-NEXT: store i32 [[I]], ptr @A, align 4
; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[I_NEXT]], [[N:%.*]]
; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[LOOPEXIT:%.*]]
diff --git a/llvm/test/Transforms/IndVarSimplify/iv-widen-elim-ext.ll b/llvm/test/Transforms/IndVarSimplify/iv-widen-elim-ext.ll
index a83e9ce74b12a..b656a1cc38f1f 100644
--- a/llvm/test/Transforms/IndVarSimplify/iv-widen-elim-ext.ll
+++ b/llvm/test/Transforms/IndVarSimplify/iv-widen-elim-ext.ll
@@ -441,7 +441,7 @@ define i32 @foo6(ptr %input, i32 %length, ptr %in) {
; CHECK-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP5]], [[INDVARS_IV_NEXT]]
; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, ptr [[IN:%.*]], i64 [[TMP6]]
; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ADD_PTR]], align 4
-; CHECK-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP1]], [[INDVARS_IV_NEXT]]
+; CHECK-NEXT: [[TMP8:%.*]] = mul nuw nsw i64 [[TMP1]], [[INDVARS_IV_NEXT]]
; CHECK-NEXT: [[ADD_PTR1:%.*]] = getelementptr inbounds i32, ptr [[IN]], i64 [[TMP8]]
; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[ADD_PTR1]], align 4
; CHECK-NEXT: [[OR:%.*]] = or i32 [[LENGTH]], [[TMP9]]
diff --git a/llvm/test/Transforms/IndVarSimplify/lftr-pr41998.ll b/llvm/test/Transforms/IndVarSimplify/lftr-pr41998.ll
index b7f4756b2757f..0a7b9a6e661f4 100644
--- a/llvm/test/Transforms/IndVarSimplify/lftr-pr41998.ll
+++ b/llvm/test/Transforms/IndVarSimplify/lftr-pr41998.ll
@@ -8,13 +8,13 @@ define void @test_int(i32 %start, ptr %p) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[START:%.*]] to i3
; CHECK-NEXT: [[TMP1:%.*]] = sub i3 0, [[TMP0]]
+; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = sext i3 [[TMP1]] to i32
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[I2:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[I2_INC:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[I2_INC]] = add nuw nsw i32 [[I2]], 1
; CHECK-NEXT: store volatile i32 [[I2_INC]], ptr [[P:%.*]], align 4
-; CHECK-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i32 [[I2_INC]] to i3
-; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i3 [[LFTR_WIDEIV]], [[TMP1]]
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[I2_INC]], [[WIDE_TRIP_COUNT]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[END:%.*]], label [[LOOP]]
; CHECK: end:
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/IndVarSimplify/loop-guard-order.ll b/llvm/test/Transforms/IndVarSimplify/loop-guard-order.ll
index 2763860e79875..81d15a96beedc 100644
--- a/llvm/test/Transforms/IndVarSimplify/loop-guard-order.ll
+++ b/llvm/test/Transforms/IndVarSimplify/loop-guard-order.ll
@@ -114,7 +114,7 @@ define i32 @urem_order1(i32 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[LOOP_PREHEADER]] ]
; CHECK-NEXT: call void @foo()
-; CHECK-NEXT: [[IV_NEXT]] = add nuw i32 [[IV]], 3
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 3
; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT_LOOPEXIT:.*]], label %[[LOOP]]
; CHECK: [[EXIT_LOOPEXIT]]:
@@ -159,7 +159,7 @@ define i32 @urem_order2(i32 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[LOOP_PREHEADER]] ]
; CHECK-NEXT: call void @foo()
-; CHECK-NEXT: [[IV_NEXT]] = add nuw i32 [[IV]], 3
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 3
; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT_LOOPEXIT:.*]], label %[[LOOP]]
; CHECK: [[EXIT_LOOPEXIT]]:
diff --git a/llvm/test/Transforms/IndVarSimplify/loop-predication.ll b/llvm/test/Transforms/IndVarSimplify/loop-predication.ll
index b02b9d71c37c4..793e8f80d443d 100644
--- a/llvm/test/Transforms/IndVarSimplify/loop-predication.ll
+++ b/llvm/test/Transforms/IndVarSimplify/loop-predication.ll
@@ -24,7 +24,7 @@ define i32 @test1(ptr %array, i32 %length, i32 %n) {
; CHECK-NEXT: [[ARRAY_I_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAY:%.*]], i64 [[I_I64]]
; CHECK-NEXT: [[ARRAY_I:%.*]] = load i32, ptr [[ARRAY_I_PTR]], align 4
; CHECK-NEXT: [[LOOP_ACC_NEXT]] = add i32 [[LOOP_ACC]], [[ARRAY_I]]
-; CHECK-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-NEXT: [[CONTINUE:%.*]] = icmp ult i32 [[I_NEXT]], [[N]]
; CHECK-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
@@ -77,7 +77,7 @@ define i32 @neg_store(ptr %array, i32 %length, i32 %n) {
; CHECK-NEXT: [[ARRAY_I:%.*]] = load i32, ptr [[ARRAY_I_PTR]], align 4
; CHECK-NEXT: [[LOOP_ACC_NEXT]] = add i32 [[LOOP_ACC]], [[ARRAY_I]]
; CHECK-NEXT: store i32 0, ptr [[ARRAY_I_PTR]], align 4
-; CHECK-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-NEXT: [[CONTINUE:%.*]] = icmp ult i32 [[I_NEXT]], [[N:%.*]]
; CHECK-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
@@ -133,7 +133,7 @@ define i32 @neg_implicit_exit(ptr %array, i32 %length, i32 %n) {
; CHECK-NEXT: [[ARRAY_I_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAY:%.*]], i64 [[I_I64]]
; CHECK-NEXT: [[ARRAY_I:%.*]] = load i32, ptr [[ARRAY_I_PTR]], align 4
; CHECK-NEXT: [[LOOP_ACC_NEXT]] = add i32 [[LOOP_ACC]], [[ARRAY_I]]
-; CHECK-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-NEXT: [[CONTINUE:%.*]] = icmp ult i32 [[I_NEXT]], [[N:%.*]]
; CHECK-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
@@ -191,7 +191,7 @@ define i32 @test2(ptr %array, i32 %length, i32 %n) {
; CHECK-NEXT: [[ARRAY_I_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAY:%.*]], i64 [[I_I64]]
; CHECK-NEXT: [[ARRAY_I:%.*]] = load i32, ptr [[ARRAY_I_PTR]], align 4
; CHECK-NEXT: [[LOOP_ACC_NEXT]] = add i32 [[LOOP_ACC]], [[ARRAY_I]]
-; CHECK-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-NEXT: [[CONTINUE:%.*]] = icmp ne i32 [[I_NEXT]], [[N]]
; CHECK-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
@@ -250,7 +250,7 @@ define i32 @two_range_checks(ptr %array.1, i32 %length.1, ptr %array.2, i32 %len
; CHECK-NEXT: [[ARRAY_2_I_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAY_2:%.*]], i64 [[I_I64]]
; CHECK-NEXT: [[ARRAY_2_I:%.*]] = load i32, ptr [[ARRAY_2_I_PTR]], align 4
; CHECK-NEXT: [[LOOP_ACC_NEXT]] = add i32 [[LOOP_ACC_1]], [[ARRAY_2_I]]
-; CHECK-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-NEXT: [[CONTINUE:%.*]] = icmp ult i32 [[I_NEXT]], [[N]]
; CHECK-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
@@ -317,7 +317,7 @@ define i32 @three_range_checks(ptr %array.1, i32 %length.1, ptr %array.2, i32 %l
; CHECK-NEXT: [[ARRAY_3_I_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAY_3:%.*]], i64 [[I_I64]]
; CHECK-NEXT: [[ARRAY_3_I:%.*]] = load i32, ptr [[ARRAY_3_I_PTR]], align 4
; CHECK-NEXT: [[LOOP_ACC_NEXT]] = add i32 [[LOOP_ACC_2]], [[ARRAY_3_I]]
-; CHECK-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-NEXT: [[CONTINUE:%.*]] = icmp ult i32 [[I_NEXT]], [[N]]
; CHECK-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
@@ -393,7 +393,7 @@ define i32 @distinct_checks(ptr %array.1, i32 %length.1, ptr %array.2, i32 %leng
; CHECK-NEXT: [[ARRAY_3_I_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAY_3:%.*]], i64 [[I_I64]]
; CHECK-NEXT: [[ARRAY_3_I:%.*]] = load i32, ptr [[ARRAY_3_I_PTR]], align 4
; CHECK-NEXT: [[LOOP_ACC_NEXT]] = add i32 [[LOOP_ACC_1]], [[ARRAY_3_I]]
-; CHECK-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-NEXT: [[CONTINUE:%.*]] = icmp ult i32 [[I_NEXT]], [[N]]
; CHECK-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
@@ -466,7 +466,7 @@ define i32 @duplicate_checks(ptr %array.1, ptr %array.2, ptr %array.3, i32 %leng
; CHECK-NEXT: [[ARRAY_3_I_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAY_3:%.*]], i64 [[I_I64]]
; CHECK-NEXT: [[ARRAY_3_I:%.*]] = load i32, ptr [[ARRAY_3_I_PTR]], align 4
; CHECK-NEXT: [[LOOP_ACC_NEXT]] = add i32 [[LOOP_ACC_1]], [[ARRAY_3_I]]
-; CHECK-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-NEXT: [[CONTINUE:%.*]] = icmp ult i32 [[I_NEXT]], [[N]]
; CHECK-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
@@ -606,7 +606,7 @@ define i32 @unconditional_latch_with_side_effect(ptr %a, i32 %length) {
; CHECK-NEXT: ret i32 -1
; CHECK: guarded:
; CHECK-NEXT: store volatile i32 0, ptr [[A:%.*]], align 4
-; CHECK-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-NEXT: br label [[LOOP]]
;
loop.preheader:
@@ -786,7 +786,7 @@ define i32 @neg_dominating_exit(ptr %array, i32 %length, i32 %length2, i32 %n) {
; CHECK-NEXT: [[ARRAY_I_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAY:%.*]], i64 [[I_I64]]
; CHECK-NEXT: [[ARRAY_I:%.*]] = load i32, ptr [[ARRAY_I_PTR]], align 4
; CHECK-NEXT: [[LOOP_ACC_NEXT]] = add i32 [[LOOP_ACC]], [[ARRAY_I]]
-; CHECK-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-NEXT: [[CONTINUE:%.*]] = icmp ult i32 [[I_NEXT]], [[N:%.*]]
; CHECK-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
diff --git a/llvm/test/Transforms/IndVarSimplify/monotonic_checks.ll b/llvm/test/Transforms/IndVarSimplify/monotonic_checks.ll
index 1f8bf5fecb248..d11bae35aad4f 100644
--- a/llvm/test/Transforms/IndVarSimplify/monotonic_checks.ll
+++ b/llvm/test/Transforms/IndVarSimplify/monotonic_checks.ll
@@ -90,7 +90,7 @@ define i32 @test_02(ptr %p) {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
-; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nsw i32 [[IV]], 1
; CHECK-NEXT: br i1 true, label [[BACKEDGE]], label [[FAIL:%.*]]
; CHECK: backedge:
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ne i32 [[IV]], 0
diff --git a/llvm/test/Transforms/IndVarSimplify/pointer-loop-guards.ll b/llvm/test/Transforms/IndVarSimplify/pointer-loop-guards.ll
index 8d9b369198507..a62edb9032528 100644
--- a/llvm/test/Transforms/IndVarSimplify/pointer-loop-guards.ll
+++ b/llvm/test/Transforms/IndVarSimplify/pointer-loop-guards.ll
@@ -19,7 +19,7 @@ define i64 @test_ptr_compare_guard(ptr %start, ptr %end) {
; CHECK-NEXT: br i1 [[C_1]], label %[[LOOP_LATCH]], label %[[EXIT_LOOPEXIT:.*]]
; CHECK: [[LOOP_LATCH]]:
; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr i8, ptr [[PTR_IV]], i64 1
-; CHECK-NEXT: [[I64_IV_NEXT]] = add nuw i64 [[I64_IV]], 1
+; CHECK-NEXT: [[I64_IV_NEXT]] = add nuw nsw i64 [[I64_IV]], 1
; CHECK-NEXT: [[C_2:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]
; CHECK-NEXT: br i1 [[C_2]], label %[[EXIT_LOOPEXIT]], label %[[LOOP_HEADER]]
; CHECK: [[EXIT_LOOPEXIT]]:
@@ -92,7 +92,7 @@ define void @test_sub_cmp(ptr align 8 %start, ptr %end) {
; CHECK-NEXT: [[C_1:%.*]] = call i1 @cond()
; CHECK-NEXT: br i1 [[C_1]], label %[[EXIT_EARLY:.*]], label %[[LOOP_LATCH]]
; CHECK: [[LOOP_LATCH]]:
-; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[CMP_LATCH:%.*]] = icmp ult i64 [[IV_NEXT]], [[PTR_DIFF]]
; CHECK-NEXT: br i1 [[CMP_LATCH]], label %[[LOOP_HEADER]], label %[[EXIT_LOOPEXIT:.*]]
; CHECK: [[EXIT_EARLY]]:
diff --git a/llvm/test/Transforms/IndVarSimplify/pr55925.ll b/llvm/test/Transforms/IndVarSimplify/pr55925.ll
index 2ad187add4e10..dc193f50ad1c9 100644
--- a/llvm/test/Transforms/IndVarSimplify/pr55925.ll
+++ b/llvm/test/Transforms/IndVarSimplify/pr55925.ll
@@ -20,7 +20,7 @@ define void @test(ptr %p) personality ptr undef {
; CHECK: loop.latch:
; CHECK-NEXT: [[TMP1:%.*]] = trunc nuw i64 [[INDVARS_IV]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @foo(i32 [[TMP1]])
-; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: br label [[LOOP]]
; CHECK: exit:
; CHECK-NEXT: [[LP:%.*]] = landingpad { ptr, i32 }
@@ -65,7 +65,7 @@ define void @test_critedge(i1 %c, ptr %p) personality ptr undef {
; CHECK: loop.latch:
; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ [[TMP1]], [[LOOP_INVOKE]] ], [ 0, [[LOOP_OTHER]] ]
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @foo(i32 [[PHI]])
-; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: br label [[LOOP]]
; CHECK: exit:
; CHECK-NEXT: [[LP:%.*]] = landingpad { ptr, i32 }
diff --git a/llvm/test/Transforms/IndVarSimplify/pr57247.ll b/llvm/test/Transforms/IndVarSimplify/pr57247.ll
index c7bc9977ef9fd..80fdd6f83794e 100644
--- a/llvm/test/Transforms/IndVarSimplify/pr57247.ll
+++ b/llvm/test/Transforms/IndVarSimplify/pr57247.ll
@@ -65,7 +65,7 @@ define i32 @test_02() {
; CHECK-NEXT: [[CMP5_I:%.*]] = icmp samesign ult i64 [[STOREMERGE611_I]], 11
; CHECK-NEXT: br i1 [[CMP5_I]], label [[INNER_LOOP]], label [[OUTER_LATCH]]
; CHECK: outer.latch:
-; CHECK-NEXT: [[IV_NEXT]] = add nuw i32 [[IV]], 10
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 10
; CHECK-NEXT: br label [[OUTER_LOOP]]
; CHECK: exit:
; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[INNER_LOOP]] ]
diff --git a/llvm/test/Transforms/IndVarSimplify/pr79861.ll b/llvm/test/Transforms/IndVarSimplify/pr79861.ll
index 6625094496139..fd90cb1a7ab61 100644
--- a/llvm/test/Transforms/IndVarSimplify/pr79861.ll
+++ b/llvm/test/Transforms/IndVarSimplify/pr79861.ll
@@ -48,7 +48,7 @@ define void @add_nowrap_flags(i64 %n) {
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_INC:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[ADD1:%.*]] = add i64 [[IV]], 123
; CHECK-NEXT: call void @use(i64 [[ADD1]])
-; CHECK-NEXT: [[IV_INC]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[IV_INC]] = add nsw i64 [[IV]], 1
; CHECK-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[IV_INC]], [[N]]
; CHECK-NEXT: br i1 [[EXIT_COND]], label [[EXIT:%.*]], label [[LOOP]]
; CHECK: exit:
@@ -83,7 +83,7 @@ define void @expander_or_disjoint(i64 %n) {
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_INC:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[IV_INC]] = add i64 [[IV]], 1
-; CHECK-NEXT: [[ADD:%.*]] = add i64 [[IV]], [[OR]]
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[IV]], [[OR]]
; CHECK-NEXT: call void @use(i64 [[ADD]])
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[IV_INC]], [[TMP0]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
diff --git a/llvm/test/Transforms/IndVarSimplify/scev-expander-preserve-lcssa.ll b/llvm/test/Transforms/IndVarSimplify/scev-expander-preserve-lcssa.ll
index 14e06fe06b412..296f10c7bc9ce 100644
--- a/llvm/test/Transforms/IndVarSimplify/scev-expander-preserve-lcssa.ll
+++ b/llvm/test/Transforms/IndVarSimplify/scev-expander-preserve-lcssa.ll
@@ -23,8 +23,8 @@ define void @test1(i8 %x, ptr %ptr) {
; CHECK-NEXT: br label [[WHILE_COND192:%.*]]
; CHECK: while.cond192:
; CHECK-NEXT: switch i8 [[X:%.*]], label [[WHILE_BODY205:%.*]] [
-; CHECK-NEXT: i8 59, label [[WHILE_COND215_PREHEADER:%.*]]
-; CHECK-NEXT: i8 10, label [[IF_END224_LOOPEXIT1:%.*]]
+; CHECK-NEXT: i8 59, label [[WHILE_COND215_PREHEADER:%.*]]
+; CHECK-NEXT: i8 10, label [[IF_END224_LOOPEXIT1:%.*]]
; CHECK-NEXT: ]
; CHECK: while.cond215.preheader:
; CHECK-NEXT: br label [[WHILE_COND215:%.*]]
@@ -103,8 +103,8 @@ define void @test2(i16 %x) {
; CHECK-NEXT: br label [[FOR_COND:%.*]]
; CHECK: for.cond:
; CHECK-NEXT: switch i16 [[X:%.*]], label [[RETURN_LOOPEXIT1:%.*]] [
-; CHECK-NEXT: i16 41, label [[FOR_END:%.*]]
-; CHECK-NEXT: i16 43, label [[FOR_COND]]
+; CHECK-NEXT: i16 41, label [[FOR_END:%.*]]
+; CHECK-NEXT: i16 43, label [[FOR_COND]]
; CHECK-NEXT: ]
; CHECK: for.end:
; CHECK-NEXT: [[I_0_LCSSA2:%.*]] = phi i32 [ 0, [[FOR_COND]] ]
@@ -365,7 +365,7 @@ define void @test5(ptr %header, i32 %conv, i8 %n) {
; CHECK-NEXT: [[CMP112:%.*]] = icmp ult i32 [[POS_8]], [[SHL]]
; CHECK-NEXT: br i1 [[CMP112]], label [[WHILE_BODY]], label [[CLEANUP122:%.*]]
; CHECK: while.body:
-; CHECK-NEXT: [[INC114]] = add nuw i32 [[POS_8]], 1
+; CHECK-NEXT: [[INC114]] = add nuw nsw i32 [[POS_8]], 1
; CHECK-NEXT: [[C_1:%.*]] = call i1 @cond()
; CHECK-NEXT: br i1 [[C_1]], label [[WHILE_COND]], label [[CLEANUP122]]
; CHECK: cleanup122:
@@ -427,8 +427,8 @@ define void @test6(i8 %x) {
; CHECK-NEXT: br label [[WHILE_COND192:%.*]]
; CHECK: while.cond192:
; CHECK-NEXT: switch i8 [[X:%.*]], label [[WHILE_BODY205:%.*]] [
-; CHECK-NEXT: i8 59, label [[WHILE_COND215_PREHEADER:%.*]]
-; CHECK-NEXT: i8 10, label [[IF_END224:%.*]]
+; CHECK-NEXT: i8 59, label [[WHILE_COND215_PREHEADER:%.*]]
+; CHECK-NEXT: i8 10, label [[IF_END224:%.*]]
; CHECK-NEXT: ]
; CHECK: while.cond215.preheader:
; CHECK-NEXT: [[I_7_LCSSA:%.*]] = phi i32 [ 0, [[WHILE_COND192]] ]
diff --git a/llvm/test/Transforms/IndVarSimplify/simplify-icmp-operands-order.ll b/llvm/test/Transforms/IndVarSimplify/simplify-icmp-operands-order.ll
index fb2fdb116f904..74efc110bbc17 100644
--- a/llvm/test/Transforms/IndVarSimplify/simplify-icmp-operands-order.ll
+++ b/llvm/test/Transforms/IndVarSimplify/simplify-icmp-operands-order.ll
@@ -83,7 +83,7 @@ define void @test_simplifycompare_rhs_not_constant2(i32 %x) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: br label %[[OUTER_HEADER:.*]]
; CHECK: [[OUTER_HEADER_LOOPEXIT:.*]]:
-; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw i64 [[INDVARS_IV:%.*]], 2
+; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV:%.*]], 2
; CHECK-NEXT: br label %[[OUTER_HEADER]]
; CHECK: [[OUTER_HEADER]]:
; CHECK-NEXT: [[INDVARS_IV]] = phi i64 [ [[INDVARS_IV_NEXT]], %[[OUTER_HEADER_LOOPEXIT]] ], [ 0, %[[ENTRY]] ]
diff --git a/llvm/test/Transforms/IndVarSimplify/strengthen-overflow.ll b/llvm/test/Transforms/IndVarSimplify/strengthen-overflow.ll
index 4a230b781d2db..0b6843b34894b 100644
--- a/llvm/test/Transforms/IndVarSimplify/strengthen-overflow.ll
+++ b/llvm/test/Transforms/IndVarSimplify/strengthen-overflow.ll
@@ -309,7 +309,7 @@ define void @test_infer_nsw(ptr %p) {
; CHECK-NEXT: br i1 [[ICMP]], label [[BB2]], label [[BB3:%.*]]
; CHECK: bb2:
; CHECK-NEXT: store i16 1, ptr [[P:%.*]], align 2
-; CHECK-NEXT: [[ADD]] = add nuw i32 [[PHI]], 2
+; CHECK-NEXT: [[ADD]] = add nuw nsw i32 [[PHI]], 2
; CHECK-NEXT: br label [[BB1]]
; CHECK: bb3:
; CHECK-NEXT: ret void
@@ -402,7 +402,7 @@ define void @test_shl_unbounded(ptr %p, i64 %n) {
; CHECK-NEXT: [[OFF:%.*]] = shl i64 [[IV]], 2
; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 [[OFF]]
; CHECK-NEXT: store i8 0, ptr [[GEP]], align 1
-; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N:%.*]]
; CHECK-NEXT: br i1 [[EC]], label [[EXIT:%.*]], label [[LOOP]]
; CHECK: exit:
@@ -430,9 +430,9 @@ define void @test_shl_nuw_only(ptr %p) {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i8 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
-; CHECK-NEXT: [[OFF:%.*]] = shl nuw i8 [[IV]], 1
+; CHECK-NEXT: [[OFF:%.*]] = shl nuw nsw i8 [[IV]], 1
; CHECK-NEXT: store i8 [[OFF]], ptr [[P:%.*]], align 1
-; CHECK-NEXT: [[IV_NEXT]] = add nuw i8 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i8 [[IV]], 1
; CHECK-NEXT: [[EC:%.*]] = icmp eq i8 [[IV_NEXT]], -128
; CHECK-NEXT: br i1 [[EC]], label [[EXIT:%.*]], label [[LOOP]]
; CHECK: exit:
diff --git a/llvm/test/Transforms/IndVarSimplify/turn-to-invariant.ll b/llvm/test/Transforms/IndVarSimplify/turn-to-invariant.ll
index 406b6ecd944f4..71ebe903083cd 100644
--- a/llvm/test/Transforms/IndVarSimplify/turn-to-invariant.ll
+++ b/llvm/test/Transforms/IndVarSimplify/turn-to-invariant.ll
@@ -930,7 +930,7 @@ define i32 @test_predicated_backedge_no_side_exit(i32 %len) {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
-; CHECK-NEXT: [[IV_NEXT]] = add nuw i32 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-NEXT: br i1 [[TMP1]], label [[BACKEDGE]], label [[FAILED:%.*]]
; CHECK: backedge:
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ult i32 [[IV_NEXT]], [[LEN]]
@@ -971,7 +971,7 @@ define i32 @test_predicated_backedge_with_side_exit(i32 %len) {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
-; CHECK-NEXT: [[IV_NEXT]] = add nuw i32 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-NEXT: [[CHECK:%.*]] = icmp ult i32 [[IV]], [[LEN]]
; CHECK-NEXT: br i1 [[CHECK]], label [[INNER_BLOCK:%.*]], label [[FAILED:%.*]]
; CHECK: inner_block:
@@ -1065,7 +1065,7 @@ define i32 @not_invariant_samesign(i32 %unknown_limit, ptr %length_ptr) {
; CHECK-NEXT: br label [[HEADER:%.*]]
; CHECK: header:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
-; CHECK-NEXT: [[IV_NEXT]] = add nuw i32 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-NEXT: [[RANGE_CHECK1_FIRST_ITER:%.*]] = icmp samesign ult i32 [[IV_NEXT]], [[UNKNOWN_LIMIT:%.*]]
; CHECK-NEXT: [[IS_POSITIVE:%.*]] = icmp sgt i32 [[UNKNOWN_LIMIT]], 0
; CHECK-NEXT: [[OR_COND:%.*]] = and i1 [[RANGE_CHECK1_FIRST_ITER]], [[IS_POSITIVE]]
diff --git a/llvm/test/Transforms/IndVarSimplify/widen-nonnegative.ll b/llvm/test/Transforms/IndVarSimplify/widen-nonnegative.ll
index e00eaafa3f192..31bae803c7ba7 100644
--- a/llvm/test/Transforms/IndVarSimplify/widen-nonnegative.ll
+++ b/llvm/test/Transforms/IndVarSimplify/widen-nonnegative.ll
@@ -143,16 +143,14 @@ exit:
define void @sext_add_nuw(ptr %A, i32 %offset, i32 %M) {
; CHECK-LABEL: @sext_add_nuw(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[OFFSET:%.*]] to i64
+; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[OFFSET:%.*]] to i64
; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[M:%.*]], i32 1)
; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[SMAX]] to i64
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[INDVARS_IV]], [[TMP0]]
-; CHECK-NEXT: [[TMP2:%.*]] = trunc nuw i64 [[TMP1]] to i32
-; CHECK-NEXT: [[IDXPROM_US:%.*]] = sext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[IDXPROM_US]]
+; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[TMP1]]
; CHECK-NEXT: tail call void @use_ptr(ptr [[ARRAYIDX_US]])
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]]
@@ -180,14 +178,13 @@ exit:
define void @sext_add_noflags(ptr %A, i32 %offset, i32 %M) {
; CHECK-LABEL: @sext_add_noflags(
; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[OFFSET:%.*]] to i64
; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[M:%.*]], i32 1)
; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[SMAX]] to i64
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = trunc nuw nsw i64 [[INDVARS_IV]] to i32
-; CHECK-NEXT: [[ADD_US:%.*]] = add i32 [[TMP0]], [[OFFSET:%.*]]
-; CHECK-NEXT: [[IDXPROM_US:%.*]] = sext i32 [[ADD_US]] to i64
+; CHECK-NEXT: [[IDXPROM_US:%.*]] = add nsw i64 [[INDVARS_IV]], [[TMP0]]
; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[IDXPROM_US]]
; CHECK-NEXT: tail call void @use_ptr(ptr [[ARRAYIDX_US]])
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
@@ -288,13 +285,14 @@ exit:
define void @zext_add_noflags(ptr %A, i32 %offset, i32 %M) {
; CHECK-LABEL: @zext_add_noflags(
; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[OFFSET:%.*]] to i64
; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[M:%.*]], i32 1)
; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[SMAX]] to i64
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = trunc nuw nsw i64 [[INDVARS_IV]] to i32
-; CHECK-NEXT: [[ADD_US:%.*]] = add i32 [[TMP0]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[INDVARS_IV]], [[TMP0]]
+; CHECK-NEXT: [[ADD_US:%.*]] = trunc nsw i64 [[TMP1]] to i32
; CHECK-NEXT: [[IDXPROM_US:%.*]] = zext i32 [[ADD_US]] to i64
; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[IDXPROM_US]]
; CHECK-NEXT: tail call void @use_ptr(ptr [[ARRAYIDX_US]])
@@ -394,14 +392,13 @@ exit:
define void @zext_nneg_add_noflags(ptr %A, i32 %offset, i32 %M) {
; CHECK-LABEL: @zext_nneg_add_noflags(
; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[OFFSET:%.*]] to i64
; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[M:%.*]], i32 1)
; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[SMAX]] to i64
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = trunc nuw nsw i64 [[INDVARS_IV]] to i32
-; CHECK-NEXT: [[ADD_US:%.*]] = add i32 [[TMP0]], [[OFFSET:%.*]]
-; CHECK-NEXT: [[IDXPROM_US:%.*]] = zext nneg i32 [[ADD_US]] to i64
+; CHECK-NEXT: [[IDXPROM_US:%.*]] = add nsw i64 [[INDVARS_IV]], [[TMP0]]
; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[IDXPROM_US]]
; CHECK-NEXT: tail call void @use_ptr(ptr [[ARRAYIDX_US]])
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
diff --git a/llvm/test/Transforms/LoopFlatten/widen-iv.ll b/llvm/test/Transforms/LoopFlatten/widen-iv.ll
index ac42acb932fc3..1c63614f9c68c 100644
--- a/llvm/test/Transforms/LoopFlatten/widen-iv.ll
+++ b/llvm/test/Transforms/LoopFlatten/widen-iv.ll
@@ -797,24 +797,30 @@ define void @test4(i16 %n, i16 %m) {
; CHECK: for.cond3.preheader.us.preheader:
; CHECK-NEXT: [[TMP0:%.*]] = sext i16 [[M]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[N]] to i64
-; CHECK-NEXT: [[FLATTEN_TRIPCOUNT:%.*]] = mul i64 [[TMP0]], [[TMP1]]
; CHECK-NEXT: br label [[FOR_COND3_PREHEADER_US:%.*]]
; CHECK: for.cond3.preheader.us:
; CHECK-NEXT: [[INDVAR2:%.*]] = phi i64 [ [[INDVAR_NEXT3:%.*]], [[FOR_COND3_FOR_COND_CLEANUP8_CRIT_EDGE_US:%.*]] ], [ 0, [[FOR_COND3_PREHEADER_US_PREHEADER]] ]
-; CHECK-NEXT: [[FLATTEN_TRUNCIV:%.*]] = trunc i64 [[INDVAR2]] to i16
+; CHECK-NEXT: [[TMP2:%.*]] = trunc nuw nsw i64 [[INDVAR2]] to i16
+; CHECK-NEXT: [[MUL_US:%.*]] = mul i16 [[TMP2]], [[M]]
+; CHECK-NEXT: [[TMP3:%.*]] = sext i16 [[MUL_US]] to i64
; CHECK-NEXT: br label [[FOR_BODY9_US:%.*]]
; CHECK: for.body9.us:
-; CHECK-NEXT: [[CONV14_US:%.*]] = sext i16 [[FLATTEN_TRUNCIV]] to i32
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ [[INDVAR_NEXT:%.*]], [[FOR_BODY9_US]] ], [ 0, [[FOR_COND3_PREHEADER_US]] ]
+; CHECK-NEXT: [[CONV19_US:%.*]] = add i64 [[INDVAR]], [[TMP3]]
+; CHECK-NEXT: [[CONV14_US:%.*]] = trunc nsw i64 [[CONV19_US]] to i32
; CHECK-NEXT: [[CALL_US:%.*]] = tail call i32 @use_32(i32 [[CONV14_US]])
+; CHECK-NEXT: [[FLATTEN_TRUNCIV:%.*]] = trunc nsw i64 [[CONV19_US]] to i16
; CHECK-NEXT: [[CALL15_US:%.*]] = tail call i32 @use_16(i16 [[FLATTEN_TRUNCIV]])
; CHECK-NEXT: [[CALL17_US:%.*]] = tail call i32 @use_32(i32 [[CONV14_US]])
-; CHECK-NEXT: [[CALL18_US:%.*]] = tail call i32 @use_16(i16 [[FLATTEN_TRUNCIV]])
-; CHECK-NEXT: [[CONV19_US:%.*]] = sext i16 [[FLATTEN_TRUNCIV]] to i64
+; CHECK-NEXT: [[TMP7:%.*]] = trunc nsw i64 [[CONV19_US]] to i16
+; CHECK-NEXT: [[CALL18_US:%.*]] = tail call i32 @use_16(i16 [[TMP7]])
; CHECK-NEXT: [[CALL20_US:%.*]] = tail call i32 @use_64(i64 [[CONV19_US]])
-; CHECK-NEXT: br label [[FOR_COND3_FOR_COND_CLEANUP8_CRIT_EDGE_US]]
+; CHECK-NEXT: [[INDVAR_NEXT]] = add nuw nsw i64 [[INDVAR]], 1
+; CHECK-NEXT: [[CMP6_US:%.*]] = icmp slt i64 [[INDVAR_NEXT]], [[TMP0]]
+; CHECK-NEXT: br i1 [[CMP6_US]], label [[FOR_BODY9_US]], label [[FOR_COND3_FOR_COND_CLEANUP8_CRIT_EDGE_US]]
; CHECK: for.cond3.for.cond.cleanup8_crit_edge.us:
; CHECK-NEXT: [[INDVAR_NEXT3]] = add i64 [[INDVAR2]], 1
-; CHECK-NEXT: [[CMP_US:%.*]] = icmp slt i64 [[INDVAR_NEXT3]], [[FLATTEN_TRIPCOUNT]]
+; CHECK-NEXT: [[CMP_US:%.*]] = icmp slt i64 [[INDVAR_NEXT3]], [[TMP1]]
; CHECK-NEXT: br i1 [[CMP_US]], label [[FOR_COND3_PREHEADER_US]], label [[FOR_COND_CLEANUP_LOOPEXIT:%.*]]
; CHECK: for.cond3.preheader:
; CHECK-NEXT: [[I_039:%.*]] = phi i16 [ [[INC22:%.*]], [[FOR_COND3_PREHEADER]] ], [ 0, [[FOR_COND3_PREHEADER_PREHEADER]] ]
diff --git a/llvm/test/Transforms/LoopStrengthReduce/ARM/illegal-addr-modes.ll b/llvm/test/Transforms/LoopStrengthReduce/ARM/illegal-addr-modes.ll
index 3844e00ae0a4f..2b6371b47237e 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/ARM/illegal-addr-modes.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/ARM/illegal-addr-modes.ll
@@ -40,7 +40,7 @@ define ptr @negativeOneCase(ptr returned %a, ptr nocapture readonly %b, i32 %n)
; CHECK: while.body5:
; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[SCEVGEP1]], align 1
; CHECK-NEXT: store i8 [[TMP1]], ptr [[SCEVGEP2]], align 1
-; CHECK-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 1
+; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i32 [[LSR_IV]], 1
; CHECK-NEXT: br label [[WHILE_COND2]]
; CHECK: while.end8:
; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[INCDEC_PTR]], i32 [[N]]
diff --git a/llvm/test/Transforms/LoopStrengthReduce/X86/2008-08-14-ShadowIV.ll b/llvm/test/Transforms/LoopStrengthReduce/X86/2008-08-14-ShadowIV.ll
index da14e631f5142..3c37ee6b6b98a 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/X86/2008-08-14-ShadowIV.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/X86/2008-08-14-ShadowIV.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt < %s -loop-reduce -S -mtriple=x86_64-unknown-unknown 2>&1 | FileCheck %s
; Provide legal integer types.
@@ -5,122 +6,201 @@ target datalayout = "n8:16:32:64"
define void @foobar(i32 %n) nounwind {
-
-; CHECK-LABEL: foobar(
-; CHECK: phi double
+; CHECK-LABEL: define void @foobar(
+; CHECK-SAME: i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[N]], 0
+; CHECK-NEXT: br i1 [[COND]], label %[[RETURN:.*]], label %[[BB_NPH:.*]]
+; CHECK: [[BB_NPH]]:
+; CHECK-NEXT: br label %[[BB:.*]]
+; CHECK: [[BB]]:
+; CHECK-NEXT: [[IV_S_:%.*]] = phi double [ 0.000000e+00, %[[BB_NPH]] ], [ [[IV_S_NEXT_:%.*]], %[[BB]] ]
+; CHECK-NEXT: [[I_03:%.*]] = phi i32 [ 0, %[[BB_NPH]] ], [ [[INDVAR_NEXT:%.*]], %[[BB]] ]
+; CHECK-NEXT: tail call void @bar(i32 [[I_03]]) #[[ATTR0]]
+; CHECK-NEXT: tail call void @foo(double [[IV_S_]]) #[[ATTR0]]
+; CHECK-NEXT: [[IV_S_NEXT_]] = fadd double [[IV_S_]], 1.000000e+00
+; CHECK-NEXT: [[INDVAR_NEXT]] = add nuw i32 [[I_03]], 1
+; CHECK-NEXT: [[SCMP:%.*]] = icmp uge i32 [[INDVAR_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[SCMP]], label %[[RETURN_LOOPEXIT:.*]], label %[[BB]]
+; CHECK: [[RETURN_LOOPEXIT]]:
+; CHECK-NEXT: br label %[[RETURN]]
+; CHECK: [[RETURN]]:
+; CHECK-NEXT: ret void
+;
entry:
- %cond = icmp eq i32 %n, 0 ; <i1>:0 [#uses=2]
- br i1 %cond, label %return, label %bb.nph
+ %cond = icmp eq i32 %n, 0 ; <i1>:0 [#uses=2]
+ br i1 %cond, label %return, label %bb.nph
bb.nph: ; preds = %entry
- %umax = select i1 %cond, i32 1, i32 %n ; <i32> [#uses=1]
- br label %bb
+ %umax = select i1 %cond, i32 1, i32 %n ; <i32> [#uses=1]
+ br label %bb
bb: ; preds = %bb, %bb.nph
- %i.03 = phi i32 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; <i32> [#uses=3]
- tail call void @bar( i32 %i.03 ) nounwind
- %tmp1 = uitofp i32 %i.03 to double ; <double>:1 [#uses=1]
- tail call void @foo( double %tmp1 ) nounwind
- %indvar.next = add nsw nuw i32 %i.03, 1 ; <i32> [#uses=2]
- %exitcond = icmp eq i32 %indvar.next, %umax ; <i1> [#uses=1]
- br i1 %exitcond, label %return, label %bb
+ %i.03 = phi i32 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; <i32> [#uses=3]
+ tail call void @bar( i32 %i.03 ) nounwind
+ %tmp1 = uitofp i32 %i.03 to double ; <double>:1 [#uses=1]
+ tail call void @foo( double %tmp1 ) nounwind
+ %indvar.next = add nsw nuw i32 %i.03, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, %umax ; <i1> [#uses=1]
+ br i1 %exitcond, label %return, label %bb
return: ; preds = %bb, %entry
- ret void
+ ret void
}
; Unable to eliminate cast because the mantissa bits for double are not enough
; to hold all of i64 IV bits.
define void @foobar2(i64 %n) nounwind {
-
-; CHECK-LABEL: foobar2(
-; CHECK-NOT: phi double
-; CHECK-NOT: phi float
+; CHECK-LABEL: define void @foobar2(
+; CHECK-SAME: i64 [[N:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[N]], 0
+; CHECK-NEXT: br i1 [[COND]], label %[[RETURN:.*]], label %[[BB_NPH:.*]]
+; CHECK: [[BB_NPH]]:
+; CHECK-NEXT: br label %[[BB:.*]]
+; CHECK: [[BB]]:
+; CHECK-NEXT: [[I_03:%.*]] = phi i64 [ 0, %[[BB_NPH]] ], [ [[INDVAR_NEXT:%.*]], %[[BB]] ]
+; CHECK-NEXT: [[TMP:%.*]] = trunc i64 [[I_03]] to i32
+; CHECK-NEXT: tail call void @bar(i32 [[TMP]]) #[[ATTR0]]
+; CHECK-NEXT: [[TMP2:%.*]] = uitofp i64 [[I_03]] to double
+; CHECK-NEXT: tail call void @foo(double [[TMP2]]) #[[ATTR0]]
+; CHECK-NEXT: [[INDVAR_NEXT]] = add nuw i64 [[I_03]], 1
+; CHECK-NEXT: [[SCMP:%.*]] = icmp uge i64 [[INDVAR_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[SCMP]], label %[[RETURN_LOOPEXIT:.*]], label %[[BB]]
+; CHECK: [[RETURN_LOOPEXIT]]:
+; CHECK-NEXT: br label %[[RETURN]]
+; CHECK: [[RETURN]]:
+; CHECK-NEXT: ret void
+;
entry:
- %cond = icmp eq i64 %n, 0 ; <i1>:0 [#uses=2]
- br i1 %cond, label %return, label %bb.nph
+ %cond = icmp eq i64 %n, 0 ; <i1>:0 [#uses=2]
+ br i1 %cond, label %return, label %bb.nph
bb.nph: ; preds = %entry
- %umax = select i1 %cond, i64 1, i64 %n ; <i64> [#uses=1]
- br label %bb
+ %umax = select i1 %cond, i64 1, i64 %n ; <i64> [#uses=1]
+ br label %bb
bb: ; preds = %bb, %bb.nph
- %i.03 = phi i64 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; <i64> [#uses=3]
- %tmp1 = trunc i64 %i.03 to i32 ; <i32>:1 [#uses=1]
- tail call void @bar( i32 %tmp1 ) nounwind
- %tmp2 = uitofp i64 %i.03 to double ; <double>:2 [#uses=1]
- tail call void @foo( double %tmp2 ) nounwind
- %indvar.next = add nsw nuw i64 %i.03, 1 ; <i64> [#uses=2]
- %exitcond = icmp eq i64 %indvar.next, %umax ; <i1> [#uses=1]
- br i1 %exitcond, label %return, label %bb
+ %i.03 = phi i64 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; <i64> [#uses=3]
+ %tmp1 = trunc i64 %i.03 to i32 ; <i32>:1 [#uses=1]
+ tail call void @bar( i32 %tmp1 ) nounwind
+ %tmp2 = uitofp i64 %i.03 to double ; <double>:2 [#uses=1]
+ tail call void @foo( double %tmp2 ) nounwind
+ %indvar.next = add nsw nuw i64 %i.03, 1 ; <i64> [#uses=2]
+ %exitcond = icmp eq i64 %indvar.next, %umax ; <i1> [#uses=1]
+ br i1 %exitcond, label %return, label %bb
return: ; preds = %bb, %entry
- ret void
+ ret void
}
; Unable to eliminate cast due to potentional overflow.
define void @foobar3() nounwind {
-
-; CHECK-LABEL: foobar3(
-; CHECK-NOT: phi double
-; CHECK-NOT: phi float
+; CHECK-LABEL: define void @foobar3(
+; CHECK-SAME: ) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[TMP0:%.*]] = tail call i32 (...) @nn() #[[ATTR0]]
+; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[TMP0]], 0
+; CHECK-NEXT: br i1 [[COND]], label %[[RETURN:.*]], label %[[BB_PREHEADER:.*]]
+; CHECK: [[BB_PREHEADER]]:
+; CHECK-NEXT: br label %[[BB:.*]]
+; CHECK: [[BB]]:
+; CHECK-NEXT: [[I_03:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], %[[BB]] ], [ 0, %[[BB_PREHEADER]] ]
+; CHECK-NEXT: tail call void @bar(i32 [[I_03]]) #[[ATTR0]]
+; CHECK-NEXT: [[TMP2:%.*]] = uitofp i32 [[I_03]] to double
+; CHECK-NEXT: tail call void @foo(double [[TMP2]]) #[[ATTR0]]
+; CHECK-NEXT: [[INDVAR_NEXT]] = add nuw i32 [[I_03]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = tail call i32 (...) @nn() #[[ATTR0]]
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ugt i32 [[TMP4]], [[INDVAR_NEXT]]
+; CHECK-NEXT: br i1 [[EXITCOND]], label %[[BB]], label %[[RETURN_LOOPEXIT:.*]]
+; CHECK: [[RETURN_LOOPEXIT]]:
+; CHECK-NEXT: br label %[[RETURN]]
+; CHECK: [[RETURN]]:
+; CHECK-NEXT: ret void
+;
entry:
- %tmp0 = tail call i32 (...) @nn( ) nounwind ; <i32>:0 [#uses=1]
- %cond = icmp eq i32 %tmp0, 0 ; <i1>:1 [#uses=1]
- br i1 %cond, label %return, label %bb
+ %tmp0 = tail call i32 (...) @nn( ) nounwind ; <i32>:0 [#uses=1]
+ %cond = icmp eq i32 %tmp0, 0 ; <i1>:1 [#uses=1]
+ br i1 %cond, label %return, label %bb
bb: ; preds = %bb, %entry
- %i.03 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=3]
- tail call void @bar( i32 %i.03 ) nounwind
- %tmp2 = uitofp i32 %i.03 to double ; <double>:2 [#uses=1]
- tail call void @foo( double %tmp2 ) nounwind
- %indvar.next = add nuw nsw i32 %i.03, 1 ; <i32>:3 [#uses=2]
- %tmp4 = tail call i32 (...) @nn( ) nounwind ; <i32>:4 [#uses=1]
- %exitcond = icmp ugt i32 %tmp4, %indvar.next ; <i1>:5 [#uses=1]
- br i1 %exitcond, label %bb, label %return
+ %i.03 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=3]
+ tail call void @bar( i32 %i.03 ) nounwind
+ %tmp2 = uitofp i32 %i.03 to double ; <double>:2 [#uses=1]
+ tail call void @foo( double %tmp2 ) nounwind
+ %indvar.next = add nuw nsw i32 %i.03, 1 ; <i32>:3 [#uses=2]
+ %tmp4 = tail call i32 (...) @nn( ) nounwind ; <i32>:4 [#uses=1]
+ %exitcond = icmp ugt i32 %tmp4, %indvar.next ; <i1>:5 [#uses=1]
+ br i1 %exitcond, label %bb, label %return
return: ; preds = %bb, %entry
- ret void
+ ret void
}
; Unable to eliminate cast due to overflow.
define void @foobar4() nounwind {
-
-; CHECK-LABEL: foobar4(
-; CHECK-NOT: phi double
-; CHECK-NOT: phi float
+; CHECK-LABEL: define void @foobar4(
+; CHECK-SAME: ) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: br label %[[BB_NPH:.*]]
+; CHECK: [[BB_NPH]]:
+; CHECK-NEXT: br label %[[BB:.*]]
+; CHECK: [[BB]]:
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], %[[BB]] ], [ 0, %[[BB_NPH]] ]
+; CHECK-NEXT: [[IV_S_:%.*]] = phi double [ 0.000000e+00, %[[BB_NPH]] ], [ [[IV_S_NEXT_:%.*]], %[[BB]] ]
+; CHECK-NEXT: tail call void @bar(i32 [[LSR_IV]]) #[[ATTR0]]
+; CHECK-NEXT: tail call void @foo(double [[IV_S_]]) #[[ATTR0]]
+; CHECK-NEXT: [[IV_S_NEXT_]] = fadd double [[IV_S_]], 1.000000e+00
+; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i32 [[LSR_IV]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], 32767
+; CHECK-NEXT: br i1 [[EXITCOND]], label %[[RETURN:.*]], label %[[BB]]
+; CHECK: [[RETURN]]:
+; CHECK-NEXT: ret void
+;
entry:
- br label %bb.nph
+ br label %bb.nph
bb.nph: ; preds = %entry
- br label %bb
+ br label %bb
bb: ; preds = %bb, %bb.nph
- %i.03 = phi i8 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; <i32> [#uses=3]
- %tmp2 = sext i8 %i.03 to i32 ; <i32>:0 [#uses=1]
- tail call void @bar( i32 %tmp2 ) nounwind
- %tmp3 = uitofp i8 %i.03 to double ; <double>:1 [#uses=1]
- tail call void @foo( double %tmp3 ) nounwind
- %indvar.next = add nsw nuw i8 %i.03, 1 ; <i32> [#uses=2]
- %tmp = sext i8 %indvar.next to i32
- %exitcond = icmp eq i32 %tmp, 32767 ; <i1> [#uses=1]
- br i1 %exitcond, label %return, label %bb
+ %i.03 = phi i8 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; <i32> [#uses=3]
+ %tmp2 = sext i8 %i.03 to i32 ; <i32>:0 [#uses=1]
+ tail call void @bar( i32 %tmp2 ) nounwind
+ %tmp3 = uitofp i8 %i.03 to double ; <double>:1 [#uses=1]
+ tail call void @foo( double %tmp3 ) nounwind
+ %indvar.next = add nsw nuw i8 %i.03, 1 ; <i32> [#uses=2]
+ %tmp = sext i8 %indvar.next to i32
+ %exitcond = icmp eq i32 %tmp, 32767 ; <i1> [#uses=1]
+ br i1 %exitcond, label %return, label %bb
return: ; preds = %bb, %entry
- ret void
+ ret void
}
; Unable to eliminate cast because the integer IV overflows (accum exceeds
; SINT_MAX).
define i32 @foobar5() {
-; CHECK-LABEL: foobar5(
-; CHECK-NOT: phi double
-; CHECK-NOT: phi float
+; CHECK-LABEL: define i32 @foobar5() {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], %[[LOOP]] ], [ 11, %[[ENTRY]] ]
+; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ -3220, %[[ENTRY]] ], [ [[ACCUM_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = sitofp i32 [[ACCUM]] to double
+; CHECK-NEXT: tail call void @foo(double [[TMP1]]) #[[ATTR0]]
+; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], 9597741
+; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i32 [[LSR_IV]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ugt i32 [[LSR_IV_NEXT]], 235
+; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret i32 [[ACCUM_NEXT]]
+;
entry:
br label %loop
@@ -141,8 +221,22 @@ exit: ; preds = %loop
; Can eliminate if we set nsw and, thus, think that we don't overflow SINT_MAX.
define i32 @foobar6() {
-; CHECK-LABEL: foobar6(
-; CHECK: phi double
+; CHECK-LABEL: define i32 @foobar6() {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], %[[LOOP]] ], [ 11, %[[ENTRY]] ]
+; CHECK-NEXT: [[IV_S_:%.*]] = phi double [ -3.220000e+03, %[[ENTRY]] ], [ [[IV_S_NEXT_:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ -3220, %[[ENTRY]] ], [ [[ACCUM_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: tail call void @foo(double [[IV_S_]]) #[[ATTR0]]
+; CHECK-NEXT: [[IV_S_NEXT_]] = fadd double [[IV_S_]], f0x41624E65A0000000
+; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], 9597741
+; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i32 [[LSR_IV]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ugt i32 [[LSR_IV_NEXT]], 235
+; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret i32 [[ACCUM_NEXT]]
+;
entry:
br label %loop
@@ -165,9 +259,21 @@ exit: ; preds = %loop
; UINT_MAX).
define i32 @foobar7() {
-; CHECK-LABEL: foobar7(
-; CHECK-NOT: phi double
-; CHECK-NOT: phi float
+; CHECK-LABEL: define i32 @foobar7() {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], %[[LOOP]] ], [ 11, %[[ENTRY]] ]
+; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ -3220, %[[ENTRY]] ], [ [[ACCUM_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = uitofp i32 [[ACCUM]] to double
+; CHECK-NEXT: tail call void @foo(double [[TMP1]]) #[[ATTR0]]
+; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], 9597741
+; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i32 [[LSR_IV]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ugt i32 [[LSR_IV_NEXT]], 235
+; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret i32 [[ACCUM_NEXT]]
+;
entry:
br label %loop
@@ -188,8 +294,22 @@ exit: ; preds = %loop
; Can eliminate if we set nuw and, thus, think that we don't overflow UINT_MAX.
define i32 @foobar8() {
-; CHECK-LABEL: foobar8(
-; CHECK: phi double
+; CHECK-LABEL: define i32 @foobar8() {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], %[[LOOP]] ], [ 11, %[[ENTRY]] ]
+; CHECK-NEXT: [[IV_S_:%.*]] = phi double [ f0x41EFFFFE6D800000, %[[ENTRY]] ], [ [[IV_S_NEXT_:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ -3220, %[[ENTRY]] ], [ [[ACCUM_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: tail call void @foo(double [[IV_S_]]) #[[ATTR0]]
+; CHECK-NEXT: [[IV_S_NEXT_]] = fadd double [[IV_S_]], f0x41624E65A0000000
+; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], 9597741
+; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i32 [[LSR_IV]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ugt i32 [[LSR_IV_NEXT]], 235
+; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret i32 [[ACCUM_NEXT]]
+;
entry:
br label %loop
diff --git a/llvm/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll b/llvm/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll
index f780bee7874cf..a5300b3fb81e1 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll
@@ -108,7 +108,7 @@ define void @test2(i32 %n, i1 %arg) nounwind uwtable {
; CHECK-NEXT: br label [[FOR_INC498:%.*]]
; CHECK: if.then477:
; CHECK-NEXT: [[SCEVGEP]] = getelementptr i8, ptr [[LSR_IV]], i64 12
-; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw i32 [[LSR_IV1]], 1
+; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i32 [[LSR_IV1]], 1
; CHECK-NEXT: br label [[FOR_COND468]]
; CHECK: for.inc498:
; CHECK-NEXT: br label [[FOR_INC498]]
diff --git a/llvm/test/Transforms/LoopStrengthReduce/X86/pr17473.ll b/llvm/test/Transforms/LoopStrengthReduce/X86/pr17473.ll
index a878fc2c39e82..f39d33e77b7a4 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/X86/pr17473.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/X86/pr17473.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt < %s -loop-reduce -S | FileCheck %s
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
@@ -7,8 +8,6 @@ target triple = "x86_64-apple-macosx10.9.0"
; expression. In this testcase, the normalized expression was denormalized to
; an expression different from the original, and we were losing sign extension.
-; CHECK: [[TMP:%[a-z]+]] = trunc i32 {{.*}} to i8
-; CHECK: {{%[a-z0-9]+}} = sext i8 [[TMP]] to i32
@j = common global i32 0, align 4
@c = common global i32 0, align 4
@@ -23,6 +22,41 @@ target triple = "x86_64-apple-macosx10.9.0"
; Function Attrs: nounwind optsize ssp uwtable
define i32 @main() #0 {
+; CHECK-LABEL: define i32 @main(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: store i8 0, ptr @h, align 1
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @j, align 4
+; CHECK-NEXT: [[TOBOOL_I:%.*]] = icmp eq i32 [[TMP0]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @d, align 4
+; CHECK-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP1]], -1
+; CHECK-NEXT: [[DOTLOBIT:%.*]] = lshr i32 [[TMP1]], 31
+; CHECK-NEXT: [[DOTLOBIT_NOT:%.*]] = xor i32 [[DOTLOBIT]], 1
+; CHECK-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK: [[FOR_BODY]]:
+; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], %[[FN3_EXIT:.*]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], %[[FN3_EXIT]] ], [ -1, %[[ENTRY]] ]
+; CHECK-NEXT: br i1 [[TOBOOL_I]], label %[[FN3_EXIT]], label %[[LAND_RHS_I:.*]]
+; CHECK: [[LAND_RHS_I]]:
+; CHECK-NEXT: store i32 0, ptr @c, align 4
+; CHECK-NEXT: br label %[[FN3_EXIT]]
+; CHECK: [[FN3_EXIT]]:
+; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i32 [[LSR_IV]], 2
+; CHECK-NEXT: [[LSR_IV_NEXT2]] = add nuw nsw i32 [[LSR_IV1]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[LSR_IV_NEXT2]] to i8
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i8 [[TMP3]], -1
+; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_BODY]], label %[[FOR_END:.*]]
+; CHECK: [[FOR_END]]:
+; CHECK-NEXT: [[DOTLOBIT_NOT_:%.*]] = select i1 [[CMP3]], i32 [[DOTLOBIT_NOT]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[LSR_IV_NEXT2]], -1
+; CHECK-NEXT: store i32 [[TMP2]], ptr @g, align 4
+; CHECK-NEXT: store i32 [[DOTLOBIT_NOT_]], ptr @i, align 4
+; CHECK-NEXT: [[TMP:%.*]] = trunc i32 [[LSR_IV_NEXT2]] to i8
+; CHECK-NEXT: store i8 [[TMP]], ptr @h, align 1
+; CHECK-NEXT: store i32 [[LSR_IV_NEXT]], ptr @e, align 4
+; CHECK-NEXT: [[CALL:%.*]] = tail call i32 (ptr, ...) @printf(ptr @.str, i32 [[LSR_IV_NEXT]]) #[[ATTR2:[0-9]+]]
+; CHECK-NEXT: ret i32 0
+;
entry:
store i8 0, ptr @h, align 1
%0 = load i32, ptr @j, align 4
diff --git a/llvm/test/Transforms/LoopStrengthReduce/two-combinations-bug.ll b/llvm/test/Transforms/LoopStrengthReduce/two-combinations-bug.ll
index 37e2f68e89a6f..ec93372c46d48 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/two-combinations-bug.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/two-combinations-bug.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
; RUN: opt < %s -loop-reduce -lsr-setupcost-depth-limit=1 -S | FileCheck %s
; This test is adapted from the n-body test of the LLVM test-suite: A bug in
@@ -12,18 +13,29 @@ target triple = "x86_64-unknown-linux-gnu"
; Function Attrs: nounwind uwtable
define dso_local void @advance(i32 %nbodies, ptr nocapture %bodies) local_unnamed_addr #0 {
-; CHECK-LABEL: @advance(
-; CHECK: for.cond.loopexit:
-; CHECK: [[LSR_IV_NEXT:%.*]] = add i64 [[LSR_IV:%.*]], -1
-; CHECK: br label %for.body
-; CHECK: for.body:
-; CHECK: [[LSR_IV]] = phi i64 [ [[LSR_IV_NEXT]]
-; CHECK: br label %for.body3
-; CHECK: for.body3:
-; CHECK: [[LSR_IV1:%.*]] = phi i64 [ [[LSR_IV_NEXT2:%.*]], %for.body3 ], [ [[LSR_IV]], %for.body ]
-; CHECK: [[LSR_IV_NEXT2]] = add i64 [[LSR_IV1]], -1
-; CHECK: [[EXITCOND:%.*]] = icmp eq i64 [[LSR_IV_NEXT2]], 0
-; CHECK: br i1 [[EXITCOND]], label %for.cond.loopexit, label %for.body3
+; CHECK-LABEL: define dso_local void @advance(
+; CHECK-SAME: i32 [[NBODIES:%.*]], ptr captures(none) [[BODIES:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[NBODIES]] to i64
+; CHECK-NEXT: [[TMP0:%.*]] = add nsw i64 [[WIDE_TRIP_COUNT]], -1
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[BODIES]], i64 72
+; CHECK-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK: [[FOR_COND_LOOPEXIT:.*]]:
+; CHECK-NEXT: [[LSR_IV_NEXT:%.*]] = add nsw i64 [[LSR_IV:%.*]], -1
+; CHECK-NEXT: [[SCEVGEP4:%.*]] = getelementptr i8, ptr [[LSR_IV3:%.*]], i64 56
+; CHECK-NEXT: br label %[[FOR_BODY]]
+; CHECK: [[FOR_BODY]]:
+; CHECK-NEXT: [[LSR_IV3]] = phi ptr [ [[SCEVGEP4]], %[[FOR_COND_LOOPEXIT]] ], [ [[SCEVGEP]], %[[ENTRY]] ]
+; CHECK-NEXT: [[LSR_IV]] = phi i64 [ [[LSR_IV_NEXT]], %[[FOR_COND_LOOPEXIT]] ], [ [[TMP0]], %[[ENTRY]] ]
+; CHECK-NEXT: br label %[[FOR_BODY3:.*]]
+; CHECK: [[FOR_BODY3]]:
+; CHECK-NEXT: [[LSR_IV5:%.*]] = phi ptr [ [[SCEVGEP6:%.*]], %[[FOR_BODY3]] ], [ [[LSR_IV3]], %[[FOR_BODY]] ]
+; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i64 [ [[LSR_IV_NEXT2:%.*]], %[[FOR_BODY3]] ], [ [[LSR_IV]], %[[FOR_BODY]] ]
+; CHECK-NEXT: [[TMP:%.*]] = load double, ptr [[LSR_IV5]], align 8, !tbaa [[DOUBLE_TBAA0:![0-9]+]]
+; CHECK-NEXT: [[LSR_IV_NEXT2]] = add i64 [[LSR_IV1]], -1
+; CHECK-NEXT: [[SCEVGEP6]] = getelementptr i8, ptr [[LSR_IV5]], i64 56
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[LSR_IV_NEXT2]], 0
+; CHECK-NEXT: br i1 [[EXITCOND]], label %[[FOR_COND_LOOPEXIT]], label %[[FOR_BODY3]]
;
entry:
%wide.trip.count = zext i32 %nbodies to i64
diff --git a/llvm/test/Transforms/LoopUnroll/AArch64/apple-unrolling.ll b/llvm/test/Transforms/LoopUnroll/AArch64/apple-unrolling.ll
index 10b22974080dc..5d865d0528d2c 100644
--- a/llvm/test/Transforms/LoopUnroll/AArch64/apple-unrolling.ll
+++ b/llvm/test/Transforms/LoopUnroll/AArch64/apple-unrolling.ll
@@ -71,7 +71,7 @@ define void @small_load_store_loop(ptr %src, ptr %dst, i64 %N, i64 %scale) {
; APPLE-NEXT: [[GEP_DST_7:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV_NEXT_6]]
; APPLE-NEXT: store float [[L_7]], ptr [[GEP_DST_7]], align 4
; APPLE-NEXT: [[IV_NEXT_7]] = add nuw nsw i64 [[IV]], 8
-; APPLE-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; APPLE-NEXT: [[NITER_NEXT_7]] = add nsw i64 [[NITER]], 8
; APPLE-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; APPLE-NEXT: br i1 [[NITER_NCMP_7]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]]
; APPLE: [[EXIT_UNR_LCSSA]]:
@@ -126,7 +126,7 @@ define void @small_load_store_loop(ptr %src, ptr %dst, i64 %N, i64 %scale) {
; OTHER-NEXT: [[GEP_DST_1:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV_NEXT]]
; OTHER-NEXT: store float [[L_1]], ptr [[GEP_DST_1]], align 4
; OTHER-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; OTHER-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; OTHER-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; OTHER-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; OTHER-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]]
; OTHER: [[EXIT_UNR_LCSSA]]:
@@ -194,7 +194,7 @@ define void @load_op_store_loop(ptr %src, ptr %dst, i64 %N, i64 %scale, float %k
; APPLE-NEXT: [[GEP_DST_1:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV_NEXT]]
; APPLE-NEXT: store float [[O_1]], ptr [[GEP_DST_1]], align 4
; APPLE-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; APPLE-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; APPLE-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; APPLE-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; APPLE-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]]
; APPLE: [[EXIT_UNR_LCSSA]]:
@@ -244,7 +244,7 @@ define void @load_op_store_loop(ptr %src, ptr %dst, i64 %N, i64 %scale, float %k
; OTHER-NEXT: [[GEP_DST_1:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV_NEXT]]
; OTHER-NEXT: store float [[O_1]], ptr [[GEP_DST_1]], align 4
; OTHER-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; OTHER-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; OTHER-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; OTHER-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; OTHER-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]]
; OTHER: [[EXIT_UNR_LCSSA]]:
@@ -313,7 +313,7 @@ define void @load_op_store_loop_multiblock(ptr %src, ptr %dst, i64 %N, i64 %scal
; APPLE: [[EXIT]]:
; APPLE-NEXT: ret void
;
-; ; OTHER-LABEL: define void @load_op_store_loop_multiblock(
+; OTHER-LABEL: define void @load_op_store_loop_multiblock(
; OTHER-SAME: ptr [[SRC:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]], i64 [[SCALE:%.*]], float [[K:%.*]]) #[[ATTR0]] {
; OTHER-NEXT: [[ENTRY:.*]]:
; OTHER-NEXT: br label %[[LOOP:.*]]
@@ -321,12 +321,12 @@ define void @load_op_store_loop_multiblock(ptr %src, ptr %dst, i64 %N, i64 %scal
; OTHER-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOPCONT:.*]] ]
; OTHER-NEXT: [[SCALED_IV:%.*]] = mul nuw nsw i64 [[IV]], [[SCALE]]
; OTHER-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds float, ptr [[SRC]], i64 [[SCALED_IV]]
-; OTHER-NEXT: [[L:%.*]] = load float, ptr [[GEP_SRC]], align 4
+; OTHER-NEXT: [[L1:%.*]] = load float, ptr [[GEP_SRC]], align 4
; OTHER-NEXT: [[AND:%.*]] = and i64 [[IV]], 1
; OTHER-NEXT: [[ODD:%.*]] = icmp eq i64 [[AND]], 1
; OTHER-NEXT: br i1 [[ODD]], label %[[LOOPODD:.*]], label %[[LOOPCONT]]
; OTHER: [[LOOPCONT]]:
-; OTHER-NEXT: [[D:%.*]] = phi float [ [[L2:%.*]], %[[LOOPODD]] ], [ [[L]], %[[LOOP]] ]
+; OTHER-NEXT: [[D:%.*]] = phi float [ [[L2:%.*]], %[[LOOPODD]] ], [ [[L1]], %[[LOOP]] ]
; OTHER-NEXT: [[O:%.*]] = fadd float [[D]], [[K]]
; OTHER-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV]]
; OTHER-NEXT: store float [[O]], ptr [[GEP_DST]], align 4
@@ -334,7 +334,7 @@ define void @load_op_store_loop_multiblock(ptr %src, ptr %dst, i64 %N, i64 %scal
; OTHER-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; OTHER-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]
; OTHER: [[LOOPODD]]:
-; OTHER-NEXT: [[L2]] = fneg float [[L]]
+; OTHER-NEXT: [[L2]] = fneg float [[L1]]
; OTHER-NEXT: br label %[[LOOPCONT]]
; OTHER: [[EXIT]]:
; OTHER-NEXT: ret void
@@ -579,7 +579,7 @@ define void @early_continue_dep_on_load_large(ptr %p.1, ptr %p.2, i64 %N, i32 %x
; APPLE-NEXT: br label %[[LOOP_LATCH_3]]
; APPLE: [[LOOP_LATCH_3]]:
; APPLE-NEXT: [[IV_NEXT_3]] = add nuw nsw i64 [[IV]], 4
-; APPLE-NEXT: [[NITER_NEXT_3]] = add i64 [[NITER]], 4
+; APPLE-NEXT: [[NITER_NEXT_3]] = add nsw i64 [[NITER]], 4
; APPLE-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i64 [[NITER_NEXT_3]], [[UNROLL_ITER]]
; APPLE-NEXT: br i1 [[NITER_NCMP_3]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP_HEADER]]
; APPLE: [[EXIT_UNR_LCSSA]]:
@@ -1062,7 +1062,7 @@ define i32 @test_add_reduction_runtime(ptr %a, i64 noundef %n) {
; APPLE-NEXT: [[TMP5:%.*]] = load i32, ptr [[GEP_A_3]], align 2
; APPLE-NEXT: [[RDX_NEXT_3]] = add i32 [[RDX_3]], [[TMP5]]
; APPLE-NEXT: [[IV_NEXT_3]] = add nuw nsw i64 [[IV]], 4
-; APPLE-NEXT: [[NITER_NEXT_3]] = add nuw i64 [[NITER]], 4
+; APPLE-NEXT: [[NITER_NEXT_3]] = add nuw nsw i64 [[NITER]], 4
; APPLE-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i64 [[NITER_NEXT_3]], [[UNROLL_ITER]]
; APPLE-NEXT: br i1 [[NITER_NCMP_3]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]]
; APPLE: [[EXIT_UNR_LCSSA]]:
@@ -1129,7 +1129,7 @@ define i32 @test_add_reduction_runtime(ptr %a, i64 noundef %n) {
; OTHER-NEXT: [[TMP5:%.*]] = load i32, ptr [[GEP_A_3]], align 2
; OTHER-NEXT: [[RDX_NEXT_3]] = add nuw nsw i32 [[RDX_NEXT_2]], [[TMP5]]
; OTHER-NEXT: [[IV_NEXT_3]] = add nuw nsw i64 [[IV]], 4
-; OTHER-NEXT: [[NITER_NEXT_3]] = add i64 [[NITER]], 4
+; OTHER-NEXT: [[NITER_NEXT_3]] = add nsw i64 [[NITER]], 4
; OTHER-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i64 [[NITER_NEXT_3]], [[UNROLL_ITER]]
; OTHER-NEXT: br i1 [[NITER_NCMP_3]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]]
; OTHER: [[EXIT_UNR_LCSSA]]:
diff --git a/llvm/test/Transforms/LoopUnroll/AArch64/runtime-unroll-generic.ll b/llvm/test/Transforms/LoopUnroll/AArch64/runtime-unroll-generic.ll
index 3411c997747d9..228e7dc3fd595 100644
--- a/llvm/test/Transforms/LoopUnroll/AArch64/runtime-unroll-generic.ll
+++ b/llvm/test/Transforms/LoopUnroll/AArch64/runtime-unroll-generic.ll
@@ -67,7 +67,7 @@ define void @runtime_unroll_generic(i32 %arg_0, ptr %arg_1, ptr %arg_2, ptr %arg
; CHECK-A55-NEXT: [[ADD21_3:%.*]] = add nsw i32 [[MUL16_3]], [[TMP12]]
; CHECK-A55-NEXT: store i32 [[ADD21_3]], ptr [[ARRAYIDX20_3]], align 4
; CHECK-A55-NEXT: [[INDVARS_IV_NEXT_3]] = add nuw nsw i64 [[INDVARS_IV]], 4
-; CHECK-A55-NEXT: [[NITER_NEXT_3]] = add i64 [[NITER]], 4
+; CHECK-A55-NEXT: [[NITER_NEXT_3]] = add nuw nsw i64 [[NITER]], 4
; CHECK-A55-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i64 [[NITER_NEXT_3]], [[UNROLL_ITER]]
; CHECK-A55-NEXT: br i1 [[NITER_NCMP_3]], label [[FOR_END_LOOPEXIT_UNR_LCSSA1:%.*]], label [[FOR_BODY6]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK-A55: for.end.loopexit.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/AArch64/vector.ll b/llvm/test/Transforms/LoopUnroll/AArch64/vector.ll
index 2bafa08a81c38..ab39b17de1e83 100644
--- a/llvm/test/Transforms/LoopUnroll/AArch64/vector.ll
+++ b/llvm/test/Transforms/LoopUnroll/AArch64/vector.ll
@@ -64,7 +64,7 @@ define void @reverse(ptr %dst, ptr %src, i64 %len) {
; APPLE-NEXT: [[ARRAYIDX2_7:%.*]] = getelementptr inbounds nuw <4 x float>, ptr [[DST]], i64 [[IV_NEXT_6]]
; APPLE-NEXT: store <4 x float> [[TMP17]], ptr [[ARRAYIDX2_7]], align 16
; APPLE-NEXT: [[IV_NEXT_7]] = add nuw nsw i64 [[IV]], 8
-; APPLE-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; APPLE-NEXT: [[NITER_NEXT_7]] = add nsw i64 [[NITER]], 8
; APPLE-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; APPLE-NEXT: br i1 [[NITER_NCMP_7]], label %[[EXIT_UNR_LCSSA:.*]], label %[[FOR_BODY]]
; APPLE: [[EXIT_UNR_LCSSA]]:
@@ -131,7 +131,7 @@ define void @reverse(ptr %dst, ptr %src, i64 %len) {
; CORTEXA55-NEXT: [[ARRAYIDX2_3:%.*]] = getelementptr inbounds nuw <4 x float>, ptr [[DST]], i64 [[IV_NEXT_2]]
; CORTEXA55-NEXT: store <4 x float> [[TMP9]], ptr [[ARRAYIDX2_3]], align 16
; CORTEXA55-NEXT: [[IV_NEXT_3]] = add nuw nsw i64 [[IV]], 4
-; CORTEXA55-NEXT: [[NITER_NEXT_3]] = add i64 [[NITER]], 4
+; CORTEXA55-NEXT: [[NITER_NEXT_3]] = add nsw i64 [[NITER]], 4
; CORTEXA55-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i64 [[NITER_NEXT_3]], [[UNROLL_ITER]]
; CORTEXA55-NEXT: br i1 [[NITER_NCMP_3]], label %[[EXIT_UNR_LCSSA:.*]], label %[[FOR_BODY]]
; CORTEXA55: [[EXIT_UNR_LCSSA]]:
diff --git a/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-convergent-uniform-tripcount.ll b/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-convergent-uniform-tripcount.ll
index d904fba1402d4..76d634a025729 100644
--- a/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-convergent-uniform-tripcount.ll
+++ b/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-convergent-uniform-tripcount.ll
@@ -77,8 +77,8 @@ define amdgpu_kernel void @runtime_unroll_uniform_trip_count(ptr addrspace(1) no
; CHECK-NEXT: call void @llvm.amdgcn.s.barrier() #4
; CHECK-NEXT: %add.7 = add i32 %load.7, %add.6
; CHECK-NEXT: store i32 %add.7, ptr addrspace(1) %arrayidx.out.7, align 4
-; CHECK-NEXT: %indvars.iv.next.7 = add i32 %indvars.iv, 8
-; CHECK-NEXT: %niter.next.7 = add i32 %niter, 8
+; CHECK-NEXT: %indvars.iv.next.7 = add nsw i32 %indvars.iv, 8
+; CHECK-NEXT: %niter.next.7 = add nsw i32 %niter, 8
; CHECK-NEXT: %niter.ncmp.7 = icmp eq i32 %niter.next.7, %unroll_iter
; CHECK-NEXT: br i1 %niter.ncmp.7, label %for.end.unr-lcssa, label %for.body
; CHECK: for.end.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/ARM/loop-unrolling.ll b/llvm/test/Transforms/LoopUnroll/ARM/loop-unrolling.ll
index c00f744ac3ddf..8060501fc5dd9 100644
--- a/llvm/test/Transforms/LoopUnroll/ARM/loop-unrolling.ll
+++ b/llvm/test/Transforms/LoopUnroll/ARM/loop-unrolling.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -mtriple=armv7 -mcpu=cortex-a57 -passes=loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-NOUNROLL
; RUN: opt -mtriple=thumbv7 -mcpu=cortex-a57 -passes=loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-NOUNROLL
; RUN: opt -mtriple=thumbv7 -mcpu=cortex-a72 -passes=loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-NOUNROLL
@@ -5,40 +6,177 @@
; RUN: opt -mtriple=thumbv8m.main -mcpu=cortex-m33 -passes=loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL
; RUN: opt -mtriple=thumbv7em -mcpu=cortex-m7 -passes=loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL
-; CHECK-LABEL: partial
define arm_aapcs_vfpcc void @partial(ptr nocapture %C, ptr nocapture readonly %A, ptr nocapture readonly %B) local_unnamed_addr #0 {
+; CHECK-NOUNROLL-LABEL: define arm_aapcs_vfpcc void @partial(
+; CHECK-NOUNROLL-SAME: ptr captures(none) [[C:%.*]], ptr readonly captures(none) [[A:%.*]], ptr readonly captures(none) [[B:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+; CHECK-NOUNROLL-NEXT: [[ENTRY:.*]]:
+; CHECK-NOUNROLL-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-NOUNROLL: [[FOR_BODY]]:
+; CHECK-NOUNROLL-NEXT: [[I_08:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[INC_1:%.*]], %[[FOR_BODY]] ]
+; CHECK-NOUNROLL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[I_08]]
+; CHECK-NOUNROLL-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+; CHECK-NOUNROLL-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[I_08]]
+; CHECK-NOUNROLL-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4
+; CHECK-NOUNROLL-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], [[TMP0]]
+; CHECK-NOUNROLL-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[I_08]]
+; CHECK-NOUNROLL-NEXT: store i32 [[MUL]], ptr [[ARRAYIDX2]], align 4
+; CHECK-NOUNROLL-NEXT: [[INC:%.*]] = add nuw nsw i32 [[I_08]], 1
+; CHECK-NOUNROLL-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INC]]
+; CHECK-NOUNROLL-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4
+; CHECK-NOUNROLL-NEXT: [[ARRAYIDX1_1:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[INC]]
+; CHECK-NOUNROLL-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX1_1]], align 4
+; CHECK-NOUNROLL-NEXT: [[MUL_1:%.*]] = mul nsw i32 [[TMP3]], [[TMP2]]
+; CHECK-NOUNROLL-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[INC]]
+; CHECK-NOUNROLL-NEXT: store i32 [[MUL_1]], ptr [[ARRAYIDX2_1]], align 4
+; CHECK-NOUNROLL-NEXT: [[INC_1]] = add nuw nsw i32 [[I_08]], 2
+; CHECK-NOUNROLL-NEXT: [[EXITCOND_1:%.*]] = icmp eq i32 [[INC_1]], 1024
+; CHECK-NOUNROLL-NEXT: br i1 [[EXITCOND_1]], label %[[FOR_COND_CLEANUP:.*]], label %[[FOR_BODY]]
+; CHECK-NOUNROLL: [[FOR_COND_CLEANUP]]:
+; CHECK-NOUNROLL-NEXT: ret void
+;
+; CHECK-UNROLL-LABEL: define arm_aapcs_vfpcc void @partial(
+; CHECK-UNROLL-SAME: ptr captures(none) [[C:%.*]], ptr readonly captures(none) [[A:%.*]], ptr readonly captures(none) [[B:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+; CHECK-UNROLL-NEXT: [[ENTRY:.*]]:
+; CHECK-UNROLL-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-UNROLL: [[FOR_BODY]]:
+; CHECK-UNROLL-NEXT: [[I_08:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[INC_15:%.*]], %[[FOR_BODY]] ]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[I_08]]
+; CHECK-UNROLL-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[I_08]]
+; CHECK-UNROLL-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4
+; CHECK-UNROLL-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], [[TMP0]]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[I_08]]
+; CHECK-UNROLL-NEXT: store i32 [[MUL]], ptr [[ARRAYIDX2]], align 4
+; CHECK-UNROLL-NEXT: [[INC:%.*]] = add nuw nsw i32 [[I_08]], 1
+; CHECK-UNROLL-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INC]]
+; CHECK-UNROLL-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1_1:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[INC]]
+; CHECK-UNROLL-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX1_1]], align 4
+; CHECK-UNROLL-NEXT: [[MUL_1:%.*]] = mul nsw i32 [[TMP3]], [[TMP2]]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[INC]]
+; CHECK-UNROLL-NEXT: store i32 [[MUL_1]], ptr [[ARRAYIDX2_1]], align 4
+; CHECK-UNROLL-NEXT: [[INC_1:%.*]] = add nuw nsw i32 [[I_08]], 2
+; CHECK-UNROLL-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INC_1]]
+; CHECK-UNROLL-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1_2:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[INC_1]]
+; CHECK-UNROLL-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX1_2]], align 4
+; CHECK-UNROLL-NEXT: [[MUL_2:%.*]] = mul nsw i32 [[TMP5]], [[TMP4]]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[INC_1]]
+; CHECK-UNROLL-NEXT: store i32 [[MUL_2]], ptr [[ARRAYIDX2_2]], align 4
+; CHECK-UNROLL-NEXT: [[INC_2:%.*]] = add nuw nsw i32 [[I_08]], 3
+; CHECK-UNROLL-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INC_2]]
+; CHECK-UNROLL-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1_3:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[INC_2]]
+; CHECK-UNROLL-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX1_3]], align 4
+; CHECK-UNROLL-NEXT: [[MUL_3:%.*]] = mul nsw i32 [[TMP7]], [[TMP6]]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2_3:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[INC_2]]
+; CHECK-UNROLL-NEXT: store i32 [[MUL_3]], ptr [[ARRAYIDX2_3]], align 4
+; CHECK-UNROLL-NEXT: [[INC_3:%.*]] = add nuw nsw i32 [[I_08]], 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INC_3]]
+; CHECK-UNROLL-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX_4]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1_4:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[INC_3]]
+; CHECK-UNROLL-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX1_4]], align 4
+; CHECK-UNROLL-NEXT: [[MUL_4:%.*]] = mul nsw i32 [[TMP9]], [[TMP8]]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2_4:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[INC_3]]
+; CHECK-UNROLL-NEXT: store i32 [[MUL_4]], ptr [[ARRAYIDX2_4]], align 4
+; CHECK-UNROLL-NEXT: [[INC_4:%.*]] = add nuw nsw i32 [[I_08]], 5
+; CHECK-UNROLL-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INC_4]]
+; CHECK-UNROLL-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_5]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1_5:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[INC_4]]
+; CHECK-UNROLL-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX1_5]], align 4
+; CHECK-UNROLL-NEXT: [[MUL_5:%.*]] = mul nsw i32 [[TMP11]], [[TMP10]]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2_5:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[INC_4]]
+; CHECK-UNROLL-NEXT: store i32 [[MUL_5]], ptr [[ARRAYIDX2_5]], align 4
+; CHECK-UNROLL-NEXT: [[INC_5:%.*]] = add nuw nsw i32 [[I_08]], 6
+; CHECK-UNROLL-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INC_5]]
+; CHECK-UNROLL-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX_6]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1_6:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[INC_5]]
+; CHECK-UNROLL-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARRAYIDX1_6]], align 4
+; CHECK-UNROLL-NEXT: [[MUL_6:%.*]] = mul nsw i32 [[TMP13]], [[TMP12]]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2_6:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[INC_5]]
+; CHECK-UNROLL-NEXT: store i32 [[MUL_6]], ptr [[ARRAYIDX2_6]], align 4
+; CHECK-UNROLL-NEXT: [[INC_6:%.*]] = add nuw nsw i32 [[I_08]], 7
+; CHECK-UNROLL-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INC_6]]
+; CHECK-UNROLL-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1_7:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[INC_6]]
+; CHECK-UNROLL-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX1_7]], align 4
+; CHECK-UNROLL-NEXT: [[MUL_7:%.*]] = mul nsw i32 [[TMP15]], [[TMP14]]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2_7:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[INC_6]]
+; CHECK-UNROLL-NEXT: store i32 [[MUL_7]], ptr [[ARRAYIDX2_7]], align 4
+; CHECK-UNROLL-NEXT: [[INC_7:%.*]] = add nuw nsw i32 [[I_08]], 8
+; CHECK-UNROLL-NEXT: [[ARRAYIDX_8:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INC_7]]
+; CHECK-UNROLL-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX_8]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1_8:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[INC_7]]
+; CHECK-UNROLL-NEXT: [[TMP17:%.*]] = load i32, ptr [[ARRAYIDX1_8]], align 4
+; CHECK-UNROLL-NEXT: [[MUL_8:%.*]] = mul nsw i32 [[TMP17]], [[TMP16]]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2_8:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[INC_7]]
+; CHECK-UNROLL-NEXT: store i32 [[MUL_8]], ptr [[ARRAYIDX2_8]], align 4
+; CHECK-UNROLL-NEXT: [[INC_8:%.*]] = add nuw nsw i32 [[I_08]], 9
+; CHECK-UNROLL-NEXT: [[ARRAYIDX_9:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INC_8]]
+; CHECK-UNROLL-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX_9]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1_9:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[INC_8]]
+; CHECK-UNROLL-NEXT: [[TMP19:%.*]] = load i32, ptr [[ARRAYIDX1_9]], align 4
+; CHECK-UNROLL-NEXT: [[MUL_9:%.*]] = mul nsw i32 [[TMP19]], [[TMP18]]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2_9:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[INC_8]]
+; CHECK-UNROLL-NEXT: store i32 [[MUL_9]], ptr [[ARRAYIDX2_9]], align 4
+; CHECK-UNROLL-NEXT: [[INC_9:%.*]] = add nuw nsw i32 [[I_08]], 10
+; CHECK-UNROLL-NEXT: [[ARRAYIDX_10:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INC_9]]
+; CHECK-UNROLL-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX_10]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1_10:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[INC_9]]
+; CHECK-UNROLL-NEXT: [[TMP21:%.*]] = load i32, ptr [[ARRAYIDX1_10]], align 4
+; CHECK-UNROLL-NEXT: [[MUL_10:%.*]] = mul nsw i32 [[TMP21]], [[TMP20]]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2_10:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[INC_9]]
+; CHECK-UNROLL-NEXT: store i32 [[MUL_10]], ptr [[ARRAYIDX2_10]], align 4
+; CHECK-UNROLL-NEXT: [[INC_10:%.*]] = add nuw nsw i32 [[I_08]], 11
+; CHECK-UNROLL-NEXT: [[ARRAYIDX_11:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INC_10]]
+; CHECK-UNROLL-NEXT: [[TMP22:%.*]] = load i32, ptr [[ARRAYIDX_11]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1_11:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[INC_10]]
+; CHECK-UNROLL-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX1_11]], align 4
+; CHECK-UNROLL-NEXT: [[MUL_11:%.*]] = mul nsw i32 [[TMP23]], [[TMP22]]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2_11:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[INC_10]]
+; CHECK-UNROLL-NEXT: store i32 [[MUL_11]], ptr [[ARRAYIDX2_11]], align 4
+; CHECK-UNROLL-NEXT: [[INC_11:%.*]] = add nuw nsw i32 [[I_08]], 12
+; CHECK-UNROLL-NEXT: [[ARRAYIDX_12:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INC_11]]
+; CHECK-UNROLL-NEXT: [[TMP24:%.*]] = load i32, ptr [[ARRAYIDX_12]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1_12:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[INC_11]]
+; CHECK-UNROLL-NEXT: [[TMP25:%.*]] = load i32, ptr [[ARRAYIDX1_12]], align 4
+; CHECK-UNROLL-NEXT: [[MUL_12:%.*]] = mul nsw i32 [[TMP25]], [[TMP24]]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2_12:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[INC_11]]
+; CHECK-UNROLL-NEXT: store i32 [[MUL_12]], ptr [[ARRAYIDX2_12]], align 4
+; CHECK-UNROLL-NEXT: [[INC_12:%.*]] = add nuw nsw i32 [[I_08]], 13
+; CHECK-UNROLL-NEXT: [[ARRAYIDX_13:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INC_12]]
+; CHECK-UNROLL-NEXT: [[TMP26:%.*]] = load i32, ptr [[ARRAYIDX_13]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1_13:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[INC_12]]
+; CHECK-UNROLL-NEXT: [[TMP27:%.*]] = load i32, ptr [[ARRAYIDX1_13]], align 4
+; CHECK-UNROLL-NEXT: [[MUL_13:%.*]] = mul nsw i32 [[TMP27]], [[TMP26]]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2_13:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[INC_12]]
+; CHECK-UNROLL-NEXT: store i32 [[MUL_13]], ptr [[ARRAYIDX2_13]], align 4
+; CHECK-UNROLL-NEXT: [[INC_13:%.*]] = add nuw nsw i32 [[I_08]], 14
+; CHECK-UNROLL-NEXT: [[ARRAYIDX_14:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INC_13]]
+; CHECK-UNROLL-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARRAYIDX_14]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1_14:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[INC_13]]
+; CHECK-UNROLL-NEXT: [[TMP29:%.*]] = load i32, ptr [[ARRAYIDX1_14]], align 4
+; CHECK-UNROLL-NEXT: [[MUL_14:%.*]] = mul nsw i32 [[TMP29]], [[TMP28]]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2_14:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[INC_13]]
+; CHECK-UNROLL-NEXT: store i32 [[MUL_14]], ptr [[ARRAYIDX2_14]], align 4
+; CHECK-UNROLL-NEXT: [[INC_14:%.*]] = add nuw nsw i32 [[I_08]], 15
+; CHECK-UNROLL-NEXT: [[ARRAYIDX_15:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INC_14]]
+; CHECK-UNROLL-NEXT: [[TMP30:%.*]] = load i32, ptr [[ARRAYIDX_15]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1_15:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[INC_14]]
+; CHECK-UNROLL-NEXT: [[TMP31:%.*]] = load i32, ptr [[ARRAYIDX1_15]], align 4
+; CHECK-UNROLL-NEXT: [[MUL_15:%.*]] = mul nsw i32 [[TMP31]], [[TMP30]]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2_15:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[INC_14]]
+; CHECK-UNROLL-NEXT: store i32 [[MUL_15]], ptr [[ARRAYIDX2_15]], align 4
+; CHECK-UNROLL-NEXT: [[INC_15]] = add nuw nsw i32 [[I_08]], 16
+; CHECK-UNROLL-NEXT: [[EXITCOND_15:%.*]] = icmp eq i32 [[INC_15]], 1024
+; CHECK-UNROLL-NEXT: br i1 [[EXITCOND_15]], label %[[FOR_COND_CLEANUP:.*]], label %[[FOR_BODY]]
+; CHECK-UNROLL: [[FOR_COND_CLEANUP]]:
+; CHECK-UNROLL-NEXT: ret void
+;
entry:
br label %for.body
-; CHECK-LABEL: for.body
for.body:
-
-; CHECK-NOUNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, %entry ], [ [[IV2:%[a-z.0-9]+]], %for.body ]
-; CHECK-NOUNROLL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
-; CHECK-NOUNROLL: [[IV2]] = add nuw nsw i32 [[IV0]], 2
-; CHECK-NOUNROLL: [[CMP:%[a-z.0-9]+]] = icmp eq i32 [[IV2]], 1024
-; CHECK-NOUNROLL: br i1 [[CMP]], label [[END:%[a-z.]+]], label %for.body
-
-; CHECK-UNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, %entry ], [ [[IV16:%[a-z.0-9]+]], %for.body ]
-; CHECK-UNROLL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
-; CHECK-UNROLL: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 2
-; CHECK-UNROLL: [[IV3:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 3
-; CHECK-UNROLL: [[IV4:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 4
-; CHECK-UNROLL: [[IV5:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 5
-; CHECK-UNROLL: [[IV6:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 6
-; CHECK-UNROLL: [[IV7:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 7
-; CHECK-UNROLL: [[IV8:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 8
-; CHECK-UNROLL: [[IV9:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 9
-; CHECK-UNROLL: [[IV10:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 10
-; CHECK-UNROLL: [[IV11:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 11
-; CHECK-UNROLL: [[IV12:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 12
-; CHECK-UNROLL: [[IV13:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 13
-; CHECK-UNROLL: [[IV14:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 14
-; CHECK-UNROLL: [[IV15:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 15
-; CHECK-UNROLL: [[IV16]] = add nuw nsw i32 [[IV0]], 16
-; CHECK-UNROLL: [[CMP:%[a-z.0-9]+]] = icmp eq i32 [[IV16]], 1024
-; CHECK-UNROLL: br i1 [[CMP]], label [[END:%[a-z.]+]], label %for.body
-
%i.08 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
%arrayidx = getelementptr inbounds i32, ptr %A, i32 %i.08
%0 = load i32, ptr %arrayidx, align 4
@@ -55,30 +193,168 @@ for.cond.cleanup:
ret void
}
-; CHECK-LABEL: runtime
define arm_aapcs_vfpcc void @runtime(ptr nocapture %C, ptr nocapture readonly %A, ptr nocapture readonly %B, i32 %N) local_unnamed_addr #0 {
+; CHECK-NOUNROLL-LABEL: define arm_aapcs_vfpcc void @runtime(
+; CHECK-NOUNROLL-SAME: ptr captures(none) [[C:%.*]], ptr readonly captures(none) [[A:%.*]], ptr readonly captures(none) [[B:%.*]], i32 [[N:%.*]]) local_unnamed_addr #[[ATTR0]] {
+; CHECK-NOUNROLL-NEXT: [[ENTRY:.*:]]
+; CHECK-NOUNROLL-NEXT: [[CMP8:%.*]] = icmp eq i32 [[N]], 0
+; CHECK-NOUNROLL-NEXT: br i1 [[CMP8]], label %[[FOR_COND_CLEANUP:.*]], label %[[FOR_BODY_PREHEADER:.*]]
+; CHECK-NOUNROLL: [[FOR_BODY_PREHEADER]]:
+; CHECK-NOUNROLL-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
+; CHECK-NOUNROLL-NEXT: [[XTRAITER:%.*]] = and i32 [[N]], 1
+; CHECK-NOUNROLL-NEXT: [[TMP1:%.*]] = icmp ult i32 [[TMP0]], 1
+; CHECK-NOUNROLL-NEXT: br i1 [[TMP1]], label %[[FOR_BODY_EPIL_PREHEADER:.*]], label %[[FOR_BODY_PREHEADER_NEW:.*]]
+; CHECK-NOUNROLL: [[FOR_BODY_PREHEADER_NEW]]:
+; CHECK-NOUNROLL-NEXT: [[UNROLL_ITER:%.*]] = sub i32 [[N]], [[XTRAITER]]
+; CHECK-NOUNROLL-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-NOUNROLL: [[FOR_BODY]]:
+; CHECK-NOUNROLL-NEXT: [[I_09:%.*]] = phi i32 [ 0, %[[FOR_BODY_PREHEADER_NEW]] ], [ [[INC_1:%.*]], %[[FOR_BODY]] ]
+; CHECK-NOUNROLL-NEXT: [[NITER:%.*]] = phi i32 [ 0, %[[FOR_BODY_PREHEADER_NEW]] ], [ [[NITER_NEXT_1:%.*]], %[[FOR_BODY]] ]
+; CHECK-NOUNROLL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[I_09]]
+; CHECK-NOUNROLL-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+; CHECK-NOUNROLL-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[I_09]]
+; CHECK-NOUNROLL-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4
+; CHECK-NOUNROLL-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], [[TMP2]]
+; CHECK-NOUNROLL-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[I_09]]
+; CHECK-NOUNROLL-NEXT: store i32 [[MUL]], ptr [[ARRAYIDX2]], align 4
+; CHECK-NOUNROLL-NEXT: [[INC:%.*]] = add nuw nsw i32 [[I_09]], 1
+; CHECK-NOUNROLL-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INC]]
+; CHECK-NOUNROLL-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4
+; CHECK-NOUNROLL-NEXT: [[ARRAYIDX1_1:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[INC]]
+; CHECK-NOUNROLL-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX1_1]], align 4
+; CHECK-NOUNROLL-NEXT: [[MUL_1:%.*]] = mul nsw i32 [[TMP5]], [[TMP4]]
+; CHECK-NOUNROLL-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[INC]]
+; CHECK-NOUNROLL-NEXT: store i32 [[MUL_1]], ptr [[ARRAYIDX2_1]], align 4
+; CHECK-NOUNROLL-NEXT: [[INC_1]] = add nuw nsw i32 [[I_09]], 2
+; CHECK-NOUNROLL-NEXT: [[NITER_NEXT_1]] = add nuw nsw i32 [[NITER]], 2
+; CHECK-NOUNROLL-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i32 [[NITER_NEXT_1]], [[UNROLL_ITER]]
+; CHECK-NOUNROLL-NEXT: br i1 [[NITER_NCMP_1]], label %[[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA:.*]], label %[[FOR_BODY]]
+; CHECK-NOUNROLL: [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]]:
+; CHECK-NOUNROLL-NEXT: [[I_09_UNR:%.*]] = phi i32 [ [[INC_1]], %[[FOR_BODY]] ]
+; CHECK-NOUNROLL-NEXT: [[LCMP_MOD:%.*]] = icmp ne i32 [[XTRAITER]], 0
+; CHECK-NOUNROLL-NEXT: br i1 [[LCMP_MOD]], label %[[FOR_BODY_EPIL_PREHEADER]], label %[[FOR_COND_CLEANUP_LOOPEXIT:.*]]
+; CHECK-NOUNROLL: [[FOR_BODY_EPIL_PREHEADER]]:
+; CHECK-NOUNROLL-NEXT: [[I_09_EPIL_INIT:%.*]] = phi i32 [ 0, %[[FOR_BODY_PREHEADER]] ], [ [[I_09_UNR]], %[[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]] ]
+; CHECK-NOUNROLL-NEXT: [[LCMP_MOD1:%.*]] = icmp ne i32 [[XTRAITER]], 0
+; CHECK-NOUNROLL-NEXT: call void @llvm.assume(i1 [[LCMP_MOD1]])
+; CHECK-NOUNROLL-NEXT: br label %[[FOR_BODY_EPIL:.*]]
+; CHECK-NOUNROLL: [[FOR_BODY_EPIL]]:
+; CHECK-NOUNROLL-NEXT: [[ARRAYIDX_EPIL:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[I_09_EPIL_INIT]]
+; CHECK-NOUNROLL-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX_EPIL]], align 4
+; CHECK-NOUNROLL-NEXT: [[ARRAYIDX1_EPIL:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[I_09_EPIL_INIT]]
+; CHECK-NOUNROLL-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX1_EPIL]], align 4
+; CHECK-NOUNROLL-NEXT: [[MUL_EPIL:%.*]] = mul nsw i32 [[TMP7]], [[TMP6]]
+; CHECK-NOUNROLL-NEXT: [[ARRAYIDX2_EPIL:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[I_09_EPIL_INIT]]
+; CHECK-NOUNROLL-NEXT: store i32 [[MUL_EPIL]], ptr [[ARRAYIDX2_EPIL]], align 4
+; CHECK-NOUNROLL-NEXT: br label %[[FOR_COND_CLEANUP_LOOPEXIT]]
+; CHECK-NOUNROLL: [[FOR_COND_CLEANUP_LOOPEXIT]]:
+; CHECK-NOUNROLL-NEXT: br label %[[FOR_COND_CLEANUP]]
+; CHECK-NOUNROLL: [[FOR_COND_CLEANUP]]:
+; CHECK-NOUNROLL-NEXT: ret void
+;
+; CHECK-UNROLL-LABEL: define arm_aapcs_vfpcc void @runtime(
+; CHECK-UNROLL-SAME: ptr captures(none) [[C:%.*]], ptr readonly captures(none) [[A:%.*]], ptr readonly captures(none) [[B:%.*]], i32 [[N:%.*]]) local_unnamed_addr #[[ATTR0]] {
+; CHECK-UNROLL-NEXT: [[ENTRY:.*:]]
+; CHECK-UNROLL-NEXT: [[CMP8:%.*]] = icmp eq i32 [[N]], 0
+; CHECK-UNROLL-NEXT: br i1 [[CMP8]], label %[[FOR_COND_CLEANUP:.*]], label %[[FOR_BODY_PREHEADER:.*]]
+; CHECK-UNROLL: [[FOR_BODY_PREHEADER]]:
+; CHECK-UNROLL-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
+; CHECK-UNROLL-NEXT: [[XTRAITER:%.*]] = and i32 [[N]], 3
+; CHECK-UNROLL-NEXT: [[TMP1:%.*]] = icmp ult i32 [[TMP0]], 3
+; CHECK-UNROLL-NEXT: br i1 [[TMP1]], label %[[FOR_BODY_EPIL_PREHEADER:.*]], label %[[FOR_BODY_PREHEADER_NEW:.*]]
+; CHECK-UNROLL: [[FOR_BODY_PREHEADER_NEW]]:
+; CHECK-UNROLL-NEXT: [[UNROLL_ITER:%.*]] = sub i32 [[N]], [[XTRAITER]]
+; CHECK-UNROLL-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-UNROLL: [[FOR_BODY]]:
+; CHECK-UNROLL-NEXT: [[I_09:%.*]] = phi i32 [ 0, %[[FOR_BODY_PREHEADER_NEW]] ], [ [[INC_3:%.*]], %[[FOR_BODY]] ]
+; CHECK-UNROLL-NEXT: [[NITER:%.*]] = phi i32 [ 0, %[[FOR_BODY_PREHEADER_NEW]] ], [ [[NITER_NEXT_3:%.*]], %[[FOR_BODY]] ]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[I_09]]
+; CHECK-UNROLL-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[I_09]]
+; CHECK-UNROLL-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4
+; CHECK-UNROLL-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], [[TMP2]]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[I_09]]
+; CHECK-UNROLL-NEXT: store i32 [[MUL]], ptr [[ARRAYIDX2]], align 4
+; CHECK-UNROLL-NEXT: [[INC:%.*]] = add nuw nsw i32 [[I_09]], 1
+; CHECK-UNROLL-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INC]]
+; CHECK-UNROLL-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1_1:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[INC]]
+; CHECK-UNROLL-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX1_1]], align 4
+; CHECK-UNROLL-NEXT: [[MUL_1:%.*]] = mul nsw i32 [[TMP5]], [[TMP4]]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[INC]]
+; CHECK-UNROLL-NEXT: store i32 [[MUL_1]], ptr [[ARRAYIDX2_1]], align 4
+; CHECK-UNROLL-NEXT: [[INC_1:%.*]] = add nuw nsw i32 [[I_09]], 2
+; CHECK-UNROLL-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INC_1]]
+; CHECK-UNROLL-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1_2:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[INC_1]]
+; CHECK-UNROLL-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX1_2]], align 4
+; CHECK-UNROLL-NEXT: [[MUL_2:%.*]] = mul nsw i32 [[TMP7]], [[TMP6]]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[INC_1]]
+; CHECK-UNROLL-NEXT: store i32 [[MUL_2]], ptr [[ARRAYIDX2_2]], align 4
+; CHECK-UNROLL-NEXT: [[INC_2:%.*]] = add nuw nsw i32 [[I_09]], 3
+; CHECK-UNROLL-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INC_2]]
+; CHECK-UNROLL-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1_3:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[INC_2]]
+; CHECK-UNROLL-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX1_3]], align 4
+; CHECK-UNROLL-NEXT: [[MUL_3:%.*]] = mul nsw i32 [[TMP9]], [[TMP8]]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2_3:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[INC_2]]
+; CHECK-UNROLL-NEXT: store i32 [[MUL_3]], ptr [[ARRAYIDX2_3]], align 4
+; CHECK-UNROLL-NEXT: [[INC_3]] = add nuw nsw i32 [[I_09]], 4
+; CHECK-UNROLL-NEXT: [[NITER_NEXT_3]] = add nuw nsw i32 [[NITER]], 4
+; CHECK-UNROLL-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i32 [[NITER_NEXT_3]], [[UNROLL_ITER]]
+; CHECK-UNROLL-NEXT: br i1 [[NITER_NCMP_3]], label %[[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA:.*]], label %[[FOR_BODY]]
+; CHECK-UNROLL: [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]]:
+; CHECK-UNROLL-NEXT: [[I_09_UNR:%.*]] = phi i32 [ [[INC_3]], %[[FOR_BODY]] ]
+; CHECK-UNROLL-NEXT: [[LCMP_MOD:%.*]] = icmp ne i32 [[XTRAITER]], 0
+; CHECK-UNROLL-NEXT: br i1 [[LCMP_MOD]], label %[[FOR_BODY_EPIL_PREHEADER]], label %[[FOR_COND_CLEANUP_LOOPEXIT:.*]]
+; CHECK-UNROLL: [[FOR_BODY_EPIL_PREHEADER]]:
+; CHECK-UNROLL-NEXT: [[I_09_EPIL_INIT:%.*]] = phi i32 [ 0, %[[FOR_BODY_PREHEADER]] ], [ [[I_09_UNR]], %[[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]] ]
+; CHECK-UNROLL-NEXT: [[LCMP_MOD1:%.*]] = icmp ne i32 [[XTRAITER]], 0
+; CHECK-UNROLL-NEXT: call void @llvm.assume(i1 [[LCMP_MOD1]])
+; CHECK-UNROLL-NEXT: br label %[[FOR_BODY_EPIL:.*]]
+; CHECK-UNROLL: [[FOR_BODY_EPIL]]:
+; CHECK-UNROLL-NEXT: [[ARRAYIDX_EPIL:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[I_09_EPIL_INIT]]
+; CHECK-UNROLL-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_EPIL]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1_EPIL:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[I_09_EPIL_INIT]]
+; CHECK-UNROLL-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX1_EPIL]], align 4
+; CHECK-UNROLL-NEXT: [[MUL_EPIL:%.*]] = mul nsw i32 [[TMP11]], [[TMP10]]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2_EPIL:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[I_09_EPIL_INIT]]
+; CHECK-UNROLL-NEXT: store i32 [[MUL_EPIL]], ptr [[ARRAYIDX2_EPIL]], align 4
+; CHECK-UNROLL-NEXT: [[INC_EPIL:%.*]] = add nuw i32 [[I_09_EPIL_INIT]], 1
+; CHECK-UNROLL-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i32 1, [[XTRAITER]]
+; CHECK-UNROLL-NEXT: br i1 [[EPIL_ITER_CMP]], label %[[FOR_BODY_EPIL_1:.*]], label %[[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA:.*]]
+; CHECK-UNROLL: [[FOR_BODY_EPIL_1]]:
+; CHECK-UNROLL-NEXT: [[ARRAYIDX_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INC_EPIL]]
+; CHECK-UNROLL-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX_EPIL_1]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[INC_EPIL]]
+; CHECK-UNROLL-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARRAYIDX1_EPIL_1]], align 4
+; CHECK-UNROLL-NEXT: [[MUL_EPIL_1:%.*]] = mul nsw i32 [[TMP13]], [[TMP12]]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[INC_EPIL]]
+; CHECK-UNROLL-NEXT: store i32 [[MUL_EPIL_1]], ptr [[ARRAYIDX2_EPIL_1]], align 4
+; CHECK-UNROLL-NEXT: [[INC_EPIL_1:%.*]] = add nuw i32 [[I_09_EPIL_INIT]], 2
+; CHECK-UNROLL-NEXT: [[EPIL_ITER_CMP_1:%.*]] = icmp ne i32 2, [[XTRAITER]]
+; CHECK-UNROLL-NEXT: br i1 [[EPIL_ITER_CMP_1]], label %[[FOR_BODY_EPIL_2:.*]], label %[[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA]]
+; CHECK-UNROLL: [[FOR_BODY_EPIL_2]]:
+; CHECK-UNROLL-NEXT: [[ARRAYIDX_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INC_EPIL_1]]
+; CHECK-UNROLL-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX_EPIL_2]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[INC_EPIL_1]]
+; CHECK-UNROLL-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX1_EPIL_2]], align 4
+; CHECK-UNROLL-NEXT: [[MUL_EPIL_2:%.*]] = mul nsw i32 [[TMP15]], [[TMP14]]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[INC_EPIL_1]]
+; CHECK-UNROLL-NEXT: store i32 [[MUL_EPIL_2]], ptr [[ARRAYIDX2_EPIL_2]], align 4
+; CHECK-UNROLL-NEXT: br label %[[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA]]
+; CHECK-UNROLL: [[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA]]:
+; CHECK-UNROLL-NEXT: br label %[[FOR_COND_CLEANUP_LOOPEXIT]]
+; CHECK-UNROLL: [[FOR_COND_CLEANUP_LOOPEXIT]]:
+; CHECK-UNROLL-NEXT: br label %[[FOR_COND_CLEANUP]]
+; CHECK-UNROLL: [[FOR_COND_CLEANUP]]:
+; CHECK-UNROLL-NEXT: ret void
+;
entry:
%cmp8 = icmp eq i32 %N, 0
br i1 %cmp8, label %for.cond.cleanup, label %for.body
-; CHECK-LABEL: for.body
for.body:
-; CHECK-NOUNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, [[PRE:%[a-z.0-9]+]] ], [ [[IV2:%[a-z.0-9]+]], %for.body ]
-; CHECK-NOUNROLL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
-; CHECK-NOUNROLL: [[IV2]] = add nuw i32 [[IV0]], 2
-; CHECK-NOUNROLL: br
-
-; CHECK-UNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, [[PRE:%[a-z.0-9]+]] ], [ [[IV4:%[a-z.0-9]+]], %for.body ]
-; CHECK-UNROLL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
-; CHECK-UNROLL: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 2
-; CHECK-UNROLL: [[IV3:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 3
-; CHECK-UNROLL: [[IV4]] = add nuw i32 [[IV0]], 4
-; CHECK-UNROLL: br
-
-; CHECK-UNROLL: for.body.epil:
-; CHECK-UNROLL: for.body.epil.1:
-; CHECK-UNROLL: for.body.epil.2:
-
%i.09 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
%arrayidx = getelementptr inbounds i32, ptr %A, i32 %i.09
%0 = load i32, ptr %arrayidx, align 4
@@ -95,8 +371,44 @@ for.cond.cleanup:
ret void
}
-; CHECK-LABEL: nested_runtime
define arm_aapcs_vfpcc void @nested_runtime(ptr nocapture %C, ptr nocapture readonly %A, ptr nocapture readonly %B, i32 %N) local_unnamed_addr #0 {
+; CHECK-NOUNROLL-LABEL: define arm_aapcs_vfpcc void @nested_runtime(
+; CHECK-NOUNROLL-SAME: ptr captures(none) [[C:%.*]], ptr readonly captures(none) [[A:%.*]], ptr readonly captures(none) [[B:%.*]], i32 [[N:%.*]]) local_unnamed_addr #[[ATTR0]] {
+; CHECK-NOUNROLL-NEXT: [[ENTRY:.*:]]
+; CHECK-NOUNROLL-NEXT: [[CMP25:%.*]] = icmp eq i32 [[N]], 0
+; CHECK-NOUNROLL-NEXT: br i1 [[CMP25]], label %[[FOR_COND_CLEANUP:.*]], label %[[FOR_BODY4_LR_PH_PREHEADER:.*]]
+; CHECK-NOUNROLL: [[FOR_BODY4_LR_PH_PREHEADER]]:
+; CHECK-NOUNROLL-NEXT: br label %[[FOR_BODY4_LR_PH:.*]]
+; CHECK-NOUNROLL: [[FOR_BODY4_LR_PH]]:
+; CHECK-NOUNROLL-NEXT: [[H_026:%.*]] = phi i32 [ [[INC11:%.*]], %[[FOR_COND_CLEANUP3:.*]] ], [ 0, %[[FOR_BODY4_LR_PH_PREHEADER]] ]
+; CHECK-NOUNROLL-NEXT: [[MUL:%.*]] = mul i32 [[H_026]], [[N]]
+; CHECK-NOUNROLL-NEXT: br label %[[FOR_BODY4:.*]]
+; CHECK-NOUNROLL: [[FOR_COND_CLEANUP_LOOPEXIT:.*]]:
+; CHECK-NOUNROLL-NEXT: br label %[[FOR_COND_CLEANUP]]
+; CHECK-NOUNROLL: [[FOR_COND_CLEANUP]]:
+; CHECK-NOUNROLL-NEXT: ret void
+; CHECK-NOUNROLL: [[FOR_COND_CLEANUP3]]:
+; CHECK-NOUNROLL-NEXT: [[INC11]] = add nuw i32 [[H_026]], 1
+; CHECK-NOUNROLL-NEXT: [[EXITCOND27:%.*]] = icmp eq i32 [[INC11]], [[N]]
+; CHECK-NOUNROLL-NEXT: br i1 [[EXITCOND27]], label %[[FOR_COND_CLEANUP_LOOPEXIT]], label %[[FOR_BODY4_LR_PH]]
+; CHECK-NOUNROLL: [[FOR_BODY4]]:
+; CHECK-NOUNROLL-NEXT: [[W_024:%.*]] = phi i32 [ 0, %[[FOR_BODY4_LR_PH]] ], [ [[INC:%.*]], %[[FOR_BODY4]] ]
+; CHECK-NOUNROLL-NEXT: [[ADD:%.*]] = add i32 [[W_024]], [[MUL]]
+; CHECK-NOUNROLL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[A]], i32 [[ADD]]
+; CHECK-NOUNROLL-NEXT: [[TMP0:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
+; CHECK-NOUNROLL-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32
+; CHECK-NOUNROLL-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[B]], i32 [[W_024]]
+; CHECK-NOUNROLL-NEXT: [[TMP1:%.*]] = load i16, ptr [[ARRAYIDX5]], align 2
+; CHECK-NOUNROLL-NEXT: [[CONV6:%.*]] = sext i16 [[TMP1]] to i32
+; CHECK-NOUNROLL-NEXT: [[MUL7:%.*]] = mul nsw i32 [[CONV6]], [[CONV]]
+; CHECK-NOUNROLL-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[W_024]]
+; CHECK-NOUNROLL-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX8]], align 4
+; CHECK-NOUNROLL-NEXT: [[ADD9:%.*]] = add nsw i32 [[MUL7]], [[TMP2]]
+; CHECK-NOUNROLL-NEXT: store i32 [[ADD9]], ptr [[ARRAYIDX8]], align 4
+; CHECK-NOUNROLL-NEXT: [[INC]] = add nuw i32 [[W_024]], 1
+; CHECK-NOUNROLL-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]
+; CHECK-NOUNROLL-NEXT: br i1 [[EXITCOND]], label %[[FOR_COND_CLEANUP3]], label %[[FOR_BODY4]]
+;
entry:
%cmp25 = icmp eq i32 %N, 0
br i1 %cmp25, label %for.cond.cleanup, label %for.body4.lr.ph
@@ -114,22 +426,7 @@ for.cond.cleanup3:
%exitcond27 = icmp eq i32 %inc11, %N
br i1 %exitcond27, label %for.cond.cleanup, label %for.body4.lr.ph
-; CHECK-LABEL: for.body4
for.body4:
-; CHECK-NOUNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, [[PRE:%[a-z0-9.]+]] ], [ [[IV1:%[a-z.0-9]+]], %for.body4 ]
-; CHECK-NOUNROLL: [[IV1]] = add nuw i32 [[IV0]], 1
-; CHECK-NOUNROLL: br
-
-; CHECK-UNROLL: for.body4.epil:
-; CHECK-UNROLL: for.body4.epil.1:
-; CHECK-UNROLL: for.body4.epil.2:
-; CHECK-UNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, [[PRE:%[a-z0-9.]+]] ], [ [[IV4:%[a-z.0-9]+]], %for.body4 ]
-; CHECK-UNROLL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
-; CHECK-UNROLL: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 2
-; CHECK-UNROLL: [[IV3:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 3
-; CHECK-UNROLL: [[IV4]] = add nuw i32 [[IV0]], 4
-; CHECK-UNROLL: br
-
%w.024 = phi i32 [ 0, %for.body4.lr.ph ], [ %inc, %for.body4 ]
%add = add i32 %w.024, %mul
%arrayidx = getelementptr inbounds i16, ptr %A, i32 %add
@@ -148,26 +445,52 @@ for.body4:
br i1 %exitcond, label %for.cond.cleanup3, label %for.body4
}
-; CHECK-LABEL: loop_call
define arm_aapcs_vfpcc void @loop_call(ptr nocapture %C, ptr nocapture readonly %A, ptr nocapture readonly %B) local_unnamed_addr #1 {
+; CHECK-NOUNROLL-LABEL: define arm_aapcs_vfpcc void @loop_call(
+; CHECK-NOUNROLL-SAME: ptr captures(none) [[C:%.*]], ptr readonly captures(none) [[A:%.*]], ptr readonly captures(none) [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
+; CHECK-NOUNROLL-NEXT: [[ENTRY:.*]]:
+; CHECK-NOUNROLL-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-NOUNROLL: [[FOR_COND_CLEANUP:.*]]:
+; CHECK-NOUNROLL-NEXT: ret void
+; CHECK-NOUNROLL: [[FOR_BODY]]:
+; CHECK-NOUNROLL-NEXT: [[I_08:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[INC:%.*]], %[[FOR_BODY]] ]
+; CHECK-NOUNROLL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[I_08]]
+; CHECK-NOUNROLL-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+; CHECK-NOUNROLL-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[I_08]]
+; CHECK-NOUNROLL-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4
+; CHECK-NOUNROLL-NEXT: [[CALL:%.*]] = tail call arm_aapcs_vfpcc i32 @some_func(i32 [[TMP0]], i32 [[TMP1]])
+; CHECK-NOUNROLL-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[I_08]]
+; CHECK-NOUNROLL-NEXT: store i32 [[CALL]], ptr [[ARRAYIDX2]], align 4
+; CHECK-NOUNROLL-NEXT: [[INC]] = add nuw nsw i32 [[I_08]], 1
+; CHECK-NOUNROLL-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], 1024
+; CHECK-NOUNROLL-NEXT: br i1 [[EXITCOND]], label %[[FOR_COND_CLEANUP]], label %[[FOR_BODY]]
+;
+; CHECK-UNROLL-LABEL: define arm_aapcs_vfpcc void @loop_call(
+; CHECK-UNROLL-SAME: ptr captures(none) [[C:%.*]], ptr readonly captures(none) [[A:%.*]], ptr readonly captures(none) [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
+; CHECK-UNROLL-NEXT: [[ENTRY:.*]]:
+; CHECK-UNROLL-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-UNROLL: [[FOR_COND_CLEANUP:.*]]:
+; CHECK-UNROLL-NEXT: ret void
+; CHECK-UNROLL: [[FOR_BODY]]:
+; CHECK-UNROLL-NEXT: [[I_08:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[INC:%.*]], %[[FOR_BODY]] ]
+; CHECK-UNROLL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[I_08]]
+; CHECK-UNROLL-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+; CHECK-UNROLL-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[I_08]]
+; CHECK-UNROLL-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4
+; CHECK-UNROLL-NEXT: [[CALL:%.*]] = tail call arm_aapcs_vfpcc i32 @some_func(i32 [[TMP0]], i32 [[TMP1]])
+; CHECK-UNROLL-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[I_08]]
+; CHECK-UNROLL-NEXT: store i32 [[CALL]], ptr [[ARRAYIDX2]], align 4
+; CHECK-UNROLL-NEXT: [[INC]] = add nuw nsw i32 [[I_08]], 1
+; CHECK-UNROLL-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], 1024
+; CHECK-UNROLL-NEXT: br i1 [[EXITCOND]], label %[[FOR_COND_CLEANUP]], label %[[FOR_BODY]]
+;
entry:
br label %for.body
for.cond.cleanup:
ret void
-; CHECK-LABEL: for.body
for.body:
-; CHECK-NOUNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, %entry ], [ [[IV1:%[a-z.0-9]+]], %for.body ]
-; CHECK-NOUNROLL: [[IV1]] = add nuw nsw i32 [[IV0]], 1
-; CHECK-NOUNROLL: icmp eq i32 [[IV1]], 1024
-; CHECK-NOUNROLL: br
-
-; CHECK-UNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, %entry ], [ [[IV1:%[a-z.0-9]+]], %for.body ]
-; CHECK-UNROLL: [[IV1]] = add nuw nsw i32 [[IV0]], 1
-; CHECK-UNROLL: icmp eq i32 [[IV1]], 1024
-; CHECK-UNROLL: br
-
%i.08 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
%arrayidx = getelementptr inbounds i32, ptr %A, i32 %i.08
%0 = load i32, ptr %arrayidx, align 4
@@ -181,27 +504,75 @@ for.body:
br i1 %exitcond, label %for.cond.cleanup, label %for.body
}
-; CHECK-LABEL: iterate_inc
-; CHECK-NOUNROLL: %n.addr.04 = phi ptr [ %1, %while.body ], [ %n, %while.body.preheader ]
-; CHECK-NOUNROLL: %tobool = icmp eq ptr %1, null
-; CHECK-NOUNROLL: br i1 %tobool
-; CHECK-NOUNROLL-NOT: load
-
-; CHECK-UNROLL: [[CMP0:%[a-z.0-9]+]] = icmp eq ptr [[VAR0:%[a-z.0-9]+]], null
-; CHECK-UNROLL: br i1 [[CMP0]], label [[END:%[a-z.0-9]+]]
-; CHECK-UNROLL: [[CMP1:%[a-z.0-9]+]] = icmp eq ptr [[VAR1:%[a-z.0-9]+]], null
-; CHECK-UNROLL: br i1 [[CMP1]], label [[END]]
-; CHECK-UNROLL: [[CMP2:%[a-z.0-9]+]] = icmp eq ptr [[VAR2:%[a-z.0-9]+]], null
-; CHECK-UNROLL: br i1 [[CMP2]], label [[END]]
-; CHECK-UNROLL: [[CMP3:%[a-z.0-9]+]] = icmp eq ptr [[VAR3:%[a-z.0-9]+]], null
-; CHECK-UNROLL: br i1 [[CMP3]], label [[END]]
-; CHECK-UNROLL: [[CMP4:%[a-z.0-9]+]] = icmp eq ptr [[VAR4:%[a-z.0-9]+]], null
-; CHECK-UNROLL: br i1 [[CMP4]], label [[END]]
-; CHECK-UNROLL-NOT: load
-
%struct.Node = type { ptr, i32 }
define arm_aapcscc void @iterate_inc(ptr %n) local_unnamed_addr #0 {
+; CHECK-NOUNROLL-LABEL: define arm_aapcscc void @iterate_inc(
+; CHECK-NOUNROLL-SAME: ptr [[N:%.*]]) local_unnamed_addr #[[ATTR0]] {
+; CHECK-NOUNROLL-NEXT: [[ENTRY:.*:]]
+; CHECK-NOUNROLL-NEXT: [[TOBOOL3:%.*]] = icmp eq ptr [[N]], null
+; CHECK-NOUNROLL-NEXT: br i1 [[TOBOOL3]], label %[[WHILE_END:.*]], label %[[WHILE_BODY_PREHEADER:.*]]
+; CHECK-NOUNROLL: [[WHILE_BODY_PREHEADER]]:
+; CHECK-NOUNROLL-NEXT: br label %[[WHILE_BODY:.*]]
+; CHECK-NOUNROLL: [[WHILE_BODY]]:
+; CHECK-NOUNROLL-NEXT: [[N_ADDR_04:%.*]] = phi ptr [ [[TMP1:%.*]], %[[WHILE_BODY]] ], [ [[N]], %[[WHILE_BODY_PREHEADER]] ]
+; CHECK-NOUNROLL-NEXT: [[VAL:%.*]] = getelementptr inbounds [[STRUCT_NODE:%.*]], ptr [[N_ADDR_04]], i32 0, i32 1
+; CHECK-NOUNROLL-NEXT: [[TMP0:%.*]] = load i32, ptr [[VAL]], align 4
+; CHECK-NOUNROLL-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+; CHECK-NOUNROLL-NEXT: store i32 [[ADD]], ptr [[VAL]], align 4
+; CHECK-NOUNROLL-NEXT: [[TMP1]] = load ptr, ptr [[N_ADDR_04]], align 4
+; CHECK-NOUNROLL-NEXT: [[TOBOOL:%.*]] = icmp eq ptr [[TMP1]], null
+; CHECK-NOUNROLL-NEXT: br i1 [[TOBOOL]], label %[[WHILE_END_LOOPEXIT:.*]], label %[[WHILE_BODY]]
+; CHECK-NOUNROLL: [[WHILE_END_LOOPEXIT]]:
+; CHECK-NOUNROLL-NEXT: br label %[[WHILE_END]]
+; CHECK-NOUNROLL: [[WHILE_END]]:
+; CHECK-NOUNROLL-NEXT: ret void
+;
+; CHECK-UNROLL-LABEL: define arm_aapcscc void @iterate_inc(
+; CHECK-UNROLL-SAME: ptr [[N:%.*]]) local_unnamed_addr #[[ATTR0]] {
+; CHECK-UNROLL-NEXT: [[ENTRY:.*:]]
+; CHECK-UNROLL-NEXT: [[TOBOOL3:%.*]] = icmp eq ptr [[N]], null
+; CHECK-UNROLL-NEXT: br i1 [[TOBOOL3]], label %[[WHILE_END:.*]], label %[[WHILE_BODY_PREHEADER:.*]]
+; CHECK-UNROLL: [[WHILE_BODY_PREHEADER]]:
+; CHECK-UNROLL-NEXT: br label %[[WHILE_BODY:.*]]
+; CHECK-UNROLL: [[WHILE_BODY]]:
+; CHECK-UNROLL-NEXT: [[N_ADDR_04:%.*]] = phi ptr [ [[N]], %[[WHILE_BODY_PREHEADER]] ], [ [[TMP7:%.*]], %[[WHILE_BODY_3:.*]] ]
+; CHECK-UNROLL-NEXT: [[VAL:%.*]] = getelementptr inbounds [[STRUCT_NODE:%.*]], ptr [[N_ADDR_04]], i32 0, i32 1
+; CHECK-UNROLL-NEXT: [[TMP0:%.*]] = load i32, ptr [[VAL]], align 4
+; CHECK-UNROLL-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+; CHECK-UNROLL-NEXT: store i32 [[ADD]], ptr [[VAL]], align 4
+; CHECK-UNROLL-NEXT: [[TMP1:%.*]] = load ptr, ptr [[N_ADDR_04]], align 4
+; CHECK-UNROLL-NEXT: [[TOBOOL:%.*]] = icmp eq ptr [[TMP1]], null
+; CHECK-UNROLL-NEXT: br i1 [[TOBOOL]], label %[[WHILE_END_LOOPEXIT:.*]], label %[[WHILE_BODY_1:.*]]
+; CHECK-UNROLL: [[WHILE_BODY_1]]:
+; CHECK-UNROLL-NEXT: [[VAL_1:%.*]] = getelementptr inbounds [[STRUCT_NODE]], ptr [[TMP1]], i32 0, i32 1
+; CHECK-UNROLL-NEXT: [[TMP2:%.*]] = load i32, ptr [[VAL_1]], align 4
+; CHECK-UNROLL-NEXT: [[ADD_1:%.*]] = add nsw i32 [[TMP2]], 1
+; CHECK-UNROLL-NEXT: store i32 [[ADD_1]], ptr [[VAL_1]], align 4
+; CHECK-UNROLL-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP1]], align 4
+; CHECK-UNROLL-NEXT: [[TOBOOL_1:%.*]] = icmp eq ptr [[TMP3]], null
+; CHECK-UNROLL-NEXT: br i1 [[TOBOOL_1]], label %[[WHILE_END_LOOPEXIT]], label %[[WHILE_BODY_2:.*]]
+; CHECK-UNROLL: [[WHILE_BODY_2]]:
+; CHECK-UNROLL-NEXT: [[VAL_2:%.*]] = getelementptr inbounds [[STRUCT_NODE]], ptr [[TMP3]], i32 0, i32 1
+; CHECK-UNROLL-NEXT: [[TMP4:%.*]] = load i32, ptr [[VAL_2]], align 4
+; CHECK-UNROLL-NEXT: [[ADD_2:%.*]] = add nsw i32 [[TMP4]], 1
+; CHECK-UNROLL-NEXT: store i32 [[ADD_2]], ptr [[VAL_2]], align 4
+; CHECK-UNROLL-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP3]], align 4
+; CHECK-UNROLL-NEXT: [[TOBOOL_2:%.*]] = icmp eq ptr [[TMP5]], null
+; CHECK-UNROLL-NEXT: br i1 [[TOBOOL_2]], label %[[WHILE_END_LOOPEXIT]], label %[[WHILE_BODY_3]]
+; CHECK-UNROLL: [[WHILE_BODY_3]]:
+; CHECK-UNROLL-NEXT: [[VAL_3:%.*]] = getelementptr inbounds [[STRUCT_NODE]], ptr [[TMP5]], i32 0, i32 1
+; CHECK-UNROLL-NEXT: [[TMP6:%.*]] = load i32, ptr [[VAL_3]], align 4
+; CHECK-UNROLL-NEXT: [[ADD_3:%.*]] = add nsw i32 [[TMP6]], 1
+; CHECK-UNROLL-NEXT: store i32 [[ADD_3]], ptr [[VAL_3]], align 4
+; CHECK-UNROLL-NEXT: [[TMP7]] = load ptr, ptr [[TMP5]], align 4
+; CHECK-UNROLL-NEXT: [[TOBOOL_3:%.*]] = icmp eq ptr [[TMP7]], null
+; CHECK-UNROLL-NEXT: br i1 [[TOBOOL_3]], label %[[WHILE_END_LOOPEXIT]], label %[[WHILE_BODY]]
+; CHECK-UNROLL: [[WHILE_END_LOOPEXIT]]:
+; CHECK-UNROLL-NEXT: br label %[[WHILE_END]]
+; CHECK-UNROLL: [[WHILE_END]]:
+; CHECK-UNROLL-NEXT: ret void
+;
entry:
%tobool3 = icmp eq ptr %n, null
br i1 %tobool3, label %while.end, label %while.body.preheader
diff --git a/llvm/test/Transforms/LoopUnroll/ARM/multi-blocks.ll b/llvm/test/Transforms/LoopUnroll/ARM/multi-blocks.ll
index 066a8b65bfce8..7614a854fab01 100644
--- a/llvm/test/Transforms/LoopUnroll/ARM/multi-blocks.ll
+++ b/llvm/test/Transforms/LoopUnroll/ARM/multi-blocks.ll
@@ -131,8 +131,8 @@ define void @test_three_blocks(ptr nocapture %Output, ptr nocapture readonly %Co
; CHECK-NEXT: br label [[FOR_INC_3]]
; CHECK: for.inc.3:
; CHECK-NEXT: [[TEMP_1_3]] = phi i32 [ [[ADD_3]], [[IF_THEN_3]] ], [ [[TEMP_1_2]], [[FOR_INC_2]] ]
-; CHECK-NEXT: [[INC_3]] = add nuw i32 [[J_010]], 4
-; CHECK-NEXT: [[NITER_NEXT_3]] = add nuw i32 [[NITER]], 4
+; CHECK-NEXT: [[INC_3]] = add nuw nsw i32 [[J_010]], 4
+; CHECK-NEXT: [[NITER_NEXT_3]] = add nuw nsw i32 [[NITER]], 4
; CHECK-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i32 [[NITER_NEXT_3]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_3]], label [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]], label [[FOR_BODY]]
;
@@ -524,7 +524,7 @@ define void @test_four_blocks(ptr nocapture %Output, ptr nocapture readonly %Con
; CHECK-NEXT: br label [[FOR_INC_2]]
; CHECK: for.inc.2:
; CHECK-NEXT: [[TEMP_1_2:%.*]] = phi i32 [ [[ADD_2]], [[IF_THEN_2]] ], [ [[SUB13_2]], [[IF_ELSE_2]] ]
-; CHECK-NEXT: [[INC_2:%.*]] = add nuw i32 [[J_027]], 3
+; CHECK-NEXT: [[INC_2:%.*]] = add nuw nsw i32 [[J_027]], 3
; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[CONDITION]], i32 [[INC_2]]
; CHECK-NEXT: [[I1_3:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4
; CHECK-NEXT: [[CMP1_3:%.*]] = icmp ugt i32 [[I1_3]], 65535
@@ -546,8 +546,8 @@ define void @test_four_blocks(ptr nocapture %Output, ptr nocapture readonly %Con
; CHECK-NEXT: br label [[FOR_INC_3]]
; CHECK: for.inc.3:
; CHECK-NEXT: [[TEMP_1_3]] = phi i32 [ [[ADD_3]], [[IF_THEN_3]] ], [ [[SUB13_3]], [[IF_ELSE_3]] ]
-; CHECK-NEXT: [[INC_3]] = add nuw i32 [[J_027]], 4
-; CHECK-NEXT: [[NITER_NEXT_3]] = add i32 [[NITER]], 4
+; CHECK-NEXT: [[INC_3]] = add nuw nsw i32 [[J_027]], 4
+; CHECK-NEXT: [[NITER_NEXT_3]] = add nsw i32 [[NITER]], 4
; CHECK-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i32 [[NITER_NEXT_3]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_3]], label [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]], label [[FOR_BODY]]
;
diff --git a/llvm/test/Transforms/LoopUnroll/NVPTX/unroll-convergent-uniform-tripcount.ll b/llvm/test/Transforms/LoopUnroll/NVPTX/unroll-convergent-uniform-tripcount.ll
index 4d7b96cfe5840..b663266202049 100644
--- a/llvm/test/Transforms/LoopUnroll/NVPTX/unroll-convergent-uniform-tripcount.ll
+++ b/llvm/test/Transforms/LoopUnroll/NVPTX/unroll-convergent-uniform-tripcount.ll
@@ -49,8 +49,8 @@ define void @runtime_unroll_uniform_trip_count(ptr %out, ptr %in, i32 %n) {
; CHECK-NEXT: %shfl.3 = call i32 @llvm.nvvm.shfl.down.i32(i32 %add.2, i32 1, i32 31)
; CHECK-NEXT: %add.3 = add i32 %load.3, %shfl.3
; CHECK-NEXT: store i32 %add.3, ptr %arrayidx.out.3, align 4
-; CHECK-NEXT: %indvars.iv.next.3 = add i32 %indvars.iv, 4
-; CHECK-NEXT: %niter.next.3 = add i32 %niter, 4
+; CHECK-NEXT: %indvars.iv.next.3 = add nsw i32 %indvars.iv, 4
+; CHECK-NEXT: %niter.next.3 = add nsw i32 %niter, 4
; CHECK-NEXT: %niter.ncmp.3 = icmp eq i32 %niter.next.3, %unroll_iter
; CHECK-NEXT: br i1 %niter.ncmp.3, label %for.end.unr-lcssa, label %for.body
; CHECK: for.end.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors-inseltpoison.ll b/llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors-inseltpoison.ll
index 5d08e9dea0889..3d7ddc0ef8cd4 100644
--- a/llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors-inseltpoison.ll
+++ b/llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors-inseltpoison.ll
@@ -48,7 +48,7 @@ define ptr @f(ptr returned %s, i32 zeroext %x, i32 signext %k) local_unnamed_add
; CHECK-NEXT: store <16 x i8> [[TMP12]], ptr [[TMP13]], align 1
; CHECK-NEXT: [[INDEX_NEXT_1]] = add i64 [[INDEX]], 32
; CHECK-NEXT: [[VEC_IND_NEXT13_1]] = add <16 x i32> [[VEC_IND12]], splat (i32 32)
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[MIDDLE_BLOCK_UNR_LCSSA_LOOPEXIT:%.*]], label [[VECTOR_BODY]]
; CHECK: middle.block.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors.ll b/llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors.ll
index 03277fc8bb644..898cb8d4ed0b7 100644
--- a/llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors.ll
+++ b/llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors.ll
@@ -48,7 +48,7 @@ define ptr @f(ptr returned %s, i32 zeroext %x, i32 signext %k) local_unnamed_add
; CHECK-NEXT: store <16 x i8> [[TMP12]], ptr [[TMP13]], align 1
; CHECK-NEXT: [[INDEX_NEXT_1]] = add i64 [[INDEX]], 32
; CHECK-NEXT: [[VEC_IND_NEXT13_1]] = add <16 x i32> [[VEC_IND12]], splat (i32 32)
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[MIDDLE_BLOCK_UNR_LCSSA_LOOPEXIT:%.*]], label [[VECTOR_BODY]]
; CHECK: middle.block.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/RISCV/vector.ll b/llvm/test/Transforms/LoopUnroll/RISCV/vector.ll
index 2c834748c79d7..35d637a23042f 100644
--- a/llvm/test/Transforms/LoopUnroll/RISCV/vector.ll
+++ b/llvm/test/Transforms/LoopUnroll/RISCV/vector.ll
@@ -81,7 +81,7 @@ define void @reverse(ptr %dst, ptr %src, i64 %len) {
; SIFIVE-NEXT: [[ARRAYIDX2_7:%.*]] = getelementptr inbounds nuw <4 x float>, ptr [[DST]], i64 [[IV_NEXT_6]]
; SIFIVE-NEXT: store <4 x float> [[TMP17]], ptr [[ARRAYIDX2_7]], align 16
; SIFIVE-NEXT: [[IV_NEXT_7]] = add nuw nsw i64 [[IV]], 8
-; SIFIVE-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; SIFIVE-NEXT: [[NITER_NEXT_7]] = add nsw i64 [[NITER]], 8
; SIFIVE-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; SIFIVE-NEXT: br i1 [[NITER_NCMP_7]], label %[[EXIT_UNR_LCSSA:.*]], label %[[FOR_BODY]]
; SIFIVE: [[EXIT_UNR_LCSSA]]:
diff --git a/llvm/test/Transforms/LoopUnroll/WebAssembly/basic-unrolling.ll b/llvm/test/Transforms/LoopUnroll/WebAssembly/basic-unrolling.ll
index d842c4adcb74d..91ccde58e33db 100644
--- a/llvm/test/Transforms/LoopUnroll/WebAssembly/basic-unrolling.ll
+++ b/llvm/test/Transforms/LoopUnroll/WebAssembly/basic-unrolling.ll
@@ -148,23 +148,23 @@ define hidden void @runtime(ptr nocapture %a, ptr nocapture readonly %b, ptr noc
; CHECK: for.body:
; CHECK-NEXT: [[I_09:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER_NEW]] ], [ [[INC_1]], [[FOR_BODY]] ]
; CHECK-NEXT: [[NITER:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER_NEW]] ], [ [[NITER_NEXT_1:%.*]], [[FOR_BODY]] ]
-; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i8], ptr [[B]], i32 [[I_09]]
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[B]], i32 [[I_09]]
; CHECK-NEXT: [[I:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [4 x i8], ptr [[C]], i32 [[I_09]]
+; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[C]], i32 [[I_09]]
; CHECK-NEXT: [[I1:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4
; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[I1]], [[I]]
-; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [4 x i8], ptr [[A]], i32 [[I_09]]
+; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i32 [[I_09]]
; CHECK-NEXT: store i32 [[MUL]], ptr [[ARRAYIDX2]], align 4
; CHECK-NEXT: [[INC:%.*]] = or disjoint i32 [[I_09]], 1
-; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds [4 x i8], ptr [[B]], i32 [[INC]]
+; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[B]], i32 [[INC]]
; CHECK-NEXT: [[I_1:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4
-; CHECK-NEXT: [[ARRAYIDX1_1:%.*]] = getelementptr inbounds [4 x i8], ptr [[C]], i32 [[INC]]
+; CHECK-NEXT: [[ARRAYIDX1_1:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[C]], i32 [[INC]]
; CHECK-NEXT: [[I1_1:%.*]] = load i32, ptr [[ARRAYIDX1_1]], align 4
; CHECK-NEXT: [[MUL_1:%.*]] = mul nsw i32 [[I1_1]], [[I_1]]
-; CHECK-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds [4 x i8], ptr [[A]], i32 [[INC]]
+; CHECK-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i32 [[INC]]
; CHECK-NEXT: store i32 [[MUL_1]], ptr [[ARRAYIDX2_1]], align 4
-; CHECK-NEXT: [[INC_1]] = add nuw i32 [[I_09]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i32 [[NITER]], 2
+; CHECK-NEXT: [[INC_1]] = add nuw nsw i32 [[I_09]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw nsw i32 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i32 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]], label [[FOR_BODY]]
;
diff --git a/llvm/test/Transforms/LoopUnroll/convergent.controlled.ll b/llvm/test/Transforms/LoopUnroll/convergent.controlled.ll
index 5dc613e733f00..b1df326d79708 100644
--- a/llvm/test/Transforms/LoopUnroll/convergent.controlled.ll
+++ b/llvm/test/Transforms/LoopUnroll/convergent.controlled.ll
@@ -314,7 +314,7 @@ define i32 @pragma_unroll_with_remainder(i32 %n) {
; CHECK-NEXT: [[TOK_LOOP_1:%.*]] = call token @llvm.experimental.convergence.anchor()
; CHECK-NEXT: call void @f() [ "convergencectrl"(token [[TOK_LOOP_1]]) ]
; CHECK-NEXT: [[INC_1]] = add nsw i32 [[X_0]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i32 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i32 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i32 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[EXIT_UNR_LCSSA:%.*]], label [[L3]], !llvm.loop [[LOOP8:![0-9]+]]
; CHECK: exit.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/expensive-tripcount.ll b/llvm/test/Transforms/LoopUnroll/expensive-tripcount.ll
index d52d6ef1b60f2..8250bef4ce47e 100644
--- a/llvm/test/Transforms/LoopUnroll/expensive-tripcount.ll
+++ b/llvm/test/Transforms/LoopUnroll/expensive-tripcount.ll
@@ -43,7 +43,7 @@ define dso_local void @complex_loop_unroll(i64 noundef %input_offset, i64 nounde
; CHECK-NEXT: [[INDVARS_IV_NEXT_6:%.*]] = add nsw i64 [[INDVARS_IV_NEXT_5]], [[STEP]]
; CHECK-NEXT: [[ADD_7]] = add i64 [[ADD_6]], [[INDVARS_IV_NEXT_6]]
; CHECK-NEXT: [[INDVARS_IV_NEXT_7]] = add nsw i64 [[INDVARS_IV_NEXT_6]], [[STEP]]
-; CHECK-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; CHECK-NEXT: [[NITER_NEXT_7]] = add nsw i64 [[NITER]], 8
; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp ne i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label %[[FOR_BODY]], label %[[FOR_END14_UNR_LCSSA:.*]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: [[FOR_END14_UNR_LCSSA]]:
diff --git a/llvm/test/Transforms/LoopUnroll/peel-last-iteration-with-guards.ll b/llvm/test/Transforms/LoopUnroll/peel-last-iteration-with-guards.ll
index c763f14b73cb8..90f4403244630 100644
--- a/llvm/test/Transforms/LoopUnroll/peel-last-iteration-with-guards.ll
+++ b/llvm/test/Transforms/LoopUnroll/peel-last-iteration-with-guards.ll
@@ -182,7 +182,7 @@ define void @peel_with_guard2(i32 %n) {
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label %[[LOOP_LATCH]]
; CHECK: [[LOOP_LATCH]]:
-; CHECK-NEXT: [[IV_NEXT]] = add nuw i32 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[N]], 1
; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_NEXT]], [[TMP2]]
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT_LOOPEXIT_PEEL_BEGIN_LOOPEXIT:.*]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]
@@ -254,7 +254,7 @@ define void @test_peel_guard_sub_1_btc(i32 %n) {
; CHECK-NEXT: [[CALL136:%.*]] = load volatile ptr, ptr null, align 4294967296
; CHECK-NEXT: br label %[[LOOP_LATCH]]
; CHECK: [[LOOP_LATCH]]:
-; CHECK-NEXT: [[IV_NEXT]] = add nuw i32 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[N]], 1
; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_NEXT]], [[TMP2]]
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT_LOOPEXIT_PEEL_BEGIN_LOOPEXIT:.*]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP4:![0-9]+]]
diff --git a/llvm/test/Transforms/LoopUnroll/peel-last-iteration-with-variable-trip-count.ll b/llvm/test/Transforms/LoopUnroll/peel-last-iteration-with-variable-trip-count.ll
index 5704be33f0f0b..b96ebfd6bd95e 100644
--- a/llvm/test/Transforms/LoopUnroll/peel-last-iteration-with-variable-trip-count.ll
+++ b/llvm/test/Transforms/LoopUnroll/peel-last-iteration-with-variable-trip-count.ll
@@ -15,7 +15,7 @@ define i32 @peel_last_with_trip_count_check_lcssa_phi(i32 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV1:%.*]] = phi i32 [ 0, %[[ENTRY_SPLIT]] ], [ [[IV_NEXT1:%.*]], %[[LOOP]] ]
; CHECK-NEXT: call void @foo(i32 2)
-; CHECK-NEXT: [[IV_NEXT1]] = add nuw i32 [[IV1]], 1
+; CHECK-NEXT: [[IV_NEXT1]] = add nuw nsw i32 [[IV1]], 1
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[N]], 1
; CHECK-NEXT: [[EC1:%.*]] = icmp ne i32 [[IV_NEXT1]], [[TMP1]]
; CHECK-NEXT: br i1 [[EC1]], label %[[LOOP]], label %[[EXIT_PEEL_BEGIN_LOOPEXIT:.*]], !llvm.loop [[LOOP0:![0-9]+]]
@@ -186,7 +186,7 @@ define i32 @peel_last_with_trip_count_check_lcssa_phi_cmp_not_invar2(i32 %n) {
; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[IV]], [[SUB]]
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C]], i32 1, i32 2
; CHECK-NEXT: call void @foo(i32 [[SEL]])
-; CHECK-NEXT: [[IV_NEXT1]] = add nuw i32 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT1]] = add nuw nsw i32 [[IV]], 1
; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[N]], 1
; CHECK-NEXT: [[EC1:%.*]] = icmp ne i32 [[IV_NEXT1]], [[TMP2]]
; CHECK-NEXT: br i1 [[EC1]], label %[[LOOP]], label %[[EXIT_PEEL_BEGIN_LOOPEXIT:.*]], !llvm.loop [[LOOP2:![0-9]+]]
@@ -242,7 +242,7 @@ define i32 @peel_last_with_trip_count_check_lcssa_phi_cmp_not_invar3(i32 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY_SPLIT]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: call void @foo(i32 2)
-; CHECK-NEXT: [[IV_NEXT]] = add nuw i32 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[N]], 1
; CHECK-NEXT: [[EC:%.*]] = icmp ne i32 [[IV_NEXT]], [[TMP1]]
; CHECK-NEXT: br i1 [[EC]], label %[[LOOP]], label %[[EXIT_PEEL_BEGIN_LOOPEXIT:.*]], !llvm.loop [[LOOP3:![0-9]+]]
@@ -360,7 +360,7 @@ define void @peel_last_with_trip_count_check_nested_loop(i32 %n) {
; CHECK-NEXT: call void @foo(i32 1)
; CHECK-NEXT: br label %[[INNER_LATCH]]
; CHECK: [[INNER_LATCH]]:
-; CHECK-NEXT: [[IV_NEXT1]] = add nuw i32 [[IV1]], 1
+; CHECK-NEXT: [[IV_NEXT1]] = add nuw nsw i32 [[IV1]], 1
; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[N]], 1
; CHECK-NEXT: [[EXITCOND_NOT1:%.*]] = icmp eq i32 [[IV_NEXT1]], [[TMP2]]
; CHECK-NEXT: br i1 [[EXITCOND_NOT1]], label %[[OUTER_HEADER_LOOPEXIT_PEEL_BEGIN_LOOPEXIT]], label %[[INNER_HEADER]], !llvm.loop [[LOOP4:![0-9]+]]
diff --git a/llvm/test/Transforms/LoopUnroll/peel-loop-min-max-intrinsics.ll b/llvm/test/Transforms/LoopUnroll/peel-loop-min-max-intrinsics.ll
index c699450afb6e5..47944467e067a 100644
--- a/llvm/test/Transforms/LoopUnroll/peel-loop-min-max-intrinsics.ll
+++ b/llvm/test/Transforms/LoopUnroll/peel-loop-min-max-intrinsics.ll
@@ -37,7 +37,7 @@ define void @test_umin(i32 %N) {
; CHECK: for.body:
; CHECK-NEXT: [[I_06:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ [[INC_PEEL4]], [[FOR_BODY_PREHEADER_PEEL_NEWPH]] ]
; CHECK-NEXT: tail call void @foo(i32 2)
-; CHECK-NEXT: [[INC]] = add nuw i32 [[I_06]], 1
+; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_06]], 1
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC]], [[N]]
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP_LOOPEXIT_LOOPEXIT:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: for.cond.cleanup.loopexit.loopexit:
@@ -96,7 +96,7 @@ define void @test_umax(i32 %N) {
; CHECK: for.body:
; CHECK-NEXT: [[I_06:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ [[INC_PEEL4]], [[FOR_BODY_PREHEADER_PEEL_NEWPH]] ]
; CHECK-NEXT: tail call void @foo(i32 [[I_06]])
-; CHECK-NEXT: [[INC]] = add nuw i32 [[I_06]], 1
+; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_06]], 1
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC]], [[N]]
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP_LOOPEXIT_LOOPEXIT:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]]
; CHECK: for.cond.cleanup.loopexit.loopexit:
diff --git a/llvm/test/Transforms/LoopUnroll/peel-loop-noalias-scope-decl.ll b/llvm/test/Transforms/LoopUnroll/peel-loop-noalias-scope-decl.ll
index 839bdbd541e4b..32267cb104d3b 100644
--- a/llvm/test/Transforms/LoopUnroll/peel-loop-noalias-scope-decl.ll
+++ b/llvm/test/Transforms/LoopUnroll/peel-loop-noalias-scope-decl.ll
@@ -10,35 +10,35 @@ target triple = "x86_64-unknown-linux-gnu"
define internal fastcc void @test01(ptr %p0, ptr %p1, ptr %p2) unnamed_addr align 2 {
; CHECK-LABEL: @test01(
; CHECK-NEXT: for.body47.lr.ph:
-; CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata !0)
+; CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META0:![0-9]+]])
; CHECK-NEXT: br label [[FOR_BODY47_PEEL_BEGIN:%.*]]
; CHECK: for.body47.peel.begin:
; CHECK-NEXT: br label [[FOR_BODY47_PEEL:%.*]]
; CHECK: for.body47.peel:
-; CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata !3)
-; CHECK-NEXT: store i8 42, ptr [[P0:%.*]], align 1, !alias.scope !3
-; CHECK-NEXT: store i8 43, ptr [[P1:%.*]], align 1, !alias.scope !0
-; CHECK-NEXT: store i8 44, ptr [[P2:%.*]], align 1, !alias.scope !5
-; CHECK-NEXT: store i8 42, ptr [[P0]], align 1, !noalias !3
-; CHECK-NEXT: store i8 43, ptr [[P1]], align 1, !noalias !0
-; CHECK-NEXT: store i8 44, ptr [[P2]], align 1, !noalias !5
+; CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
+; CHECK-NEXT: store i8 42, ptr [[P0:%.*]], align 1, !alias.scope [[META3]]
+; CHECK-NEXT: store i8 43, ptr [[P1:%.*]], align 1, !alias.scope [[META0]]
+; CHECK-NEXT: store i8 44, ptr [[P2:%.*]], align 1, !alias.scope [[META5:![0-9]+]]
+; CHECK-NEXT: store i8 42, ptr [[P0]], align 1, !noalias [[META3]]
+; CHECK-NEXT: store i8 43, ptr [[P1]], align 1, !noalias [[META0]]
+; CHECK-NEXT: store i8 44, ptr [[P2]], align 1, !noalias [[META5]]
; CHECK-NEXT: [[CMP52_PEEL:%.*]] = icmp eq i32 0, 0
; CHECK-NEXT: br i1 [[CMP52_PEEL]], label [[COND_TRUE_PEEL:%.*]], label [[COND_END_PEEL:%.*]]
; CHECK: cond.true.peel:
-; CHECK-NEXT: store i8 52, ptr [[P0]], align 1, !alias.scope !3
-; CHECK-NEXT: store i8 53, ptr [[P1]], align 1, !alias.scope !0
-; CHECK-NEXT: store i8 54, ptr [[P2]], align 1, !alias.scope !5
-; CHECK-NEXT: store i8 52, ptr [[P0]], align 1, !noalias !3
-; CHECK-NEXT: store i8 53, ptr [[P1]], align 1, !noalias !0
-; CHECK-NEXT: store i8 54, ptr [[P2]], align 1, !noalias !5
+; CHECK-NEXT: store i8 52, ptr [[P0]], align 1, !alias.scope [[META3]]
+; CHECK-NEXT: store i8 53, ptr [[P1]], align 1, !alias.scope [[META0]]
+; CHECK-NEXT: store i8 54, ptr [[P2]], align 1, !alias.scope [[META5]]
+; CHECK-NEXT: store i8 52, ptr [[P0]], align 1, !noalias [[META3]]
+; CHECK-NEXT: store i8 53, ptr [[P1]], align 1, !noalias [[META0]]
+; CHECK-NEXT: store i8 54, ptr [[P2]], align 1, !noalias [[META5]]
; CHECK-NEXT: br label [[COND_END_PEEL]]
; CHECK: cond.end.peel:
-; CHECK-NEXT: store i8 62, ptr [[P0]], align 1, !alias.scope !3
-; CHECK-NEXT: store i8 63, ptr [[P1]], align 1, !alias.scope !0
-; CHECK-NEXT: store i8 64, ptr [[P2]], align 1, !alias.scope !5
-; CHECK-NEXT: store i8 62, ptr [[P0]], align 1, !noalias !3
-; CHECK-NEXT: store i8 63, ptr [[P1]], align 1, !noalias !0
-; CHECK-NEXT: store i8 64, ptr [[P2]], align 1, !noalias !5
+; CHECK-NEXT: store i8 62, ptr [[P0]], align 1, !alias.scope [[META3]]
+; CHECK-NEXT: store i8 63, ptr [[P1]], align 1, !alias.scope [[META0]]
+; CHECK-NEXT: store i8 64, ptr [[P2]], align 1, !alias.scope [[META5]]
+; CHECK-NEXT: store i8 62, ptr [[P0]], align 1, !noalias [[META3]]
+; CHECK-NEXT: store i8 63, ptr [[P1]], align 1, !noalias [[META0]]
+; CHECK-NEXT: store i8 64, ptr [[P2]], align 1, !noalias [[META5]]
; CHECK-NEXT: [[INC_PEEL:%.*]] = add nuw i32 0, 1
; CHECK-NEXT: [[EXITCOND_NOT_PEEL:%.*]] = icmp eq i32 [[INC_PEEL]], undef
; CHECK-NEXT: br i1 [[EXITCOND_NOT_PEEL]], label [[FOR_COND_CLEANUP46:%.*]], label [[FOR_BODY47_PEEL_NEXT:%.*]]
@@ -54,31 +54,31 @@ define internal fastcc void @test01(ptr %p0, ptr %p1, ptr %p2) unnamed_addr alig
; CHECK-NEXT: ret void
; CHECK: for.body47:
; CHECK-NEXT: [[J_02:%.*]] = phi i32 [ [[INC_PEEL]], [[FOR_BODY47_LR_PH_PEEL_NEWPH]] ], [ [[INC:%.*]], [[COND_END:%.*]] ]
-; CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata !6)
-; CHECK-NEXT: store i8 42, ptr [[P0]], align 1, !alias.scope !6
-; CHECK-NEXT: store i8 43, ptr [[P1]], align 1, !alias.scope !0
-; CHECK-NEXT: store i8 44, ptr [[P2]], align 1, !alias.scope !8
-; CHECK-NEXT: store i8 42, ptr [[P0]], align 1, !noalias !6
-; CHECK-NEXT: store i8 43, ptr [[P1]], align 1, !noalias !0
-; CHECK-NEXT: store i8 44, ptr [[P2]], align 1, !noalias !8
+; CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
+; CHECK-NEXT: store i8 42, ptr [[P0]], align 1, !alias.scope [[META6]]
+; CHECK-NEXT: store i8 43, ptr [[P1]], align 1, !alias.scope [[META0]]
+; CHECK-NEXT: store i8 44, ptr [[P2]], align 1, !alias.scope [[META8:![0-9]+]]
+; CHECK-NEXT: store i8 42, ptr [[P0]], align 1, !noalias [[META6]]
+; CHECK-NEXT: store i8 43, ptr [[P1]], align 1, !noalias [[META0]]
+; CHECK-NEXT: store i8 44, ptr [[P2]], align 1, !noalias [[META8]]
; CHECK-NEXT: br i1 false, label [[COND_TRUE:%.*]], label [[COND_END]]
; CHECK: cond.true:
-; CHECK-NEXT: store i8 52, ptr [[P0]], align 1, !alias.scope !6
-; CHECK-NEXT: store i8 53, ptr [[P1]], align 1, !alias.scope !0
-; CHECK-NEXT: store i8 54, ptr [[P2]], align 1, !alias.scope !8
-; CHECK-NEXT: store i8 52, ptr [[P0]], align 1, !noalias !6
-; CHECK-NEXT: store i8 53, ptr [[P1]], align 1, !noalias !0
-; CHECK-NEXT: store i8 54, ptr [[P2]], align 1, !noalias !8
+; CHECK-NEXT: store i8 52, ptr [[P0]], align 1, !alias.scope [[META6]]
+; CHECK-NEXT: store i8 53, ptr [[P1]], align 1, !alias.scope [[META0]]
+; CHECK-NEXT: store i8 54, ptr [[P2]], align 1, !alias.scope [[META8]]
+; CHECK-NEXT: store i8 52, ptr [[P0]], align 1, !noalias [[META6]]
+; CHECK-NEXT: store i8 53, ptr [[P1]], align 1, !noalias [[META0]]
+; CHECK-NEXT: store i8 54, ptr [[P2]], align 1, !noalias [[META8]]
; CHECK-NEXT: br label [[COND_END]]
; CHECK: cond.end:
-; CHECK-NEXT: store i8 62, ptr [[P0]], align 1, !alias.scope !6
-; CHECK-NEXT: store i8 63, ptr [[P1]], align 1, !alias.scope !0
-; CHECK-NEXT: store i8 64, ptr [[P2]], align 1, !alias.scope !8
-; CHECK-NEXT: store i8 62, ptr [[P0]], align 1, !noalias !6
-; CHECK-NEXT: store i8 63, ptr [[P1]], align 1, !noalias !0
-; CHECK-NEXT: store i8 64, ptr [[P2]], align 1, !noalias !8
-; CHECK-NEXT: [[INC]] = add nuw i32 [[J_02]], 1
-; CHECK-NEXT: br i1 undef, label [[FOR_COND_CLEANUP46_LOOPEXIT:%.*]], label [[FOR_BODY47]], [[LOOP9:!llvm.loop !.*]]
+; CHECK-NEXT: store i8 62, ptr [[P0]], align 1, !alias.scope [[META6]]
+; CHECK-NEXT: store i8 63, ptr [[P1]], align 1, !alias.scope [[META0]]
+; CHECK-NEXT: store i8 64, ptr [[P2]], align 1, !alias.scope [[META8]]
+; CHECK-NEXT: store i8 62, ptr [[P0]], align 1, !noalias [[META6]]
+; CHECK-NEXT: store i8 63, ptr [[P1]], align 1, !noalias [[META0]]
+; CHECK-NEXT: store i8 64, ptr [[P2]], align 1, !noalias [[META8]]
+; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[J_02]], 1
+; CHECK-NEXT: br i1 undef, label [[FOR_COND_CLEANUP46_LOOPEXIT:%.*]], label [[FOR_BODY47]], !llvm.loop [[LOOP9:![0-9]+]]
;
for.body47.lr.ph:
call void @llvm.experimental.noalias.scope.decl(metadata !5)
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-exit-phi-scev-invalidation.ll b/llvm/test/Transforms/LoopUnroll/runtime-exit-phi-scev-invalidation.ll
index 047360178aa06..c3d5d66eaacf5 100644
--- a/llvm/test/Transforms/LoopUnroll/runtime-exit-phi-scev-invalidation.ll
+++ b/llvm/test/Transforms/LoopUnroll/runtime-exit-phi-scev-invalidation.ll
@@ -60,7 +60,7 @@ define void @pr56282() {
; CHECK-NEXT: [[C_1_7:%.*]] = icmp ugt i32 [[V_7]], 0
; CHECK-NEXT: br i1 [[C_1_7]], label [[INNER_1_LATCH_7]], label [[EXIT_DEOPT_LOOPEXIT]]
; CHECK: inner.1.latch.7:
-; CHECK-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; CHECK-NEXT: [[NITER_NEXT_7]] = add nsw i64 [[NITER]], 8
; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp ne i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label [[INNER_1_HEADER]], label [[OUTER_MIDDLE_UNR_LCSSA:%.*]]
; CHECK: outer.middle.unr-lcssa:
@@ -95,7 +95,7 @@ define void @pr56282() {
; CHECK: inner.2.preheader:
; CHECK-NEXT: br label [[INNER_2]]
; CHECK: inner.2:
-; CHECK-NEXT: [[OUTER_IV_NEXT]] = add nuw i64 [[OUTER_IV]], 1
+; CHECK-NEXT: [[OUTER_IV_NEXT]] = add nuw nsw i64 [[OUTER_IV]], 1
; CHECK-NEXT: br label [[OUTER_HEADER]]
; CHECK: exit:
; CHECK-NEXT: ret void
@@ -188,7 +188,7 @@ define void @pr56286(i64 %x, ptr %src, ptr %dst, ptr %ptr.src) !prof !0 {
; CHECK-NEXT: [[L_1_LCSSA_UNR:%.*]] = phi i32 [ poison, [[OUTER_HEADER]] ], [ [[L_1_LCSSA_UNR_PH]], [[INNER_1_HEADER_PROL_LOOPEXIT_UNR_LCSSA]] ]
; CHECK-NEXT: [[INNER_1_IV_UNR:%.*]] = phi i64 [ [[X]], [[OUTER_HEADER]] ], [ [[INNER_1_IV_UNR_PH]], [[INNER_1_HEADER_PROL_LOOPEXIT_UNR_LCSSA]] ]
; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 7
-; CHECK-NEXT: br i1 [[TMP4]], label [[OUTER_MIDDLE:%.*]], label [[OUTER_HEADER_NEW:%.*]], !prof [[PROF6:![0-9]+]]
+; CHECK-NEXT: br i1 [[TMP4]], label [[OUTER_MIDDLE:%.*]], label [[OUTER_HEADER_NEW:%.*]], !prof [[PROF3]]
; CHECK: outer.header.new:
; CHECK-NEXT: br label [[INNER_1_HEADER:%.*]]
; CHECK: inner.1.header:
@@ -232,7 +232,7 @@ define void @pr56286(i64 %x, ptr %src, ptr %dst, ptr %ptr.src) !prof !0 {
; CHECK-NEXT: store i32 [[L_1_7]], ptr [[DST]], align 8
; CHECK-NEXT: [[INNER_1_IV_NEXT_7]] = add i64 [[INNER_1_IV]], 8
; CHECK-NEXT: [[CMP_2_7:%.*]] = icmp sgt i64 [[INNER_1_IV_NEXT_6]], 0
-; CHECK-NEXT: br i1 [[CMP_2_7]], label [[OUTER_MIDDLE_UNR_LCSSA:%.*]], label [[INNER_1_HEADER]], !prof [[PROF7:![0-9]+]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK-NEXT: br i1 [[CMP_2_7]], label [[OUTER_MIDDLE_UNR_LCSSA:%.*]], label [[INNER_1_HEADER]], !prof [[PROF6:![0-9]+]], !llvm.loop [[LOOP7:![0-9]+]]
; CHECK: outer.middle.unr-lcssa:
; CHECK-NEXT: [[L_1_LCSSA_PH:%.*]] = phi i32 [ [[L_1_7]], [[INNER_1_LATCH_7]] ]
; CHECK-NEXT: br label [[OUTER_MIDDLE]]
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-i128.ll b/llvm/test/Transforms/LoopUnroll/runtime-i128.ll
index fec8626e8c59c..e5955c59e2ca4 100644
--- a/llvm/test/Transforms/LoopUnroll/runtime-i128.ll
+++ b/llvm/test/Transforms/LoopUnroll/runtime-i128.ll
@@ -26,8 +26,8 @@ define void @test(i128 %n, i128 %m) {
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: call void @foo()
-; CHECK-NEXT: [[IV_NEXT_7]] = add i128 [[IV]], 8
-; CHECK-NEXT: [[NITER_NEXT_7]] = add i128 [[NITER]], 8
+; CHECK-NEXT: [[IV_NEXT_7]] = add nsw i128 [[IV]], 8
+; CHECK-NEXT: [[NITER_NEXT_7]] = add nsw i128 [[NITER]], 8
; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp ne i128 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label [[LOOP]], label [[EXIT_UNR_LCSSA:%.*]]
; CHECK: exit.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-loop-at-most-two-exits.ll b/llvm/test/Transforms/LoopUnroll/runtime-loop-at-most-two-exits.ll
index 85de29de750fa..75e6a1fbcd2b8 100644
--- a/llvm/test/Transforms/LoopUnroll/runtime-loop-at-most-two-exits.ll
+++ b/llvm/test/Transforms/LoopUnroll/runtime-loop-at-most-two-exits.ll
@@ -68,8 +68,8 @@ define i32 @test(ptr nocapture %a, i64 %n) {
; ENABLED-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_6]]
; ENABLED-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4
; ENABLED-NEXT: [[ADD_7]] = add nsw i32 [[TMP10]], [[ADD_6]]
-; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add i64 [[INDVARS_IV]], 8
-; ENABLED-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add nsw i64 [[INDVARS_IV]], 8
+; ENABLED-NEXT: [[NITER_NEXT_7]] = add nsw i64 [[NITER]], 8
; ENABLED-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; ENABLED-NEXT: br i1 [[NITER_NCMP_7]], label [[FOR_END_UNR_LCSSA:%.*]], label [[HEADER]]
; ENABLED: for.end.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll b/llvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll
index 8746df07621f0..573231ca58062 100644
--- a/llvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll
+++ b/llvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll
@@ -76,8 +76,8 @@ define void @test1(i64 %trip, i1 %cond) {
; EPILOG: loop_exiting_bb2.7:
; EPILOG-NEXT: br i1 false, label %loop_latch.7, label %exit3.loopexit
; EPILOG: loop_latch.7:
-; EPILOG-NEXT: %iv_next.7 = add i64 %iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %iv_next.7 = add nsw i64 %iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nsw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit2.loopexit.unr-lcssa
; EPILOG: exit1.loopexit:
@@ -143,8 +143,8 @@ define void @test1(i64 %trip, i1 %cond) {
; EPILOG-BLOCK: loop_exiting_bb2.1:
; EPILOG-BLOCK-NEXT: br i1 false, label %loop_latch.1, label %exit3.loopexit
; EPILOG-BLOCK: loop_latch.1:
-; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %iv_next.1 = add nsw i64 %iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nsw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit2.loopexit.unr-lcssa, !llvm.loop !0
; EPILOG-BLOCK: exit1.loopexit:
@@ -445,8 +445,8 @@ define i32 @test2(ptr nocapture %a, i64 %n) {
; EPILOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6
; EPILOG-NEXT: %10 = load i32, ptr %arrayidx.7, align 4
; EPILOG-NEXT: %add.7 = add nsw i32 %10, %add.6
-; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %indvars.iv.next.7 = add nsw i64 %indvars.iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nsw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %for.end.unr-lcssa, label %header
; EPILOG: for.end.unr-lcssa:
@@ -525,8 +525,8 @@ define i32 @test2(ptr nocapture %a, i64 %n) {
; EPILOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; EPILOG-BLOCK-NEXT: %4 = load i32, ptr %arrayidx.1, align 4
; EPILOG-BLOCK-NEXT: %add.1 = add nsw i32 %4, %add
-; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add nsw i64 %indvars.iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nsw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %for.end.unr-lcssa, label %header, !llvm.loop !2
; EPILOG-BLOCK: for.end.unr-lcssa:
@@ -873,7 +873,7 @@ define void @test3(i64 %trip, i64 %add, i1 %arg) {
; EPILOG: loop_latch.7:
; EPILOG-NEXT: %iv_next.7 = add nuw nsw i64 %iv, 8
; EPILOG-NEXT: %sum.next.7 = add i64 %sum.next.6, %add
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %niter.next.7 = add nsw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit2.loopexit.unr-lcssa
; EPILOG: exit1.loopexit:
@@ -950,7 +950,7 @@ define void @test3(i64 %trip, i64 %add, i1 %arg) {
; EPILOG-BLOCK: loop_latch.1:
; EPILOG-BLOCK-NEXT: %iv_next.1 = add nuw nsw i64 %iv, 2
; EPILOG-BLOCK-NEXT: %sum.next.1 = add i64 %sum.next, %add
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nsw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit2.loopexit.unr-lcssa, !llvm.loop !3
; EPILOG-BLOCK: exit1.loopexit:
@@ -1281,8 +1281,8 @@ define i32 @hdr_latch_same_exit(ptr nocapture %a, i64 %n, i1 %cond) {
; EPILOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6
; EPILOG-NEXT: %10 = load i32, ptr %arrayidx.7, align 4
; EPILOG-NEXT: %add.7 = add nsw i32 %10, %add.6
-; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %indvars.iv.next.7 = add nsw i64 %indvars.iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nsw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %latchExit.unr-lcssa, label %header
; EPILOG: latchExit.unr-lcssa:
@@ -1364,8 +1364,8 @@ define i32 @hdr_latch_same_exit(ptr nocapture %a, i64 %n, i1 %cond) {
; EPILOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; EPILOG-BLOCK-NEXT: %4 = load i32, ptr %arrayidx.1, align 4
; EPILOG-BLOCK-NEXT: %add.1 = add nsw i32 %4, %add
-; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add nsw i64 %indvars.iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nsw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %latchExit.unr-lcssa, label %header, !llvm.loop !4
; EPILOG-BLOCK: latchExit.unr-lcssa:
@@ -1719,8 +1719,8 @@ define i32 @otherblock_latch_same_exit(ptr nocapture %a, i64 %n, i1 %cond) {
; EPILOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6
; EPILOG-NEXT: %10 = load i32, ptr %arrayidx.7, align 4
; EPILOG-NEXT: %add.7 = add nsw i32 %10, %add.6
-; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %indvars.iv.next.7 = add nsw i64 %indvars.iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nsw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %latchExit.unr-lcssa, label %header
; EPILOG: latchExit.unr-lcssa:
@@ -1802,8 +1802,8 @@ define i32 @otherblock_latch_same_exit(ptr nocapture %a, i64 %n, i1 %cond) {
; EPILOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; EPILOG-BLOCK-NEXT: %4 = load i32, ptr %arrayidx.1, align 4
; EPILOG-BLOCK-NEXT: %add.1 = add nsw i32 %4, %add
-; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add nsw i64 %indvars.iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nsw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %latchExit.unr-lcssa, label %header, !llvm.loop !5
; EPILOG-BLOCK: latchExit.unr-lcssa:
@@ -2158,8 +2158,8 @@ define i32 @otherblock_latch_same_exit2(ptr nocapture %a, i64 %n, i1 %cond) {
; EPILOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6
; EPILOG-NEXT: %10 = load i32, ptr %arrayidx.7, align 4
; EPILOG-NEXT: %add.7 = add nsw i32 %10, %add.6
-; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %indvars.iv.next.7 = add nsw i64 %indvars.iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nsw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %latchExit.unr-lcssa, label %header
; EPILOG: latchExit.unr-lcssa:
@@ -2241,8 +2241,8 @@ define i32 @otherblock_latch_same_exit2(ptr nocapture %a, i64 %n, i1 %cond) {
; EPILOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; EPILOG-BLOCK-NEXT: %4 = load i32, ptr %arrayidx.1, align 4
; EPILOG-BLOCK-NEXT: %add.1 = add nsw i32 %4, %add
-; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add nsw i64 %indvars.iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nsw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %latchExit.unr-lcssa, label %header, !llvm.loop !6
; EPILOG-BLOCK: latchExit.unr-lcssa:
@@ -2598,8 +2598,8 @@ define i32 @otherblock_latch_same_exit3(ptr nocapture %a, i64 %n, i1 %cond) {
; EPILOG-NEXT: %cmp.7 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.7, label %latchExit.epilog-lcssa.loopexit, label %latch.7
; EPILOG: latch.7:
-; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %indvars.iv.next.7 = add nsw i64 %indvars.iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nsw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %latchExit.unr-lcssa, label %header
; EPILOG: latchExit.unr-lcssa:
@@ -2681,8 +2681,8 @@ define i32 @otherblock_latch_same_exit3(ptr nocapture %a, i64 %n, i1 %cond) {
; EPILOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42
; EPILOG-BLOCK-NEXT: br i1 %cmp.1, label %latchExit.epilog-lcssa.loopexit, label %latch.1
; EPILOG-BLOCK: latch.1:
-; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add nsw i64 %indvars.iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nsw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %latchExit.unr-lcssa, label %header, !llvm.loop !7
; EPILOG-BLOCK: latchExit.unr-lcssa:
@@ -3038,11 +3038,11 @@ define void @unique_exit(i32 %N, i32 %M) {
; EPILOG-NEXT: %cmp1.6 = icmp ult i32 %inc.6, %N
; EPILOG-NEXT: br i1 %cmp1.6, label %latch.6, label %latchExit.epilog-lcssa.loopexit
; EPILOG: latch.6:
-; EPILOG-NEXT: %inc.7 = add nuw i32 %i4, 8
+; EPILOG-NEXT: %inc.7 = add nuw nsw i32 %i4, 8
; EPILOG-NEXT: %cmp1.7 = icmp ult i32 %inc.7, %N
; EPILOG-NEXT: br i1 %cmp1.7, label %latch.7, label %latchExit.epilog-lcssa.loopexit
; EPILOG: latch.7:
-; EPILOG-NEXT: %niter.next.7 = add nuw i32 %niter, 8
+; EPILOG-NEXT: %niter.next.7 = add nuw nsw i32 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i32 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %header, label %latchExit.unr-lcssa
; EPILOG: latchExit.unr-lcssa:
@@ -3098,11 +3098,11 @@ define void @unique_exit(i32 %N, i32 %M) {
; EPILOG-BLOCK-NEXT: %cmp1 = icmp ult i32 %inc, %N
; EPILOG-BLOCK-NEXT: br i1 %cmp1, label %latch, label %latchExit.epilog-lcssa.loopexit
; EPILOG-BLOCK: latch:
-; EPILOG-BLOCK-NEXT: %inc.1 = add nuw i32 %i4, 2
+; EPILOG-BLOCK-NEXT: %inc.1 = add nuw nsw i32 %i4, 2
; EPILOG-BLOCK-NEXT: %cmp1.1 = icmp ult i32 %inc.1, %N
; EPILOG-BLOCK-NEXT: br i1 %cmp1.1, label %latch.1, label %latchExit.epilog-lcssa.loopexit
; EPILOG-BLOCK: latch.1:
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add nuw i32 %niter, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nuw nsw i32 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i32 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %header, label %latchExit.unr-lcssa, !llvm.loop !8
; EPILOG-BLOCK: latchExit.unr-lcssa:
@@ -3166,35 +3166,35 @@ define void @unique_exit(i32 %N, i32 %M) {
; PROLOG-NEXT: br label %header
; PROLOG: header:
; PROLOG-NEXT: %i4 = phi i32 [ %i4.unr, %preheader.new ], [ %inc.7, %latch.7 ]
-; PROLOG-NEXT: %inc = add nuw i32 %i4, 1
+; PROLOG-NEXT: %inc = add nuw nsw i32 %i4, 1
; PROLOG-NEXT: %cmp1 = icmp ult i32 %inc, %N
; PROLOG-NEXT: br i1 %cmp1, label %latch, label %latchExit.unr-lcssa.loopexit
; PROLOG: latch:
-; PROLOG-NEXT: %inc.1 = add nuw i32 %i4, 2
+; PROLOG-NEXT: %inc.1 = add nuw nsw i32 %i4, 2
; PROLOG-NEXT: %cmp1.1 = icmp ult i32 %inc.1, %N
; PROLOG-NEXT: br i1 %cmp1.1, label %latch.1, label %latchExit.unr-lcssa.loopexit
; PROLOG: latch.1:
-; PROLOG-NEXT: %inc.2 = add nuw i32 %i4, 3
+; PROLOG-NEXT: %inc.2 = add nuw nsw i32 %i4, 3
; PROLOG-NEXT: %cmp1.2 = icmp ult i32 %inc.2, %N
; PROLOG-NEXT: br i1 %cmp1.2, label %latch.2, label %latchExit.unr-lcssa.loopexit
; PROLOG: latch.2:
-; PROLOG-NEXT: %inc.3 = add nuw i32 %i4, 4
+; PROLOG-NEXT: %inc.3 = add nuw nsw i32 %i4, 4
; PROLOG-NEXT: %cmp1.3 = icmp ult i32 %inc.3, %N
; PROLOG-NEXT: br i1 %cmp1.3, label %latch.3, label %latchExit.unr-lcssa.loopexit
; PROLOG: latch.3:
-; PROLOG-NEXT: %inc.4 = add nuw i32 %i4, 5
+; PROLOG-NEXT: %inc.4 = add nuw nsw i32 %i4, 5
; PROLOG-NEXT: %cmp1.4 = icmp ult i32 %inc.4, %N
; PROLOG-NEXT: br i1 %cmp1.4, label %latch.4, label %latchExit.unr-lcssa.loopexit
; PROLOG: latch.4:
-; PROLOG-NEXT: %inc.5 = add nuw i32 %i4, 6
+; PROLOG-NEXT: %inc.5 = add nuw nsw i32 %i4, 6
; PROLOG-NEXT: %cmp1.5 = icmp ult i32 %inc.5, %N
; PROLOG-NEXT: br i1 %cmp1.5, label %latch.5, label %latchExit.unr-lcssa.loopexit
; PROLOG: latch.5:
-; PROLOG-NEXT: %inc.6 = add nuw i32 %i4, 7
+; PROLOG-NEXT: %inc.6 = add nuw nsw i32 %i4, 7
; PROLOG-NEXT: %cmp1.6 = icmp ult i32 %inc.6, %N
; PROLOG-NEXT: br i1 %cmp1.6, label %latch.6, label %latchExit.unr-lcssa.loopexit
; PROLOG: latch.6:
-; PROLOG-NEXT: %inc.7 = add nuw i32 %i4, 8
+; PROLOG-NEXT: %inc.7 = add nuw nsw i32 %i4, 8
; PROLOG-NEXT: %cmp1.7 = icmp ult i32 %inc.7, %N
; PROLOG-NEXT: br i1 %cmp1.7, label %latch.7, label %latchExit.unr-lcssa.loopexit
; PROLOG: latch.7:
@@ -3238,11 +3238,11 @@ define void @unique_exit(i32 %N, i32 %M) {
; PROLOG-BLOCK-NEXT: br label %header
; PROLOG-BLOCK: header:
; PROLOG-BLOCK-NEXT: %i4 = phi i32 [ %i4.unr, %preheader.new ], [ %inc.1, %latch.1 ]
-; PROLOG-BLOCK-NEXT: %inc = add nuw i32 %i4, 1
+; PROLOG-BLOCK-NEXT: %inc = add nuw nsw i32 %i4, 1
; PROLOG-BLOCK-NEXT: %cmp1 = icmp ult i32 %inc, %N
; PROLOG-BLOCK-NEXT: br i1 %cmp1, label %latch, label %latchExit.unr-lcssa.loopexit
; PROLOG-BLOCK: latch:
-; PROLOG-BLOCK-NEXT: %inc.1 = add nuw i32 %i4, 2
+; PROLOG-BLOCK-NEXT: %inc.1 = add nuw nsw i32 %i4, 2
; PROLOG-BLOCK-NEXT: %cmp1.1 = icmp ult i32 %inc.1, %N
; PROLOG-BLOCK-NEXT: br i1 %cmp1.1, label %latch.1, label %latchExit.unr-lcssa.loopexit
; PROLOG-BLOCK: latch.1:
@@ -3298,7 +3298,7 @@ define i64 @test5(i64 %trip, i64 %add, i1 %cond) {
; EPILOG-NEXT: %niter = phi i64 [ 0, %entry.new ], [ %niter.next.7, %loop_latch.7 ]
; EPILOG-NEXT: br i1 %cond, label %loop_latch, label %loop_exiting
; EPILOG: loop_exiting:
-; EPILOG-NEXT: %ivy = add i64 %iv, %add
+; EPILOG-NEXT: %ivy = add nsw i64 %iv, %add
; EPILOG-NEXT: switch i64 %sum, label %loop_latch [
; EPILOG-NEXT: i64 24, label %exit1.loopexit
; EPILOG-NEXT: i64 42, label %exit1.loopexit
@@ -3376,7 +3376,7 @@ define i64 @test5(i64 %trip, i64 %add, i1 %cond) {
; EPILOG: loop_latch.7:
; EPILOG-NEXT: %iv_next.7 = add nuw nsw i64 %iv, 8
; EPILOG-NEXT: %sum.next.7 = add i64 %sum.next.6, %add
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %niter.next.7 = add nsw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %latchexit.unr-lcssa
; EPILOG: exit1.loopexit:
@@ -3441,7 +3441,7 @@ define i64 @test5(i64 %trip, i64 %add, i1 %cond) {
; EPILOG-BLOCK-NEXT: %niter = phi i64 [ 0, %entry.new ], [ %niter.next.1, %loop_latch.1 ]
; EPILOG-BLOCK-NEXT: br i1 %cond, label %loop_latch, label %loop_exiting
; EPILOG-BLOCK: loop_exiting:
-; EPILOG-BLOCK-NEXT: %ivy = add i64 %iv, %add
+; EPILOG-BLOCK-NEXT: %ivy = add nsw i64 %iv, %add
; EPILOG-BLOCK-NEXT: switch i64 %sum, label %loop_latch [
; EPILOG-BLOCK-NEXT: i64 24, label %exit1.loopexit
; EPILOG-BLOCK-NEXT: i64 42, label %exit1.loopexit
@@ -3459,7 +3459,7 @@ define i64 @test5(i64 %trip, i64 %add, i1 %cond) {
; EPILOG-BLOCK: loop_latch.1:
; EPILOG-BLOCK-NEXT: %iv_next.1 = add nuw nsw i64 %iv, 2
; EPILOG-BLOCK-NEXT: %sum.next.1 = add i64 %sum.next, %add
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nsw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %latchexit.unr-lcssa, !llvm.loop !9
; EPILOG-BLOCK: exit1.loopexit:
@@ -3817,8 +3817,8 @@ define i32 @test6(ptr nocapture %a, i64 %n, i1 %cond, i32 %x) {
; EPILOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6
; EPILOG-NEXT: %load.7 = load i32, ptr %arrayidx.7, align 4
; EPILOG-NEXT: %add.7 = add nsw i32 %load.7, %add.6
-; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %indvars.iv.next.7 = add nsw i64 %indvars.iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nsw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %latch_exit.unr-lcssa, label %header
; EPILOG: latch_exit.unr-lcssa:
@@ -3902,8 +3902,8 @@ define i32 @test6(ptr nocapture %a, i64 %n, i1 %cond, i32 %x) {
; EPILOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; EPILOG-BLOCK-NEXT: %load.1 = load i32, ptr %arrayidx.1, align 4
; EPILOG-BLOCK-NEXT: %add.1 = add nsw i32 %load.1, %add
-; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add nsw i64 %indvars.iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nsw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %latch_exit.unr-lcssa, label %header, !llvm.loop !10
; EPILOG-BLOCK: latch_exit.unr-lcssa:
@@ -4221,7 +4221,7 @@ define i32 @test7(i32 %arg, i32 %arg1, i32 %arg2) {
; EPILOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.7
; EPILOG: latch.7:
; EPILOG-NEXT: %add.7 = add nuw nsw i64 %i6, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %niter.next.7 = add nsw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %header, label %latchexit.unr-lcssa
; EPILOG: latchexit.unr-lcssa:
@@ -4283,7 +4283,7 @@ define i32 @test7(i32 %arg, i32 %arg1, i32 %arg2) {
; EPILOG-BLOCK-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.1
; EPILOG-BLOCK: latch.1:
; EPILOG-BLOCK-NEXT: %add.1 = add nuw nsw i64 %i6, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nsw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %header, label %latchexit.unr-lcssa, !llvm.loop !11
; EPILOG-BLOCK: latchexit.unr-lcssa:
@@ -4800,7 +4800,7 @@ define ptr addrspace(1) @test9(ptr nocapture readonly %arg, i32 %n) {
; EPILOG-NEXT: br i1 true, label %latch.7, label %innerexit.loopexit
; EPILOG: latch.7:
; EPILOG-NEXT: %iv.next.7 = add nuw nsw i64 %phi, 8
-; EPILOG-NEXT: %niter.next.7 = add i32 %niter, 8
+; EPILOG-NEXT: %niter.next.7 = add nsw i32 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i32 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %header, label %outerLatch.loopexit.unr-lcssa
; EPILOG: outerLatch.loopexit.unr-lcssa:
@@ -4871,7 +4871,7 @@ define ptr addrspace(1) @test9(ptr nocapture readonly %arg, i32 %n) {
; EPILOG-BLOCK-NEXT: br i1 true, label %latch.1, label %innerexit.loopexit.loopexit
; EPILOG-BLOCK: latch.1:
; EPILOG-BLOCK-NEXT: %iv.next.1 = add nuw nsw i64 %phi, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i32 %niter, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nsw i32 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i32 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %header, label %outerLatch.loopexit.unr-lcssa, !llvm.loop !14
; EPILOG-BLOCK: outerLatch.loopexit.unr-lcssa:
@@ -4908,7 +4908,7 @@ define ptr addrspace(1) @test9(ptr nocapture readonly %arg, i32 %n) {
; EPILOG-BLOCK-NEXT: br i1 true, label %latch.1.1, label %innerexit.loopexit.loopexit5
; EPILOG-BLOCK: latch.1.1:
; EPILOG-BLOCK-NEXT: %iv.next.1.1 = add nuw nsw i64 %phi.1, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1.1 = add i32 %niter.1, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1.1 = add nsw i32 %niter.1, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1.1 = icmp ne i32 %niter.next.1.1, %unroll_iter.1
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1.1, label %header.1, label %outerLatch.loopexit.unr-lcssa.1, !llvm.loop !14
; EPILOG-BLOCK: outerLatch.loopexit.unr-lcssa.1:
@@ -5192,8 +5192,8 @@ define void @test10(i64 %trip, i64 %trip2) {
; EPILOG-NEXT: %cmp_early.7 = icmp ne i64 %iv_next.6, %trip2
; EPILOG-NEXT: br i1 %cmp_early.7, label %loop_latch.7, label %exit1.loopexit
; EPILOG: loop_latch.7:
-; EPILOG-NEXT: %iv_next.7 = add i64 %iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %iv_next.7 = add nsw i64 %iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nsw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit2.unr-lcssa
; EPILOG: exit1.loopexit:
@@ -5250,8 +5250,8 @@ define void @test10(i64 %trip, i64 %trip2) {
; EPILOG-BLOCK-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2
; EPILOG-BLOCK-NEXT: br i1 %cmp_early.1, label %loop_latch.1, label %exit1.loopexit
; EPILOG-BLOCK: loop_latch.1:
-; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %iv_next.1 = add nsw i64 %iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nsw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit2.unr-lcssa, !llvm.loop !16
; EPILOG-BLOCK: exit1.loopexit:
@@ -5466,8 +5466,8 @@ define void @test11(i64 %trip, i1 %cond) {
; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: br i1 %cond, label %loop_latch.7, label %exit1.loopexit
; EPILOG: loop_latch.7:
-; EPILOG-NEXT: %iv_next.7 = add i64 %iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %iv_next.7 = add nsw i64 %iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nsw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit2.unr-lcssa
; EPILOG: exit1.loopexit:
@@ -5520,8 +5520,8 @@ define void @test11(i64 %trip, i1 %cond) {
; EPILOG-BLOCK-NEXT: call void @bar()
; EPILOG-BLOCK-NEXT: br i1 %cond, label %loop_latch.1, label %exit1.loopexit
; EPILOG-BLOCK: loop_latch.1:
-; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %iv_next.1 = add nsw i64 %iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nsw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit2.unr-lcssa, !llvm.loop !17
; EPILOG-BLOCK: exit1.loopexit:
@@ -5743,8 +5743,8 @@ define void @test12(i64 %trip, i64 %trip2, i1 %cond) {
; EPILOG: loop_exiting_bb2.7:
; EPILOG-NEXT: br i1 %cond, label %loop_latch.7, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.7:
-; EPILOG-NEXT: %iv_next.7 = add i64 %iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %iv_next.7 = add nsw i64 %iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nsw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit1.unr-lcssa
; EPILOG: exit1.unr-lcssa:
@@ -5805,8 +5805,8 @@ define void @test12(i64 %trip, i64 %trip2, i1 %cond) {
; EPILOG-BLOCK: loop_exiting_bb2.1:
; EPILOG-BLOCK-NEXT: br i1 %cond, label %loop_latch.1, label %exit1.epilog-lcssa.loopexit
; EPILOG-BLOCK: loop_latch.1:
-; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %iv_next.1 = add nsw i64 %iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nsw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit1.unr-lcssa, !llvm.loop !18
; EPILOG-BLOCK: exit1.unr-lcssa:
@@ -6083,8 +6083,8 @@ define void @test13(i64 %trip, i64 %trip2) {
; EPILOG-NEXT: %unknown.7 = call i1 @unknown_cond()
; EPILOG-NEXT: br i1 %unknown.7, label %loop_latch.7, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.7:
-; EPILOG-NEXT: %iv_next.7 = add i64 %iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %iv_next.7 = add nsw i64 %iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nsw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit1.unr-lcssa
; EPILOG: exit1.unr-lcssa:
@@ -6148,8 +6148,8 @@ define void @test13(i64 %trip, i64 %trip2) {
; EPILOG-BLOCK-NEXT: %unknown.1 = call i1 @unknown_cond()
; EPILOG-BLOCK-NEXT: br i1 %unknown.1, label %loop_latch.1, label %exit1.epilog-lcssa.loopexit
; EPILOG-BLOCK: loop_latch.1:
-; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %iv_next.1 = add nsw i64 %iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nsw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit1.unr-lcssa, !llvm.loop !19
; EPILOG-BLOCK: exit1.unr-lcssa:
@@ -6423,8 +6423,8 @@ define void @test14(i64 %trip, i1 %cond) {
; EPILOG-NEXT: %unknown.7 = call i1 @unknown_cond()
; EPILOG-NEXT: br i1 %unknown.7, label %loop_latch.7, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.7:
-; EPILOG-NEXT: %iv_next.7 = add i64 %iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %iv_next.7 = add nsw i64 %iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nsw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit1.unr-lcssa
; EPILOG: exit1.unr-lcssa:
@@ -6484,8 +6484,8 @@ define void @test14(i64 %trip, i1 %cond) {
; EPILOG-BLOCK-NEXT: %unknown.1 = call i1 @unknown_cond()
; EPILOG-BLOCK-NEXT: br i1 %unknown.1, label %loop_latch.1, label %exit1.epilog-lcssa.loopexit
; EPILOG-BLOCK: loop_latch.1:
-; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %iv_next.1 = add nsw i64 %iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nsw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit1.unr-lcssa, !llvm.loop !20
; EPILOG-BLOCK: exit1.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-multiexit-heuristic.ll b/llvm/test/Transforms/LoopUnroll/runtime-multiexit-heuristic.ll
index 99276e44095e6..ea9dfe5838a99 100644
--- a/llvm/test/Transforms/LoopUnroll/runtime-multiexit-heuristic.ll
+++ b/llvm/test/Transforms/LoopUnroll/runtime-multiexit-heuristic.ll
@@ -32,67 +32,67 @@ define i32 @test1(ptr nocapture %a, i64 %n) {
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[TMP0]], 42
; CHECK-NEXT: br i1 [[CMP]], label [[OTHEREXIT_LOOPEXIT:%.*]], label [[LATCH:%.*]]
; CHECK: latch:
-; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i8], ptr [[A:%.*]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A:%.*]], i64 [[INDVARS_IV]]
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[SUM_02]]
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_1:%.*]]
; CHECK: for.exiting_block.1:
; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_1:%.*]]
; CHECK: latch.1:
-; CHECK-NEXT: [[TMP13:%.*]] = getelementptr [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
-; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr i8, ptr [[TMP13]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP13]], i64 4
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4
; CHECK-NEXT: [[ADD_1:%.*]] = add nsw i32 [[TMP4]], [[ADD]]
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_2:%.*]]
; CHECK: for.exiting_block.2:
; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_2:%.*]]
; CHECK: latch.2:
-; CHECK-NEXT: [[TMP15:%.*]] = getelementptr [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
-; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr i8, ptr [[TMP15]], i64 8
+; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP15]], i64 8
; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4
; CHECK-NEXT: [[ADD_2:%.*]] = add nsw i32 [[TMP5]], [[ADD_1]]
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_3:%.*]]
; CHECK: for.exiting_block.3:
; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_3:%.*]]
; CHECK: latch.3:
-; CHECK-NEXT: [[TMP17:%.*]] = getelementptr [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
-; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr i8, ptr [[TMP17]], i64 12
+; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP17]], i64 12
; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4
; CHECK-NEXT: [[ADD_3:%.*]] = add nsw i32 [[TMP6]], [[ADD_2]]
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_4:%.*]]
; CHECK: for.exiting_block.4:
; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_4:%.*]]
; CHECK: latch.4:
-; CHECK-NEXT: [[TMP18:%.*]] = getelementptr [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
-; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr i8, ptr [[TMP18]], i64 16
+; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP18]], i64 16
; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX_4]], align 4
; CHECK-NEXT: [[ADD_4:%.*]] = add nsw i32 [[TMP7]], [[ADD_3]]
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_5:%.*]]
; CHECK: for.exiting_block.5:
; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_5:%.*]]
; CHECK: latch.5:
-; CHECK-NEXT: [[TMP12:%.*]] = getelementptr [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
-; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr i8, ptr [[TMP12]], i64 20
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP12]], i64 20
; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX_5]], align 4
; CHECK-NEXT: [[ADD_5:%.*]] = add nsw i32 [[TMP8]], [[ADD_4]]
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_6:%.*]]
; CHECK: for.exiting_block.6:
; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_6:%.*]]
; CHECK: latch.6:
-; CHECK-NEXT: [[TMP14:%.*]] = getelementptr [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
-; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr i8, ptr [[TMP14]], i64 24
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP14]], i64 24
; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX_6]], align 4
; CHECK-NEXT: [[ADD_6:%.*]] = add nsw i32 [[TMP9]], [[ADD_5]]
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_7:%.*]]
; CHECK: for.exiting_block.7:
; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_7]]
; CHECK: latch.7:
-; CHECK-NEXT: [[TMP16:%.*]] = getelementptr [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
-; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr i8, ptr [[TMP16]], i64 28
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP16]], i64 28
; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4
; CHECK-NEXT: [[ADD_7]] = add nsw i32 [[TMP10]], [[ADD_6]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_7]] = add i64 [[INDVARS_IV]], 8
-; CHECK-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; CHECK-NEXT: [[INDVARS_IV_NEXT_7]] = add nuw nsw i64 [[INDVARS_IV]], 8
+; CHECK-NEXT: [[NITER_NEXT_7]] = add nuw nsw i64 [[NITER]], 8
; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label [[LATCHEXIT_UNR_LCSSA:%.*]], label [[HEADER]]
; CHECK: latchexit.unr-lcssa:
@@ -244,8 +244,8 @@ define i32 @test1(ptr nocapture %a, i64 %n) {
; ENABLED-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_6]]
; ENABLED-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4
; ENABLED-NEXT: [[ADD_7]] = add nsw i32 [[TMP10]], [[ADD_6]]
-; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add i64 [[INDVARS_IV]], 8
-; ENABLED-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add nsw i64 [[INDVARS_IV]], 8
+; ENABLED-NEXT: [[NITER_NEXT_7]] = add nsw i64 [[NITER]], 8
; ENABLED-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; ENABLED-NEXT: br i1 [[NITER_NCMP_7]], label [[LATCHEXIT_UNR_LCSSA:%.*]], label [[HEADER]]
; ENABLED: latchexit.unr-lcssa:
@@ -457,8 +457,8 @@ define i32 @test2(ptr nocapture %a, i64 %n) {
; ENABLED-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_6]]
; ENABLED-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4
; ENABLED-NEXT: [[ADD_7]] = add nsw i32 [[TMP10]], [[ADD_6]]
-; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add i64 [[INDVARS_IV]], 8
-; ENABLED-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add nsw i64 [[INDVARS_IV]], 8
+; ENABLED-NEXT: [[NITER_NEXT_7]] = add nsw i64 [[NITER]], 8
; ENABLED-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; ENABLED-NEXT: br i1 [[NITER_NCMP_7]], label [[LATCHEXIT_UNR_LCSSA:%.*]], label [[HEADER]]
; ENABLED: latchexit.unr-lcssa:
@@ -757,67 +757,67 @@ define i32 @test5(ptr nocapture %a, i64 %n) {
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[TMP0]], 42
; CHECK-NEXT: br i1 [[CMP]], label [[OTHEREXIT_LOOPEXIT:%.*]], label [[LATCH:%.*]]
; CHECK: latch:
-; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i8], ptr [[A:%.*]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A:%.*]], i64 [[INDVARS_IV]]
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[SUM_02]]
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_1:%.*]]
; CHECK: for.exiting_block.1:
; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_1:%.*]]
; CHECK: latch.1:
-; CHECK-NEXT: [[TMP13:%.*]] = getelementptr [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
-; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr i8, ptr [[TMP13]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP13]], i64 4
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4
; CHECK-NEXT: [[ADD_1:%.*]] = add nsw i32 [[TMP4]], [[ADD]]
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_2:%.*]]
; CHECK: for.exiting_block.2:
; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_2:%.*]]
; CHECK: latch.2:
-; CHECK-NEXT: [[TMP15:%.*]] = getelementptr [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
-; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr i8, ptr [[TMP15]], i64 8
+; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP15]], i64 8
; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4
; CHECK-NEXT: [[ADD_2:%.*]] = add nsw i32 [[TMP5]], [[ADD_1]]
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_3:%.*]]
; CHECK: for.exiting_block.3:
; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_3:%.*]]
; CHECK: latch.3:
-; CHECK-NEXT: [[TMP17:%.*]] = getelementptr [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
-; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr i8, ptr [[TMP17]], i64 12
+; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP17]], i64 12
; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4
; CHECK-NEXT: [[ADD_3:%.*]] = add nsw i32 [[TMP6]], [[ADD_2]]
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_4:%.*]]
; CHECK: for.exiting_block.4:
; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_4:%.*]]
; CHECK: latch.4:
-; CHECK-NEXT: [[TMP18:%.*]] = getelementptr [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
-; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr i8, ptr [[TMP18]], i64 16
+; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP18]], i64 16
; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX_4]], align 4
; CHECK-NEXT: [[ADD_4:%.*]] = add nsw i32 [[TMP7]], [[ADD_3]]
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_5:%.*]]
; CHECK: for.exiting_block.5:
; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_5:%.*]]
; CHECK: latch.5:
-; CHECK-NEXT: [[TMP12:%.*]] = getelementptr [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
-; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr i8, ptr [[TMP12]], i64 20
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP12]], i64 20
; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX_5]], align 4
; CHECK-NEXT: [[ADD_5:%.*]] = add nsw i32 [[TMP8]], [[ADD_4]]
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_6:%.*]]
; CHECK: for.exiting_block.6:
; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_6:%.*]]
; CHECK: latch.6:
-; CHECK-NEXT: [[TMP14:%.*]] = getelementptr [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
-; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr i8, ptr [[TMP14]], i64 24
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP14]], i64 24
; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX_6]], align 4
; CHECK-NEXT: [[ADD_6:%.*]] = add nsw i32 [[TMP9]], [[ADD_5]]
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_7:%.*]]
; CHECK: for.exiting_block.7:
; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_7]]
; CHECK: latch.7:
-; CHECK-NEXT: [[TMP16:%.*]] = getelementptr [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
-; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr i8, ptr [[TMP16]], i64 28
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP16]], i64 28
; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4
; CHECK-NEXT: [[ADD_7]] = add nsw i32 [[TMP10]], [[ADD_6]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_7]] = add i64 [[INDVARS_IV]], 8
-; CHECK-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; CHECK-NEXT: [[INDVARS_IV_NEXT_7]] = add nuw nsw i64 [[INDVARS_IV]], 8
+; CHECK-NEXT: [[NITER_NEXT_7]] = add nuw nsw i64 [[NITER]], 8
; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label [[LATCHEXIT_UNR_LCSSA:%.*]], label [[HEADER]]
; CHECK: latchexit.unr-lcssa:
@@ -974,8 +974,8 @@ define i32 @test5(ptr nocapture %a, i64 %n) {
; ENABLED-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_6]]
; ENABLED-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4
; ENABLED-NEXT: [[ADD_7]] = add nsw i32 [[TMP10]], [[ADD_6]]
-; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add i64 [[INDVARS_IV]], 8
-; ENABLED-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add nsw i64 [[INDVARS_IV]], 8
+; ENABLED-NEXT: [[NITER_NEXT_7]] = add nsw i64 [[NITER]], 8
; ENABLED-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; ENABLED-NEXT: br i1 [[NITER_NCMP_7]], label [[LATCHEXIT_UNR_LCSSA:%.*]], label [[HEADER]]
; ENABLED: latchexit.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-unroll-assume-no-remainder.ll b/llvm/test/Transforms/LoopUnroll/runtime-unroll-assume-no-remainder.ll
index 73f7fd37a0099..02e16ae1969ba 100644
--- a/llvm/test/Transforms/LoopUnroll/runtime-unroll-assume-no-remainder.ll
+++ b/llvm/test/Transforms/LoopUnroll/runtime-unroll-assume-no-remainder.ll
@@ -110,7 +110,7 @@ define dso_local void @cannotProveDivisibleTC(ptr noalias nocapture %a, ptr noal
; CHECK-NEXT: [[ARRAYIDX4_1:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 [[INC]]
; CHECK-NEXT: store i8 [[ADD_1]], ptr [[ARRAYIDX4_1]], align 1
; CHECK-NEXT: [[INC_1]] = add nuw nsw i32 [[I_011]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i32 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i32 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp ne i32 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[FOR_BODY]], label [[EXIT_LOOPEXIT_UNR_LCSSA:%.*]], !llvm.loop [[LOOP2:![0-9]+]]
; CHECK: exit.loopexit.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions-min-max.ll b/llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions-min-max.ll
index 203a99e8a7ffd..c7561f33a8c40 100644
--- a/llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions-min-max.ll
+++ b/llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions-min-max.ll
@@ -25,7 +25,7 @@ define i32 @test_smin_reduction(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[GEP_A_1]], align 4
; CHECK-NEXT: [[RDX_NEXT_1]] = call i32 @llvm.smin.i32(i32 [[MIN_1]], i32 [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -92,7 +92,7 @@ define i32 @test_smax_reduction(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[GEP_A_1]], align 4
; CHECK-NEXT: [[RDX_NEXT_1]] = call i32 @llvm.smax.i32(i32 [[MAX_1]], i32 [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP2:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -164,7 +164,7 @@ define float @test_fmin_reduction(ptr %a, i64 %n) {
; CHECK-NEXT: [[CMP_1:%.*]] = fcmp olt float [[RDX_NEXT]], [[TMP3]]
; CHECK-NEXT: [[RDX_NEXT_1]] = select i1 [[CMP_1]], float [[RDX_NEXT]], float [[TMP3]]
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -233,7 +233,7 @@ define float @test_fmax_reduction(ptr %a, i64 %n) {
; CHECK-NEXT: [[CMP_1:%.*]] = fcmp ogt float [[RDX_NEXT]], [[TMP3]]
; CHECK-NEXT: [[RDX_NEXT_1]] = select i1 [[CMP_1]], float [[RDX_NEXT]], float [[TMP3]]
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP4:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -306,7 +306,7 @@ define float @test_fast_math_fmin_reduction(ptr %a, i64 %n) {
; CHECK-NEXT: [[CMP_1:%.*]] = fcmp nnan ninf nsz olt float [[MIN_1]], [[TMP3]]
; CHECK-NEXT: [[RDX_NEXT_1]] = select nsz i1 [[CMP_1]], float [[MIN_1]], float [[TMP3]]
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -378,7 +378,7 @@ define float @test_fast_math_fmax_reduction(ptr %a, i64 %n) {
; CHECK-NEXT: [[CMP_1:%.*]] = fcmp nnan ninf nsz ogt float [[MAX_1]], [[TMP3]]
; CHECK-NEXT: [[RDX_NEXT_1]] = select nsz i1 [[CMP_1]], float [[MAX_1]], float [[TMP3]]
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP6:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -452,7 +452,7 @@ define float @test_fast_math_fmin_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[GEP_A_1]], align 4
; CHECK-NEXT: [[RDX_NEXT_1]] = call nsz float @llvm.minnum.f32(float [[MIN_1]], float [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -520,7 +520,7 @@ define float @test_fast_math_fmax_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[GEP_A_1]], align 4
; CHECK-NEXT: [[RDX_NEXT_1]] = call nsz float @llvm.maxnum.f32(float [[MAX_1]], float [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP8:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -588,9 +588,9 @@ define <4 x float> @test_vector_fmax_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr [[GEP_A_1]], align 16
; CHECK-NEXT: [[RDX_NEXT_1]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[RDX_1]], <4 x float> [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
-; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP14:![0-9]+]]
+; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
; CHECK-NEXT: [[RES_PH:%.*]] = phi <4 x float> [ [[RDX_NEXT_1]], %[[LOOP]] ]
; CHECK-NEXT: [[IV_UNR:%.*]] = phi i64 [ [[IV_NEXT_1]], %[[LOOP]] ]
@@ -655,9 +655,9 @@ define <4 x float> @test_vector_fmin_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr [[GEP_A_1]], align 16
; CHECK-NEXT: [[RDX_NEXT_1]] = call <4 x float> @llvm.minnum.v4f32(<4 x float> [[RDX_1]], <4 x float> [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
-; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]
+; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP10:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
; CHECK-NEXT: [[RES_PH:%.*]] = phi <4 x float> [ [[RDX_NEXT_1]], %[[LOOP]] ]
; CHECK-NEXT: [[IV_UNR:%.*]] = phi i64 [ [[IV_NEXT_1]], %[[LOOP]] ]
@@ -722,9 +722,9 @@ define <4 x i32> @test_vector_smax_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[GEP_A_1]], align 16
; CHECK-NEXT: [[RDX_NEXT_1]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[MAX_1]], <4 x i32> [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
-; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP10:![0-9]+]]
+; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP11:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
; CHECK-NEXT: [[RES_PH:%.*]] = phi <4 x i32> [ [[RDX_NEXT_1]], %[[LOOP]] ]
; CHECK-NEXT: [[IV_UNR:%.*]] = phi i64 [ [[IV_NEXT_1]], %[[LOOP]] ]
@@ -789,9 +789,9 @@ define <4 x i32> @test_vector_smin_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[GEP_A_1]], align 16
; CHECK-NEXT: [[RDX_NEXT_1]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[MIN_1]], <4 x i32> [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
-; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP11:![0-9]+]]
+; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP12:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
; CHECK-NEXT: [[RES_PH:%.*]] = phi <4 x i32> [ [[RDX_NEXT_1]], %[[LOOP]] ]
; CHECK-NEXT: [[IV_UNR:%.*]] = phi i64 [ [[IV_NEXT_1]], %[[LOOP]] ]
@@ -856,9 +856,9 @@ define <4 x i32> @test_vector_umax_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[GEP_A_1]], align 16
; CHECK-NEXT: [[RDX_NEXT_1]] = call <4 x i32> @llvm.umax.v4i32(<4 x i32> [[MAX_1]], <4 x i32> [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
-; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP12:![0-9]+]]
+; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP13:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
; CHECK-NEXT: [[RES_PH:%.*]] = phi <4 x i32> [ [[RDX_NEXT_1]], %[[LOOP]] ]
; CHECK-NEXT: [[IV_UNR:%.*]] = phi i64 [ [[IV_NEXT_1]], %[[LOOP]] ]
@@ -923,9 +923,9 @@ define <4 x i32> @test_vector_umin_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[GEP_A_1]], align 16
; CHECK-NEXT: [[RDX_NEXT_1]] = call <4 x i32> @llvm.umin.v4i32(<4 x i32> [[MIN_1]], <4 x i32> [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
-; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP13:![0-9]+]]
+; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP14:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
; CHECK-NEXT: [[RES_PH:%.*]] = phi <4 x i32> [ [[RDX_NEXT_1]], %[[LOOP]] ]
; CHECK-NEXT: [[IV_UNR:%.*]] = phi i64 [ [[IV_NEXT_1]], %[[LOOP]] ]
@@ -994,7 +994,7 @@ define i32 @test_smin_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[GEP_A_1]], align 4
; CHECK-NEXT: [[RDX_NEXT_1]] = call i32 @llvm.smin.i32(i32 [[MIN_1]], i32 [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP15:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -1062,7 +1062,7 @@ define i32 @test_smax_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[GEP_A_1]], align 4
; CHECK-NEXT: [[RDX_NEXT_1]] = call i32 @llvm.smax.i32(i32 [[MAX_1]], i32 [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP16:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -1130,7 +1130,7 @@ define i32 @test_umin_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[GEP_A_1]], align 4
; CHECK-NEXT: [[RDX_NEXT_1]] = call i32 @llvm.umin.i32(i32 [[MIN_1]], i32 [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP17:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -1198,7 +1198,7 @@ define i32 @test_umax_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[GEP_A_1]], align 4
; CHECK-NEXT: [[RDX_NEXT_1]] = call i32 @llvm.umax.i32(i32 [[MAX_1]], i32 [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP18:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions.ll b/llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions.ll
index 6492e01bd1fa7..8e8521d3e1bac 100644
--- a/llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions.ll
+++ b/llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions.ll
@@ -25,7 +25,7 @@ define i32 @test_add_reduction(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[GEP_A_1]], align 2
; CHECK-NEXT: [[RDX_NEXT_1]] = add i32 [[RDX_1]], [[TMP3]]
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -85,7 +85,7 @@ define i32 @test_add_reduction_constant_op(ptr %a, i64 %n) {
; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[NITER_NEXT_1:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[RDX_NEXT_1]] = add nuw nsw i32 [[RDX]], 2
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP2:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -168,7 +168,7 @@ define i32 @test_add_reduction_8x_unroll(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[GEP_A_7]], align 2
; CHECK-NEXT: [[RDX_NEXT_7]] = add nuw nsw i32 [[RDX_NEXT_6]], [[TMP9]]
; CHECK-NEXT: [[IV_NEXT_7]] = add nuw nsw i64 [[IV]], 8
-; CHECK-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; CHECK-NEXT: [[NITER_NEXT_7]] = add nsw i64 [[NITER]], 8
; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -244,7 +244,7 @@ define <4 x i32> @test_vector_add_reduction(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[GEP_A_1]], align 16
; CHECK-NEXT: [[RDX_NEXT_1]] = add <4 x i32> [[RDX_1]], [[TMP3]]
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -311,7 +311,7 @@ define float @test_fadd_reduction(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[GEP_A_1]], align 16
; CHECK-NEXT: [[RDX_NEXT_1]] = fadd reassoc float [[RDX_1]], [[TMP3]]
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP6:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -377,7 +377,7 @@ define float @test_fadd_no_reassoc(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[GEP_A_1]], align 16
; CHECK-NEXT: [[RDX_NEXT_1]] = fadd float [[RDX_NEXT]], [[TMP3]]
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -442,7 +442,7 @@ define float @test_fadd_other_fastmath(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[GEP_A_1]], align 16
; CHECK-NEXT: [[RDX_NEXT_1]] = fadd contract float [[RDX_NEXT]], [[TMP3]]
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP8:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -512,7 +512,7 @@ define float @test_fmuladd_reduction(ptr %a, ptr %b, i64 %n) {
; CHECK-NEXT: [[Y_1:%.*]] = load float, ptr [[GEP_B_1]], align 4
; CHECK-NEXT: [[RDX_NEXT_1]] = call reassoc nsz float @llvm.fmuladd.f32(float [[X_1]], float [[Y_1]], float [[RDX_1]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -582,7 +582,7 @@ define float @test_fmuladd_reduction_constant_op(ptr %a, i64 %n) {
; CHECK-NEXT: [[X_1:%.*]] = load float, ptr [[GEP_A_1]], align 4
; CHECK-NEXT: [[RDX_NEXT_1]] = call reassoc nnan ninf nsz float @llvm.fmuladd.f32(float [[X_1]], float 1.000000e+00, float [[RDX_NEXT]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP10:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-unroll-remainder.ll b/llvm/test/Transforms/LoopUnroll/runtime-unroll-remainder.ll
index 3c9c3bd10a93c..387492c72dd91 100644
--- a/llvm/test/Transforms/LoopUnroll/runtime-unroll-remainder.ll
+++ b/llvm/test/Transforms/LoopUnroll/runtime-unroll-remainder.ll
@@ -93,7 +93,7 @@ define i32 @unroll(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N)
; CHECK-NEXT: [[MUL_3:%.*]] = mul nsw i32 [[TMP14]], [[TMP13]]
; CHECK-NEXT: [[ADD_3]] = add nsw i32 [[MUL_3]], [[ADD_2]]
; CHECK-NEXT: [[INDVARS_IV_NEXT_3]] = add nuw nsw i64 [[INDVARS_IV]], 4
-; CHECK-NEXT: [[NITER_NEXT_3]] = add i64 [[NITER]], 4
+; CHECK-NEXT: [[NITER_NEXT_3]] = add nuw nsw i64 [[NITER]], 4
; CHECK-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i64 [[NITER_NEXT_3]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_3]], label [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]], label [[FOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
;
diff --git a/llvm/test/Transforms/LoopUnroll/scev-invalidation-lcssa.ll b/llvm/test/Transforms/LoopUnroll/scev-invalidation-lcssa.ll
index fd07238b16421..2de0ac0e880f3 100644
--- a/llvm/test/Transforms/LoopUnroll/scev-invalidation-lcssa.ll
+++ b/llvm/test/Transforms/LoopUnroll/scev-invalidation-lcssa.ll
@@ -37,8 +37,8 @@ define i32 @f(i1 %cond1) #0 !prof !0 {
; CHECK: loop2:
; CHECK-NEXT: [[PHI:%.*]] = phi i64 [ 0, [[ENTRY2_NEW]] ], [ [[INC_7:%.*]], [[LOOP2]] ]
; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[ENTRY2_NEW]] ], [ [[NITER_NEXT_7:%.*]], [[LOOP2]] ]
-; CHECK-NEXT: [[INC_7]] = add i64 [[PHI]], 8
-; CHECK-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; CHECK-NEXT: [[INC_7]] = add nsw i64 [[PHI]], 8
+; CHECK-NEXT: [[NITER_NEXT_7]] = add nsw i64 [[NITER]], 8
; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label [[EXIT2_UNR_LCSSA:%.*]], label [[LOOP2]]
; CHECK: exit2.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/shifted-tripcount.ll b/llvm/test/Transforms/LoopUnroll/shifted-tripcount.ll
index 4f3f861d308e9..b5de0bfcc664a 100644
--- a/llvm/test/Transforms/LoopUnroll/shifted-tripcount.ll
+++ b/llvm/test/Transforms/LoopUnroll/shifted-tripcount.ll
@@ -17,7 +17,7 @@ define void @latch_exit(ptr nocapture %p, i64 %n) nounwind {
; CHECK-NEXT: [[MUL9:%.*]] = fmul double [[TMP8]], [[TMP4]]
; CHECK-NEXT: store double [[MUL9]], ptr [[ARRAYIDX7]], align 8
; CHECK-NEXT: [[ARRAYIDX7_1:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16]]
-; CHECK-NEXT: [[TMP16_1]] = add i64 [[I_013]], 2
+; CHECK-NEXT: [[TMP16_1]] = add nsw i64 [[I_013]], 2
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16_1]]
; CHECK-NEXT: [[TMP4_1:%.*]] = load double, ptr [[ARRAYIDX_1]], align 8
; CHECK-NEXT: [[MUL9_1:%.*]] = fmul double [[TMP4]], [[TMP4_1]]
@@ -66,7 +66,7 @@ define void @non_latch_exit(ptr nocapture %p, i64 %n) nounwind {
; CHECK-NEXT: br label [[LATCH:%.*]]
; CHECK: latch:
; CHECK-NEXT: [[ARRAYIDX7_1:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16]]
-; CHECK-NEXT: [[TMP16_1]] = add i64 [[I_013]], 2
+; CHECK-NEXT: [[TMP16_1]] = add nsw i64 [[I_013]], 2
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16_1]]
; CHECK-NEXT: [[TMP4_1:%.*]] = load double, ptr [[ARRAYIDX_1]], align 8
; CHECK-NEXT: [[MUL9_1:%.*]] = fmul double [[TMP4]], [[TMP4_1]]
diff --git a/llvm/test/Transforms/LoopUnroll/tripcount-overflow.ll b/llvm/test/Transforms/LoopUnroll/tripcount-overflow.ll
index f839c88b93e54..80e5ea0d078d5 100644
--- a/llvm/test/Transforms/LoopUnroll/tripcount-overflow.ll
+++ b/llvm/test/Transforms/LoopUnroll/tripcount-overflow.ll
@@ -25,8 +25,8 @@ define i32 @foo(i32 %N) {
; EPILOG-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY_NEW]] ], [ [[INC_1:%.*]], [[WHILE_BODY]] ]
; EPILOG-NEXT: [[NITER:%.*]] = phi i32 [ 0, [[ENTRY_NEW]] ], [ [[NITER_NEXT_1:%.*]], [[WHILE_BODY]] ]
; EPILOG-NEXT: [[INC:%.*]] = add nuw nsw i32 [[I]], 1
-; EPILOG-NEXT: [[INC_1]] = add i32 [[I]], 2
-; EPILOG-NEXT: [[NITER_NEXT_1]] = add i32 [[NITER]], 2
+; EPILOG-NEXT: [[INC_1]] = add nsw i32 [[I]], 2
+; EPILOG-NEXT: [[NITER_NEXT_1]] = add nsw i32 [[NITER]], 2
; EPILOG-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i32 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; EPILOG-NEXT: br i1 [[NITER_NCMP_1]], label [[WHILE_END_UNR_LCSSA:%.*]], label [[WHILE_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; EPILOG: while.end.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/unroll-loads-cse.ll b/llvm/test/Transforms/LoopUnroll/unroll-loads-cse.ll
index 4ae1518cf594d..ebaeef8f09acf 100644
--- a/llvm/test/Transforms/LoopUnroll/unroll-loads-cse.ll
+++ b/llvm/test/Transforms/LoopUnroll/unroll-loads-cse.ll
@@ -33,7 +33,7 @@ define void @cse_matching_load_from_previous_unrolled_iteration(ptr %src, ptr no
; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IV_NEXT]]
; CHECK-NEXT: store i64 [[MUL_1]], ptr [[GEP_DST_1]], align 8
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[EXIT_UNR_LCSSA:%.*]], label [[LOOP]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: exit.unr-lcssa:
@@ -113,7 +113,7 @@ define void @cse_different_load_types(ptr %src, ptr noalias %dst, i64 %N) {
; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IV_NEXT]]
; CHECK-NEXT: store i64 [[MUL_1]], ptr [[GEP_DST_1]], align 8
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[EXIT_UNR_LCSSA:%.*]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: exit.unr-lcssa:
@@ -194,7 +194,7 @@ define void @cse_volatile_loads(ptr %src, ptr noalias %dst, i64 %N) {
; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IV_NEXT]]
; CHECK-NEXT: store i64 [[MUL_1]], ptr [[GEP_DST_1]], align 8
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[EXIT_UNR_LCSSA:%.*]], label [[LOOP]], !llvm.loop [[LOOP4:![0-9]+]]
; CHECK: exit.unr-lcssa:
@@ -272,7 +272,7 @@ define void @cse_atomic_loads(ptr %src, ptr noalias %dst, i64 %N) {
; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IV_NEXT]]
; CHECK-NEXT: store i64 [[MUL_1]], ptr [[GEP_DST_1]], align 8
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[EXIT_UNR_LCSSA:%.*]], label [[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK: exit.unr-lcssa:
@@ -350,7 +350,7 @@ define void @cse_load_may_be_clobbered(ptr %src, ptr %dst, i64 %N) {
; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IV_NEXT]]
; CHECK-NEXT: store i64 [[MUL_1]], ptr [[GEP_DST_1]], align 8
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[EXIT_UNR_LCSSA:%.*]], label [[LOOP]], !llvm.loop [[LOOP6:![0-9]+]]
; CHECK: exit.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnrollAndJam/dependencies_visit_order.ll b/llvm/test/Transforms/LoopUnrollAndJam/dependencies_visit_order.ll
index 351065080119d..dcf6e396cf0e4 100644
--- a/llvm/test/Transforms/LoopUnrollAndJam/dependencies_visit_order.ll
+++ b/llvm/test/Transforms/LoopUnrollAndJam/dependencies_visit_order.ll
@@ -24,13 +24,12 @@ define void @test1() {
; CHECK-NEXT: [[I4017_3:%.*]] = zext i16 [[I42_2]] to i64
; CHECK-NEXT: [[I13_I_3:%.*]] = add nuw nsw i64 [[I4017_3]], 1
; CHECK-NEXT: [[I42_3]] = trunc i64 [[I13_I_3]] to i16
-; CHECK-NEXT: [[NITER_NEXT_3]] = add nuw i16 [[NITER]], 4
+; CHECK-NEXT: [[NITER_NEXT_3]] = add nuw nsw i16 [[NITER]], 4
; CHECK-NEXT: br label [[BB10_PREHEADER:%.*]]
; CHECK: bb10.preheader:
; CHECK-NEXT: br i1 true, label [[BB38]], label [[BB10_PREHEADER]]
; CHECK: bb38:
-; CHECK-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i16 [[NITER_NEXT_3]], -28
-; CHECK-NEXT: br i1 [[NITER_NCMP_3]], label [[BB1_BB43_CRIT_EDGE_UNR_LCSSA:%.*]], label [[BB5_PREHEADER]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-NEXT: br i1 false, label [[BB1_BB43_CRIT_EDGE_UNR_LCSSA:%.*]], label [[BB5_PREHEADER]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: bb1.bb43_crit_edge.unr-lcssa:
; CHECK-NEXT: [[I10_UNR:%.*]] = phi i16 [ [[I42_3]], [[BB38]] ]
; CHECK-NEXT: br i1 true, label [[BB5_PREHEADER_EPIL_PREHEADER]], label [[BB1_BB43_CRIT_EDGE:%.*]]
diff --git a/llvm/test/Transforms/LoopUnrollAndJam/unroll-and-jam.ll b/llvm/test/Transforms/LoopUnrollAndJam/unroll-and-jam.ll
index 27b4143303692..3004ac671e9b8 100644
--- a/llvm/test/Transforms/LoopUnrollAndJam/unroll-and-jam.ll
+++ b/llvm/test/Transforms/LoopUnrollAndJam/unroll-and-jam.ll
@@ -27,8 +27,8 @@ define void @test1(i32 %N, i32 %M, ptr noalias nocapture %A, ptr noalias nocaptu
; CHECK-NEXT: [[ADD8:%.*]] = add nuw nsw i32 [[I]], 1
; CHECK-NEXT: [[ADD8_1:%.*]] = add nuw nsw i32 [[I]], 2
; CHECK-NEXT: [[ADD8_2:%.*]] = add nuw nsw i32 [[I]], 3
-; CHECK-NEXT: [[ADD8_3]] = add nuw i32 [[I]], 4
-; CHECK-NEXT: [[NITER_NEXT_3]] = add nuw i32 [[NITER]], 4
+; CHECK-NEXT: [[ADD8_3]] = add nuw nsw i32 [[I]], 4
+; CHECK-NEXT: [[NITER_NEXT_3]] = add nuw nsw i32 [[NITER]], 4
; CHECK-NEXT: br label %[[FOR_INNER:.*]]
; CHECK: [[FOR_INNER]]:
; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, %[[FOR_OUTER]] ], [ [[INC:%.*]], %[[FOR_INNER]] ]
@@ -42,19 +42,19 @@ define void @test1(i32 %N, i32 %M, ptr noalias nocapture %A, ptr noalias nocaptu
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J]]
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[INT_TBAA0:![0-9]+]]
; CHECK-NEXT: [[ADD]] = add i32 [[TMP2]], [[SUM]]
-; CHECK-NEXT: [[INC]] = add nuw i32 [[J]], 1
+; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[J]], 1
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_1]]
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4, !tbaa [[INT_TBAA0]]
; CHECK-NEXT: [[ADD_1]] = add i32 [[TMP3]], [[SUM_1]]
-; CHECK-NEXT: [[INC_1]] = add nuw i32 [[J_1]], 1
+; CHECK-NEXT: [[INC_1]] = add nuw nsw i32 [[J_1]], 1
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_2]]
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4, !tbaa [[INT_TBAA0]]
; CHECK-NEXT: [[ADD_2]] = add i32 [[TMP4]], [[SUM_2]]
-; CHECK-NEXT: [[INC_2]] = add nuw i32 [[J_2]], 1
+; CHECK-NEXT: [[INC_2]] = add nuw nsw i32 [[J_2]], 1
; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_3]]
; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4, !tbaa [[INT_TBAA0]]
; CHECK-NEXT: [[ADD_3]] = add i32 [[TMP5]], [[SUM_3]]
-; CHECK-NEXT: [[INC_3]] = add nuw i32 [[J_3]], 1
+; CHECK-NEXT: [[INC_3]] = add nuw nsw i32 [[J_3]], 1
; CHECK-NEXT: [[EXITCOND_3:%.*]] = icmp eq i32 [[INC_3]], [[M]]
; CHECK-NEXT: br i1 [[EXITCOND_3]], label %[[FOR_LATCH]], label %[[FOR_INNER]]
; CHECK: [[FOR_LATCH]]:
@@ -412,22 +412,22 @@ define void @test3(i32 %M, ptr noalias nocapture %A, ptr noalias nocapture reado
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[INT_TBAA0]]
; CHECK-NEXT: [[SUB:%.*]] = add i32 [[SUM]], 10
; CHECK-NEXT: [[ADD]] = sub i32 [[SUB]], [[TMP0]]
-; CHECK-NEXT: [[INC]] = add nuw i32 [[J]], 1
+; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[J]], 1
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_1]]
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4, !tbaa [[INT_TBAA0]]
; CHECK-NEXT: [[SUB_1:%.*]] = add i32 [[SUM_1]], 10
; CHECK-NEXT: [[ADD_1]] = sub i32 [[SUB_1]], [[TMP1]]
-; CHECK-NEXT: [[INC_1]] = add nuw i32 [[J_1]], 1
+; CHECK-NEXT: [[INC_1]] = add nuw nsw i32 [[J_1]], 1
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_2]]
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4, !tbaa [[INT_TBAA0]]
; CHECK-NEXT: [[SUB_2:%.*]] = add i32 [[SUM_2]], 10
; CHECK-NEXT: [[ADD_2]] = sub i32 [[SUB_2]], [[TMP2]]
-; CHECK-NEXT: [[INC_2]] = add nuw i32 [[J_2]], 1
+; CHECK-NEXT: [[INC_2]] = add nuw nsw i32 [[J_2]], 1
; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_3]]
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4, !tbaa [[INT_TBAA0]]
; CHECK-NEXT: [[SUB_3:%.*]] = add i32 [[SUM_3]], 10
; CHECK-NEXT: [[ADD_3]] = sub i32 [[SUB_3]], [[TMP3]]
-; CHECK-NEXT: [[INC_3]] = add nuw i32 [[J_3]], 1
+; CHECK-NEXT: [[INC_3]] = add nuw nsw i32 [[J_3]], 1
; CHECK-NEXT: [[EXITCOND_3:%.*]] = icmp eq i32 [[INC_3]], [[M]]
; CHECK-NEXT: br i1 [[EXITCOND_3]], label %[[FOR_LATCH:.*]], label %[[FOR_INNER]]
; CHECK: [[FOR_LATCH]]:
@@ -500,7 +500,7 @@ define void @test4(i32 %M, ptr noalias nocapture %A, ptr noalias nocapture reado
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[INT_TBAA0]]
; CHECK-NEXT: [[SUB:%.*]] = add i32 [[SUM]], 10
; CHECK-NEXT: [[ADD]] = sub i32 [[SUB]], [[TMP0]]
-; CHECK-NEXT: [[INC]] = add nuw i32 [[J]], 1
+; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[J]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[M]]
; CHECK-NEXT: br i1 [[EXITCOND]], label %[[FOR_LATCH:.*]], label %[[FOR_INNER]]
; CHECK: [[FOR_LATCH]]:
@@ -1127,8 +1127,8 @@ define void @test9(i32 %N, i32 %M, ptr nocapture %A, ptr nocapture readonly %B)
; CHECK-NEXT: [[ADD8:%.*]] = add nuw nsw i32 [[I]], 1
; CHECK-NEXT: [[ADD8_1:%.*]] = add nuw nsw i32 [[I]], 2
; CHECK-NEXT: [[ADD8_2:%.*]] = add nuw nsw i32 [[I]], 3
-; CHECK-NEXT: [[ADD8_3]] = add nuw i32 [[I]], 4
-; CHECK-NEXT: [[NITER_NEXT_3]] = add nuw i32 [[NITER]], 4
+; CHECK-NEXT: [[ADD8_3]] = add nuw nsw i32 [[I]], 4
+; CHECK-NEXT: [[NITER_NEXT_3]] = add nuw nsw i32 [[NITER]], 4
; CHECK-NEXT: br label %[[FOR_INNER:.*]]
; CHECK: [[FOR_INNER]]:
; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, %[[FOR_OUTER]] ], [ [[INC:%.*]], %[[FOR_INNER]] ]
@@ -1143,22 +1143,22 @@ define void @test9(i32 %N, i32 %M, ptr nocapture %A, ptr nocapture readonly %B)
; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[ARRAYIDX]], align 4, !tbaa [[SHORT_TBAA9:![0-9]+]]
; CHECK-NEXT: [[SEXT:%.*]] = sext i16 [[TMP2]] to i32
; CHECK-NEXT: [[ADD]] = add i32 [[SEXT]], [[SUM]]
-; CHECK-NEXT: [[INC]] = add nuw i32 [[J]], 1
+; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[J]], 1
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i16, ptr [[B]], i32 [[J_1]]
; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr [[ARRAYIDX_1]], align 4, !tbaa [[SHORT_TBAA9]]
; CHECK-NEXT: [[SEXT_1:%.*]] = sext i16 [[TMP3]] to i32
; CHECK-NEXT: [[ADD_1]] = add i32 [[SEXT_1]], [[SUM_1]]
-; CHECK-NEXT: [[INC_1]] = add nuw i32 [[J_1]], 1
+; CHECK-NEXT: [[INC_1]] = add nuw nsw i32 [[J_1]], 1
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i16, ptr [[B]], i32 [[J_2]]
; CHECK-NEXT: [[TMP4:%.*]] = load i16, ptr [[ARRAYIDX_2]], align 4, !tbaa [[SHORT_TBAA9]]
; CHECK-NEXT: [[SEXT_2:%.*]] = sext i16 [[TMP4]] to i32
; CHECK-NEXT: [[ADD_2]] = add i32 [[SEXT_2]], [[SUM_2]]
-; CHECK-NEXT: [[INC_2]] = add nuw i32 [[J_2]], 1
+; CHECK-NEXT: [[INC_2]] = add nuw nsw i32 [[J_2]], 1
; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i16, ptr [[B]], i32 [[J_3]]
; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[ARRAYIDX_3]], align 4, !tbaa [[SHORT_TBAA9]]
; CHECK-NEXT: [[SEXT_3:%.*]] = sext i16 [[TMP5]] to i32
; CHECK-NEXT: [[ADD_3]] = add i32 [[SEXT_3]], [[SUM_3]]
-; CHECK-NEXT: [[INC_3]] = add nuw i32 [[J_3]], 1
+; CHECK-NEXT: [[INC_3]] = add nuw nsw i32 [[J_3]], 1
; CHECK-NEXT: [[EXITCOND_3:%.*]] = icmp eq i32 [[INC_3]], [[M]]
; CHECK-NEXT: br i1 [[EXITCOND_3]], label %[[FOR_LATCH]], label %[[FOR_INNER]]
; CHECK: [[FOR_LATCH]]:
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/bounded-load.ll b/llvm/test/Transforms/LoopVectorize/AArch64/bounded-load.ll
index d2ad63e810731..7ab8fa80893c4 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/bounded-load.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/bounded-load.ll
@@ -527,9 +527,7 @@ define i32 @reverse_load_with_bounded(ptr %A, ptr %B, i32 %N) {
; CHECK: [[VECTOR_SCEVCHECK]]:
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], 3
-; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 1, [[N]]
-; CHECK-NEXT: [[TMP3:%.*]] = or i1 [[TMP1]], [[TMP2]]
-; CHECK-NEXT: br i1 [[TMP3]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
+; CHECK-NEXT: br i1 [[TMP1]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
; CHECK: [[VECTOR_MAIN_LOOP_ITER_CHECK]]:
; CHECK-NEXT: [[MIN_ITERS_CHECK2:%.*]] = icmp ult i32 [[N]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK2]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]]
@@ -616,11 +614,11 @@ define i32 @reverse_load_with_bounded(ptr %A, ptr %B, i32 %N) {
; CHECK-NEXT: br i1 [[CMP_N26]], label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]]
; CHECK: [[VEC_EPILOG_SCALAR_PH]]:
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC19]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ITER_CHECK]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX26:%.*]] = phi i32 [ [[TMP34]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP24]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ITER_CHECK]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX25:%.*]] = phi i32 [ [[TMP34]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP24]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ITER_CHECK]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[BC_MERGE_RDX26]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[BC_MERGE_RDX25]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 4
; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[BOUNDED]]
; CHECK-NEXT: [[LV1:%.*]] = load i32, ptr [[GEP1]], align 4
diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
index 3cb08f283a14f..21f50e6bc68fc 100644
--- a/llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
+++ b/llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
@@ -239,15 +239,6 @@ define void @f2(ptr noalias %A, ptr noalias %B, i32 %n) {
; VF-TWO-CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[WIDE_TRIP_COUNT]], 2
; VF-TWO-CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; VF-TWO-CHECK: [[VECTOR_SCEVCHECK]]:
-; VF-TWO-CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[WIDE_TRIP_COUNT]], -1
-; VF-TWO-CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; VF-TWO-CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32
-; VF-TWO-CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[TMP0]], [[TMP2]]
-; VF-TWO-CHECK-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[TMP3]], [[TMP0]]
-; VF-TWO-CHECK-NEXT: [[TMP6:%.*]] = icmp ugt i64 [[TMP1]], 4294967295
-; VF-TWO-CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP4]], [[TMP6]]
-; VF-TWO-CHECK-NEXT: br i1 [[TMP7]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
-; VF-TWO-CHECK: [[VECTOR_MAIN_LOOP_ITER_CHECK]]:
; VF-TWO-CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[WIDE_TRIP_COUNT]], 32
; VF-TWO-CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]]
; VF-TWO-CHECK: [[VECTOR_PH]]:
@@ -320,7 +311,7 @@ define void @f2(ptr noalias %A, ptr noalias %B, i32 %n) {
; VF-TWO-CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_MOD_VF]], 2
; VF-TWO-CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF3]]
; VF-TWO-CHECK: [[VEC_EPILOG_PH]]:
-; VF-TWO-CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
+; VF-TWO-CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
; VF-TWO-CHECK-NEXT: [[N_MOD_VF16:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 1
; VF-TWO-CHECK-NEXT: [[N_VEC17:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[N_MOD_VF16]]
; VF-TWO-CHECK-NEXT: [[IND_END:%.*]] = trunc i64 [[N_VEC17]] to i32
@@ -353,15 +344,6 @@ define void @f2(ptr noalias %A, ptr noalias %B, i32 %n) {
; VF-FOUR-CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[WIDE_TRIP_COUNT]], 4
; VF-FOUR-CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; VF-FOUR-CHECK: [[VECTOR_SCEVCHECK]]:
-; VF-FOUR-CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[WIDE_TRIP_COUNT]], -1
-; VF-FOUR-CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; VF-FOUR-CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32
-; VF-FOUR-CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[TMP0]], [[TMP2]]
-; VF-FOUR-CHECK-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[TMP3]], [[TMP0]]
-; VF-FOUR-CHECK-NEXT: [[TMP6:%.*]] = icmp ugt i64 [[TMP1]], 4294967295
-; VF-FOUR-CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP4]], [[TMP6]]
-; VF-FOUR-CHECK-NEXT: br i1 [[TMP7]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
-; VF-FOUR-CHECK: [[VECTOR_MAIN_LOOP_ITER_CHECK]]:
; VF-FOUR-CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[WIDE_TRIP_COUNT]], 32
; VF-FOUR-CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]]
; VF-FOUR-CHECK: [[VECTOR_PH]]:
@@ -434,7 +416,7 @@ define void @f2(ptr noalias %A, ptr noalias %B, i32 %n) {
; VF-FOUR-CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_MOD_VF]], 4
; VF-FOUR-CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF3]]
; VF-FOUR-CHECK: [[VEC_EPILOG_PH]]:
-; VF-FOUR-CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
+; VF-FOUR-CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
; VF-FOUR-CHECK-NEXT: [[N_MOD_VF16:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 3
; VF-FOUR-CHECK-NEXT: [[N_VEC17:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[N_MOD_VF16]]
; VF-FOUR-CHECK-NEXT: [[IND_END:%.*]] = trunc i64 [[N_VEC17]] to i32
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-narrow-iv.ll b/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-narrow-iv.ll
index 708f488b93eef..a07437cdd3cdd 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-narrow-iv.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-narrow-iv.ll
@@ -287,23 +287,18 @@ define void @narrow_iv_i8_sext_i64_wrapping(ptr noalias %arr, ptr noalias %out)
; RV64: [[LOOP]]:
; RV64-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 16 x ptr> poison, ptr [[OUT]], i64 0
; RV64-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 16 x ptr> [[BROADCAST_SPLATINSERT]], <vscale x 16 x ptr> poison, <vscale x 16 x i32> zeroinitializer
-; RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.stepvector.nxv16i8()
-; RV64-NEXT: [[TMP1:%.*]] = mul <vscale x 16 x i8> [[TMP0]], splat (i8 4)
; RV64-NEXT: br label %[[EXIT:.*]]
; RV64: [[EXIT]]:
-; RV64-NEXT: [[VEC_IND:%.*]] = phi <vscale x 16 x i8> [ [[TMP1]], %[[LOOP]] ], [ [[VEC_IND_NEXT:%.*]], %[[EXIT]] ]
+; RV64-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[LOOP]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[EXIT]] ]
; RV64-NEXT: [[AVL:%.*]] = phi i32 [ 64, %[[LOOP]] ], [ [[AVL_NEXT:%.*]], %[[EXIT]] ]
; RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[AVL]], i32 16, i1 true)
-; RV64-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
-; RV64-NEXT: [[TMP4:%.*]] = shl i8 [[TMP3]], 2
-; RV64-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[TMP4]], i64 0
-; RV64-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <vscale x 16 x i8> [[BROADCAST_SPLATINSERT1]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
-; RV64-NEXT: [[TMP5:%.*]] = sext <vscale x 16 x i8> [[VEC_IND]] to <vscale x 16 x i64>
-; RV64-NEXT: [[WIDE_GEP:%.*]] = getelementptr [1024 x i8], ptr [[ARR]], <vscale x 16 x i64> [[TMP5]]
-; RV64-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 16 x i8> @llvm.vp.gather.nxv16i8.nxv16p0(<vscale x 16 x ptr> align 1 [[WIDE_GEP]], <vscale x 16 x i1> splat (i1 true), i32 [[TMP2]])
+; RV64-NEXT: [[TMP1:%.*]] = zext i32 [[INDEX]] to i64
+; RV64-NEXT: [[TMP4:%.*]] = shl i64 [[TMP1]], 12
+; RV64-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[ARR]], i64 [[TMP4]]
+; RV64-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vp.strided.load.nxv16i8.p0.i64(ptr align 1 [[TMP3]], i64 4096, <vscale x 16 x i1> splat (i1 true), i32 [[TMP2]])
; RV64-NEXT: call void @llvm.vp.scatter.nxv16i8.nxv16p0(<vscale x 16 x i8> [[WIDE_MASKED_GATHER]], <vscale x 16 x ptr> align 1 [[BROADCAST_SPLAT]], <vscale x 16 x i1> splat (i1 true), i32 [[TMP2]])
+; RV64-NEXT: [[CURRENT_ITERATION_NEXT]] = add nuw i32 [[TMP2]], [[INDEX]]
; RV64-NEXT: [[AVL_NEXT]] = sub nuw i32 [[AVL]], [[TMP2]]
-; RV64-NEXT: [[VEC_IND_NEXT]] = add <vscale x 16 x i8> [[VEC_IND]], [[BROADCAST_SPLAT2]]
; RV64-NEXT: [[TMP6:%.*]] = icmp eq i32 [[AVL_NEXT]], 0
; RV64-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[EXIT]], !llvm.loop [[LOOP6:![0-9]+]]
; RV64: [[MIDDLE_BLOCK]]:
@@ -318,23 +313,17 @@ define void @narrow_iv_i8_sext_i64_wrapping(ptr noalias %arr, ptr noalias %out)
; RV32: [[LOOP]]:
; RV32-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 16 x ptr> poison, ptr [[OUT]], i64 0
; RV32-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 16 x ptr> [[BROADCAST_SPLATINSERT]], <vscale x 16 x ptr> poison, <vscale x 16 x i32> zeroinitializer
-; RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.stepvector.nxv16i8()
-; RV32-NEXT: [[TMP1:%.*]] = mul <vscale x 16 x i8> [[TMP0]], splat (i8 4)
; RV32-NEXT: br label %[[EXIT:.*]]
; RV32: [[EXIT]]:
-; RV32-NEXT: [[VEC_IND:%.*]] = phi <vscale x 16 x i8> [ [[TMP1]], %[[LOOP]] ], [ [[VEC_IND_NEXT:%.*]], %[[EXIT]] ]
+; RV32-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[LOOP]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[EXIT]] ]
; RV32-NEXT: [[AVL:%.*]] = phi i32 [ 64, %[[LOOP]] ], [ [[AVL_NEXT:%.*]], %[[EXIT]] ]
; RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[AVL]], i32 16, i1 true)
-; RV32-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
-; RV32-NEXT: [[TMP4:%.*]] = shl i8 [[TMP3]], 2
-; RV32-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[TMP4]], i64 0
-; RV32-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <vscale x 16 x i8> [[BROADCAST_SPLATINSERT1]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
-; RV32-NEXT: [[TMP5:%.*]] = sext <vscale x 16 x i8> [[VEC_IND]] to <vscale x 16 x i64>
-; RV32-NEXT: [[WIDE_GEP:%.*]] = getelementptr [1024 x i8], ptr [[ARR]], <vscale x 16 x i64> [[TMP5]]
-; RV32-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 16 x i8> @llvm.vp.gather.nxv16i8.nxv16p0(<vscale x 16 x ptr> align 1 [[WIDE_GEP]], <vscale x 16 x i1> splat (i1 true), i32 [[TMP2]])
+; RV32-NEXT: [[TMP1:%.*]] = shl i32 [[INDEX]], 12
+; RV32-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[ARR]], i32 [[TMP1]]
+; RV32-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vp.strided.load.nxv16i8.p0.i32(ptr align 1 [[TMP3]], i32 4096, <vscale x 16 x i1> splat (i1 true), i32 [[TMP2]])
; RV32-NEXT: call void @llvm.vp.scatter.nxv16i8.nxv16p0(<vscale x 16 x i8> [[WIDE_MASKED_GATHER]], <vscale x 16 x ptr> align 1 [[BROADCAST_SPLAT]], <vscale x 16 x i1> splat (i1 true), i32 [[TMP2]])
+; RV32-NEXT: [[CURRENT_ITERATION_NEXT]] = add nuw i32 [[TMP2]], [[INDEX]]
; RV32-NEXT: [[AVL_NEXT]] = sub nuw i32 [[AVL]], [[TMP2]]
-; RV32-NEXT: [[VEC_IND_NEXT]] = add <vscale x 16 x i8> [[VEC_IND]], [[BROADCAST_SPLAT2]]
; RV32-NEXT: [[TMP6:%.*]] = icmp eq i32 [[AVL_NEXT]], 0
; RV32-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[EXIT]], !llvm.loop [[LOOP6:![0-9]+]]
; RV32: [[MIDDLE_BLOCK]]:
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-iv-outside-user.ll b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-iv-outside-user.ll
index 4e083dd9ffe76..bac0df0ee443c 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-iv-outside-user.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-iv-outside-user.ll
@@ -8,15 +8,12 @@ define i32 @f(ptr noalias %p, i32 %start, i32 %step, i32 %n) {
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], 1
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[N]], 0
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
-; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[TMP2:%.*]] = mul i32 [[TMP0]], [[STEP]]
; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[START]], [[TMP2]]
; CHECK-NEXT: br label %[[EXIT:.*]]
; CHECK: [[EXIT]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[EXIT]] ]
-; CHECK-NEXT: [[AVL:%.*]] = phi i32 [ [[TMP0]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[EXIT]] ]
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[LOOP]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[EXIT]] ]
+; CHECK-NEXT: [[AVL:%.*]] = phi i32 [ [[TMP0]], %[[LOOP]] ], [ [[AVL_NEXT:%.*]], %[[EXIT]] ]
; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[AVL]], i32 4, i1 true)
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[P]], i32 [[INDEX]]
; CHECK-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP6]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP3]])
@@ -28,23 +25,9 @@ define i32 @f(ptr noalias %p, i32 %start, i32 %step, i32 %n) {
; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[EXIT]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: [[IND_ESCAPE:%.*]] = sub i32 [[TMP5]], [[STEP]]
-; CHECK-NEXT: br label %[[EXIT1:.*]]
-; CHECK: [[SCALAR_PH]]:
; CHECK-NEXT: br label %[[LOOP1:.*]]
; CHECK: [[LOOP1]]:
-; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP1]] ]
-; CHECK-NEXT: [[IV2:%.*]] = phi i32 [ [[START]], %[[SCALAR_PH]] ], [ [[IV2_NEXT:%.*]], %[[LOOP1]] ]
-; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
-; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[GEP]], align 4
-; CHECK-NEXT: [[Y:%.*]] = add i32 [[X]], 1
-; CHECK-NEXT: store i32 [[Y]], ptr [[GEP]], align 4
-; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
-; CHECK-NEXT: [[IV2_NEXT]] = add i32 [[IV2]], [[STEP]]
-; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV]], [[N]]
-; CHECK-NEXT: br i1 [[EC]], label %[[EXIT1]], label %[[LOOP1]], !llvm.loop [[LOOP3:![0-9]+]]
-; CHECK: [[EXIT1]]:
-; CHECK-NEXT: [[IV2_LCSSA:%.*]] = phi i32 [ [[IV2]], %[[LOOP1]] ], [ [[IND_ESCAPE]], %[[MIDDLE_BLOCK]] ]
-; CHECK-NEXT: ret i32 [[IV2_LCSSA]]
+; CHECK-NEXT: ret i32 [[IND_ESCAPE]]
;
entry:
br label %loop
diff --git a/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll b/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
index 35c58e0880402..77cd767d494a1 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
@@ -9,10 +9,7 @@ define void @test_store_initially_interleave(i32 %n, ptr noalias %src) #0 {
; I64-NEXT: [[ITER_CHECK:.*:]]
; I64-NEXT: [[TMP0:%.*]] = add i32 [[N]], 1
; I64-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i32 [[TMP0]], 4
-; I64-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; I64: [[VECTOR_SCEVCHECK]]:
-; I64-NEXT: [[TMP1:%.*]] = icmp slt i32 [[N]], 0
-; I64-NEXT: br i1 [[TMP1]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
+; I64-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
; I64: [[VECTOR_MAIN_LOOP_ITER_CHECK]]:
; I64-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ule i32 [[TMP0]], 16
; I64-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]]
diff --git a/llvm/test/Transforms/LoopVectorize/alias-mask-data-tail-folding-style.ll b/llvm/test/Transforms/LoopVectorize/alias-mask-data-tail-folding-style.ll
index 674676d21101b..6d2f7fcd54d35 100644
--- a/llvm/test/Transforms/LoopVectorize/alias-mask-data-tail-folding-style.ll
+++ b/llvm/test/Transforms/LoopVectorize/alias-mask-data-tail-folding-style.ll
@@ -10,10 +10,6 @@ define void @test(ptr %src, ptr %dst, i32 %n) {
; CHECK-NEXT: [[UMAX3:%.*]] = call i32 @llvm.umax.i32(i32 [[N]], i32 1)
; CHECK-NEXT: br label %[[VECTOR_SCEVCHECK:.*]]
; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.usub.sat.i32(i32 [[N]], i32 1)
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 0
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH:.*]], label %[[VECTOR_CLAMPED_VF_CHECK:.*]]
-; CHECK: [[VECTOR_CLAMPED_VF_CHECK]]:
; CHECK-NEXT: [[ALIAS_MASK:%.*]] = call <4 x i1> @llvm.loop.dependence.war.mask.v4i1.i64(i64 [[SRC2]], i64 [[DST1]], i64 4)
; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i1> [[ALIAS_MASK]] to <4 x i64>
; CHECK-NEXT: [[NUM_ACTIVE_LANES:%.*]] = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> [[TMP3]])
@@ -22,7 +18,7 @@ define void @test(ptr %src, ptr %dst, i32 %n) {
; CHECK-NEXT: [[TMP8:%.*]] = sub i32 -1, [[UMAX3]]
; CHECK-NEXT: [[VF_STEP_OVERFLOW:%.*]] = icmp ult i32 [[TMP8]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = or i1 [[VF_IS_SCALAR]], [[VF_STEP_OVERFLOW]]
-; CHECK-NEXT: br i1 [[TMP9]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: br i1 [[TMP9]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[TMP10:%.*]] = sub i32 [[TMP7]], 1
; CHECK-NEXT: [[N_RND_UP:%.*]] = add i32 [[UMAX3]], [[TMP10]]
diff --git a/llvm/test/Transforms/LoopVectorize/alias-mask.ll b/llvm/test/Transforms/LoopVectorize/alias-mask.ll
index 47e2cd8f9f3ec..e5acedf8b01b7 100644
--- a/llvm/test/Transforms/LoopVectorize/alias-mask.ll
+++ b/llvm/test/Transforms/LoopVectorize/alias-mask.ll
@@ -574,14 +574,11 @@ define i64 @any_of_reduction(i64 %a, ptr %src, ptr %dst, i32 %n) {
; CHECK-SAME: i64 [[A:%.*]], ptr [[SRC:%.*]], ptr [[DST:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[DST1:%.*]] = ptrtoaddr ptr [[DST]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[DST1]], 4
+; CHECK-NEXT: [[TMP0:%.*]] = add nuw i64 [[DST1]], 4
; CHECK-NEXT: [[SRC2:%.*]] = ptrtoaddr ptr [[SRC]] to i64
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[SRC2]], 4
+; CHECK-NEXT: [[TMP1:%.*]] = add nuw i64 [[SRC2]], 4
; CHECK-NEXT: br label %[[VECTOR_SCEVCHECK:.*]]
; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[N]], 1
-; CHECK-NEXT: br i1 [[TMP2]], label %[[SCALAR_PH:.*]], label %[[VECTOR_CLAMPED_VF_CHECK:.*]]
-; CHECK: [[VECTOR_CLAMPED_VF_CHECK]]:
; CHECK-NEXT: [[ALIAS_MASK:%.*]] = call <4 x i1> @llvm.loop.dependence.war.mask.v4i1.i64(i64 [[TMP1]], i64 [[TMP0]], i64 4)
; CHECK-NEXT: [[TMP4:%.*]] = zext <4 x i1> [[ALIAS_MASK]] to <4 x i64>
; CHECK-NEXT: [[NUM_ACTIVE_LANES:%.*]] = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> [[TMP4]])
@@ -590,7 +587,7 @@ define i64 @any_of_reduction(i64 %a, ptr %src, ptr %dst, i32 %n) {
; CHECK-NEXT: [[TMP7:%.*]] = sub i32 -1, [[N]]
; CHECK-NEXT: [[VF_STEP_OVERFLOW:%.*]] = icmp ult i32 [[TMP7]], [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = or i1 [[VF_IS_SCALAR]], [[VF_STEP_OVERFLOW]]
-; CHECK-NEXT: br i1 [[TMP8]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: br i1 [[TMP8]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = sub i32 [[N]], 1
; CHECK-NEXT: [[TMP9:%.*]] = sub i32 [[TMP6]], 1
diff --git a/llvm/test/Transforms/LoopVectorize/div-exact.ll b/llvm/test/Transforms/LoopVectorize/div-exact.ll
index 11ea08f7da4e9..1de92d0251db3 100644
--- a/llvm/test/Transforms/LoopVectorize/div-exact.ll
+++ b/llvm/test/Transforms/LoopVectorize/div-exact.ll
@@ -8,17 +8,13 @@ define void @unknown_divisor(ptr noalias %p, i32 %n, i1 %c) {
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 0
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
-; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i32 [[N]], 3
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i1> poison, i1 [[C]], i64 0
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT]], <4 x i1> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE14:.*]] ]
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_SCEVCHECK]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE14:.*]] ]
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[INDEX]], 1
; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[INDEX]], 2
; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[INDEX]], 3
@@ -86,7 +82,7 @@ define void @unknown_divisor(ptr noalias %p, i32 %n, i1 %c) {
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
@@ -134,15 +130,11 @@ define void @unknown_dividend(ptr noalias %p, i32 %n, i1 %c) {
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 0
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
-; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i32 [[N]], 3
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE14:.*]] ]
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_SCEVCHECK]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE14:.*]] ]
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[INDEX]], 1
; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[INDEX]], 2
; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[INDEX]], 3
@@ -210,7 +202,7 @@ define void @unknown_dividend(ptr noalias %p, i32 %n, i1 %c) {
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
index 7cd5faf5dd9bd..ceef32c2332b7 100644
--- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
+++ b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
@@ -783,11 +783,7 @@ define void @sink_dominance(ptr %ptr, i32 %N) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[UMAX1:%.*]] = call i32 @llvm.umax.i32(i32 [[N:%.*]], i32 1)
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[UMAX1]], 4
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
-; CHECK: vector.scevcheck:
-; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.usub.sat.i32(i32 [[N]], i32 1)
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 0
-; CHECK-NEXT: br i1 [[TMP1]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i32 [[UMAX1]], 3
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[UMAX1]], [[N_MOD_VF]]
@@ -811,8 +807,8 @@ define void @sink_dominance(ptr %ptr, i32 %N) {
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[UMAX1]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
; CHECK: scalar.ph:
-; CHECK-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i64 [ [[VECTOR_RECUR_EXTRACT]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ]
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ], [ 0, [[VECTOR_SCEVCHECK]] ]
+; CHECK-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i64 [ [[VECTOR_RECUR_EXTRACT]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[SCALAR_RECUR:%.*]] = phi i64 [ [[SCALAR_RECUR_INIT]], [[SCALAR_PH]] ], [ [[FOR_NEXT:%.*]], [[LOOP]] ]
@@ -861,11 +857,7 @@ define void @sink_dominance_2(ptr %ptr, i32 %N) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[UMAX1:%.*]] = call i32 @llvm.umax.i32(i32 [[N:%.*]], i32 1)
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[UMAX1]], 4
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
-; CHECK: vector.scevcheck:
-; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.usub.sat.i32(i32 [[N]], i32 1)
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 0
-; CHECK-NEXT: br i1 [[TMP1]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i32 [[UMAX1]], 3
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[UMAX1]], [[N_MOD_VF]]
@@ -891,8 +883,8 @@ define void @sink_dominance_2(ptr %ptr, i32 %N) {
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[UMAX1]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
; CHECK: scalar.ph:
-; CHECK-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i64 [ [[VECTOR_RECUR_EXTRACT]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ]
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ], [ 0, [[VECTOR_SCEVCHECK]] ]
+; CHECK-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i64 [ [[VECTOR_RECUR_EXTRACT]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[SCALAR_RECUR:%.*]] = phi i64 [ [[SCALAR_RECUR_INIT]], [[SCALAR_PH]] ], [ [[FOR_NEXT:%.*]], [[LOOP]] ]
diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll
index db6aa937120c3..e44434d01adf3 100644
--- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll
+++ b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll
@@ -15,33 +15,10 @@ define i8 @recurrence_phi_with_same_incoming_values_after_simplifications(i8 %fo
; CHECK: [[VECTOR_BODY]]:
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i32 1, [[INDEX]]
-; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[OFFSET_IDX]], 1
-; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[OFFSET_IDX]], 2
-; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[OFFSET_IDX]], 3
-; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[OFFSET_IDX]], 4
-; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[OFFSET_IDX]], 5
-; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[OFFSET_IDX]], 6
-; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[OFFSET_IDX]], 7
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[OFFSET_IDX]]
-; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP2]]
-; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP3]]
-; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP4]]
-; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP5]]
-; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP6]]
-; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP7]]
-; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP8]]
-; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i8> [[TMP0]], i64 0
-; CHECK-NEXT: store i8 [[TMP17]], ptr [[TMP9]], align 1
-; CHECK-NEXT: [[TMP18:%.*]] = extractelement <4 x i8> [[TMP0]], i64 1
-; CHECK-NEXT: store i8 [[TMP18]], ptr [[TMP10]], align 1
-; CHECK-NEXT: [[TMP19:%.*]] = extractelement <4 x i8> [[TMP0]], i64 2
-; CHECK-NEXT: store i8 [[TMP19]], ptr [[TMP11]], align 1
-; CHECK-NEXT: [[TMP20:%.*]] = extractelement <4 x i8> [[TMP0]], i64 3
-; CHECK-NEXT: store i8 [[TMP20]], ptr [[TMP12]], align 1
-; CHECK-NEXT: store i8 [[TMP17]], ptr [[TMP13]], align 1
-; CHECK-NEXT: store i8 [[TMP18]], ptr [[TMP14]], align 1
-; CHECK-NEXT: store i8 [[TMP19]], ptr [[TMP15]], align 1
-; CHECK-NEXT: store i8 [[TMP20]], ptr [[TMP16]], align 1
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[TMP9]], i64 4
+; CHECK-NEXT: store <4 x i8> [[TMP0]], ptr [[TMP9]], align 1
+; CHECK-NEXT: store <4 x i8> [[TMP0]], ptr [[TMP3]], align 1
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
; CHECK-NEXT: [[TMP21:%.*]] = icmp eq i32 [[INDEX_NEXT]], -8
; CHECK-NEXT: br i1 [[TMP21]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
diff --git a/llvm/test/Transforms/LoopVectorize/interleaved-accesses-dead-member.ll b/llvm/test/Transforms/LoopVectorize/interleaved-accesses-dead-member.ll
index 32a5b38651d27..e0c0daadf7987 100644
--- a/llvm/test/Transforms/LoopVectorize/interleaved-accesses-dead-member.ll
+++ b/llvm/test/Transforms/LoopVectorize/interleaved-accesses-dead-member.ll
@@ -7,11 +7,7 @@ define void @dead_member_order(ptr noalias %src, ptr noalias %dst1, ptr noalias
; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST1:%.*]], ptr noalias [[DST2:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 0
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i32 [[N]], 3
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
@@ -73,11 +69,7 @@ define void @dead_member_metadata(ptr noalias %src, ptr noalias %dst, i32 %N) {
; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 0
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i32 [[N]], 3
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
diff --git a/llvm/test/Transforms/LoopVectorize/iv_outside_user.ll b/llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
index 8448f3eaba7d1..79c2490e6cd2b 100644
--- a/llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
+++ b/llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
@@ -1424,11 +1424,7 @@ define i32 @added_step(i32 %n, i32 %step_base, ptr %p) {
; VEC-NEXT: [[STEP:%.*]] = add i32 [[STEP_BASE]], 1
; VEC-NEXT: [[UMAX1:%.*]] = call i32 @llvm.umax.i32(i32 [[N]], i32 1)
; VEC-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[UMAX1]], 2
-; VEC-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; VEC: [[VECTOR_SCEVCHECK]]:
-; VEC-NEXT: [[TMP0:%.*]] = call i32 @llvm.usub.sat.i32(i32 [[N]], i32 1)
-; VEC-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 0
-; VEC-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; VEC-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; VEC: [[VECTOR_PH]]:
; VEC-NEXT: [[N_MOD_VF:%.*]] = and i32 [[UMAX1]], 1
; VEC-NEXT: [[N_VEC:%.*]] = sub i32 [[UMAX1]], [[N_MOD_VF]]
@@ -1451,7 +1447,7 @@ define i32 @added_step(i32 %n, i32 %step_base, ptr %p) {
; VEC-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[UMAX1]], [[N_VEC]]
; VEC-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; VEC: [[SCALAR_PH]]:
-; VEC-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
+; VEC-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; VEC-NEXT: br label %[[LOOP:.*]]
; VEC: [[LOOP]]:
; VEC-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
diff --git a/llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll b/llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
index d4beb9b078a6a..1ed675e9a1364 100644
--- a/llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
+++ b/llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
@@ -147,15 +147,7 @@ define signext i32 @f2(ptr noalias %A, ptr noalias %B, i32 signext %n) {
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[TMP0]] to i64
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[WIDE_TRIP_COUNT]], 4
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[WIDE_TRIP_COUNT]], -1
-; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32
-; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[TMP0]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[TMP3]], [[TMP0]]
-; CHECK-NEXT: [[TMP6:%.*]] = icmp ugt i64 [[TMP1]], 4294967295
-; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP4]], [[TMP6]]
-; CHECK-NEXT: br i1 [[TMP7]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
; CHECK: [[VECTOR_MAIN_LOOP_ITER_CHECK]]:
; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[WIDE_TRIP_COUNT]], 8
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]]
@@ -212,8 +204,8 @@ define signext i32 @f2(ptr noalias %A, ptr noalias %B, i32 signext %n) {
; CHECK-NEXT: [[CMP_N6:%.*]] = icmp eq i64 [[WIDE_TRIP_COUNT]], [[N_VEC3]]
; CHECK-NEXT: br i1 [[CMP_N6]], label %[[FOR_END_LOOPEXIT]], label %[[VEC_EPILOG_SCALAR_PH]]
; CHECK: [[VEC_EPILOG_SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL8:%.*]] = phi i64 [ [[N_VEC3]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ITER_CHECK]] ]
-; CHECK-NEXT: [[BC_RESUME_VAL9:%.*]] = phi i32 [ [[IND_END]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[IND_END4]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ITER_CHECK]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL8:%.*]] = phi i64 [ [[N_VEC3]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ITER_CHECK]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL9:%.*]] = phi i32 [ [[IND_END]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[IND_END4]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ITER_CHECK]] ]
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
; CHECK: [[FOR_BODY]]:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL8]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY]] ]
@@ -918,7 +910,7 @@ exit:
; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}
; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]], [[META2]]}
-; CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]]}
+; CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META2]], [[META1]]}
; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]], [[META2]]}
; CHECK: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]}
; CHECK: [[LOOP11]] = distinct !{[[LOOP11]], [[META2]], [[META1]]}
diff --git a/llvm/test/Transforms/LoopVectorize/pointer-induction.ll b/llvm/test/Transforms/LoopVectorize/pointer-induction.ll
index 0ee54814ae02e..63331f508136b 100644
--- a/llvm/test/Transforms/LoopVectorize/pointer-induction.ll
+++ b/llvm/test/Transforms/LoopVectorize/pointer-induction.ll
@@ -282,11 +282,7 @@ define void @outside_lattice(ptr noalias %p, ptr noalias %q, i32 %n) {
; DEFAULT-NEXT: [[TMP0:%.*]] = zext i32 [[N:%.*]] to i64
; DEFAULT-NEXT: [[TMP1:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP0]], i64 1)
; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 4
-; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
-; DEFAULT: vector.scevcheck:
-; DEFAULT-NEXT: [[TMP2:%.*]] = call i32 @llvm.usub.sat.i32(i32 [[N]], i32 1)
-; DEFAULT-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP2]], 0
-; DEFAULT-NEXT: br i1 [[TMP3]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
+; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; DEFAULT: vector.ph:
; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = and i64 [[TMP1]], 3
; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[N_MOD_VF]]
@@ -313,8 +309,8 @@ define void @outside_lattice(ptr noalias %p, ptr noalias %q, i32 %n) {
; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP1]], [[N_VEC]]
; DEFAULT-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[SCALAR_PH]]
; DEFAULT: scalar.ph:
-; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP5]], [[MIDDLE_BLOCK]] ], [ [[P]], [[ENTRY:%.*]] ], [ [[P]], [[VECTOR_SCEVCHECK]] ]
-; DEFAULT-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i32 [ [[TMP6]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ], [ 0, [[VECTOR_SCEVCHECK]] ]
+; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP5]], [[MIDDLE_BLOCK]] ], [ [[P]], [[ENTRY:%.*]] ]
+; DEFAULT-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i32 [ [[TMP6]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ]
; DEFAULT-NEXT: br label [[FOR_BODY:%.*]]
; DEFAULT: for.body:
; DEFAULT-NEXT: [[IV_PTR:%.*]] = phi ptr [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_PTR_NEXT:%.*]], [[FOR_BODY]] ]
@@ -335,11 +331,7 @@ define void @outside_lattice(ptr noalias %p, ptr noalias %q, i32 %n) {
; STRIDED-NEXT: [[TMP0:%.*]] = zext i32 [[N:%.*]] to i64
; STRIDED-NEXT: [[TMP1:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP0]], i64 1)
; STRIDED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 4
-; STRIDED-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
-; STRIDED: vector.scevcheck:
-; STRIDED-NEXT: [[TMP2:%.*]] = call i32 @llvm.usub.sat.i32(i32 [[N]], i32 1)
-; STRIDED-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP2]], 0
-; STRIDED-NEXT: br i1 [[TMP3]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
+; STRIDED-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; STRIDED: vector.ph:
; STRIDED-NEXT: [[N_MOD_VF:%.*]] = and i64 [[TMP1]], 3
; STRIDED-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[N_MOD_VF]]
@@ -366,8 +358,8 @@ define void @outside_lattice(ptr noalias %p, ptr noalias %q, i32 %n) {
; STRIDED-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP1]], [[N_VEC]]
; STRIDED-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[SCALAR_PH]]
; STRIDED: scalar.ph:
-; STRIDED-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP5]], [[MIDDLE_BLOCK]] ], [ [[P]], [[ENTRY:%.*]] ], [ [[P]], [[VECTOR_SCEVCHECK]] ]
-; STRIDED-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i32 [ [[TMP6]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ], [ 0, [[VECTOR_SCEVCHECK]] ]
+; STRIDED-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP5]], [[MIDDLE_BLOCK]] ], [ [[P]], [[ENTRY:%.*]] ]
+; STRIDED-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i32 [ [[TMP6]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ]
; STRIDED-NEXT: br label [[FOR_BODY:%.*]]
; STRIDED: for.body:
; STRIDED-NEXT: [[IV_PTR:%.*]] = phi ptr [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_PTR_NEXT:%.*]], [[FOR_BODY]] ]
diff --git a/llvm/test/Transforms/LoopVectorize/reverse_induction.ll b/llvm/test/Transforms/LoopVectorize/reverse_induction.ll
index f72afc8a3a391..ad32acccd013c 100644
--- a/llvm/test/Transforms/LoopVectorize/reverse_induction.ll
+++ b/llvm/test/Transforms/LoopVectorize/reverse_induction.ll
@@ -116,26 +116,52 @@ define i32 @reverse_induction_i16(i16 %startval, ptr %ptr) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: br label %[[VECTOR_SCEVCHECK:.*]]
; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i16 [[STARTVAL]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = sub i16 [[TMP0]], 1023
-; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i16 [[TMP1]], [[TMP0]]
-; CHECK-NEXT: br i1 [[TMP2]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
-; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_SCEVCHECK]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_SCEVCHECK]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_SCEVCHECK]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i32 [[INDEX]] to i16
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i16 [[STARTVAL]], [[DOTCAST]]
; CHECK-NEXT: [[TMP7:%.*]] = add i16 [[OFFSET_IDX]], -1
-; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[PTR]], i16 [[TMP7]]
-; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[TMP9]], i64 -3
-; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP9]], i64 -7
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP11]], align 4
-; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP13]], align 4
-; CHECK-NEXT: [[REVERSE:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
-; CHECK-NEXT: [[REVERSE4:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD3]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT: [[TMP3:%.*]] = add i16 [[OFFSET_IDX]], -2
+; CHECK-NEXT: [[TMP4:%.*]] = add i16 [[OFFSET_IDX]], -3
+; CHECK-NEXT: [[TMP5:%.*]] = add i16 [[OFFSET_IDX]], -4
+; CHECK-NEXT: [[TMP6:%.*]] = add i16 [[OFFSET_IDX]], -5
+; CHECK-NEXT: [[TMP32:%.*]] = add i16 [[OFFSET_IDX]], -6
+; CHECK-NEXT: [[TMP8:%.*]] = add i16 [[OFFSET_IDX]], -7
+; CHECK-NEXT: [[TMP9:%.*]] = add i16 [[OFFSET_IDX]], -1
+; CHECK-NEXT: [[TMP10:%.*]] = add i16 [[TMP7]], -1
+; CHECK-NEXT: [[TMP11:%.*]] = add i16 [[TMP3]], -1
+; CHECK-NEXT: [[TMP12:%.*]] = add i16 [[TMP4]], -1
+; CHECK-NEXT: [[TMP13:%.*]] = add i16 [[TMP5]], -1
+; CHECK-NEXT: [[TMP40:%.*]] = add i16 [[TMP6]], -1
+; CHECK-NEXT: [[TMP41:%.*]] = add i16 [[TMP32]], -1
+; CHECK-NEXT: [[TMP42:%.*]] = add i16 [[TMP8]], -1
+; CHECK-NEXT: [[TMP43:%.*]] = getelementptr inbounds i32, ptr [[PTR]], i16 [[TMP9]]
+; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[PTR]], i16 [[TMP10]]
+; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[PTR]], i16 [[TMP11]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i32, ptr [[PTR]], i16 [[TMP12]]
+; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, ptr [[PTR]], i16 [[TMP13]]
+; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i32, ptr [[PTR]], i16 [[TMP40]]
+; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i32, ptr [[PTR]], i16 [[TMP41]]
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i32, ptr [[PTR]], i16 [[TMP42]]
+; CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP43]], align 4
+; CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP18]], align 4
+; CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP19]], align 4
+; CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP20]], align 4
+; CHECK-NEXT: [[TMP29:%.*]] = insertelement <4 x i32> poison, i32 [[TMP25]], i64 0
+; CHECK-NEXT: [[TMP30:%.*]] = insertelement <4 x i32> [[TMP29]], i32 [[TMP26]], i64 1
+; CHECK-NEXT: [[TMP31:%.*]] = insertelement <4 x i32> [[TMP30]], i32 [[TMP27]], i64 2
+; CHECK-NEXT: [[REVERSE:%.*]] = insertelement <4 x i32> [[TMP31]], i32 [[TMP28]], i64 3
+; CHECK-NEXT: [[TMP33:%.*]] = load i32, ptr [[TMP21]], align 4
+; CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr [[TMP22]], align 4
+; CHECK-NEXT: [[TMP35:%.*]] = load i32, ptr [[TMP23]], align 4
+; CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP24]], align 4
+; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x i32> poison, i32 [[TMP33]], i64 0
+; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i32> [[TMP37]], i32 [[TMP34]], i64 1
+; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i32> [[TMP38]], i32 [[TMP35]], i64 2
+; CHECK-NEXT: [[REVERSE4:%.*]] = insertelement <4 x i32> [[TMP39]], i32 [[TMP36]], i64 3
; CHECK-NEXT: [[TMP14]] = add <4 x i32> [[REVERSE]], [[VEC_PHI]]
; CHECK-NEXT: [[TMP15]] = add <4 x i32> [[REVERSE4]], [[VEC_PHI2]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
@@ -144,23 +170,9 @@ define i32 @reverse_induction_i16(i16 %startval, ptr %ptr) {
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP15]], [[TMP14]]
; CHECK-NEXT: [[TMP17:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX]])
-; CHECK-NEXT: br label %[[LOOPEND:.*]]
-; CHECK: [[SCALAR_PH]]:
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
; CHECK: [[FOR_BODY]]:
-; CHECK-NEXT: [[ADD_I7:%.*]] = phi i16 [ [[STARTVAL]], %[[SCALAR_PH]] ], [ [[ADD_I:%.*]], %[[FOR_BODY]] ]
-; CHECK-NEXT: [[I_06:%.*]] = phi i32 [ 0, %[[SCALAR_PH]] ], [ [[INC4:%.*]], %[[FOR_BODY]] ]
-; CHECK-NEXT: [[REDUX5:%.*]] = phi i32 [ 0, %[[SCALAR_PH]] ], [ [[INC_REDUX:%.*]], %[[FOR_BODY]] ]
-; CHECK-NEXT: [[ADD_I]] = add i16 [[ADD_I7]], -1
-; CHECK-NEXT: [[KIND__I:%.*]] = getelementptr inbounds i32, ptr [[PTR]], i16 [[ADD_I]]
-; CHECK-NEXT: [[TMP_I1:%.*]] = load i32, ptr [[KIND__I]], align 4
-; CHECK-NEXT: [[INC_REDUX]] = add i32 [[TMP_I1]], [[REDUX5]]
-; CHECK-NEXT: [[INC4]] = add i32 [[I_06]], 1
-; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[INC4]], 1024
-; CHECK-NEXT: br i1 [[EXITCOND]], label %[[FOR_BODY]], label %[[LOOPEND]], !llvm.loop [[LOOP5:![0-9]+]]
-; CHECK: [[LOOPEND]]:
-; CHECK-NEXT: [[INC_REDUX_LCSSA:%.*]] = phi i32 [ [[INC_REDUX]], %[[FOR_BODY]] ], [ [[TMP17]], %[[MIDDLE_BLOCK]] ]
-; CHECK-NEXT: ret i32 [[INC_REDUX_LCSSA]]
+; CHECK-NEXT: ret i32 [[TMP17]]
;
entry:
br label %for.body
@@ -224,7 +236,7 @@ define void @reverse_forward_induction_i64_i8() {
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i8> [[STEP_ADD]], splat (i8 4)
; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
-; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: br label %[[WHILE_END:.*]]
; CHECK: [[WHILE_END]]:
@@ -275,7 +287,7 @@ define void @reverse_forward_induction_i64_i8_signed() {
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i8> [[STEP_ADD]], splat (i8 4)
; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
-; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
+; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: br label %[[WHILE_END:.*]]
; CHECK: [[WHILE_END]]:
@@ -305,7 +317,6 @@ while.end:
; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]], [[META2]]}
; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
-; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]}
+; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]], [[META2]]}
; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}
-; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]], [[META2]]}
;.
diff --git a/llvm/test/Transforms/LoopVectorize/simplify-logic.ll b/llvm/test/Transforms/LoopVectorize/simplify-logic.ll
index 2a3e645b65045..c6aa91453cd10 100644
--- a/llvm/test/Transforms/LoopVectorize/simplify-logic.ll
+++ b/llvm/test/Transforms/LoopVectorize/simplify-logic.ll
@@ -7,11 +7,7 @@ define void @logical_and(ptr noalias %p, ptr noalias %q, ptr noalias %r, i32 %n)
; CHECK-SAME: ptr noalias [[P:%.*]], ptr noalias [[Q:%.*]], ptr noalias [[R:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 0
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i32 [[N]], 3
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
@@ -66,11 +62,7 @@ define void @logical_and_outer_commute(ptr noalias %p, ptr noalias %q, ptr noali
; CHECK-SAME: ptr noalias [[P:%.*]], ptr noalias [[Q:%.*]], ptr noalias [[R:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 0
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i32 [[N]], 3
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
@@ -126,11 +118,7 @@ define void @logical_and_inner_commute(ptr noalias %p, ptr noalias %q, ptr noali
; CHECK-SAME: ptr noalias [[P:%.*]], ptr noalias [[Q:%.*]], ptr noalias [[R:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 0
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i32 [[N]], 3
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
@@ -185,11 +173,7 @@ define void @logical_and_inner_outer_commute(ptr noalias %p, ptr noalias %q, ptr
; CHECK-SAME: ptr noalias [[P:%.*]], ptr noalias [[Q:%.*]], ptr noalias [[R:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 0
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i32 [[N]], 3
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
@@ -245,11 +229,7 @@ define void @logical_or(ptr noalias %p, ptr noalias %q, ptr noalias %r, i32 %n)
; CHECK-SAME: ptr noalias [[P:%.*]], ptr noalias [[Q:%.*]], ptr noalias [[R:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 0
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i32 [[N]], 3
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
@@ -305,11 +285,7 @@ define void @logical_or_outer_commute(ptr noalias %p, ptr noalias %q, ptr noalia
; CHECK-SAME: ptr noalias [[P:%.*]], ptr noalias [[Q:%.*]], ptr noalias [[R:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 0
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i32 [[N]], 3
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
@@ -365,11 +341,7 @@ define void @logical_or_inner_commute(ptr noalias %p, ptr noalias %q, ptr noalia
; CHECK-SAME: ptr noalias [[P:%.*]], ptr noalias [[Q:%.*]], ptr noalias [[R:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 0
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i32 [[N]], 3
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
@@ -425,11 +397,7 @@ define void @logical_or_inner_outer_commute(ptr noalias %p, ptr noalias %q, ptr
; CHECK-SAME: ptr noalias [[P:%.*]], ptr noalias [[Q:%.*]], ptr noalias [[R:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 0
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i32 [[N]], 3
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
diff --git a/llvm/test/Transforms/LoopVectorize/widen-intrinsic-tail-fold.ll b/llvm/test/Transforms/LoopVectorize/widen-intrinsic-tail-fold.ll
index 69a50456657ea..f5dbde204a7b9 100644
--- a/llvm/test/Transforms/LoopVectorize/widen-intrinsic-tail-fold.ll
+++ b/llvm/test/Transforms/LoopVectorize/widen-intrinsic-tail-fold.ll
@@ -7,15 +7,11 @@ define void @tf_ctlz_range(ptr %p, i32 %n) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: br label %[[VECTOR_SCEVCHECK:.*]]
; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 0
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
-; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 0, i32 [[N]])
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], %[[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_SCEVCHECK]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], %[[VECTOR_SCEVCHECK]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[P]], i32 [[INDEX]]
; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 [[TMP2]], <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i32> poison)
; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> [[WIDE_MASKED_LOAD]], i1 false)
@@ -24,21 +20,10 @@ define void @tf_ctlz_range(ptr %p, i32 %n) {
; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 [[INDEX_NEXT]], i32 [[N]])
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i1> [[ACTIVE_LANE_MASK_NEXT]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = xor i1 [[TMP4]], true
-; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
-; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: br label %[[EXIT:.*]]
+; CHECK-NEXT: br i1 [[TMP5]], label %[[SCALAR_PH:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: [[SCALAR_PH]]:
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[P_GEP:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
-; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[P_GEP]], align 4
-; CHECK-NEXT: [[Y:%.*]] = call i32 @llvm.ctlz.i32(i32 range(i32 1, 0) [[X]], i1 false)
-; CHECK-NEXT: store i32 [[Y]], ptr [[P_GEP]], align 4
-; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
-; CHECK-NEXT: [[DONE:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
-; CHECK: [[EXIT]]:
; CHECK-NEXT: ret void
;
entry:
@@ -64,15 +49,11 @@ define void @tf_minnum_noundef(ptr noalias %p, ptr noalias %q, i32 %n) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: br label %[[VECTOR_SCEVCHECK:.*]]
; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 0
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
-; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 0, i32 [[N]])
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], %[[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_SCEVCHECK]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], %[[VECTOR_SCEVCHECK]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr float, ptr [[P]], i32 [[INDEX]]
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr float, ptr [[Q]], i32 [[INDEX]]
; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x float> @llvm.masked.load.v4f32.p0(ptr align 4 [[TMP2]], <4 x i1> [[ACTIVE_LANE_MASK]], <4 x float> poison)
@@ -83,23 +64,10 @@ define void @tf_minnum_noundef(ptr noalias %p, ptr noalias %q, i32 %n) {
; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 [[INDEX_NEXT]], i32 [[N]])
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i1> [[ACTIVE_LANE_MASK_NEXT]], i64 0
; CHECK-NEXT: [[TMP6:%.*]] = xor i1 [[TMP5]], true
-; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
-; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: br label %[[EXIT:.*]]
+; CHECK-NEXT: br i1 [[TMP6]], label %[[SCALAR_PH:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: [[SCALAR_PH]]:
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[P_GEP:%.*]] = getelementptr float, ptr [[P]], i32 [[IV]]
-; CHECK-NEXT: [[Q_GEP:%.*]] = getelementptr float, ptr [[Q]], i32 [[IV]]
-; CHECK-NEXT: [[A:%.*]] = load float, ptr [[P_GEP]], align 4
-; CHECK-NEXT: [[B:%.*]] = load float, ptr [[Q_GEP]], align 4
-; CHECK-NEXT: [[Y:%.*]] = call noundef float @llvm.minnum.f32(float [[A]], float [[B]])
-; CHECK-NEXT: store float [[Y]], ptr [[P_GEP]], align 4
-; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
-; CHECK-NEXT: [[DONE:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
-; CHECK: [[EXIT]]:
; CHECK-NEXT: ret void
;
entry:
diff --git a/llvm/test/Transforms/LoopVersioningLICM/loopversioningLICM1.ll b/llvm/test/Transforms/LoopVersioningLICM/loopversioningLICM1.ll
index 1f27894109de0..e9fc36a3ea77e 100644
--- a/llvm/test/Transforms/LoopVersioningLICM/loopversioningLICM1.ll
+++ b/llvm/test/Transforms/LoopVersioningLICM/loopversioningLICM1.ll
@@ -27,8 +27,8 @@ define i32 @foo(ptr nocapture %var1, ptr nocapture readnone %var2, ptr nocapture
; CHECK-NEXT: [[CMP212:%.*]] = icmp ult i32 [[J_016]], [[ITR]]
; CHECK-NEXT: br i1 [[CMP212]], label [[FOR_BODY3_LVER_CHECK:%.*]], label [[FOR_INC11]]
; CHECK: for.body3.lver.check:
-; CHECK-NEXT: [[ADD:%.*]] = add i32 [[I_015]], [[ITR]]
-; CHECK-NEXT: [[IDXPROM6:%.*]] = zext i32 [[I_015]] to i64
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[I_015]], [[ITR]]
+; CHECK-NEXT: [[IDXPROM6:%.*]] = zext nneg i32 [[I_015]] to i64
; CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[VAR3]], i64 [[IDXPROM6]]
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[J_016]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = shl nuw nsw i64 [[TMP3]], 2
@@ -78,7 +78,7 @@ define i32 @foo(ptr nocapture %var1, ptr nocapture readnone %var2, ptr nocapture
; CHECK-NEXT: br label [[FOR_INC11]]
; CHECK: for.inc11:
; CHECK-NEXT: [[J_1_LCSSA]] = phi i32 [ [[J_016]], [[FOR_COND1_PREHEADER]] ], [ [[ITR]], [[FOR_INC11_LOOPEXIT]] ]
-; CHECK-NEXT: [[INC12]] = add nuw i32 [[I_015]], 1
+; CHECK-NEXT: [[INC12]] = add nuw nsw i32 [[I_015]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[INC12]], [[ITR]]
; CHECK-NEXT: [[INDVAR_NEXT]] = add i64 [[INDVAR]], 1
; CHECK-NEXT: br i1 [[CMP]], label [[FOR_COND1_PREHEADER]], label [[FOR_END13_LOOPEXIT:%.*]]
diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/constraint-elimination-placement.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/constraint-elimination-placement.ll
index be18ec052c8d0..4c15cba04f261 100644
--- a/llvm/test/Transforms/PhaseOrdering/AArch64/constraint-elimination-placement.ll
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/constraint-elimination-placement.ll
@@ -33,8 +33,7 @@ define i1 @test_order_1(ptr %this, ptr noalias %other, i1 %tobool9.not, i32 %cal
; CHECK-NEXT: br i1 [[CMP44]], label [[FOR_BODY45]], label [[FOR_COND]]
; CHECK: for.inc57:
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[INDVARS_IV_NEXT]], 4294967295
-; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[TMP1]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV]], 0
; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND41_PREHEADER_PREHEADER]], label [[FOR_COND41_PREHEADER]]
; CHECK: exit:
; CHECK-NEXT: ret i1 false
diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll
index bfed4b193562f..e60ba2f0f8703 100644
--- a/llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll
@@ -33,7 +33,7 @@ define void @partial_unroll_forced(i32 %N, ptr %src, ptr noalias %dst) {
; CHECK-NEXT: [[ADD_1:%.*]] = fadd <8 x half> [[L_1]], [[L_1]]
; CHECK-NEXT: store <8 x half> [[ADD_1]], ptr [[DST_IDX_1]], align 16
; CHECK-NEXT: [[INDVARS_IV_NEXT_1]] = add nuw nsw i64 [[INDVARS_IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[EXIT_LOOPEXIT_UNR_LCSSA:%.*]], label [[LOOP_LATCH]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: exit.loopexit.unr-lcssa:
@@ -107,7 +107,7 @@ define void @cse_matching_load_from_previous_unrolled_iteration(i32 %N, ptr %src
; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr [8 x i8], ptr [[DST]], i64 [[INDVARS_IV_NEXT]]
; CHECK-NEXT: store <2 x i32> [[MUL_1]], ptr [[GEP_DST_1]], align 8
; CHECK-NEXT: [[INDVARS_IV_NEXT_1]] = add nuw nsw i64 [[INDVARS_IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw nsw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[EXIT_LOOPEXIT_UNR_LCSSA:%.*]], label [[LOOP_LATCH]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: exit.loopexit.unr-lcssa:
diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/hoist-runtime-checks.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/hoist-runtime-checks.ll
index 5a1dd3dcc6ef4..28161bca600ee 100644
--- a/llvm/test/Transforms/PhaseOrdering/AArch64/hoist-runtime-checks.ll
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/hoist-runtime-checks.ll
@@ -182,7 +182,7 @@ define dso_local noundef i32 @sum_prefix_with_sum(ptr %s.coerce0, i64 %s.coerce1
; CHECK-NEXT: [[VEC_PHI9:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH1]] ], [ [[TMP4:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[VEC_PHI11:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH1]] ], [ [[TMP9:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[VEC_PHI12:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH1]] ], [ [[TMP8:%.*]], [[FOR_BODY]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x i8], ptr [[S_COERCE0]], i64 [[INDEX]]
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[S_COERCE0]], i64 [[INDEX]]
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 16
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 32
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 48
@@ -216,7 +216,7 @@ define dso_local noundef i32 @sum_prefix_with_sum(ptr %s.coerce0, i64 %s.coerce1
; CHECK: vec.epilog.vector.body:
; CHECK-NEXT: [[INDEX20:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT23:%.*]], [[FOR_BODY1]] ]
; CHECK-NEXT: [[VEC_PHI21:%.*]] = phi <4 x i32> [ [[TMP11]], [[VEC_EPILOG_PH]] ], [ [[TMP13:%.*]], [[FOR_BODY1]] ]
-; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8], ptr [[S_COERCE0]], i64 [[INDEX20]]
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[S_COERCE0]], i64 [[INDEX20]]
; CHECK-NEXT: [[WIDE_LOAD22:%.*]] = load <4 x i32>, ptr [[TMP12]], align 4
; CHECK-NEXT: [[TMP13]] = add <4 x i32> [[WIDE_LOAD22]], [[VEC_PHI21]]
; CHECK-NEXT: [[INDEX_NEXT23]] = add nuw i64 [[INDEX20]], 4
@@ -236,10 +236,10 @@ define dso_local noundef i32 @sum_prefix_with_sum(ptr %s.coerce0, i64 %s.coerce1
; CHECK: for.body:
; CHECK-NEXT: [[I_07:%.*]] = phi i64 [ [[INC:%.*]], [[FOR_BODY2]] ], [ [[I_07_PH]], [[FOR_BODY_PREHEADER11]] ]
; CHECK-NEXT: [[RET_06:%.*]] = phi i32 [ [[ADD1]], [[FOR_BODY2]] ], [ [[RET_06_PH]], [[FOR_BODY_PREHEADER11]] ]
-; CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [4 x i8], ptr [[S_COERCE0]], i64 [[I_07]]
+; CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[S_COERCE0]], i64 [[I_07]]
; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX_I]], align 4
; CHECK-NEXT: [[ADD1]] = add nsw i32 [[TMP7]], [[RET_06]]
-; CHECK-NEXT: [[INC]] = add nuw i64 [[I_07]], 1
+; CHECK-NEXT: [[INC]] = add nuw nsw i64 [[I_07]], 1
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]]
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY2]], !llvm.loop [[LOOP9:![0-9]+]]
; CHECK: cond.false.i:
diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/peel-multiple-unreachable-exits-for-vectorization.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/peel-multiple-unreachable-exits-for-vectorization.ll
index 0ecc93c8d1cf5..4122496e99482 100644
--- a/llvm/test/Transforms/PhaseOrdering/AArch64/peel-multiple-unreachable-exits-for-vectorization.ll
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/peel-multiple-unreachable-exits-for-vectorization.ll
@@ -95,7 +95,7 @@ define i64 @sum_2_at_with_int_conversion(ptr %A, ptr %B, i64 %N) {
; CHECK-NEXT: [[LV_I9:%.*]] = load i64, ptr [[GEP_IDX_I8]], align 8
; CHECK-NEXT: [[ADD:%.*]] = add i64 [[LV_I]], [[SUM]]
; CHECK-NEXT: [[SUM_NEXT]] = add i64 [[ADD]], [[LV_I9]]
-; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV]], [[SMAX]]
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: error.i:
@@ -241,7 +241,7 @@ define i64 @sum_3_at_with_int_conversion(ptr %A, ptr %B, ptr %C, i64 %N) {
; CHECK-NEXT: [[ADD_1:%.*]] = add i64 [[LV_I]], [[SUM]]
; CHECK-NEXT: [[ADD_2:%.*]] = add i64 [[ADD_1]], [[LV_I9]]
; CHECK-NEXT: [[SUM_NEXT]] = add i64 [[ADD_2]], [[LV_I20]]
-; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV]], [[SMAX]]
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK: error.i:
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll b/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll
index b264d3a630e41..af99675b51b8a 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll
@@ -37,7 +37,7 @@ define dso_local void @_Z13vecIncFromPtrP12FloatVecPair(ptr %FVP) {
; O1-NEXT: [[TMP6:%.*]] = load float, ptr [[ARRAYIDX_I5_I]], align 4, !tbaa [[FLOAT_TBAA9]]
; O1-NEXT: [[ADD_I:%.*]] = fadd float [[TMP5]], [[TMP6]]
; O1-NEXT: store float [[ADD_I]], ptr [[ARRAYIDX_I5_I]], align 4, !tbaa [[FLOAT_TBAA9]]
-; O1-NEXT: [[INC_I]] = add nuw i32 [[J_07_I]], 1
+; O1-NEXT: [[INC_I]] = add nuw nsw i32 [[J_07_I]], 1
; O1-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[TMP1]]
; O1-NEXT: br i1 [[EXITCOND_NOT_I]], label %[[_ZN12FLOATVECPAIR6VECINCEV_EXIT]], label %[[FOR_BODY7_I]], !llvm.loop [[LOOP11:![0-9]+]]
; O1: [[_ZN12FLOATVECPAIR6VECINCEV_EXIT]]:
@@ -68,7 +68,7 @@ define dso_local void @_Z13vecIncFromPtrP12FloatVecPair(ptr %FVP) {
; O23-NEXT: [[TMP6:%.*]] = load float, ptr [[ARRAYIDX_I3_I]], align 4, !tbaa [[FLOAT_TBAA9]]
; O23-NEXT: [[ADD_I]] = fadd float [[TMP5]], [[TMP6]]
; O23-NEXT: store float [[ADD_I]], ptr [[ARRAYIDX_I5_I]], align 4, !tbaa [[FLOAT_TBAA9]]
-; O23-NEXT: [[INC_I]] = add nuw i32 [[J_07_I]], 1
+; O23-NEXT: [[INC_I]] = add nuw nsw i32 [[J_07_I]], 1
; O23-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[TMP1]]
; O23-NEXT: br i1 [[EXITCOND_NOT_I]], label %[[_ZN12FLOATVECPAIR6VECINCEV_EXIT]], label %[[FOR_BODY7_I]], !llvm.loop [[LOOP11:![0-9]+]]
; O23: [[_ZN12FLOATVECPAIR6VECINCEV_EXIT]]:
diff --git a/llvm/test/Transforms/PhaseOrdering/loop-access-checks.ll b/llvm/test/Transforms/PhaseOrdering/loop-access-checks.ll
index 7bba70a97b1bb..17a38a4d6210c 100644
--- a/llvm/test/Transforms/PhaseOrdering/loop-access-checks.ll
+++ b/llvm/test/Transforms/PhaseOrdering/loop-access-checks.ll
@@ -147,11 +147,11 @@ define void @foo(ptr noundef nonnull align 8 dereferenceable(24) noalias %vec) #
; CHECK-NEXT: ret void
; CHECK: [[FOR_BODY]]:
; CHECK-NEXT: [[I_010:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ 0, %[[ENTRY]] ]
-; CHECK-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds [8 x i8], ptr [[TMP1]], i64 [[I_010]]
+; CHECK-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds nuw [8 x i8], ptr [[TMP1]], i64 [[I_010]]
; CHECK-NEXT: [[TMP2:%.*]] = load double, ptr [[ADD_PTR_I]], align 8
; CHECK-NEXT: [[ADD:%.*]] = fadd double [[TMP2]], 1.000000e+00
; CHECK-NEXT: store double [[ADD]], ptr [[ADD_PTR_I]], align 8
-; CHECK-NEXT: [[INC]] = add nuw i64 [[I_010]], 1
+; CHECK-NEXT: [[INC]] = add nuw nsw i64 [[I_010]], 1
; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i64 [[INC]], [[SUB_PTR_DIV_I_I]]
; CHECK-NEXT: br i1 [[CMP_NOT]], label %[[FOR_COND_CLEANUP]], label %[[FOR_BODY]]
;
@@ -354,7 +354,7 @@ define void @monkey(ptr noundef %arr, i32 noundef %len) {
; CHECK: [[FOR_COND_CLEANUP]]:
; CHECK-NEXT: ret void
; CHECK: [[FOR_COND_CLEANUP3]]:
-; CHECK-NEXT: [[INC]] = add nuw i32 [[I_09]], 1
+; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_09]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[INC]], [[LEN]]
; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_BODY4_PREHEADER]], label %[[FOR_COND_CLEANUP]]
; CHECK: [[FOR_BODY4]]:
@@ -364,7 +364,7 @@ define void @monkey(ptr noundef %arr, i32 noundef %len) {
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ADD_PTR_I]], align 4
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
; CHECK-NEXT: store i32 [[ADD]], ptr [[ADD_PTR_I]], align 4
-; CHECK-NEXT: [[DEC]] = add i32 [[K_07]], -1
+; CHECK-NEXT: [[DEC]] = add nsw i32 [[K_07]], -1
; CHECK-NEXT: [[CMP2_NOT:%.*]] = icmp eq i32 [[DEC]], 0
; CHECK-NEXT: br i1 [[CMP2_NOT]], label %[[FOR_COND_CLEANUP3]], label %[[FOR_BODY4]]
;
diff --git a/llvm/test/Transforms/PhaseOrdering/swap-promotion.ll b/llvm/test/Transforms/PhaseOrdering/swap-promotion.ll
index 059a122262786..35ac5003ebbe7 100644
--- a/llvm/test/Transforms/PhaseOrdering/swap-promotion.ll
+++ b/llvm/test/Transforms/PhaseOrdering/swap-promotion.ll
@@ -24,7 +24,7 @@ define i32 @test(i32 %n) {
; CHECK: loop:
; CHECK-NEXT: [[P1_SROA_5_0:%.*]] = phi i32 [ 1, [[TMP0:%.*]] ], [ [[V2_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[P1_SROA_0_0:%.*]] = phi i32 [ 0, [[TMP0]] ], [ [[V1_INC:%.*]], [[LOOP]] ]
-; CHECK-NEXT: [[V1_INC]] = add i32 [[P1_SROA_0_0]], 1
+; CHECK-NEXT: [[V1_INC]] = add nuw nsw i32 [[P1_SROA_0_0]], 1
; CHECK-NEXT: [[V2_NEXT]] = shl i32 [[P1_SROA_5_0]], 1
; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[V1_INC]], [[N:%.*]]
; CHECK-NEXT: br i1 [[C]], label [[EXIT:%.*]], label [[LOOP]]
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