[llvm] [SCEV] Rework wrap-flag-inference in zext-addrec (PR #217405)
Ramkumar Ramachandra via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 21 10:30:08 PDT 2026
https://github.com/artagnon updated https://github.com/llvm/llvm-project/pull/217405
>From 0526ad0a7ae855549d04f08d6675dd8b80f8bc65 Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: Wed, 19 Aug 2026 18:09:39 +0100
Subject: [PATCH 1/2] [SCEV] Rework wrap-flag-inferrence in zext-addrec
Rewrite getZeroExtendExprImpl to avoid the roundabout method of creating
zero-extend expressions to check no-wrap, by computing the no-wrap
information using induction and reading it off the expression directly.
The new code has much better compile-time, while not being exactly
equivalent to the old code.
---
llvm/lib/Analysis/ScalarEvolution.cpp | 132 +++---------------
.../no-wrap-unknown-becount.ll | 2 +-
.../CodeGen/PowerPC/hardware-loops-crash.ll | 9 +-
.../test/Transforms/IndVarSimplify/pr66066.ll | 2 +-
.../PhaseOrdering/scev-custom-dl.ll | 2 +-
5 files changed, 28 insertions(+), 119 deletions(-)
diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp
index ebd58c825faa5..60529a1159bcb 100644
--- a/llvm/lib/Analysis/ScalarEvolution.cpp
+++ b/llvm/lib/Analysis/ScalarEvolution.cpp
@@ -1656,117 +1656,36 @@ const SCEV *ScalarEvolution::getZeroExtendExprImpl(SCEVUse Op, Type *Ty,
// operands (often constants). This allows analysis of something like
// this: for (unsigned char X = 0; X < 100; ++X) { int Y = X; }
if (match(Op, m_scev_AffineAddRec(m_SCEV(Start), m_SCEV(Step), m_Loop(L)))) {
+ // Redo the AddRec check, computing nuw this time.
const auto *AR = cast<SCEVAddRecExpr>(Op);
- unsigned BitWidth = getTypeSizeInBits(AR->getType());
-
- // The no-unsigned-wrap case is handled before the uniquing lookup above.
-
- // Check whether the backedge-taken count is SCEVCouldNotCompute.
- // Note that this serves two purposes: It filters out loops that are
- // simply not analyzable, and it covers the case where this code is
- // being called from within backedge-taken count analysis, such that
- // attempting to ask for the backedge-taken count would likely result
- // in infinite recursion. In the later case, the analysis code will
- // cope with a conservative value, and it will take care to purge
- // that value once it has finished.
- const SCEV *MaxBECount = getConstantMaxBackedgeTakenCount(L);
- if (!isa<SCEVCouldNotCompute>(MaxBECount)) {
- // Manually compute the final value for AR, checking for overflow.
+ inferNoWrapViaConstantRanges(AR);
+ auto NewFlags = proveNoUnsignedWrapViaInduction(AR);
+ if (!hasFlags(NewFlags, SCEV::FlagNUW) &&
+ proveNoWrapByVaryingStart<SCEVZeroExtendExpr>(Start, Step, L))
+ NewFlags |= SCEV::FlagNUW;
+ setNoWrapFlags(const_cast<SCEVAddRecExpr *>(AR), NewFlags);
- // Check whether the backedge-taken count can be losslessly casted to
- // the addrec's type. The count is always unsigned.
- const SCEV *CastedMaxBECount =
- getTruncateOrZeroExtend(MaxBECount, Start->getType(), Depth);
- const SCEV *RecastedMaxBECount = getTruncateOrZeroExtend(
- CastedMaxBECount, MaxBECount->getType(), Depth);
- if (MaxBECount == RecastedMaxBECount) {
- Type *WideTy = IntegerType::get(getContext(), BitWidth * 2);
- // Check whether Start+Step*MaxBECount has no unsigned overflow.
- const SCEV *ZMul =
- getMulExpr(CastedMaxBECount, Step, SCEV::FlagAnyWrap, Depth + 1);
- const SCEV *ZAdd = getZeroExtendExpr(
- getAddExpr(Start, ZMul, SCEV::FlagAnyWrap, Depth + 1), WideTy,
- Depth + 1);
- const SCEV *WideStart = getZeroExtendExpr(Start, WideTy, Depth + 1);
- const SCEV *WideMaxBECount =
- getZeroExtendExpr(CastedMaxBECount, WideTy, Depth + 1);
- const SCEV *OperandExtendedAdd =
- getAddExpr(WideStart,
- getMulExpr(WideMaxBECount,
- getZeroExtendExpr(Step, WideTy, Depth + 1),
- SCEV::FlagAnyWrap, Depth + 1),
- SCEV::FlagAnyWrap, Depth + 1);
- if (ZAdd == OperandExtendedAdd) {
- // Cache knowledge of AR NUW, which is propagated to this AddRec.
- setNoWrapFlags(const_cast<SCEVAddRecExpr *>(AR), SCEV::FlagNUW);
- // Return the expression with the addrec on the outside.
- Start =
- getExtendAddRecStart<SCEVZeroExtendExpr>(AR, Ty, this, Depth + 1);
- Step = getZeroExtendExpr(Step, Ty, Depth + 1);
- return getAddRecExpr(Start, Step, L, AR->getNoWrapFlags());
- }
- // Similar to above, only this time treat the step value as signed.
- // This covers loops that count down.
- OperandExtendedAdd =
- getAddExpr(WideStart,
- getMulExpr(WideMaxBECount,
- getSignExtendExpr(Step, WideTy, Depth + 1),
- SCEV::FlagAnyWrap, Depth + 1),
- SCEV::FlagAnyWrap, Depth + 1);
- if (ZAdd == OperandExtendedAdd) {
- // Cache knowledge of AR NW, which is propagated to this AddRec.
- // Negative step causes unsigned wrap, but it still can't self-wrap.
- setNoWrapFlags(const_cast<SCEVAddRecExpr *>(AR), SCEV::FlagNW);
- // Return the expression with the addrec on the outside.
- Start =
- getExtendAddRecStart<SCEVZeroExtendExpr>(AR, Ty, this, Depth + 1);
- Step = getSignExtendExpr(Step, Ty, Depth + 1);
- return getAddRecExpr(Start, Step, L, AR->getNoWrapFlags());
- }
- }
+ // If we have nuw, the zero-extend distributes over the recurrence.
+ if (AR->hasNoUnsignedWrap()) {
+ Start = getExtendAddRecStart<SCEVZeroExtendExpr>(AR, Ty, this, Depth + 1);
+ Step = getZeroExtendExpr(Step, Ty, Depth + 1);
+ return getAddRecExpr(Start, Step, L, AR->getNoWrapFlags());
}
- // Normally, in the cases we can prove no-overflow via a
- // backedge guarding condition, we can also compute a backedge
- // taken count for the loop. The exceptions are assumptions and
- // guards present in the loop -- SCEV is not great at exploiting
- // these to compute max backedge taken counts, but can still use
- // these to prove lack of overflow. Use this fact to avoid
- // doing extra work that may not pay off.
- if (!isa<SCEVCouldNotCompute>(MaxBECount) || HasGuards ||
- !AC.assumptions().empty()) {
-
- auto NewFlags = proveNoUnsignedWrapViaInduction(AR);
- setNoWrapFlags(const_cast<SCEVAddRecExpr *>(AR), NewFlags);
- if (AR->hasNoUnsignedWrap()) {
- // Same as nuw case above - duplicated here to avoid a compile time
- // issue. It's not clear that the order of checks does matter, but
- // it's one of two issue possible causes for a change which was
- // reverted. Be conservative for the moment.
+ // For a negative step, we can sign-extend the step iff doing so only
+ // traverses values in the range sext([0,SMAX]). Note that this does not
+ // imply no-self-wrap.
+ if (isKnownNegative(Step)) {
+ unsigned BitWidth = getTypeSizeInBits(AR->getType());
+ const SCEV *N =
+ getConstant(APInt::getMaxValue(BitWidth) - getSignedRangeMin(Step));
+ if (isLoopBackedgeGuardedByCond(L, ICmpInst::ICMP_UGT, AR, N) ||
+ isKnownOnEveryIteration(ICmpInst::ICMP_UGT, AR, N)) {
Start =
getExtendAddRecStart<SCEVZeroExtendExpr>(AR, Ty, this, Depth + 1);
- Step = getZeroExtendExpr(Step, Ty, Depth + 1);
+ Step = getSignExtendExpr(Step, Ty, Depth + 1);
return getAddRecExpr(Start, Step, L, AR->getNoWrapFlags());
}
-
- // For a negative step, we can extend the operands iff doing so only
- // traverses values in the range zext([0,UINT_MAX]).
- if (isKnownNegative(Step)) {
- const SCEV *N =
- getConstant(APInt::getMaxValue(BitWidth) - getSignedRangeMin(Step));
- if (isLoopBackedgeGuardedByCond(L, ICmpInst::ICMP_UGT, AR, N) ||
- isKnownOnEveryIteration(ICmpInst::ICMP_UGT, AR, N)) {
- // Cache knowledge of AR NW, which is propagated to this
- // AddRec. Negative step causes unsigned wrap, but it
- // still can't self-wrap.
- setNoWrapFlags(const_cast<SCEVAddRecExpr *>(AR), SCEV::FlagNW);
- // Return the expression with the addrec on the outside.
- Start =
- getExtendAddRecStart<SCEVZeroExtendExpr>(AR, Ty, this, Depth + 1);
- Step = getSignExtendExpr(Step, Ty, Depth + 1);
- return getAddRecExpr(Start, Step, L, AR->getNoWrapFlags());
- }
- }
}
// zext({C,+,Step}) --> (zext(D) + zext({C-D,+,Step}))<nuw><nsw>
@@ -1784,13 +1703,6 @@ const SCEV *ScalarEvolution::getZeroExtendExprImpl(SCEVUse Op, Type *Ty,
Depth + 1);
}
}
-
- if (proveNoWrapByVaryingStart<SCEVZeroExtendExpr>(Start, Step, L)) {
- setNoWrapFlags(const_cast<SCEVAddRecExpr *>(AR), SCEV::FlagNUW);
- Start = getExtendAddRecStart<SCEVZeroExtendExpr>(AR, Ty, this, Depth + 1);
- Step = getZeroExtendExpr(Step, Ty, Depth + 1);
- return getAddRecExpr(Start, Step, L, AR->getNoWrapFlags());
- }
}
// zext(A % B) --> zext(A) % zext(B)
diff --git a/llvm/test/Analysis/ScalarEvolution/no-wrap-unknown-becount.ll b/llvm/test/Analysis/ScalarEvolution/no-wrap-unknown-becount.ll
index 0aa13c5b06ca2..bbc36da11dda7 100644
--- a/llvm/test/Analysis/ScalarEvolution/no-wrap-unknown-becount.ll
+++ b/llvm/test/Analysis/ScalarEvolution/no-wrap-unknown-becount.ll
@@ -251,7 +251,7 @@ define void @u_2(ptr %cond) {
; CHECK-NEXT: %iv.inc = add i32 %iv, -2
; CHECK-NEXT: --> {29998,+,-2}<%loop> U: [0,-1) S: [-2147483648,2147483647) Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %iv.zext = zext i32 %iv to i64
-; CHECK-NEXT: --> {30000,+,-2}<nw><%loop> U: [0,-1) S: [-9223372036854775808,9223372036854775807) Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
+; CHECK-NEXT: --> {30000,+,-2}<%loop> U: [0,-1) S: [-9223372036854775808,9223372036854775807) Exits: <<Unknown>> LoopDispositions: { %loop: Computable }
; CHECK-NEXT: %c = load volatile i1, ptr %cond, align 1
; CHECK-NEXT: --> %c U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Variant }
; CHECK-NEXT: Determining loop execution counts for: @u_2
diff --git a/llvm/test/CodeGen/PowerPC/hardware-loops-crash.ll b/llvm/test/CodeGen/PowerPC/hardware-loops-crash.ll
index afa0f8c4adc0a..7616847afef80 100644
--- a/llvm/test/CodeGen/PowerPC/hardware-loops-crash.ll
+++ b/llvm/test/CodeGen/PowerPC/hardware-loops-crash.ll
@@ -24,22 +24,19 @@ define void @test() {
; CHECK-NEXT: call void @llvm.set.loop.iterations.i64(i64 51)
; CHECK-NEXT: br label [[WHILE_COND25:%.*]]
; CHECK: while.cond25:
-; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ 0, [[WHILE_COND25_PREHEADER]] ], [ [[INDVAR_NEXT:%.*]], [[LAND_RHS:%.*]] ]
-; CHECK-NEXT: [[INDVARS_IV349:%.*]] = phi i64 [ [[INDVARS_IV_NEXT350:%.*]], [[LAND_RHS]] ], [ [[INDVARS_IV349_PH]], [[WHILE_COND25_PREHEADER]] ]
+; CHECK-NEXT: [[INDVARS_IV349:%.*]] = phi i64 [ [[INDVARS_IV_NEXT350:%.*]], [[LAND_RHS:%.*]] ], [ [[INDVARS_IV349_PH]], [[WHILE_COND25_PREHEADER]] ]
; CHECK-NEXT: [[TMP0:%.*]] = call i1 @llvm.loop.decrement.i64(i64 1)
; CHECK-NEXT: br i1 [[TMP0]], label [[LAND_RHS]], label [[WHILE_END187:%.*]]
; CHECK: land.rhs:
; CHECK-NEXT: [[INDVARS_IV_NEXT350]] = add nsw i64 [[INDVARS_IV349]], -1
; CHECK-NEXT: [[C_1:%.*]] = call i1 @cond()
-; CHECK-NEXT: [[INDVAR_NEXT]] = add i64 [[INDVAR]], 1
; CHECK-NEXT: br i1 [[C_1]], label [[WHILE_COND25]], label [[WHILE_END:%.*]]
; CHECK: while.end:
-; CHECK-NEXT: [[INDVAR_LCSSA1:%.*]] = phi i64 [ [[INDVAR]], [[LAND_RHS]] ]
; CHECK-NEXT: [[C_2:%.*]] = call i1 @cond()
; CHECK-NEXT: br i1 [[C_2]], label [[WHILE_END187]], label [[WHILE_COND35_PREHEADER:%.*]]
; CHECK: while.cond35.preheader:
-; CHECK-NEXT: [[TMP1:%.*]] = mul nsw i64 [[INDVAR_LCSSA1]], -1
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 51
+; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[INDVARS_IV349]], 4294967295
+; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
; CHECK-NEXT: call void @llvm.set.loop.iterations.i64(i64 [[TMP2]])
; CHECK-NEXT: br label [[WHILE_COND35:%.*]]
; CHECK: while.cond35:
diff --git a/llvm/test/Transforms/IndVarSimplify/pr66066.ll b/llvm/test/Transforms/IndVarSimplify/pr66066.ll
index 5bb0d8371b3e3..cfd29876b302d 100644
--- a/llvm/test/Transforms/IndVarSimplify/pr66066.ll
+++ b/llvm/test/Transforms/IndVarSimplify/pr66066.ll
@@ -9,7 +9,7 @@ define void @test() {
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i8 [ 1, [[ENTRY:%.*]] ], [ [[IV_DEC:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[IV_DEC]] = add nsw i8 [[IV]], -1
-; CHECK-NEXT: [[SHL:%.*]] = shl nuw i8 [[IV]], 7
+; CHECK-NEXT: [[SHL:%.*]] = shl i8 [[IV]], 7
; CHECK-NEXT: call void @use(i8 [[SHL]])
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[SHL]], 0
; CHECK-NEXT: br i1 [[CMP1]], label [[EXIT:%.*]], label [[LOOP]]
diff --git a/llvm/test/Transforms/PhaseOrdering/scev-custom-dl.ll b/llvm/test/Transforms/PhaseOrdering/scev-custom-dl.ll
index bdcaaca9390c5..60f2c30291eaa 100644
--- a/llvm/test/Transforms/PhaseOrdering/scev-custom-dl.ll
+++ b/llvm/test/Transforms/PhaseOrdering/scev-custom-dl.ll
@@ -141,7 +141,7 @@ define i32 @test_loop_idiom_recogize(i32 %x, i32 %y, ptr %lam, ptr %alp) nounwin
; CHECK-NEXT: Classifying expressions for: @test_loop_idiom_recogize
; CHECK-NEXT: %indvar = phi i32 [ 0, %bb1.thread ], [ %indvar.next, %bb1 ]
; CHECK-NEXT: --> {0,+,1}<nuw><nsw><%bb1> U: [0,256) S: [0,256) Exits: 255 LoopDispositions: { %bb1: Computable }
-; CHECK-NEXT: %i.0.reg2mem.0 = sub nuw nsw i32 255, %indvar
+; CHECK-NEXT: %i.0.reg2mem.0 = sub nsw i32 255, %indvar
; CHECK-NEXT: --> {255,+,-1}<nsw><%bb1> U: [0,256) S: [0,256) Exits: 0 LoopDispositions: { %bb1: Computable }
; CHECK-NEXT: %0 = getelementptr [4 x i8], ptr %alp, i32 %i.0.reg2mem.0
; CHECK-NEXT: --> {(1020 + %alp),+,-4}<nw><%bb1> U: full-set S: full-set Exits: %alp LoopDispositions: { %bb1: Computable }
>From c6bf88ae8c77050c244ac9c5e1b0a9b866416c57 Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: Fri, 21 Aug 2026 17:28:51 +0100
Subject: [PATCH 2/2] [SCEV] Learning from closed incorrect-nw patch
---
llvm/lib/Analysis/ScalarEvolution.cpp | 18 +-
.../ScalarEvolution/2012-05-29-MulAddRec.ll | 56 +++-
.../IndVarSimplify/2011-09-10-widen-nsw.ll | 30 +-
.../IndVarSimplify/AArch64/widen-loop-comp.ll | 7 +-
.../IndVarSimplify/ARM/code-size.ll | 4 +-
.../IndVarSimplify/X86/eliminate-trunc.ll | 18 +-
.../Transforms/IndVarSimplify/X86/iv-widen.ll | 2 +-
.../IndVarSimplify/X86/overflow-intrinsics.ll | 11 +-
.../Transforms/IndVarSimplify/X86/pr59615.ll | 5 +-
.../Transforms/IndVarSimplify/ada-loops.ll | 5 +-
.../addrec_no_exec_on_every_iteration.ll | 275 +++++++++++++++++-
.../Transforms/IndVarSimplify/elim-extend.ll | 2 +-
.../IndVarSimplify/eliminate-exit.ll | 8 +-
.../eliminate-max-from-min-exit.ll | 2 +-
.../IndVarSimplify/floating-point-iv.ll | 2 +-
.../IndVarSimplify/infer-poison-flags.ll | 6 +-
.../IndVarSimplify/iv-ext-samesign.ll | 96 +++---
.../test/Transforms/IndVarSimplify/iv-sext.ll | 4 +-
.../IndVarSimplify/iv-widen-elim-ext.ll | 6 +-
.../Transforms/IndVarSimplify/lftr-pr31181.ll | 8 +-
.../Transforms/IndVarSimplify/lftr-pr41998.ll | 4 +-
.../Transforms/IndVarSimplify/lftr-reuse.ll | 6 +-
llvm/test/Transforms/IndVarSimplify/lftr.ll | 4 +-
.../IndVarSimplify/pr30806-phi-scev.ll | 2 +-
.../test/Transforms/IndVarSimplify/pr55925.ll | 4 +-
.../test/Transforms/IndVarSimplify/pr79861.ll | 4 +-
.../IndVarSimplify/predicated_ranges.ll | 12 +-
.../IndVarSimplify/strengthen-overflow.ll | 2 +-
.../IndVarSimplify/widen-nonnegative.ll | 27 +-
llvm/test/Transforms/LoopFlatten/widen-iv.ll | 99 ++++---
llvm/test/Transforms/LoopFlatten/widen-iv2.ll | 5 +-
.../ARM/illegal-addr-modes.ll | 2 +-
.../RISCV/term-fold-crash.ll | 18 +-
.../lsr-term-fold-negative-testcase.ll | 2 +-
.../scev-incorrect-nuw-inference.ll | 19 +-
.../LoopUnroll/AArch64/apple-unrolling.ll | 20 +-
.../AArch64/runtime-unroll-generic.ll | 2 +-
.../Transforms/LoopUnroll/AArch64/vector.ll | 8 +-
.../unroll-convergent-uniform-tripcount.ll | 4 +-
.../Transforms/LoopUnroll/ARM/multi-blocks.ll | 2 +-
.../unroll-convergent-uniform-tripcount.ll | 4 +-
...unrolling-legalize-vectors-inseltpoison.ll | 2 +-
.../PowerPC/p8-unrolling-legalize-vectors.ll | 2 +-
.../Transforms/LoopUnroll/RISCV/vector.ll | 4 +-
.../LoopUnroll/convergent.controlled.ll | 10 +-
.../LoopUnroll/expensive-tripcount.ll | 2 +-
.../runtime-exit-phi-scev-invalidation.ll | 6 +-
.../Transforms/LoopUnroll/runtime-i128.ll | 4 +-
.../runtime-loop-at-most-two-exits.ll | 4 +-
.../LoopUnroll/runtime-loop-multiple-exits.ll | 118 ++++----
.../LoopUnroll/runtime-multiexit-heuristic.ll | 20 +-
.../runtime-unroll-assume-no-remainder.ll | 2 +-
.../runtime-unroll-reductions-min-max.ll | 48 +--
.../LoopUnroll/runtime-unroll-reductions.ll | 18 +-
.../LoopUnroll/runtime-unroll-remainder.ll | 2 +-
.../LoopUnroll/scev-invalidation-lcssa.ll | 4 +-
.../LoopUnroll/shifted-tripcount.ll | 4 +-
.../LoopUnroll/tripcount-overflow.ll | 4 +-
.../Transforms/LoopUnroll/unroll-loads-cse.ll | 10 +-
.../RISCV/riscv-vector-reverse.ll | 52 +---
.../X86/scev-checks-unprofitable.ll | 29 +-
.../nested-loops-scev-expansion.ll | 15 +-
llvm/test/Transforms/LoopVectorize/optsize.ll | 117 +++-----
.../LoopVersioningLICM/loopversioningLICM1.ll | 2 +-
.../AArch64/extra-unroll-simplifications.ll | 4 +-
.../PhaseOrdering/AArch64/loopflatten.ll | 24 +-
.../PhaseOrdering/SystemZ/sub-xor.ll | 131 +--------
.../PhaseOrdering/scev-custom-dl.ll | 2 +-
.../single-iteration-loop-sroa.ll | 12 +-
.../PhaseOrdering/swap-promotion.ll | 2 +-
70 files changed, 835 insertions(+), 634 deletions(-)
diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp
index 60529a1159bcb..89f666d9c3165 100644
--- a/llvm/lib/Analysis/ScalarEvolution.cpp
+++ b/llvm/lib/Analysis/ScalarEvolution.cpp
@@ -1656,13 +1656,13 @@ const SCEV *ScalarEvolution::getZeroExtendExprImpl(SCEVUse Op, Type *Ty,
// operands (often constants). This allows analysis of something like
// this: for (unsigned char X = 0; X < 100; ++X) { int Y = X; }
if (match(Op, m_scev_AffineAddRec(m_SCEV(Start), m_SCEV(Step), m_Loop(L)))) {
- // Redo the AddRec check, computing nuw this time.
+ // Redo the AddRec check, computing wrap-flags this time.
const auto *AR = cast<SCEVAddRecExpr>(Op);
inferNoWrapViaConstantRanges(AR);
auto NewFlags = proveNoUnsignedWrapViaInduction(AR);
if (!hasFlags(NewFlags, SCEV::FlagNUW) &&
proveNoWrapByVaryingStart<SCEVZeroExtendExpr>(Start, Step, L))
- NewFlags |= SCEV::FlagNUW;
+ NewFlags = setFlags(NewFlags, SCEV::FlagNUW);
setNoWrapFlags(const_cast<SCEVAddRecExpr *>(AR), NewFlags);
// If we have nuw, the zero-extend distributes over the recurrence.
@@ -1672,15 +1672,17 @@ const SCEV *ScalarEvolution::getZeroExtendExprImpl(SCEVUse Op, Type *Ty,
return getAddRecExpr(Start, Step, L, AR->getNoWrapFlags());
}
- // For a negative step, we can sign-extend the step iff doing so only
- // traverses values in the range sext([0,SMAX]). Note that this does not
- // imply no-self-wrap.
- if (isKnownNegative(Step)) {
+ if (AR->hasNoSelfWrap() || isKnownNegative(Step)) {
+ // We can sign-extend if no-self-wrap, or if the step is negative and
+ // doing so only traverses values in the range sext([0,SMAX]).
unsigned BitWidth = getTypeSizeInBits(AR->getType());
const SCEV *N =
getConstant(APInt::getMaxValue(BitWidth) - getSignedRangeMin(Step));
- if (isLoopBackedgeGuardedByCond(L, ICmpInst::ICMP_UGT, AR, N) ||
- isKnownOnEveryIteration(ICmpInst::ICMP_UGT, AR, N)) {
+ bool CanUseSExtForStep =
+ AR->hasNoSelfWrap() ||
+ isLoopBackedgeGuardedByCond(L, ICmpInst::ICMP_UGT, AR, N) ||
+ isKnownOnEveryIteration(ICmpInst::ICMP_UGT, AR, N);
+ if (CanUseSExtForStep) {
Start =
getExtendAddRecStart<SCEVZeroExtendExpr>(AR, Ty, this, Depth + 1);
Step = getSignExtendExpr(Step, Ty, Depth + 1);
diff --git a/llvm/test/Analysis/ScalarEvolution/2012-05-29-MulAddRec.ll b/llvm/test/Analysis/ScalarEvolution/2012-05-29-MulAddRec.ll
index 1d735d9d3dccc..75f853e149180 100644
--- a/llvm/test/Analysis/ScalarEvolution/2012-05-29-MulAddRec.ll
+++ b/llvm/test/Analysis/ScalarEvolution/2012-05-29-MulAddRec.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt < %s -S -passes='loop(indvars),loop-unroll' | FileCheck %s
;
; loop-unroll fully unrolls the inner loop, creating an interesting
@@ -12,17 +13,52 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
declare void @use(i8 %x)
-; CHECK: @func
-; CHECK: for.cond:
-; CHECK: %inc1 = phi i8 [ 0, %entry ], [ %0, %for.body ]
-; CHECK: br label %for.body
-
-; CHECK: for.body:
-; CHECK: %inc.9 = add i8 %inc1, 10
-; CHECK: %0 = add i8 %inc1, 10
-; CHECK: br label %for.cond
-
define void @func() noreturn nounwind uwtable ssp {
+; CHECK-LABEL: define void @func(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: br label %[[FOR_COND:.*]]
+; CHECK: [[FOR_COND]]:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i8 [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY:.*]] ], [ 10, %[[ENTRY]] ]
+; CHECK-NEXT: [[MUL3:%.*]] = phi i8 [ undef, %[[ENTRY]] ], [ [[MUL_9:%.*]], %[[FOR_BODY]] ]
+; CHECK-NEXT: [[INC1:%.*]] = phi i8 [ 0, %[[ENTRY]] ], [ [[TMP0:%.*]], %[[FOR_BODY]] ]
+; CHECK-NEXT: call void @use(i8 [[INC1]])
+; CHECK-NEXT: br label %[[FOR_BODY]]
+; CHECK: [[FOR_BODY]]:
+; CHECK-NEXT: [[INC:%.*]] = add nuw i8 [[INC1]], 1
+; CHECK-NEXT: [[MUL:%.*]] = mul i8 [[INC1]], [[MUL3]]
+; CHECK-NEXT: call void @use(i8 [[INC]])
+; CHECK-NEXT: [[INC_1:%.*]] = add nuw i8 [[INC1]], 2
+; CHECK-NEXT: [[MUL_1:%.*]] = mul i8 [[INC]], [[MUL]]
+; CHECK-NEXT: call void @use(i8 [[INC_1]])
+; CHECK-NEXT: [[INC_2:%.*]] = add nuw i8 [[INC1]], 3
+; CHECK-NEXT: [[MUL_2:%.*]] = mul i8 [[INC_1]], [[MUL_1]]
+; CHECK-NEXT: call void @use(i8 [[INC_2]])
+; CHECK-NEXT: [[INC_3:%.*]] = add nuw i8 [[INC1]], 4
+; CHECK-NEXT: [[MUL_3:%.*]] = mul i8 [[INC_2]], [[MUL_2]]
+; CHECK-NEXT: call void @use(i8 [[INC_3]])
+; CHECK-NEXT: [[INC_4:%.*]] = add nuw i8 [[INC1]], 5
+; CHECK-NEXT: [[MUL_4:%.*]] = mul i8 [[INC_3]], [[MUL_3]]
+; CHECK-NEXT: call void @use(i8 [[INC_4]])
+; CHECK-NEXT: [[INC_5:%.*]] = add nuw i8 [[INC1]], 6
+; CHECK-NEXT: [[MUL_5:%.*]] = mul i8 [[INC_4]], [[MUL_4]]
+; CHECK-NEXT: call void @use(i8 [[INC_5]])
+; CHECK-NEXT: [[INC_6:%.*]] = add nuw i8 [[INC1]], 7
+; CHECK-NEXT: [[MUL_6:%.*]] = mul i8 [[INC_5]], [[MUL_5]]
+; CHECK-NEXT: call void @use(i8 [[INC_6]])
+; CHECK-NEXT: [[INC_7:%.*]] = add nuw i8 [[INC1]], 8
+; CHECK-NEXT: [[MUL_7:%.*]] = mul i8 [[INC_6]], [[MUL_6]]
+; CHECK-NEXT: call void @use(i8 [[INC_7]])
+; CHECK-NEXT: [[INC_8:%.*]] = add nuw i8 [[INC1]], 9
+; CHECK-NEXT: [[MUL_8:%.*]] = mul i8 [[INC_7]], [[MUL_7]]
+; CHECK-NEXT: call void @use(i8 [[INC_8]])
+; CHECK-NEXT: [[INC_9:%.*]] = add nuw i8 [[INC1]], 10
+; CHECK-NEXT: [[MUL_9]] = mul i8 [[INC_8]], [[MUL_8]]
+; CHECK-NEXT: call void @use(i8 [[INC_9]])
+; CHECK-NEXT: [[TMP0]] = add i8 [[INC1]], 10
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i8 [[INDVARS_IV]], 10
+; CHECK-NEXT: br label %[[FOR_COND]]
+;
entry:
br label %for.cond
diff --git a/llvm/test/Transforms/IndVarSimplify/2011-09-10-widen-nsw.ll b/llvm/test/Transforms/IndVarSimplify/2011-09-10-widen-nsw.ll
index 66f73acc539d8..894d406afcafa 100644
--- a/llvm/test/Transforms/IndVarSimplify/2011-09-10-widen-nsw.ll
+++ b/llvm/test/Transforms/IndVarSimplify/2011-09-10-widen-nsw.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt < %s -passes=indvars -S | FileCheck %s
; Test WidenIV::GetExtendedOperandRecurrence.
; %add, %sub and %mul should be extended to i64 because it is nsw, even though its
@@ -8,6 +9,31 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
declare void @use(i64 %x)
define void @test(i1 %arg) nounwind {
+; CHECK-LABEL: define void @test(
+; CHECK-SAME: i1 [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: br i1 [[ARG]], label %[[FOR_BODY11:.*]], label %[[FOR_END285:.*]]
+; CHECK: [[FOR_BODY11]]:
+; CHECK-NEXT: br label %[[FOR_BODY153:.*]]
+; CHECK: [[FOR_BODY153]]:
+; CHECK-NEXT: br i1 [[ARG]], label %[[FOR_BODY170_PREHEADER:.*]], label %[[FOR_BODY153]]
+; CHECK: [[FOR_BODY170_PREHEADER]]:
+; CHECK-NEXT: br label %[[FOR_BODY170:.*]]
+; CHECK: [[FOR_BODY170]]:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[FOR_BODY170_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY170]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
+; CHECK-NEXT: call void @use(i64 [[TMP0]])
+; CHECK-NEXT: [[TMP1:%.*]] = sub nsw i64 [[INDVARS_IV]], 2
+; CHECK-NEXT: call void @use(i64 [[TMP1]])
+; CHECK-NEXT: [[TMP2:%.*]] = sub nuw nsw i64 4, [[INDVARS_IV]]
+; CHECK-NEXT: call void @use(i64 [[TMP2]])
+; CHECK-NEXT: [[TMP3:%.*]] = mul nsw i64 [[INDVARS_IV]], 8
+; CHECK-NEXT: call void @use(i64 [[TMP3]])
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 4
+; CHECK-NEXT: br label %[[FOR_BODY170]]
+; CHECK: [[FOR_END285]]:
+; CHECK-NEXT: ret void
+;
entry:
br i1 %arg, label %for.body11, label %for.end285
@@ -19,10 +45,6 @@ for.body11: ; preds = %entry
for.body153: ; preds = %for.body153, %for.body11
br i1 %arg, label %for.body170, label %for.body153
-; CHECK: add nuw nsw i64 %indvars.iv, 1
-; CHECK: sub nsw i64 %indvars.iv, 2
-; CHECK: sub nsw i64 4, %indvars.iv
-; CHECK: mul nsw i64 %indvars.iv, 8
for.body170: ; preds = %for.body170, %for.body153
%i2.19 = phi i32 [ %add249, %for.body170 ], [ 0, %for.body153 ]
diff --git a/llvm/test/Transforms/IndVarSimplify/AArch64/widen-loop-comp.ll b/llvm/test/Transforms/IndVarSimplify/AArch64/widen-loop-comp.ll
index d4498baf0577a..fd60cd0e9ca64 100644
--- a/llvm/test/Transforms/IndVarSimplify/AArch64/widen-loop-comp.ll
+++ b/llvm/test/Transforms/IndVarSimplify/AArch64/widen-loop-comp.ll
@@ -412,10 +412,9 @@ define i32 @test8(ptr %a, i32 %b, i32 %init) {
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[ADD]] = add nsw i32 [[SUM_0]], [[TMP2]]
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
-; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i64 0, [[INDVARS_IV_NEXT]]
-; CHECK-NEXT: br i1 [[CMP2]], label [[FOR_COND]], label [[FOR_END]]
+; CHECK-NEXT: br i1 true, label [[FOR_COND]], label [[FOR_END]]
; CHECK: for.end:
-; CHECK-NEXT: [[SUM_0_LCSSA:%.*]] = phi i32 [ [[SUM_0]], [[FOR_BODY]] ], [ [[SUM_0]], [[FOR_COND]] ]
+; CHECK-NEXT: [[SUM_0_LCSSA:%.*]] = phi i32 [ 0, [[FOR_BODY]] ], [ [[SUM_0]], [[FOR_COND]] ]
; CHECK-NEXT: ret i32 [[SUM_0_LCSSA]]
; CHECK: leave:
; CHECK-NEXT: ret i32 0
@@ -508,7 +507,7 @@ declare void @consume.i1(i1)
define i32 @test10(i32 %v) {
; CHECK-LABEL: @test10(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[SEXT:%.*]] = sext i32 [[V:%.*]] to i64
+; CHECK-NEXT: [[SEXT:%.*]] = zext i32 [[V:%.*]] to i64
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
diff --git a/llvm/test/Transforms/IndVarSimplify/ARM/code-size.ll b/llvm/test/Transforms/IndVarSimplify/ARM/code-size.ll
index 712b6ae399f2e..0e945324315b5 100644
--- a/llvm/test/Transforms/IndVarSimplify/ARM/code-size.ll
+++ b/llvm/test/Transforms/IndVarSimplify/ARM/code-size.ll
@@ -53,7 +53,7 @@ define void @expandOuterRecurrence(i32 %arg) nounwind #0 {
; CHECK-V8M-NEXT: br label [[OUTER:%.*]]
; CHECK-V8M: outer:
; CHECK-V8M-NEXT: [[I:%.*]] = phi i32 [ [[I_INC:%.*]], [[OUTER_INC:%.*]] ], [ 0, [[OUTER_PREHEADER]] ]
-; CHECK-V8M-NEXT: [[SUB2:%.*]] = sub nsw i32 [[ARG]], [[I]]
+; CHECK-V8M-NEXT: [[SUB2:%.*]] = sub nuw nsw i32 [[ARG]], [[I]]
; CHECK-V8M-NEXT: [[SUB3:%.*]] = sub nsw i32 [[SUB2]], 1
; CHECK-V8M-NEXT: [[CMP2:%.*]] = icmp slt i32 0, [[SUB3]]
; CHECK-V8M-NEXT: br i1 [[CMP2]], label [[INNER_PH:%.*]], label [[OUTER_INC]]
@@ -80,7 +80,7 @@ define void @expandOuterRecurrence(i32 %arg) nounwind #0 {
; CHECK-V8A-NEXT: br label [[OUTER:%.*]]
; CHECK-V8A: outer:
; CHECK-V8A-NEXT: [[I:%.*]] = phi i32 [ [[I_INC:%.*]], [[OUTER_INC:%.*]] ], [ 0, [[OUTER_PREHEADER]] ]
-; CHECK-V8A-NEXT: [[SUB2:%.*]] = sub nsw i32 [[ARG]], [[I]]
+; CHECK-V8A-NEXT: [[SUB2:%.*]] = sub nuw nsw i32 [[ARG]], [[I]]
; CHECK-V8A-NEXT: [[SUB3:%.*]] = sub nsw i32 [[SUB2]], 1
; CHECK-V8A-NEXT: [[CMP2:%.*]] = icmp slt i32 0, [[SUB3]]
; CHECK-V8A-NEXT: br i1 [[CMP2]], label [[INNER_PH:%.*]], label [[OUTER_INC]]
diff --git a/llvm/test/Transforms/IndVarSimplify/X86/eliminate-trunc.ll b/llvm/test/Transforms/IndVarSimplify/X86/eliminate-trunc.ll
index a506739ad6cc8..c16066f2733c6 100644
--- a/llvm/test/Transforms/IndVarSimplify/X86/eliminate-trunc.ll
+++ b/llvm/test/Transforms/IndVarSimplify/X86/eliminate-trunc.ll
@@ -223,12 +223,12 @@ define void @test_01_unsigned(i32 %n) {
; CHECK-LABEL: @test_01_unsigned(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N:%.*]], 1
+; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[TMP0]] to i64
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
-; CHECK-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i64 [[IV_NEXT]] to i32
-; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[LFTR_WIDEIV]], [[TMP0]]
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[IV_NEXT]], [[WIDE_TRIP_COUNT]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: ret void
@@ -251,12 +251,12 @@ define void @test_02_unsigned(i32 %n) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[UMAX:%.*]] = call i32 @llvm.umax.i32(i32 [[N:%.*]], i32 -2)
; CHECK-NEXT: [[TMP0:%.*]] = add nsw i32 [[UMAX]], 1
+; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[TMP0]] to i64
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 4294967294, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
-; CHECK-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i64 [[IV_NEXT]] to i32
-; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[LFTR_WIDEIV]], [[TMP0]]
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[IV_NEXT]], [[WIDE_TRIP_COUNT]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: ret void
@@ -300,12 +300,12 @@ define void @test_04_unsigned(i32 %n) {
; CHECK-LABEL: @test_04_unsigned(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N:%.*]], 1
+; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[TMP0]] to i64
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
-; CHECK-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i64 [[IV_NEXT]] to i32
-; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[LFTR_WIDEIV]], [[TMP0]]
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[IV_NEXT]], [[WIDE_TRIP_COUNT]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: ret void
@@ -328,12 +328,12 @@ define void @test_05_unsigned(i32 %n) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[UMAX:%.*]] = call i32 @llvm.umax.i32(i32 [[N:%.*]], i32 1)
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[UMAX]], 1
+; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[TMP0]] to i64
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 1, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
-; CHECK-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i64 [[IV_NEXT]] to i32
-; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[LFTR_WIDEIV]], [[TMP0]]
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[IV_NEXT]], [[WIDE_TRIP_COUNT]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: ret void
@@ -649,7 +649,7 @@ define void @test_13d(i32 %n) {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ -20, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
-; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 2
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 2
; CHECK-NEXT: [[TMP0:%.*]] = icmp slt i64 [[IV]], 1024
; CHECK-NEXT: br i1 [[TMP0]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
diff --git a/llvm/test/Transforms/IndVarSimplify/X86/iv-widen.ll b/llvm/test/Transforms/IndVarSimplify/X86/iv-widen.ll
index 45bb66d1d7d80..d4e511b62fad1 100644
--- a/llvm/test/Transforms/IndVarSimplify/X86/iv-widen.ll
+++ b/llvm/test/Transforms/IndVarSimplify/X86/iv-widen.ll
@@ -171,7 +171,7 @@ define void @loop_2(i32 %size, i32 %nsteps, i32 %hsize, ptr %lined, i8 %arg) {
; CHECK: for.body:
; CHECK-NEXT: [[INDVARS_IV9:%.*]] = phi i64 [ [[INDVARS_IV_NEXT10:%.*]], [[FOR_INC:%.*]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: [[TMP2:%.*]] = mul nsw i64 [[INDVARS_IV9]], [[TMP0]]
-; CHECK-NEXT: [[TMP3:%.*]] = add nsw i64 [[TMP2]], [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], [[TMP1]]
; CHECK-NEXT: br i1 [[CMP215]], label [[FOR_BODY2_PREHEADER:%.*]], label [[FOR_INC]]
; CHECK: for.body2.preheader:
; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[SIZE]] to i64
diff --git a/llvm/test/Transforms/IndVarSimplify/X86/overflow-intrinsics.ll b/llvm/test/Transforms/IndVarSimplify/X86/overflow-intrinsics.ll
index 9b9bc68ba7ad8..cf80cb40ed557 100644
--- a/llvm/test/Transforms/IndVarSimplify/X86/overflow-intrinsics.ll
+++ b/llvm/test/Transforms/IndVarSimplify/X86/overflow-intrinsics.ll
@@ -149,12 +149,12 @@ define void @f_uadd_overflow(ptr %a) {
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], %[[CONT:.*]] ], [ -6, %[[ENTRY]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[INDVARS_IV]]
; CHECK-NEXT: store i8 0, ptr [[ARRAYIDX]], align 1
-; CHECK-NEXT: br i1 true, label %[[TRAP:.*]], label %[[CONT]], !nosanitize [[META0]]
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
+; CHECK-NEXT: br i1 false, label %[[TRAP:.*]], label %[[CONT]], !nosanitize [[META0]]
; CHECK: [[TRAP]]:
; CHECK-NEXT: tail call void @llvm.trap(), !nosanitize [[META0]]
; CHECK-NEXT: unreachable, !nosanitize [[META0]]
; CHECK: [[CONT]]:
-; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: br i1 true, label %[[FOR_BODY]], label %[[FOR_COND_CLEANUP]]
;
entry:
@@ -334,13 +334,14 @@ define void @f_usub_overflow(ptr nocapture %a) {
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], %[[CONT:.*]] ], [ 15, %[[ENTRY]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[INDVARS_IV]]
; CHECK-NEXT: store i8 0, ptr [[ARRAYIDX]], align 1
-; CHECK-NEXT: br i1 true, label %[[TRAP:.*]], label %[[CONT]], !nosanitize [[META0]]
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], -1
+; CHECK-NEXT: br i1 false, label %[[TRAP:.*]], label %[[CONT]], !nosanitize [[META0]]
; CHECK: [[TRAP]]:
; CHECK-NEXT: tail call void @llvm.trap(), !nosanitize [[META0]]
; CHECK-NEXT: unreachable, !nosanitize [[META0]]
; CHECK: [[CONT]]:
-; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], -1
-; CHECK-NEXT: br i1 true, label %[[FOR_BODY]], label %[[FOR_COND_CLEANUP]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i64 [[INDVARS_IV_NEXT]], -1
+; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_BODY]], label %[[FOR_COND_CLEANUP]]
;
entry:
br label %for.body
diff --git a/llvm/test/Transforms/IndVarSimplify/X86/pr59615.ll b/llvm/test/Transforms/IndVarSimplify/X86/pr59615.ll
index 1e5a4156686ad..5bda5974f24a4 100644
--- a/llvm/test/Transforms/IndVarSimplify/X86/pr59615.ll
+++ b/llvm/test/Transforms/IndVarSimplify/X86/pr59615.ll
@@ -8,11 +8,12 @@ define void @test() {
; CHECK-LABEL: @test(
; CHECK-NEXT: bb:
; CHECK-NEXT: [[VAR:%.*]] = load atomic i32, ptr addrspace(1) poison unordered, align 8, !range [[RNG0:![0-9]+]], !invariant.load [[META1:![0-9]+]], !noundef [[META1]]
+; CHECK-NEXT: [[VAR1:%.*]] = add nsw i32 [[VAR]], -1
; CHECK-NEXT: [[VAR2:%.*]] = icmp eq i32 [[VAR]], 0
; CHECK-NEXT: br i1 [[VAR2]], label [[BB18:%.*]], label [[BB19:%.*]]
; CHECK: bb3:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[BB19]] ], [ [[INDVARS_IV_NEXT:%.*]], [[BB12:%.*]] ]
-; CHECK-NEXT: br i1 true, label [[BB8:%.*]], label [[BB7:%.*]]
+; CHECK-NEXT: br i1 [[VAR6_FIRST_ITER:%.*]], label [[BB8:%.*]], label [[BB7:%.*]]
; CHECK: bb7:
; CHECK-NEXT: ret void
; CHECK: bb8:
@@ -31,7 +32,9 @@ define void @test() {
; CHECK: bb18:
; CHECK-NEXT: ret void
; CHECK: bb19:
+; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[VAR1]] to i64
; CHECK-NEXT: [[TMP1]] = zext i32 [[VAR]] to i64
+; CHECK-NEXT: [[VAR6_FIRST_ITER]] = icmp ult i64 [[TMP2]], [[TMP1]]
; CHECK-NEXT: br label [[BB3]]
;
bb:
diff --git a/llvm/test/Transforms/IndVarSimplify/ada-loops.ll b/llvm/test/Transforms/IndVarSimplify/ada-loops.ll
index 83f2f212a4385..2cc44197aa79b 100644
--- a/llvm/test/Transforms/IndVarSimplify/ada-loops.ll
+++ b/llvm/test/Transforms/IndVarSimplify/ada-loops.ll
@@ -25,12 +25,11 @@ define void @kinds__sbytezero(ptr nocapture %a) nounwind {
; CHECK-NEXT: br label [[BB:%.*]]
; CHECK: bb:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i32 [ [[INDVARS_IV_NEXT:%.*]], [[BB]] ], [ -128, [[BB_THREAD:%.*]] ]
-; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i32 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i32 [[INDVARS_IV]], 1
; CHECK-NEXT: [[TMP3:%.*]] = add nsw i32 [[INDVARS_IV_NEXT]], 128
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr [256 x i32], ptr [[A]], i32 0, i32 [[TMP3]]
; CHECK-NEXT: store i32 0, ptr [[TMP4]], align 4
-; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[INDVARS_IV_NEXT]], 127
-; CHECK-NEXT: br i1 [[TMP0]], label [[RETURN:%.*]], label [[BB]]
+; CHECK-NEXT: br i1 false, label [[RETURN:%.*]], label [[BB]]
; CHECK: return:
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/IndVarSimplify/addrec_no_exec_on_every_iteration.ll b/llvm/test/Transforms/IndVarSimplify/addrec_no_exec_on_every_iteration.ll
index d8bf1567d00ed..4edc16b8b9b60 100644
--- a/llvm/test/Transforms/IndVarSimplify/addrec_no_exec_on_every_iteration.ll
+++ b/llvm/test/Transforms/IndVarSimplify/addrec_no_exec_on_every_iteration.ll
@@ -6,7 +6,278 @@ target triple = "x86_64-unknown-linux-gnu"
; Function Attrs: nofree norecurse nounwind uwtable
define void @test(ptr nocapture readnone %arg, ptr noalias nocapture readnone %arg1, ptr noalias nocapture readnone %arg2, ptr noalias nocapture readonly %arg3, ptr noalias nocapture readnone %arg4) local_unnamed_addr #0 {
-; CHECK-LABEL: @test
+; CHECK-LABEL: @test(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[ARG3:%.*]], align 8, !invariant.load [[META0:![0-9]+]], !dereferenceable [[META1:![0-9]+]], !align [[META2:![0-9]+]]
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[ARG3]], i64 3
+; CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !invariant.load [[META0]], !dereferenceable [[META3:![0-9]+]], !align [[META2]]
+; CHECK-NEXT: br label [[BB9:%.*]]
+; CHECK: bb9:
+; CHECK-NEXT: [[TMP10:%.*]] = phi i64 [ 0, [[BB:%.*]] ], [ [[TMP34:%.*]], [[BB33:%.*]] ]
+; CHECK-NEXT: [[TMP11:%.*]] = sub nuw nsw i64 9, [[TMP10]]
+; CHECK-NEXT: br label [[BB12:%.*]]
+; CHECK: bb12:
+; CHECK-NEXT: [[TMP13:%.*]] = phi i64 [ 0, [[BB9]] ], [ [[TMP31:%.*]], [[BB30:%.*]] ]
+; CHECK-NEXT: [[TMP14:%.*]] = sub nuw nsw i64 4, [[TMP13]]
+; CHECK-NEXT: br label [[BB15:%.*]]
+; CHECK: bb15:
+; CHECK-NEXT: [[TMP16:%.*]] = phi i64 [ 0, [[BB12]] ], [ [[TMP28:%.*]], [[BB27:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = mul nuw nsw i64 [[TMP16]], -2
+; CHECK-NEXT: [[TMP18:%.*]] = add nsw i64 [[TMP17]], 2
+; CHECK-NEXT: br label [[BB19:%.*]]
+; CHECK: bb19:
+; CHECK-NEXT: [[TMP20:%.*]] = phi i64 [ 0, [[BB15]] ], [ [[TMP25:%.*]], [[BB19]] ]
+; CHECK-NEXT: [[TMP21:%.*]] = add nuw nsw i64 [[TMP18]], [[TMP20]]
+; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x [4 x [10 x [5 x float]]]], ptr [[TMP5]], i64 0, i64 0, i64 [[TMP21]], i64 [[TMP11]], i64 [[TMP14]]
+; CHECK-NEXT: [[TMP23:%.*]] = load float, ptr [[TMP22]], align 4, !invariant.load [[META0]], !noalias [[META4:![0-9]+]]
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds [10 x [5 x [2 x [1 x [2 x float]]]]], ptr [[TMP7]], i64 0, i64 [[TMP10]], i64 [[TMP13]], i64 [[TMP16]], i64 0, i64 [[TMP20]]
+; CHECK-NEXT: store float [[TMP23]], ptr [[TMP24]], align 4, !alias.scope [[META4]], !noalias [[META7:![0-9]+]]
+; CHECK-NEXT: [[TMP25]] = add nuw nsw i64 [[TMP20]], 1
+; CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP20]], 0
+; CHECK-NEXT: br i1 [[TMP26]], label [[BB19]], label [[BB27]]
+; CHECK: bb27:
+; CHECK-NEXT: [[TMP28]] = add nuw nsw i64 [[TMP16]], 1
+; CHECK-NEXT: [[TMP29:%.*]] = icmp eq i64 [[TMP16]], 0
+; CHECK-NEXT: br i1 [[TMP29]], label [[BB15]], label [[BB30]]
+; CHECK: bb30:
+; CHECK-NEXT: [[TMP31]] = add nuw nsw i64 [[TMP13]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[TMP31]], 5
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[BB33]], label [[BB12]]
+; CHECK: bb33:
+; CHECK-NEXT: [[TMP34]] = add nuw nsw i64 [[TMP10]], 1
+; CHECK-NEXT: [[EXITCOND1:%.*]] = icmp eq i64 [[TMP34]], 10
+; CHECK-NEXT: br i1 [[EXITCOND1]], label [[BB36:%.*]], label [[BB9]]
+; CHECK: bb36:
+; CHECK-NEXT: [[TMP37:%.*]] = getelementptr inbounds ptr, ptr [[ARG3]], i64 1
+; CHECK-NEXT: [[TMP39:%.*]] = load ptr, ptr [[TMP37]], align 8, !invariant.load [[META0]], !dereferenceable [[META10:![0-9]+]], !align [[META2]]
+; CHECK-NEXT: [[TMP40:%.*]] = getelementptr inbounds i8, ptr [[TMP7]], i64 800
+; CHECK-NEXT: br label [[BB42:%.*]]
+; CHECK: bb42:
+; CHECK-NEXT: [[TMP43:%.*]] = phi i64 [ 0, [[BB36]] ], [ [[TMP64:%.*]], [[BB63:%.*]] ]
+; CHECK-NEXT: br label [[BB44:%.*]]
+; CHECK: bb44:
+; CHECK-NEXT: [[TMP45:%.*]] = phi i64 [ 0, [[BB42]] ], [ [[TMP61:%.*]], [[BB60:%.*]] ]
+; CHECK-NEXT: br label [[BB46:%.*]]
+; CHECK: bb46:
+; CHECK-NEXT: [[TMP47:%.*]] = phi i64 [ 0, [[BB44]] ], [ [[TMP58:%.*]], [[BB57:%.*]] ]
+; CHECK-NEXT: br label [[BB48:%.*]]
+; CHECK: bb48:
+; CHECK-NEXT: [[TMP49:%.*]] = phi i64 [ 0, [[BB46]] ], [ [[TMP55:%.*]], [[BB48]] ]
+; CHECK-NEXT: [[TMP50:%.*]] = shl nuw nsw i64 [[TMP49]], 1
+; CHECK-NEXT: [[TMP51:%.*]] = add nuw nsw i64 [[TMP50]], [[TMP43]]
+; CHECK-NEXT: [[TMP52:%.*]] = getelementptr inbounds [1 x [4 x [6 x [7 x float]]]], ptr [[TMP39]], i64 0, i64 0, i64 [[TMP51]], i64 [[TMP45]], i64 [[TMP47]]
+; CHECK-NEXT: [[TMP53:%.*]] = load float, ptr [[TMP52]], align 4, !invariant.load [[META0]], !noalias [[META11:![0-9]+]]
+; CHECK-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x [6 x [7 x [2 x [1 x float]]]]], ptr [[TMP40]], i64 0, i64 [[TMP43]], i64 [[TMP45]], i64 [[TMP47]], i64 [[TMP49]], i64 0
+; CHECK-NEXT: store float [[TMP53]], ptr [[TMP54]], align 4, !alias.scope [[META11]], !noalias [[META12:![0-9]+]]
+; CHECK-NEXT: [[TMP55]] = add nuw nsw i64 [[TMP49]], 1
+; CHECK-NEXT: [[TMP56:%.*]] = icmp eq i64 [[TMP49]], 0
+; CHECK-NEXT: br i1 [[TMP56]], label [[BB48]], label [[BB57]]
+; CHECK: bb57:
+; CHECK-NEXT: [[TMP58]] = add nuw nsw i64 [[TMP47]], 1
+; CHECK-NEXT: [[EXITCOND2:%.*]] = icmp eq i64 [[TMP58]], 7
+; CHECK-NEXT: br i1 [[EXITCOND2]], label [[BB60]], label [[BB46]]
+; CHECK: bb60:
+; CHECK-NEXT: [[TMP61]] = add nuw nsw i64 [[TMP45]], 1
+; CHECK-NEXT: [[EXITCOND3:%.*]] = icmp eq i64 [[TMP61]], 6
+; CHECK-NEXT: br i1 [[EXITCOND3]], label [[BB63]], label [[BB44]]
+; CHECK: bb63:
+; CHECK-NEXT: [[TMP64]] = add nuw nsw i64 [[TMP43]], 1
+; CHECK-NEXT: [[TMP65:%.*]] = icmp eq i64 [[TMP43]], 0
+; CHECK-NEXT: br i1 [[TMP65]], label [[BB42]], label [[BB66:%.*]]
+; CHECK: bb66:
+; CHECK-NEXT: [[TMP67:%.*]] = getelementptr inbounds i8, ptr [[TMP7]], i64 1472
+; CHECK-NEXT: br label [[BB69:%.*]]
+; CHECK: bb69:
+; CHECK-NEXT: [[TMP70:%.*]] = phi i64 [ 0, [[BB66]] ], [ [[TMP141:%.*]], [[BB140:%.*]] ]
+; CHECK-NEXT: br label [[BB71:%.*]]
+; CHECK: bb71:
+; CHECK-NEXT: [[TMP72:%.*]] = phi i64 [ 0, [[BB69]] ], [ [[TMP138:%.*]], [[BB137:%.*]] ]
+; CHECK-NEXT: [[TMP73:%.*]] = shl nuw nsw i64 [[TMP72]], 1
+; CHECK-NEXT: [[TMP74:%.*]] = add nuw nsw i64 [[TMP73]], -2
+; CHECK-NEXT: br label [[BB75:%.*]]
+; CHECK: bb75:
+; CHECK-NEXT: [[TMP76:%.*]] = phi i64 [ 0, [[BB71]] ], [ [[TMP135:%.*]], [[BB134:%.*]] ]
+; CHECK-NEXT: [[TMP77:%.*]] = add nuw nsw i64 [[TMP76]], -1
+; CHECK-NEXT: br label [[BB78:%.*]]
+; CHECK: bb78:
+; CHECK-NEXT: [[TMP79:%.*]] = phi i64 [ 0, [[BB75]] ], [ [[TMP132:%.*]], [[BB129:%.*]] ]
+; CHECK-NEXT: br label [[BB80:%.*]]
+; CHECK: bb80:
+; CHECK-NEXT: [[TMP81:%.*]] = phi float [ 0.000000e+00, [[BB78]] ], [ [[TMP126:%.*]], [[BB125:%.*]] ]
+; CHECK-NEXT: [[TMP82:%.*]] = phi i64 [ 0, [[BB78]] ], [ [[TMP127:%.*]], [[BB125]] ]
+; CHECK-NEXT: [[TMP83:%.*]] = shl nuw nsw i64 [[TMP82]], 1
+; CHECK-NEXT: [[TMP84:%.*]] = add nuw nsw i64 [[TMP83]], -1
+; CHECK-NEXT: [[TMP85:%.*]] = icmp ult i64 [[TMP84]], 10
+; CHECK-NEXT: [[TMP86:%.*]] = sub nuw nsw i64 5, [[TMP82]]
+; CHECK-NEXT: br i1 [[TMP85]], label [[BB88:%.*]], label [[BB87:%.*]]
+; CHECK: bb87:
+; CHECK-NEXT: br label [[BB124:%.*]]
+; CHECK: bb88:
+; CHECK-NEXT: br label [[BB89:%.*]]
+; CHECK: bb89:
+; CHECK-NEXT: [[TMP90:%.*]] = phi float [ [[TMP101:%.*]], [[BB100:%.*]] ], [ [[TMP81]], [[BB88]] ]
+; CHECK-NEXT: [[TMP91:%.*]] = phi i64 [ [[TMP102:%.*]], [[BB100]] ], [ 0, [[BB88]] ]
+; CHECK-NEXT: [[TMP92:%.*]] = add nuw nsw i64 [[TMP74]], [[TMP91]]
+; CHECK-NEXT: [[TMP93:%.*]] = icmp ult i64 [[TMP92]], 5
+; CHECK-NEXT: [[TMP94:%.*]] = sub nuw nsw i64 6, [[TMP91]]
+; CHECK-NEXT: br i1 [[TMP93]], label [[BB96:%.*]], label [[BB95:%.*]]
+; CHECK: bb95:
+; CHECK-NEXT: br label [[BB99:%.*]]
+; CHECK: bb96:
+; CHECK-NEXT: br label [[BB104:%.*]]
+; CHECK: bb97:
+; CHECK-NEXT: [[TMP98:%.*]] = phi float [ [[TMP111:%.*]], [[BB110:%.*]] ]
+; CHECK-NEXT: br label [[BB100]]
+; CHECK: bb99:
+; CHECK-NEXT: br label [[BB100]]
+; CHECK: bb100:
+; CHECK-NEXT: [[TMP101]] = phi float [ [[TMP98]], [[BB97:%.*]] ], [ [[TMP90]], [[BB99]] ]
+; CHECK-NEXT: [[TMP102]] = add nuw nsw i64 [[TMP91]], 1
+; CHECK-NEXT: [[EXITCOND4:%.*]] = icmp eq i64 [[TMP102]], 7
+; CHECK-NEXT: br i1 [[EXITCOND4]], label [[BB122:%.*]], label [[BB89]]
+; CHECK: bb104:
+; CHECK-NEXT: [[TMP105:%.*]] = phi float [ [[TMP111]], [[BB110]] ], [ [[TMP90]], [[BB96]] ]
+; CHECK-NEXT: [[TMP106:%.*]] = phi i64 [ [[TMP112:%.*]], [[BB110]] ], [ 0, [[BB96]] ]
+; CHECK-NEXT: [[TMP107:%.*]] = shl nuw nsw i64 [[TMP106]], 1
+; CHECK-NEXT: [[BUGGED:%.*]] = add nuw nsw i64 [[TMP77]], [[TMP107]]
+; CHECK-NEXT: [[TMP109:%.*]] = icmp ult i64 [[BUGGED]], 2
+; CHECK-NEXT: br i1 [[TMP109]], label [[BB114:%.*]], label [[BB110]]
+; CHECK: bb110:
+; CHECK-NEXT: [[TMP111]] = phi float [ [[TMP121:%.*]], [[BB114]] ], [ [[TMP105]], [[BB104]] ]
+; CHECK-NEXT: [[TMP112]] = add nuw nsw i64 [[TMP106]], 1
+; CHECK-NEXT: [[TMP113:%.*]] = icmp eq i64 [[TMP106]], 0
+; CHECK-NEXT: br i1 [[TMP113]], label [[BB104]], label [[BB97]]
+; CHECK: bb114:
+; CHECK-NEXT: [[TMP115:%.*]] = sub nuw nsw i64 1, [[TMP106]]
+; CHECK-NEXT: [[TMP116:%.*]] = getelementptr inbounds [2 x [6 x [7 x [2 x [1 x float]]]]], ptr [[TMP40]], i64 0, i64 [[TMP70]], i64 [[TMP86]], i64 [[TMP94]], i64 [[TMP115]], i64 0
+; CHECK-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x [5 x [2 x [1 x [2 x float]]]]], ptr [[TMP7]], i64 0, i64 [[TMP84]], i64 [[TMP92]], i64 [[BUGGED]], i64 0, i64 [[TMP79]]
+; CHECK-NEXT: [[TMP118:%.*]] = load float, ptr [[TMP117]], align 4, !alias.scope [[META4]], !noalias [[META7]]
+; CHECK-NEXT: [[TMP119:%.*]] = load float, ptr [[TMP116]], align 4, !alias.scope [[META11]], !noalias [[META12]]
+; CHECK-NEXT: [[TMP120:%.*]] = fmul reassoc nsz contract float [[TMP118]], [[TMP119]]
+; CHECK-NEXT: [[TMP121]] = fadd reassoc nsz contract float [[TMP105]], [[TMP120]]
+; CHECK-NEXT: br label [[BB110]]
+; CHECK: bb122:
+; CHECK-NEXT: [[TMP123:%.*]] = phi float [ [[TMP101]], [[BB100]] ]
+; CHECK-NEXT: br label [[BB125]]
+; CHECK: bb124:
+; CHECK-NEXT: br label [[BB125]]
+; CHECK: bb125:
+; CHECK-NEXT: [[TMP126]] = phi float [ [[TMP123]], [[BB122]] ], [ [[TMP81]], [[BB124]] ]
+; CHECK-NEXT: [[TMP127]] = add nuw nsw i64 [[TMP82]], 1
+; CHECK-NEXT: [[EXITCOND5:%.*]] = icmp eq i64 [[TMP127]], 6
+; CHECK-NEXT: br i1 [[EXITCOND5]], label [[BB129]], label [[BB80]]
+; CHECK: bb129:
+; CHECK-NEXT: [[TMP130:%.*]] = phi float [ [[TMP126]], [[BB125]] ]
+; CHECK-NEXT: [[TMP131:%.*]] = getelementptr inbounds [2 x [1 x [2 x [2 x [2 x float]]]]], ptr [[TMP67]], i64 0, i64 [[TMP70]], i64 0, i64 [[TMP72]], i64 [[TMP76]], i64 [[TMP79]]
+; CHECK-NEXT: store float [[TMP130]], ptr [[TMP131]], align 4, !alias.scope [[META13:![0-9]+]], !noalias [[META14:![0-9]+]]
+; CHECK-NEXT: [[TMP132]] = add nuw nsw i64 [[TMP79]], 1
+; CHECK-NEXT: [[TMP133:%.*]] = icmp eq i64 [[TMP79]], 0
+; CHECK-NEXT: br i1 [[TMP133]], label [[BB78]], label [[BB134]]
+; CHECK: bb134:
+; CHECK-NEXT: [[TMP135]] = add nuw nsw i64 [[TMP76]], 1
+; CHECK-NEXT: [[TMP136:%.*]] = icmp eq i64 [[TMP76]], 0
+; CHECK-NEXT: br i1 [[TMP136]], label [[BB75]], label [[BB137]]
+; CHECK: bb137:
+; CHECK-NEXT: [[TMP138]] = add nuw nsw i64 [[TMP72]], 1
+; CHECK-NEXT: [[TMP139:%.*]] = icmp eq i64 [[TMP72]], 0
+; CHECK-NEXT: br i1 [[TMP139]], label [[BB71]], label [[BB140]]
+; CHECK: bb140:
+; CHECK-NEXT: [[TMP141]] = add nuw nsw i64 [[TMP70]], 1
+; CHECK-NEXT: [[TMP142:%.*]] = icmp eq i64 [[TMP70]], 0
+; CHECK-NEXT: br i1 [[TMP142]], label [[BB69]], label [[BB143:%.*]]
+; CHECK: bb143:
+; CHECK-NEXT: [[TMP144:%.*]] = getelementptr inbounds ptr, ptr [[ARG3]], i64 2
+; CHECK-NEXT: [[TMP146:%.*]] = load ptr, ptr [[TMP144]], align 8, !invariant.load [[META0]], !dereferenceable [[META16:![0-9]+]], !align [[META2]]
+; CHECK-NEXT: br label [[BB147:%.*]]
+; CHECK: bb147:
+; CHECK-NEXT: br label [[BB148:%.*]]
+; CHECK: bb148:
+; CHECK-NEXT: br label [[BB149:%.*]]
+; CHECK: bb149:
+; CHECK-NEXT: [[TMP151:%.*]] = load float, ptr [[TMP67]], align 4, !alias.scope [[META13]], !noalias [[META14]]
+; CHECK-NEXT: store float [[TMP151]], ptr [[TMP146]], align 4, !alias.scope [[META17:![0-9]+]], !noalias [[META13]]
+; CHECK-NEXT: [[TMP153:%.*]] = getelementptr inbounds [2 x [1 x [2 x [2 x [2 x float]]]]], ptr [[TMP67]], i64 0, i64 0, i64 0, i64 1, i64 0, i64 0
+; CHECK-NEXT: [[TMP154:%.*]] = load float, ptr [[TMP153]], align 4, !alias.scope [[META13]], !noalias [[META14]]
+; CHECK-NEXT: [[TMP155:%.*]] = getelementptr inbounds [4 x [2 x [1 x [2 x float]]]], ptr [[TMP146]], i64 0, i64 0, i64 0, i64 0, i64 1
+; CHECK-NEXT: store float [[TMP154]], ptr [[TMP155]], align 4, !alias.scope [[META17]], !noalias [[META13]]
+; CHECK-NEXT: br label [[BB156:%.*]]
+; CHECK: bb156:
+; CHECK-NEXT: [[TMP157:%.*]] = getelementptr inbounds [2 x [1 x [2 x [2 x [2 x float]]]]], ptr [[TMP67]], i64 0, i64 1, i64 0, i64 0, i64 0, i64 0
+; CHECK-NEXT: [[TMP158:%.*]] = load float, ptr [[TMP157]], align 4, !alias.scope [[META13]], !noalias [[META14]]
+; CHECK-NEXT: [[TMP159:%.*]] = getelementptr inbounds [4 x [2 x [1 x [2 x float]]]], ptr [[TMP146]], i64 0, i64 0, i64 1, i64 0, i64 0
+; CHECK-NEXT: store float [[TMP158]], ptr [[TMP159]], align 4, !alias.scope [[META17]], !noalias [[META13]]
+; CHECK-NEXT: [[TMP160:%.*]] = getelementptr inbounds [2 x [1 x [2 x [2 x [2 x float]]]]], ptr [[TMP67]], i64 0, i64 1, i64 0, i64 1, i64 0, i64 0
+; CHECK-NEXT: [[TMP161:%.*]] = load float, ptr [[TMP160]], align 4, !alias.scope [[META13]], !noalias [[META14]]
+; CHECK-NEXT: [[TMP162:%.*]] = getelementptr inbounds [4 x [2 x [1 x [2 x float]]]], ptr [[TMP146]], i64 0, i64 0, i64 1, i64 0, i64 1
+; CHECK-NEXT: store float [[TMP161]], ptr [[TMP162]], align 4, !alias.scope [[META17]], !noalias [[META13]]
+; CHECK-NEXT: br label [[BB163:%.*]]
+; CHECK: bb163:
+; CHECK-NEXT: br label [[BB164:%.*]]
+; CHECK: bb164:
+; CHECK-NEXT: [[TMP165:%.*]] = getelementptr inbounds [2 x [1 x [2 x [2 x [2 x float]]]]], ptr [[TMP67]], i64 0, i64 0, i64 0, i64 0, i64 0, i64 1
+; CHECK-NEXT: [[TMP166:%.*]] = load float, ptr [[TMP165]], align 4, !alias.scope [[META13]], !noalias [[META14]]
+; CHECK-NEXT: [[TMP167:%.*]] = getelementptr inbounds [4 x [2 x [1 x [2 x float]]]], ptr [[TMP146]], i64 0, i64 1, i64 0, i64 0, i64 0
+; CHECK-NEXT: store float [[TMP166]], ptr [[TMP167]], align 4, !alias.scope [[META17]], !noalias [[META13]]
+; CHECK-NEXT: [[TMP168:%.*]] = getelementptr inbounds [2 x [1 x [2 x [2 x [2 x float]]]]], ptr [[TMP67]], i64 0, i64 0, i64 0, i64 1, i64 0, i64 1
+; CHECK-NEXT: [[TMP169:%.*]] = load float, ptr [[TMP168]], align 4, !alias.scope [[META13]], !noalias [[META14]]
+; CHECK-NEXT: [[TMP170:%.*]] = getelementptr inbounds [4 x [2 x [1 x [2 x float]]]], ptr [[TMP146]], i64 0, i64 1, i64 0, i64 0, i64 1
+; CHECK-NEXT: store float [[TMP169]], ptr [[TMP170]], align 4, !alias.scope [[META17]], !noalias [[META13]]
+; CHECK-NEXT: br label [[BB171:%.*]]
+; CHECK: bb171:
+; CHECK-NEXT: [[TMP172:%.*]] = getelementptr inbounds [2 x [1 x [2 x [2 x [2 x float]]]]], ptr [[TMP67]], i64 0, i64 1, i64 0, i64 0, i64 0, i64 1
+; CHECK-NEXT: [[TMP173:%.*]] = load float, ptr [[TMP172]], align 4, !alias.scope [[META13]], !noalias [[META14]]
+; CHECK-NEXT: [[TMP174:%.*]] = getelementptr inbounds [4 x [2 x [1 x [2 x float]]]], ptr [[TMP146]], i64 0, i64 1, i64 1, i64 0, i64 0
+; CHECK-NEXT: store float [[TMP173]], ptr [[TMP174]], align 4, !alias.scope [[META17]], !noalias [[META13]]
+; CHECK-NEXT: [[TMP175:%.*]] = getelementptr inbounds [2 x [1 x [2 x [2 x [2 x float]]]]], ptr [[TMP67]], i64 0, i64 1, i64 0, i64 1, i64 0, i64 1
+; CHECK-NEXT: [[TMP176:%.*]] = load float, ptr [[TMP175]], align 4, !alias.scope [[META13]], !noalias [[META14]]
+; CHECK-NEXT: [[TMP177:%.*]] = getelementptr inbounds [4 x [2 x [1 x [2 x float]]]], ptr [[TMP146]], i64 0, i64 1, i64 1, i64 0, i64 1
+; CHECK-NEXT: store float [[TMP176]], ptr [[TMP177]], align 4, !alias.scope [[META17]], !noalias [[META13]]
+; CHECK-NEXT: br label [[BB178:%.*]]
+; CHECK: bb178:
+; CHECK-NEXT: br label [[BB179:%.*]]
+; CHECK: bb179:
+; CHECK-NEXT: [[TMP180:%.*]] = getelementptr inbounds [2 x [1 x [2 x [2 x [2 x float]]]]], ptr [[TMP67]], i64 0, i64 0, i64 0, i64 0, i64 1, i64 0
+; CHECK-NEXT: [[TMP181:%.*]] = load float, ptr [[TMP180]], align 4, !alias.scope [[META13]], !noalias [[META14]]
+; CHECK-NEXT: [[TMP182:%.*]] = getelementptr inbounds [4 x [2 x [1 x [2 x float]]]], ptr [[TMP146]], i64 0, i64 2, i64 0, i64 0, i64 0
+; CHECK-NEXT: store float [[TMP181]], ptr [[TMP182]], align 4, !alias.scope [[META17]], !noalias [[META13]]
+; CHECK-NEXT: [[TMP183:%.*]] = getelementptr inbounds [2 x [1 x [2 x [2 x [2 x float]]]]], ptr [[TMP67]], i64 0, i64 0, i64 0, i64 1, i64 1, i64 0
+; CHECK-NEXT: [[TMP184:%.*]] = load float, ptr [[TMP183]], align 4, !alias.scope [[META13]], !noalias [[META14]]
+; CHECK-NEXT: [[TMP185:%.*]] = getelementptr inbounds [4 x [2 x [1 x [2 x float]]]], ptr [[TMP146]], i64 0, i64 2, i64 0, i64 0, i64 1
+; CHECK-NEXT: store float [[TMP184]], ptr [[TMP185]], align 4, !alias.scope [[META17]], !noalias [[META13]]
+; CHECK-NEXT: br label [[BB186:%.*]]
+; CHECK: bb186:
+; CHECK-NEXT: [[TMP187:%.*]] = getelementptr inbounds [2 x [1 x [2 x [2 x [2 x float]]]]], ptr [[TMP67]], i64 0, i64 1, i64 0, i64 0, i64 1, i64 0
+; CHECK-NEXT: [[TMP188:%.*]] = load float, ptr [[TMP187]], align 4, !alias.scope [[META13]], !noalias [[META14]]
+; CHECK-NEXT: [[TMP189:%.*]] = getelementptr inbounds [4 x [2 x [1 x [2 x float]]]], ptr [[TMP146]], i64 0, i64 2, i64 1, i64 0, i64 0
+; CHECK-NEXT: store float [[TMP188]], ptr [[TMP189]], align 4, !alias.scope [[META17]], !noalias [[META13]]
+; CHECK-NEXT: [[TMP190:%.*]] = getelementptr inbounds [2 x [1 x [2 x [2 x [2 x float]]]]], ptr [[TMP67]], i64 0, i64 1, i64 0, i64 1, i64 1, i64 0
+; CHECK-NEXT: [[TMP191:%.*]] = load float, ptr [[TMP190]], align 4, !alias.scope [[META13]], !noalias [[META14]]
+; CHECK-NEXT: [[TMP192:%.*]] = getelementptr inbounds [4 x [2 x [1 x [2 x float]]]], ptr [[TMP146]], i64 0, i64 2, i64 1, i64 0, i64 1
+; CHECK-NEXT: store float [[TMP191]], ptr [[TMP192]], align 4, !alias.scope [[META17]], !noalias [[META13]]
+; CHECK-NEXT: br label [[BB193:%.*]]
+; CHECK: bb193:
+; CHECK-NEXT: br label [[BB194:%.*]]
+; CHECK: bb194:
+; CHECK-NEXT: [[TMP195:%.*]] = getelementptr inbounds [2 x [1 x [2 x [2 x [2 x float]]]]], ptr [[TMP67]], i64 0, i64 0, i64 0, i64 0, i64 1, i64 1
+; CHECK-NEXT: [[TMP196:%.*]] = load float, ptr [[TMP195]], align 4, !alias.scope [[META13]], !noalias [[META14]]
+; CHECK-NEXT: [[TMP197:%.*]] = getelementptr inbounds [4 x [2 x [1 x [2 x float]]]], ptr [[TMP146]], i64 0, i64 3, i64 0, i64 0, i64 0
+; CHECK-NEXT: store float [[TMP196]], ptr [[TMP197]], align 4, !alias.scope [[META17]], !noalias [[META13]]
+; CHECK-NEXT: [[TMP198:%.*]] = getelementptr inbounds [2 x [1 x [2 x [2 x [2 x float]]]]], ptr [[TMP67]], i64 0, i64 0, i64 0, i64 1, i64 1, i64 1
+; CHECK-NEXT: [[TMP199:%.*]] = load float, ptr [[TMP198]], align 4, !alias.scope [[META13]], !noalias [[META14]]
+; CHECK-NEXT: [[TMP200:%.*]] = getelementptr inbounds [4 x [2 x [1 x [2 x float]]]], ptr [[TMP146]], i64 0, i64 3, i64 0, i64 0, i64 1
+; CHECK-NEXT: store float [[TMP199]], ptr [[TMP200]], align 4, !alias.scope [[META17]], !noalias [[META13]]
+; CHECK-NEXT: br label [[BB201:%.*]]
+; CHECK: bb201:
+; CHECK-NEXT: [[TMP202:%.*]] = getelementptr inbounds [2 x [1 x [2 x [2 x [2 x float]]]]], ptr [[TMP67]], i64 0, i64 1, i64 0, i64 0, i64 1, i64 1
+; CHECK-NEXT: [[TMP203:%.*]] = load float, ptr [[TMP202]], align 4, !alias.scope [[META13]], !noalias [[META14]]
+; CHECK-NEXT: [[TMP204:%.*]] = getelementptr inbounds [4 x [2 x [1 x [2 x float]]]], ptr [[TMP146]], i64 0, i64 3, i64 1, i64 0, i64 0
+; CHECK-NEXT: store float [[TMP203]], ptr [[TMP204]], align 4, !alias.scope [[META17]], !noalias [[META13]]
+; CHECK-NEXT: [[TMP205:%.*]] = getelementptr inbounds [2 x [1 x [2 x [2 x [2 x float]]]]], ptr [[TMP67]], i64 0, i64 1, i64 0, i64 1, i64 1, i64 1
+; CHECK-NEXT: [[TMP206:%.*]] = load float, ptr [[TMP205]], align 4, !alias.scope [[META13]], !noalias [[META14]]
+; CHECK-NEXT: [[TMP207:%.*]] = getelementptr inbounds [4 x [2 x [1 x [2 x float]]]], ptr [[TMP146]], i64 0, i64 3, i64 1, i64 0, i64 1
+; CHECK-NEXT: store float [[TMP206]], ptr [[TMP207]], align 4, !alias.scope [[META17]], !noalias [[META13]]
+; CHECK-NEXT: ret void
+;
bb:
%tmp5 = load ptr, ptr %arg3, align 8, !invariant.load !0, !dereferenceable !1, !align !2
%tmp6 = getelementptr inbounds ptr, ptr %arg3, i64 3
@@ -169,8 +440,6 @@ bb104: ; preds = %bb110, %bb96
%tmp105 = phi float [ %tmp111, %bb110 ], [ %tmp90, %bb96 ]
%tmp106 = phi i64 [ %tmp112, %bb110 ], [ 0, %bb96 ]
%tmp107 = shl nuw nsw i64 %tmp106, 1
- ; CHECK-NOT: %bugged = add nuw nsw
- ; CHECK: %bugged = add nsw
%bugged = add i64 %tmp77, %tmp107
%tmp109 = icmp ult i64 %bugged, 2
br i1 %tmp109, label %bb114, label %bb110
diff --git a/llvm/test/Transforms/IndVarSimplify/elim-extend.ll b/llvm/test/Transforms/IndVarSimplify/elim-extend.ll
index 01c95dadd1626..d8bcb4f0ff326 100644
--- a/llvm/test/Transforms/IndVarSimplify/elim-extend.ll
+++ b/llvm/test/Transforms/IndVarSimplify/elim-extend.ll
@@ -121,7 +121,7 @@ define void @nestedIV(ptr %address, i32 %limit) nounwind {
; CHECK: outerloop:
; CHECK-NEXT: [[INDVARS_IV1:%.*]] = phi i64 [ [[INDVARS_IV_NEXT2:%.*]], [[OUTERMERGE:%.*]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: [[INNERCOUNT:%.*]] = phi i32 [ [[INNERCOUNT_MERGE:%.*]], [[OUTERMERGE]] ], [ 0, [[ENTRY]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[INDVARS_IV1]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[INDVARS_IV1]], -1
; CHECK-NEXT: [[ADR1:%.*]] = getelementptr i8, ptr [[ADDRESS:%.*]], i64 [[TMP1]]
; CHECK-NEXT: store i8 0, ptr [[ADR1]], align 1
; CHECK-NEXT: br label [[INNERPREHEADER:%.*]]
diff --git a/llvm/test/Transforms/IndVarSimplify/eliminate-exit.ll b/llvm/test/Transforms/IndVarSimplify/eliminate-exit.ll
index b20891d2f9ed8..839476192d246 100644
--- a/llvm/test/Transforms/IndVarSimplify/eliminate-exit.ll
+++ b/llvm/test/Transforms/IndVarSimplify/eliminate-exit.ll
@@ -10,7 +10,7 @@ define void @ult(i64 %n, i64 %m) {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
-; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i64 [[IV]], [[N]]
; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH]], label [[EXIT_LOOPEXIT:%.*]]
; CHECK: latch:
@@ -46,7 +46,7 @@ define void @ugt(i64 %n, i64 %m) {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
-; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
; CHECK-NEXT: br i1 true, label [[LATCH]], label [[EXIT_LOOPEXIT:%.*]]
; CHECK: latch:
; CHECK-NEXT: call void @side_effect()
@@ -82,7 +82,7 @@ define void @ule(i64 %n, i64 %m) {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
-; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i64 [[IV]], [[N]]
; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH]], label [[EXIT_LOOPEXIT:%.*]]
; CHECK: latch:
@@ -119,7 +119,7 @@ define void @uge(i64 %n, i64 %m) {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
-; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i64 [[IV]], [[N]]
; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH]], label [[EXIT_LOOPEXIT:%.*]]
; CHECK: latch:
diff --git a/llvm/test/Transforms/IndVarSimplify/eliminate-max-from-min-exit.ll b/llvm/test/Transforms/IndVarSimplify/eliminate-max-from-min-exit.ll
index 0c24716d6aaaf..5a126d332971a 100644
--- a/llvm/test/Transforms/IndVarSimplify/eliminate-max-from-min-exit.ll
+++ b/llvm/test/Transforms/IndVarSimplify/eliminate-max-from-min-exit.ll
@@ -71,7 +71,7 @@ define i8 @umax_exit_from_umin(i32 %start, i32 %limit) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[K:%.*]] = phi i32 [ [[INC:%.*]], %[[LOOP]] ], [ [[START]], %[[PH2]] ]
; CHECK-NEXT: call void @use()
-; CHECK-NEXT: [[INC]] = add i32 [[K]], 1
+; CHECK-NEXT: [[INC]] = add nuw i32 [[K]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[K]], [[UMIN]]
; CHECK-NEXT: br i1 [[COND]], label %[[LOOP]], label %[[LOOP_EXIT:.*]]
; CHECK: [[LOOP_EXIT]]:
diff --git a/llvm/test/Transforms/IndVarSimplify/floating-point-iv.ll b/llvm/test/Transforms/IndVarSimplify/floating-point-iv.ll
index d45785b7818cf..3e81fed4f8603 100644
--- a/llvm/test/Transforms/IndVarSimplify/floating-point-iv.ll
+++ b/llvm/test/Transforms/IndVarSimplify/floating-point-iv.ll
@@ -39,7 +39,7 @@ define void @test2() nounwind {
; CHECK-NEXT: [[IV_INT:%.*]] = phi i32 [ -10, [[ENTRY:%.*]] ], [ [[DOTINT:%.*]], [[BB]] ]
; CHECK-NEXT: [[INDVAR_CONV:%.*]] = sitofp i32 [[IV_INT]] to double
; CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @foo(double [[INDVAR_CONV]]) #[[ATTR0]]
-; CHECK-NEXT: [[DOTINT]] = add nsw i32 [[IV_INT]], 2
+; CHECK-NEXT: [[DOTINT]] = add nuw nsw i32 [[IV_INT]], 2
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[DOTINT]], -1
; CHECK-NEXT: br i1 [[TMP1]], label [[BB]], label [[RETURN:%.*]]
; CHECK: return:
diff --git a/llvm/test/Transforms/IndVarSimplify/infer-poison-flags.ll b/llvm/test/Transforms/IndVarSimplify/infer-poison-flags.ll
index 6b28b933687e4..1fc5fdf9e58c1 100644
--- a/llvm/test/Transforms/IndVarSimplify/infer-poison-flags.ll
+++ b/llvm/test/Transforms/IndVarSimplify/infer-poison-flags.ll
@@ -63,7 +63,7 @@ define void @add_cr_nsw() {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[I:%.*]] = phi i32 [ -10, [[ENTRY:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP]] ]
-; CHECK-NEXT: [[I_NEXT]] = add nsw i32 [[I]], 1
+; CHECK-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-NEXT: store i32 [[I]], ptr @A, align 4
; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[I_NEXT]], 10
; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[LOOPEXIT:%.*]]
@@ -90,7 +90,7 @@ define void @add_cr_none() {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[I:%.*]] = phi i32 [ 10, [[ENTRY:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP]] ]
-; CHECK-NEXT: [[I_NEXT]] = add i32 [[I]], 1
+; CHECK-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
; CHECK-NEXT: store i32 [[I]], ptr @A, align 4
; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[I_NEXT]], 0
; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[LOOPEXIT:%.*]]
@@ -117,7 +117,7 @@ define void @add_unknown_none(i32 %n) {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP]] ]
-; CHECK-NEXT: [[I_NEXT]] = add i32 [[I]], 1
+; CHECK-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
; CHECK-NEXT: store i32 [[I]], ptr @A, align 4
; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[I_NEXT]], [[N:%.*]]
; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[LOOPEXIT:%.*]]
diff --git a/llvm/test/Transforms/IndVarSimplify/iv-ext-samesign.ll b/llvm/test/Transforms/IndVarSimplify/iv-ext-samesign.ll
index c4e26c98ed24a..d7e4de379ae32 100644
--- a/llvm/test/Transforms/IndVarSimplify/iv-ext-samesign.ll
+++ b/llvm/test/Transforms/IndVarSimplify/iv-ext-samesign.ll
@@ -8,23 +8,27 @@ define i32 @iv_zext_zext_sgt_slt(i32 %iter.count, ptr %ptr) {
; CHECK-SAME: i32 [[ITER_COUNT:%.*]], ptr [[PTR:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[TMP0:%.*]] = add nsw i32 [[ITER_COUNT]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[ITER_COUNT]] to i64
; CHECK-NEXT: br label %[[OUTER_LOOP:.*]]
; CHECK: [[PH_LOOPEXIT:.*]]:
; CHECK-NEXT: br label %[[PH:.*]]
; CHECK: [[PH]]:
-; CHECK-NEXT: [[INDVARS_IV_NEXT2:%.*]] = add i32 [[INDVARS_IV1:%.*]], -1
+; CHECK-NEXT: [[INDVARS_IV_NEXT4:%.*]] = add i64 [[WIDE_TRIP_COUNT:%.*]], -1
+; CHECK-NEXT: [[INDVARS_IV_NEXT6:%.*]] = add nsw i64 [[INDVARS_IV5:%.*]], -1
; CHECK-NEXT: br label %[[OUTER_LOOP]]
; CHECK: [[OUTER_LOOP]]:
-; CHECK-NEXT: [[INDVARS_IV1]] = phi i32 [ [[INDVARS_IV_NEXT2]], %[[PH]] ], [ [[TMP0]], %[[ENTRY]] ]
-; CHECK-NEXT: [[IV_OUTER:%.*]] = phi i32 [ [[IV_OUTER_1:%.*]], %[[PH]] ], [ [[ITER_COUNT]], %[[ENTRY]] ]
-; CHECK-NEXT: [[IV_OUTER_1]] = add nsw i32 [[IV_OUTER]], -1
+; CHECK-NEXT: [[INDVARS_IV5]] = phi i64 [ [[INDVARS_IV_NEXT6]], %[[PH]] ], [ [[TMP2]], %[[ENTRY]] ]
+; CHECK-NEXT: [[WIDE_TRIP_COUNT]] = phi i64 [ [[INDVARS_IV_NEXT4]], %[[PH]] ], [ [[TMP1]], %[[ENTRY]] ]
+; CHECK-NEXT: [[IV_OUTER:%.*]] = trunc nuw i64 [[INDVARS_IV5]] to i32
+; CHECK-NEXT: [[IV_OUTER_1:%.*]] = add nsw i32 [[IV_OUTER]], -1
; CHECK-NEXT: [[EXT_OUTER:%.*]] = zext nneg i32 [[IV_OUTER_1]] to i64
; CHECK-NEXT: [[GEP_OUTER:%.*]] = getelementptr i8, ptr [[PTR]], i64 [[EXT_OUTER]]
; CHECK-NEXT: store i8 0, ptr [[GEP_OUTER]], align 1
-; CHECK-NEXT: [[EXIT_COND_OUTER:%.*]] = icmp sgt i32 [[IV_OUTER]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = trunc nuw i64 [[INDVARS_IV5]] to i32
+; CHECK-NEXT: [[EXIT_COND_OUTER:%.*]] = icmp sgt i32 [[TMP4]], 1
; CHECK-NEXT: br i1 [[EXIT_COND_OUTER]], label %[[INNER_LOOP_PREHEADER:.*]], label %[[PH]]
; CHECK: [[INNER_LOOP_PREHEADER]]:
-; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[INDVARS_IV1]] to i64
; CHECK-NEXT: br label %[[INNER_LOOP:.*]]
; CHECK: [[INNER_LOOP]]:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[INNER_LOOP_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[INNER_LOOP]] ]
@@ -69,23 +73,26 @@ define i32 @iv_zext_zext_gt_slt(i32 %iter.count, ptr %ptr) {
; CHECK-SAME: i32 [[ITER_COUNT:%.*]], ptr [[PTR:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[TMP0:%.*]] = add nsw i32 [[ITER_COUNT]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[ITER_COUNT]] to i64
; CHECK-NEXT: br label %[[OUTER_LOOP:.*]]
; CHECK: [[PH_LOOPEXIT:.*]]:
; CHECK-NEXT: br label %[[PH:.*]]
; CHECK: [[PH]]:
-; CHECK-NEXT: [[INDVARS_IV_NEXT3:%.*]] = add i32 [[INDVARS_IV1:%.*]], -1
+; CHECK-NEXT: [[INDVARS_IV_NEXT4:%.*]] = add i64 [[WIDE_TRIP_COUNT:%.*]], -1
+; CHECK-NEXT: [[INDVARS_IV_NEXT6:%.*]] = add nsw i64 [[INDVARS_IV5:%.*]], -1
; CHECK-NEXT: br label %[[OUTER_LOOP]]
; CHECK: [[OUTER_LOOP]]:
-; CHECK-NEXT: [[INDVARS_IV1]] = phi i32 [ [[INDVARS_IV_NEXT3]], %[[PH]] ], [ [[TMP0]], %[[ENTRY]] ]
-; CHECK-NEXT: [[IV_OUTER:%.*]] = phi i32 [ [[IV_OUTER_1:%.*]], %[[PH]] ], [ [[ITER_COUNT]], %[[ENTRY]] ]
-; CHECK-NEXT: [[IV_OUTER_1]] = add nsw i32 [[IV_OUTER]], -1
+; CHECK-NEXT: [[INDVARS_IV5]] = phi i64 [ [[INDVARS_IV_NEXT6]], %[[PH]] ], [ [[TMP2]], %[[ENTRY]] ]
+; CHECK-NEXT: [[WIDE_TRIP_COUNT]] = phi i64 [ [[INDVARS_IV_NEXT4]], %[[PH]] ], [ [[TMP1]], %[[ENTRY]] ]
+; CHECK-NEXT: [[IV_OUTER:%.*]] = trunc nuw i64 [[INDVARS_IV5]] to i32
+; CHECK-NEXT: [[IV_OUTER_1:%.*]] = add nsw i32 [[IV_OUTER]], -1
; CHECK-NEXT: [[INDVARS_IV_NEXT2:%.*]] = zext nneg i32 [[IV_OUTER_1]] to i64
; CHECK-NEXT: [[GEP_OUTER:%.*]] = getelementptr i8, ptr [[PTR]], i64 [[INDVARS_IV_NEXT2]]
; CHECK-NEXT: store i8 0, ptr [[GEP_OUTER]], align 1
-; CHECK-NEXT: [[EXIT_COND_OUTER:%.*]] = icmp samesign ugt i32 [[IV_OUTER]], 1
+; CHECK-NEXT: [[EXIT_COND_OUTER:%.*]] = icmp samesign ugt i64 [[INDVARS_IV5]], 1
; CHECK-NEXT: br i1 [[EXIT_COND_OUTER]], label %[[INNER_LOOP_PREHEADER:.*]], label %[[PH]]
; CHECK: [[INNER_LOOP_PREHEADER]]:
-; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[INDVARS_IV1]] to i64
; CHECK-NEXT: br label %[[INNER_LOOP:.*]]
; CHECK: [[INNER_LOOP]]:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[INNER_LOOP_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[INNER_LOOP]] ]
@@ -188,23 +195,27 @@ define i32 @iv_zext_zext_sgt_lt(i32 %iter.count, ptr %ptr) {
; CHECK-SAME: i32 [[ITER_COUNT:%.*]], ptr [[PTR:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[TMP0:%.*]] = add nsw i32 [[ITER_COUNT]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[ITER_COUNT]] to i64
; CHECK-NEXT: br label %[[OUTER_LOOP:.*]]
; CHECK: [[PH_LOOPEXIT:.*]]:
; CHECK-NEXT: br label %[[PH:.*]]
; CHECK: [[PH]]:
-; CHECK-NEXT: [[INDVARS_IV_NEXT2:%.*]] = add i32 [[INDVARS_IV1:%.*]], -1
+; CHECK-NEXT: [[INDVARS_IV_NEXT4:%.*]] = add i64 [[WIDE_TRIP_COUNT:%.*]], -1
+; CHECK-NEXT: [[INDVARS_IV_NEXT6:%.*]] = add nsw i64 [[INDVARS_IV5:%.*]], -1
; CHECK-NEXT: br label %[[OUTER_LOOP]]
; CHECK: [[OUTER_LOOP]]:
-; CHECK-NEXT: [[INDVARS_IV1]] = phi i32 [ [[INDVARS_IV_NEXT2]], %[[PH]] ], [ [[TMP0]], %[[ENTRY]] ]
-; CHECK-NEXT: [[IV_OUTER:%.*]] = phi i32 [ [[IV_OUTER_1:%.*]], %[[PH]] ], [ [[ITER_COUNT]], %[[ENTRY]] ]
-; CHECK-NEXT: [[IV_OUTER_1]] = add nsw i32 [[IV_OUTER]], -1
+; CHECK-NEXT: [[INDVARS_IV5]] = phi i64 [ [[INDVARS_IV_NEXT6]], %[[PH]] ], [ [[TMP2]], %[[ENTRY]] ]
+; CHECK-NEXT: [[WIDE_TRIP_COUNT]] = phi i64 [ [[INDVARS_IV_NEXT4]], %[[PH]] ], [ [[TMP1]], %[[ENTRY]] ]
+; CHECK-NEXT: [[IV_OUTER:%.*]] = trunc nuw i64 [[INDVARS_IV5]] to i32
+; CHECK-NEXT: [[IV_OUTER_1:%.*]] = add nsw i32 [[IV_OUTER]], -1
; CHECK-NEXT: [[EXT_OUTER:%.*]] = zext nneg i32 [[IV_OUTER_1]] to i64
; CHECK-NEXT: [[GEP_OUTER:%.*]] = getelementptr i8, ptr [[PTR]], i64 [[EXT_OUTER]]
; CHECK-NEXT: store i8 0, ptr [[GEP_OUTER]], align 1
-; CHECK-NEXT: [[EXIT_COND_OUTER:%.*]] = icmp sgt i32 [[IV_OUTER]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = trunc nuw i64 [[INDVARS_IV5]] to i32
+; CHECK-NEXT: [[EXIT_COND_OUTER:%.*]] = icmp sgt i32 [[TMP4]], 1
; CHECK-NEXT: br i1 [[EXIT_COND_OUTER]], label %[[INNER_LOOP_PREHEADER:.*]], label %[[PH]]
; CHECK: [[INNER_LOOP_PREHEADER]]:
-; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[INDVARS_IV1]] to i64
; CHECK-NEXT: br label %[[INNER_LOOP:.*]]
; CHECK: [[INNER_LOOP]]:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[INNER_LOOP_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[INNER_LOOP]] ]
@@ -248,18 +259,22 @@ define i32 @iv_zext_zext_sgt_lt_exitlimit(i32 %iter.count, i32 %exit.limit, ptr
; CHECK-LABEL: define i32 @iv_zext_zext_sgt_lt_exitlimit(
; CHECK-SAME: i32 [[ITER_COUNT:%.*]], i32 [[EXIT_LIMIT:%.*]], ptr [[PTR:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[ITER_COUNT]] to i64
; CHECK-NEXT: br label %[[OUTER_LOOP:.*]]
; CHECK: [[PH_LOOPEXIT:.*]]:
; CHECK-NEXT: br label %[[PH:.*]]
; CHECK: [[PH]]:
+; CHECK-NEXT: [[INDVARS_IV_NEXT2:%.*]] = add nsw i64 [[INDVARS_IV1:%.*]], -1
; CHECK-NEXT: br label %[[OUTER_LOOP]]
; CHECK: [[OUTER_LOOP]]:
-; CHECK-NEXT: [[IV_OUTER:%.*]] = phi i32 [ [[IV_OUTER_1:%.*]], %[[PH]] ], [ [[ITER_COUNT]], %[[ENTRY]] ]
-; CHECK-NEXT: [[IV_OUTER_1]] = add nsw i32 [[IV_OUTER]], -1
+; CHECK-NEXT: [[INDVARS_IV1]] = phi i64 [ [[INDVARS_IV_NEXT2]], %[[PH]] ], [ [[TMP0]], %[[ENTRY]] ]
+; CHECK-NEXT: [[IV_OUTER:%.*]] = trunc nuw i64 [[INDVARS_IV1]] to i32
+; CHECK-NEXT: [[IV_OUTER_1:%.*]] = add nsw i32 [[IV_OUTER]], -1
; CHECK-NEXT: [[EXT_OUTER:%.*]] = zext nneg i32 [[IV_OUTER_1]] to i64
; CHECK-NEXT: [[GEP_OUTER:%.*]] = getelementptr i8, ptr [[PTR]], i64 [[EXT_OUTER]]
; CHECK-NEXT: store i8 0, ptr [[GEP_OUTER]], align 1
-; CHECK-NEXT: [[EXIT_COND_OUTER:%.*]] = icmp sgt i32 [[IV_OUTER]], [[EXIT_LIMIT]]
+; CHECK-NEXT: [[TMP2:%.*]] = trunc nuw i64 [[INDVARS_IV1]] to i32
+; CHECK-NEXT: [[EXIT_COND_OUTER:%.*]] = icmp sgt i32 [[TMP2]], [[EXIT_LIMIT]]
; CHECK-NEXT: br i1 [[EXIT_COND_OUTER]], label %[[INNER_LOOP_PREHEADER:.*]], label %[[PH]]
; CHECK: [[INNER_LOOP_PREHEADER]]:
; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[IV_OUTER_1]] to i64
@@ -307,23 +322,26 @@ define i32 @iv_zext_zext_gt_lt(i32 %iter.count, ptr %ptr) {
; CHECK-SAME: i32 [[ITER_COUNT:%.*]], ptr [[PTR:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[TMP0:%.*]] = add nsw i32 [[ITER_COUNT]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[ITER_COUNT]] to i64
; CHECK-NEXT: br label %[[OUTER_LOOP:.*]]
; CHECK: [[PH_LOOPEXIT:.*]]:
; CHECK-NEXT: br label %[[PH:.*]]
; CHECK: [[PH]]:
-; CHECK-NEXT: [[INDVARS_IV_NEXT2:%.*]] = add i32 [[INDVARS_IV1:%.*]], -1
+; CHECK-NEXT: [[INDVARS_IV_NEXT4:%.*]] = add i64 [[WIDE_TRIP_COUNT:%.*]], -1
+; CHECK-NEXT: [[INDVARS_IV_NEXT6:%.*]] = add nsw i64 [[INDVARS_IV5:%.*]], -1
; CHECK-NEXT: br label %[[OUTER_LOOP]]
; CHECK: [[OUTER_LOOP]]:
-; CHECK-NEXT: [[INDVARS_IV1]] = phi i32 [ [[INDVARS_IV_NEXT2]], %[[PH]] ], [ [[TMP0]], %[[ENTRY]] ]
-; CHECK-NEXT: [[IV_OUTER:%.*]] = phi i32 [ [[IV_OUTER_1:%.*]], %[[PH]] ], [ [[ITER_COUNT]], %[[ENTRY]] ]
-; CHECK-NEXT: [[IV_OUTER_1]] = add nsw i32 [[IV_OUTER]], -1
+; CHECK-NEXT: [[INDVARS_IV5]] = phi i64 [ [[INDVARS_IV_NEXT6]], %[[PH]] ], [ [[TMP2]], %[[ENTRY]] ]
+; CHECK-NEXT: [[WIDE_TRIP_COUNT]] = phi i64 [ [[INDVARS_IV_NEXT4]], %[[PH]] ], [ [[TMP1]], %[[ENTRY]] ]
+; CHECK-NEXT: [[IV_OUTER:%.*]] = trunc nuw i64 [[INDVARS_IV5]] to i32
+; CHECK-NEXT: [[IV_OUTER_1:%.*]] = add nsw i32 [[IV_OUTER]], -1
; CHECK-NEXT: [[EXT_OUTER:%.*]] = zext nneg i32 [[IV_OUTER_1]] to i64
; CHECK-NEXT: [[GEP_OUTER:%.*]] = getelementptr i8, ptr [[PTR]], i64 [[EXT_OUTER]]
; CHECK-NEXT: store i8 0, ptr [[GEP_OUTER]], align 1
-; CHECK-NEXT: [[EXIT_COND_OUTER:%.*]] = icmp samesign ugt i32 [[IV_OUTER]], 1
+; CHECK-NEXT: [[EXIT_COND_OUTER:%.*]] = icmp samesign ugt i64 [[INDVARS_IV5]], 1
; CHECK-NEXT: br i1 [[EXIT_COND_OUTER]], label %[[INNER_LOOP_PREHEADER:.*]], label %[[PH]]
; CHECK: [[INNER_LOOP_PREHEADER]]:
-; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[INDVARS_IV1]] to i64
; CHECK-NEXT: br label %[[INNER_LOOP:.*]]
; CHECK: [[INNER_LOOP]]:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[INNER_LOOP_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[INNER_LOOP]] ]
@@ -368,23 +386,23 @@ define i32 @iv_sext_sext_sgt_slt(i32 %iter.count, ptr %ptr) {
; CHECK-SAME: i32 [[ITER_COUNT:%.*]], ptr [[PTR:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[TMP0:%.*]] = add nsw i32 [[ITER_COUNT]], -1
+; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP0]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[ITER_COUNT]] to i64
; CHECK-NEXT: br label %[[OUTER_LOOP:.*]]
; CHECK: [[PH_LOOPEXIT:.*]]:
; CHECK-NEXT: br label %[[PH:.*]]
; CHECK: [[PH]]:
-; CHECK-NEXT: [[INDVARS_IV_NEXT2:%.*]] = add i32 [[INDVARS_IV1:%.*]], -1
+; CHECK-NEXT: [[INDVARS_IV_NEXT5:%.*]] = add i64 [[WIDE_TRIP_COUNT:%.*]], -1
; CHECK-NEXT: br label %[[OUTER_LOOP]]
; CHECK: [[OUTER_LOOP]]:
; CHECK-NEXT: [[INDVARS_IV3:%.*]] = phi i64 [ [[INDVARS_IV_NEXT4:%.*]], %[[PH]] ], [ [[TMP1]], %[[ENTRY]] ]
-; CHECK-NEXT: [[INDVARS_IV1]] = phi i32 [ [[INDVARS_IV_NEXT2]], %[[PH]] ], [ [[TMP0]], %[[ENTRY]] ]
+; CHECK-NEXT: [[WIDE_TRIP_COUNT]] = phi i64 [ [[INDVARS_IV_NEXT5]], %[[PH]] ], [ [[TMP2]], %[[ENTRY]] ]
; CHECK-NEXT: [[INDVARS_IV_NEXT4]] = add nsw i64 [[INDVARS_IV3]], -1
; CHECK-NEXT: [[GEP_OUTER:%.*]] = getelementptr i8, ptr [[PTR]], i64 [[INDVARS_IV_NEXT4]]
; CHECK-NEXT: store i8 0, ptr [[GEP_OUTER]], align 1
; CHECK-NEXT: [[EXIT_COND_OUTER:%.*]] = icmp sgt i64 [[INDVARS_IV3]], 1
; CHECK-NEXT: br i1 [[EXIT_COND_OUTER]], label %[[INNER_LOOP_PREHEADER:.*]], label %[[PH]]
; CHECK: [[INNER_LOOP_PREHEADER]]:
-; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[INDVARS_IV1]] to i64
; CHECK-NEXT: br label %[[INNER_LOOP:.*]]
; CHECK: [[INNER_LOOP]]:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[INNER_LOOP_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[INNER_LOOP]] ]
@@ -429,23 +447,23 @@ define i32 @iv_sext_sext_gt_slt(i32 %iter.count, ptr %ptr) {
; CHECK-SAME: i32 [[ITER_COUNT:%.*]], ptr [[PTR:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[TMP1:%.*]] = add nsw i32 [[ITER_COUNT]], -1
+; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[ITER_COUNT]] to i64
; CHECK-NEXT: br label %[[OUTER_LOOP:.*]]
; CHECK: [[PH_LOOPEXIT:.*]]:
; CHECK-NEXT: br label %[[PH:.*]]
; CHECK: [[PH]]:
-; CHECK-NEXT: [[INDVARS_IV_NEXT3:%.*]] = add i32 [[INDVARS_IV2:%.*]], -1
+; CHECK-NEXT: [[INDVARS_IV_NEXT4:%.*]] = add i64 [[WIDE_TRIP_COUNT:%.*]], -1
; CHECK-NEXT: br label %[[OUTER_LOOP]]
; CHECK: [[OUTER_LOOP]]:
; CHECK-NEXT: [[INDVARS_IV1:%.*]] = phi i64 [ [[INDVARS_IV_NEXT2:%.*]], %[[PH]] ], [ [[TMP0]], %[[ENTRY]] ]
-; CHECK-NEXT: [[INDVARS_IV2]] = phi i32 [ [[INDVARS_IV_NEXT3]], %[[PH]] ], [ [[TMP1]], %[[ENTRY]] ]
+; CHECK-NEXT: [[WIDE_TRIP_COUNT]] = phi i64 [ [[INDVARS_IV_NEXT4]], %[[PH]] ], [ [[TMP2]], %[[ENTRY]] ]
; CHECK-NEXT: [[INDVARS_IV_NEXT2]] = add nsw i64 [[INDVARS_IV1]], -1
; CHECK-NEXT: [[GEP_OUTER:%.*]] = getelementptr i8, ptr [[PTR]], i64 [[INDVARS_IV_NEXT2]]
; CHECK-NEXT: store i8 0, ptr [[GEP_OUTER]], align 1
; CHECK-NEXT: [[EXIT_COND_OUTER:%.*]] = icmp samesign ugt i64 [[INDVARS_IV1]], 1
; CHECK-NEXT: br i1 [[EXIT_COND_OUTER]], label %[[INNER_LOOP_PREHEADER:.*]], label %[[PH]]
; CHECK: [[INNER_LOOP_PREHEADER]]:
-; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[INDVARS_IV2]] to i64
; CHECK-NEXT: br label %[[INNER_LOOP:.*]]
; CHECK: [[INNER_LOOP]]:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[INNER_LOOP_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[INNER_LOOP]] ]
@@ -548,23 +566,23 @@ define i32 @iv_sext_sext_sgt_lt(i32 %iter.count, ptr %ptr) {
; CHECK-SAME: i32 [[ITER_COUNT:%.*]], ptr [[PTR:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[TMP0:%.*]] = add nsw i32 [[ITER_COUNT]], -1
+; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP0]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[ITER_COUNT]] to i64
; CHECK-NEXT: br label %[[OUTER_LOOP:.*]]
; CHECK: [[PH_LOOPEXIT:.*]]:
; CHECK-NEXT: br label %[[PH:.*]]
; CHECK: [[PH]]:
-; CHECK-NEXT: [[INDVARS_IV_NEXT2:%.*]] = add i32 [[INDVARS_IV1:%.*]], -1
+; CHECK-NEXT: [[INDVARS_IV_NEXT5:%.*]] = add i64 [[WIDE_TRIP_COUNT:%.*]], -1
; CHECK-NEXT: br label %[[OUTER_LOOP]]
; CHECK: [[OUTER_LOOP]]:
; CHECK-NEXT: [[INDVARS_IV3:%.*]] = phi i64 [ [[INDVARS_IV_NEXT4:%.*]], %[[PH]] ], [ [[TMP1]], %[[ENTRY]] ]
-; CHECK-NEXT: [[INDVARS_IV1]] = phi i32 [ [[INDVARS_IV_NEXT2]], %[[PH]] ], [ [[TMP0]], %[[ENTRY]] ]
+; CHECK-NEXT: [[WIDE_TRIP_COUNT]] = phi i64 [ [[INDVARS_IV_NEXT5]], %[[PH]] ], [ [[TMP2]], %[[ENTRY]] ]
; CHECK-NEXT: [[INDVARS_IV_NEXT4]] = add nsw i64 [[INDVARS_IV3]], -1
; CHECK-NEXT: [[GEP_OUTER:%.*]] = getelementptr i8, ptr [[PTR]], i64 [[INDVARS_IV_NEXT4]]
; CHECK-NEXT: store i8 0, ptr [[GEP_OUTER]], align 1
; CHECK-NEXT: [[EXIT_COND_OUTER:%.*]] = icmp sgt i64 [[INDVARS_IV3]], 1
; CHECK-NEXT: br i1 [[EXIT_COND_OUTER]], label %[[INNER_LOOP_PREHEADER:.*]], label %[[PH]]
; CHECK: [[INNER_LOOP_PREHEADER]]:
-; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[INDVARS_IV1]] to i64
; CHECK-NEXT: br label %[[INNER_LOOP:.*]]
; CHECK: [[INNER_LOOP]]:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[INNER_LOOP_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[INNER_LOOP]] ]
@@ -667,23 +685,23 @@ define i32 @iv_sext_sext_gt_lt(i32 %iter.count, ptr %ptr) {
; CHECK-SAME: i32 [[ITER_COUNT:%.*]], ptr [[PTR:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[TMP0:%.*]] = add nsw i32 [[ITER_COUNT]], -1
+; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP0]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[ITER_COUNT]] to i64
; CHECK-NEXT: br label %[[OUTER_LOOP:.*]]
; CHECK: [[PH_LOOPEXIT:.*]]:
; CHECK-NEXT: br label %[[PH:.*]]
; CHECK: [[PH]]:
-; CHECK-NEXT: [[INDVARS_IV_NEXT2:%.*]] = add i32 [[INDVARS_IV1:%.*]], -1
+; CHECK-NEXT: [[INDVARS_IV_NEXT5:%.*]] = add i64 [[WIDE_TRIP_COUNT:%.*]], -1
; CHECK-NEXT: br label %[[OUTER_LOOP]]
; CHECK: [[OUTER_LOOP]]:
; CHECK-NEXT: [[INDVARS_IV3:%.*]] = phi i64 [ [[INDVARS_IV_NEXT4:%.*]], %[[PH]] ], [ [[TMP1]], %[[ENTRY]] ]
-; CHECK-NEXT: [[INDVARS_IV1]] = phi i32 [ [[INDVARS_IV_NEXT2]], %[[PH]] ], [ [[TMP0]], %[[ENTRY]] ]
+; CHECK-NEXT: [[WIDE_TRIP_COUNT]] = phi i64 [ [[INDVARS_IV_NEXT5]], %[[PH]] ], [ [[TMP2]], %[[ENTRY]] ]
; CHECK-NEXT: [[INDVARS_IV_NEXT4]] = add nsw i64 [[INDVARS_IV3]], -1
; CHECK-NEXT: [[GEP_OUTER:%.*]] = getelementptr i8, ptr [[PTR]], i64 [[INDVARS_IV_NEXT4]]
; CHECK-NEXT: store i8 0, ptr [[GEP_OUTER]], align 1
; CHECK-NEXT: [[EXIT_COND_OUTER:%.*]] = icmp samesign ugt i64 [[INDVARS_IV3]], 1
; CHECK-NEXT: br i1 [[EXIT_COND_OUTER]], label %[[INNER_LOOP_PREHEADER:.*]], label %[[PH]]
; CHECK: [[INNER_LOOP_PREHEADER]]:
-; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[INDVARS_IV1]] to i64
; CHECK-NEXT: br label %[[INNER_LOOP:.*]]
; CHECK: [[INNER_LOOP]]:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[INNER_LOOP_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[INNER_LOOP]] ]
diff --git a/llvm/test/Transforms/IndVarSimplify/iv-sext.ll b/llvm/test/Transforms/IndVarSimplify/iv-sext.ll
index 8ec82188d8fb1..5c0e900eac3f7 100644
--- a/llvm/test/Transforms/IndVarSimplify/iv-sext.ll
+++ b/llvm/test/Transforms/IndVarSimplify/iv-sext.ll
@@ -29,11 +29,11 @@ define void @t(ptr %pval1, ptr %peakWeight, ptr %nrgReducePeakrate, i32 %bandEdg
; CHECK-NEXT: [[VAL4:%.*]] = icmp samesign ugt i64 [[INDVARS_IV1]], 0
; CHECK-NEXT: br i1 [[VAL4]], label [[BB1:%.*]], label [[BB3_PREHEADER:%.*]]
; CHECK: bb1:
-; CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[INDVARS_IV1]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[INDVARS_IV1]], -1
; CHECK-NEXT: [[VAL7:%.*]] = getelementptr float, ptr [[PVAL1]], i64 [[TMP1]]
; CHECK-NEXT: [[VAL8:%.*]] = load float, ptr [[VAL7]], align 4
; CHECK-NEXT: [[VAL9:%.*]] = fadd float [[VAL8]], [[DISTERBLO_120]]
-; CHECK-NEXT: [[TMP2:%.*]] = add nsw i64 [[INDVARS_IV1]], -1
+; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[INDVARS_IV1]], -1
; CHECK-NEXT: [[VAL12:%.*]] = getelementptr float, ptr [[PVAL1]], i64 [[TMP2]]
; CHECK-NEXT: [[VAL13:%.*]] = load float, ptr [[VAL12]], align 4
; CHECK-NEXT: [[VAL14:%.*]] = fsub float [[DISTERBHI_121]], [[VAL13]]
diff --git a/llvm/test/Transforms/IndVarSimplify/iv-widen-elim-ext.ll b/llvm/test/Transforms/IndVarSimplify/iv-widen-elim-ext.ll
index a83e9ce74b12a..ba41c59796a37 100644
--- a/llvm/test/Transforms/IndVarSimplify/iv-widen-elim-ext.ll
+++ b/llvm/test/Transforms/IndVarSimplify/iv-widen-elim-ext.ll
@@ -155,7 +155,7 @@ define i32 @foo2(i32 %M) {
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [100 x i32], ptr @b, i64 0, i64 [[INDVARS_IV]]
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
-; CHECK-NEXT: [[TMP3:%.*]] = add nsw i64 [[INDVARS_IV]], [[TMP0]]
+; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[INDVARS_IV]], [[TMP0]]
; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x i32], ptr @a, i64 0, i64 [[TMP3]]
; CHECK-NEXT: store i32 [[ADD]], ptr [[ARRAYIDX5]], align 4
; CHECK-NEXT: br label [[FOR_INC]]
@@ -223,7 +223,7 @@ define i32 @foo3(i32 %M) {
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [100 x i32], ptr @b, i64 0, i64 [[INDVARS_IV]]
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
-; CHECK-NEXT: [[TMP3:%.*]] = add nsw i64 [[INDVARS_IV]], [[TMP0]]
+; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[INDVARS_IV]], [[TMP0]]
; CHECK-NEXT: [[TMP4:%.*]] = trunc nsw i64 [[TMP3]] to i32
; CHECK-NEXT: [[IDXPROM4:%.*]] = zext i32 [[TMP4]] to i64
; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x i32], ptr @a, i64 0, i64 [[IDXPROM4]]
@@ -516,7 +516,7 @@ define void @foo7(i32 %n, ptr %a, i32 %x) {
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[TMP3]]
; CHECK-NEXT: [[TMP4:%.*]] = trunc nsw i64 [[INDVARS_IV]] to i32
; CHECK-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4
-; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], [[TMP0]]
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], [[TMP0]]
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i64 [[INDVARS_IV_NEXT]], [[TMP1]]
; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_COND_CLEANUP_LOOPEXIT:%.*]]
;
diff --git a/llvm/test/Transforms/IndVarSimplify/lftr-pr31181.ll b/llvm/test/Transforms/IndVarSimplify/lftr-pr31181.ll
index e836a7dfccea0..3c95633628dad 100644
--- a/llvm/test/Transforms/IndVarSimplify/lftr-pr31181.ll
+++ b/llvm/test/Transforms/IndVarSimplify/lftr-pr31181.ll
@@ -193,7 +193,7 @@ define i32 @switch_to_different_iv_post_inc(ptr %ptr, i1 %always_false) {
; CHECK-NEXT: store volatile i32 [[IV2]], ptr [[PTR]], align 4
; CHECK-NEXT: br label [[ALWAYS_TAKEN]]
; CHECK: always_taken:
-; CHECK-NEXT: [[IV_INC]] = add nsw i32 [[IV]], 1
+; CHECK-NEXT: [[IV_INC]] = add nuw nsw i32 [[IV]], 1
; CHECK-NEXT: [[IV2_INC]] = add nuw i32 [[IV2]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV2_INC]], -2147483627
; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND]], label [[FOR_END:%.*]]
@@ -241,7 +241,7 @@ define i32 @switch_to_different_iv_pre_inc(ptr %ptr, i1 %always_false) {
; CHECK-NEXT: store volatile i32 [[IV2]], ptr [[PTR]], align 4
; CHECK-NEXT: br label [[ALWAYS_TAKEN]]
; CHECK: always_taken:
-; CHECK-NEXT: [[IV_INC]] = add nsw i32 [[IV]], 1
+; CHECK-NEXT: [[IV_INC]] = add nuw nsw i32 [[IV]], 1
; CHECK-NEXT: [[IV2_INC]] = add nuw i32 [[IV2]], 1
; CHECK-NEXT: br label [[FOR_COND]]
; CHECK: for.end:
@@ -287,7 +287,7 @@ define i32 @switch_to_different_iv_first_poison(ptr %ptr, i1 %always_false) {
; CHECK-NEXT: br label [[ALWAYS_TAKEN]]
; CHECK: always_taken:
; CHECK-NEXT: [[IV2_INC]] = add nuw nsw i32 [[IV2]], 1
-; CHECK-NEXT: [[IV_INC]] = add nsw i32 [[IV]], 1
+; CHECK-NEXT: [[IV_INC]] = add nuw nsw i32 [[IV]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV2_INC]], -2147483628
; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND]], label [[FOR_END:%.*]]
; CHECK: for.end:
@@ -330,7 +330,7 @@ define i32 @switch_to_different_iv_second_poison(ptr %ptr, i1 %always_false) {
; CHECK-NEXT: br label [[ALWAYS_TAKEN]]
; CHECK: always_taken:
; CHECK-NEXT: [[IV2_INC]] = add nsw i32 [[IV2]], 1
-; CHECK-NEXT: [[IV_INC]] = add nsw i32 [[IV]], 1
+; CHECK-NEXT: [[IV_INC]] = add nuw nsw i32 [[IV]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV2_INC]], -2147483629
; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND]], label [[FOR_END:%.*]]
; CHECK: for.end:
diff --git a/llvm/test/Transforms/IndVarSimplify/lftr-pr41998.ll b/llvm/test/Transforms/IndVarSimplify/lftr-pr41998.ll
index b7f4756b2757f..8b89cae7560cf 100644
--- a/llvm/test/Transforms/IndVarSimplify/lftr-pr41998.ll
+++ b/llvm/test/Transforms/IndVarSimplify/lftr-pr41998.ll
@@ -8,13 +8,13 @@ define void @test_int(i32 %start, ptr %p) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[START:%.*]] to i3
; CHECK-NEXT: [[TMP1:%.*]] = sub i3 0, [[TMP0]]
+; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i3 [[TMP1]] to i32
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[I2:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[I2_INC:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[I2_INC]] = add nuw nsw i32 [[I2]], 1
; CHECK-NEXT: store volatile i32 [[I2_INC]], ptr [[P:%.*]], align 4
-; CHECK-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i32 [[I2_INC]] to i3
-; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i3 [[LFTR_WIDEIV]], [[TMP1]]
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[I2_INC]], [[WIDE_TRIP_COUNT]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[END:%.*]], label [[LOOP]]
; CHECK: end:
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/IndVarSimplify/lftr-reuse.ll b/llvm/test/Transforms/IndVarSimplify/lftr-reuse.ll
index 7409fc8db0cac..d1548504b87cc 100644
--- a/llvm/test/Transforms/IndVarSimplify/lftr-reuse.ll
+++ b/llvm/test/Transforms/IndVarSimplify/lftr-reuse.ll
@@ -71,7 +71,7 @@ define void @expandOuterRecurrence(i32 %arg) nounwind {
; CHECK: outer:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i32 [ [[SUB1]], [[OUTER_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[OUTER_INC:%.*]] ]
; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[I_INC:%.*]], [[OUTER_INC]] ], [ 0, [[OUTER_PREHEADER]] ]
-; CHECK-NEXT: [[SUB2:%.*]] = sub nsw i32 [[ARG]], [[I]]
+; CHECK-NEXT: [[SUB2:%.*]] = sub nuw nsw i32 [[ARG]], [[I]]
; CHECK-NEXT: [[SUB3:%.*]] = sub nsw i32 [[SUB2]], 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 0, [[SUB3]]
; CHECK-NEXT: br i1 [[CMP2]], label [[INNER_PH:%.*]], label [[OUTER_INC]]
@@ -141,14 +141,14 @@ define void @guardedloop(ptr %matrix, ptr %vector,
; CHECK: loop:
; CHECK-NEXT: [[INDVARS_IV2:%.*]] = phi i64 [ 0, [[LOOP_PREHEADER]] ], [ [[INDVARS_IV_NEXT3:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[LOOP_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[INDVARS_IV]], [[INDVARS_IV2]]
+; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[INDVARS_IV]], [[INDVARS_IV2]]
; CHECK-NEXT: [[MATRIXP:%.*]] = getelementptr inbounds [0 x double], ptr [[MATRIX:%.*]], i32 0, i64 [[TMP1]]
; CHECK-NEXT: [[V1:%.*]] = load double, ptr [[MATRIXP]], align 8
; CHECK-NEXT: call void @use(double [[V1]])
; CHECK-NEXT: [[VECTORP:%.*]] = getelementptr inbounds [0 x double], ptr [[VECTOR:%.*]], i32 0, i64 [[INDVARS_IV2]]
; CHECK-NEXT: [[V2:%.*]] = load double, ptr [[VECTORP]], align 8
; CHECK-NEXT: call void @use(double [[V2]])
-; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], [[TMP0]]
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], [[TMP0]]
; CHECK-NEXT: [[INDVARS_IV_NEXT3]] = add nuw nsw i64 [[INDVARS_IV2]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT3]], [[WIDE_TRIP_COUNT]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[RETURN_LOOPEXIT:%.*]]
diff --git a/llvm/test/Transforms/IndVarSimplify/lftr.ll b/llvm/test/Transforms/IndVarSimplify/lftr.ll
index 5ee62ba357ab6..2f1bf9063563e 100644
--- a/llvm/test/Transforms/IndVarSimplify/lftr.ll
+++ b/llvm/test/Transforms/IndVarSimplify/lftr.ll
@@ -41,7 +41,7 @@ define i32 @pre_to_post_sub() {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[I:%.*]] = phi i32 [ 1000, [[ENTRY:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP]] ]
-; CHECK-NEXT: [[I_NEXT]] = sub nsw i32 [[I]], 1
+; CHECK-NEXT: [[I_NEXT]] = sub nuw nsw i32 [[I]], 1
; CHECK-NEXT: store i32 [[I]], ptr @A, align 4
; CHECK-NEXT: [[C:%.*]] = icmp samesign ugt i32 [[I]], 0
; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[LOOPEXIT:%.*]]
@@ -366,8 +366,8 @@ define i32 @extend_const_postinc() #0 {
; CHECK: do.body:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i32 [ [[INDVARS_IV_NEXT:%.*]], [[DO_BODY]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: call void @bar(i32 [[INDVARS_IV]]) #[[ATTR2]]
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[INDVARS_IV]], 255
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i32 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[INDVARS_IV]], 255
; CHECK-NEXT: br i1 [[CMP]], label [[DO_END:%.*]], label [[DO_BODY]]
; CHECK: do.end:
; CHECK-NEXT: ret i32 0
diff --git a/llvm/test/Transforms/IndVarSimplify/pr30806-phi-scev.ll b/llvm/test/Transforms/IndVarSimplify/pr30806-phi-scev.ll
index 6a2bbfa5447a9..8e2c102722b21 100644
--- a/llvm/test/Transforms/IndVarSimplify/pr30806-phi-scev.ll
+++ b/llvm/test/Transforms/IndVarSimplify/pr30806-phi-scev.ll
@@ -43,7 +43,7 @@ define void @foo(ptr %buf, i32 %denominator, ptr %flag) local_unnamed_addr {
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[WHILE_BODY]] ], [ 0, [[WHILE_BODY_LR_PH]] ]
; CHECK-NEXT: [[BUF_ADDR_07:%.*]] = phi ptr [ [[BUF]], [[WHILE_BODY_LR_PH]] ], [ [[CALL:%.*]], [[WHILE_BODY]] ]
; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[DIV]] to i64
-; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], [[TMP2]]
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], [[TMP2]]
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr @theSize, align 4
; CHECK-NEXT: store i32 [[TMP3]], ptr [[I]], align 4
; CHECK-NEXT: call void @bar(ptr nonnull [[I]], i64 [[INDVARS_IV_NEXT]])
diff --git a/llvm/test/Transforms/IndVarSimplify/pr55925.ll b/llvm/test/Transforms/IndVarSimplify/pr55925.ll
index 2ad187add4e10..58364be62e283 100644
--- a/llvm/test/Transforms/IndVarSimplify/pr55925.ll
+++ b/llvm/test/Transforms/IndVarSimplify/pr55925.ll
@@ -18,9 +18,9 @@ define void @test(ptr %p) personality ptr undef {
; CHECK-NEXT: [[RES:%.*]] = invoke i32 @foo(i32 returned [[TMP0]])
; CHECK-NEXT: to label [[LOOP_LATCH]] unwind label [[EXIT:%.*]]
; CHECK: loop.latch:
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: [[TMP1:%.*]] = trunc nuw i64 [[INDVARS_IV]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @foo(i32 [[TMP1]])
-; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1
; CHECK-NEXT: br label [[LOOP]]
; CHECK: exit:
; CHECK-NEXT: [[LP:%.*]] = landingpad { ptr, i32 }
@@ -64,8 +64,8 @@ define void @test_critedge(i1 %c, ptr %p) personality ptr undef {
; CHECK-NEXT: br label [[LOOP_LATCH]]
; CHECK: loop.latch:
; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ [[TMP1]], [[LOOP_INVOKE]] ], [ 0, [[LOOP_OTHER]] ]
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @foo(i32 [[PHI]])
-; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1
; CHECK-NEXT: br label [[LOOP]]
; CHECK: exit:
; CHECK-NEXT: [[LP:%.*]] = landingpad { ptr, i32 }
diff --git a/llvm/test/Transforms/IndVarSimplify/pr79861.ll b/llvm/test/Transforms/IndVarSimplify/pr79861.ll
index 6625094496139..be2617b681233 100644
--- a/llvm/test/Transforms/IndVarSimplify/pr79861.ll
+++ b/llvm/test/Transforms/IndVarSimplify/pr79861.ll
@@ -48,7 +48,7 @@ define void @add_nowrap_flags(i64 %n) {
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_INC:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[ADD1:%.*]] = add i64 [[IV]], 123
; CHECK-NEXT: call void @use(i64 [[ADD1]])
-; CHECK-NEXT: [[IV_INC]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[IV_INC]] = add nuw i64 [[IV]], 1
; CHECK-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[IV_INC]], [[N]]
; CHECK-NEXT: br i1 [[EXIT_COND]], label [[EXIT:%.*]], label [[LOOP]]
; CHECK: exit:
@@ -83,7 +83,7 @@ define void @expander_or_disjoint(i64 %n) {
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_INC:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[IV_INC]] = add i64 [[IV]], 1
-; CHECK-NEXT: [[ADD:%.*]] = add i64 [[IV]], [[OR]]
+; CHECK-NEXT: [[ADD:%.*]] = add nuw i64 [[IV]], [[OR]]
; CHECK-NEXT: call void @use(i64 [[ADD]])
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[IV_INC]], [[TMP0]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
diff --git a/llvm/test/Transforms/IndVarSimplify/predicated_ranges.ll b/llvm/test/Transforms/IndVarSimplify/predicated_ranges.ll
index d005804ff633e..b6eef4109e4c7 100644
--- a/llvm/test/Transforms/IndVarSimplify/predicated_ranges.ll
+++ b/llvm/test/Transforms/IndVarSimplify/predicated_ranges.ll
@@ -118,7 +118,7 @@ define void @predicated_outside_loop_signed_neg(i32 %arg) nounwind #0 {
; CHECK-NEXT: br label [[OUTER:%.*]]
; CHECK: outer:
; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[I_INC:%.*]], [[OUTER_INC:%.*]] ], [ 0, [[OUTER_PREHEADER]] ]
-; CHECK-NEXT: [[SUB2:%.*]] = sub nsw i32 [[ARG]], [[I]]
+; CHECK-NEXT: [[SUB2:%.*]] = sub nuw nsw i32 [[ARG]], [[I]]
; CHECK-NEXT: [[SUB3:%.*]] = sub nsw i32 [[SUB2]], 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 0, [[SUB3]]
; CHECK-NEXT: br i1 [[CMP2]], label [[INNER_PH:%.*]], label [[OUTER_INC]]
@@ -177,7 +177,7 @@ define void @predicated_outside_loop_signed_pos(i32 %arg) nounwind #0 {
; CHECK-NEXT: br label [[OUTER:%.*]]
; CHECK: outer:
; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[I_INC:%.*]], [[OUTER_INC:%.*]] ], [ 0, [[OUTER_PREHEADER]] ]
-; CHECK-NEXT: [[SUB2:%.*]] = sub nsw i32 [[ARG]], [[I]]
+; CHECK-NEXT: [[SUB2:%.*]] = sub nuw nsw i32 [[ARG]], [[I]]
; CHECK-NEXT: [[SUB3:%.*]] = sub nsw i32 [[SUB2]], 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 0, [[SUB3]]
; CHECK-NEXT: br i1 [[CMP2]], label [[INNER_PH:%.*]], label [[OUTER_INC]]
@@ -235,7 +235,7 @@ define void @predicated_outside_loop_unsigned(i32 %arg) nounwind #0 {
; CHECK-NEXT: br label [[OUTER:%.*]]
; CHECK: outer:
; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[I_INC:%.*]], [[OUTER_INC:%.*]] ], [ 0, [[OUTER_PREHEADER]] ]
-; CHECK-NEXT: [[SUB2:%.*]] = sub nsw i32 [[ARG]], [[I]]
+; CHECK-NEXT: [[SUB2:%.*]] = sub nuw nsw i32 [[ARG]], [[I]]
; CHECK-NEXT: [[SUB3:%.*]] = sub nsw i32 [[SUB2]], 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i32 0, [[SUB3]]
; CHECK-NEXT: br i1 [[CMP2]], label [[INNER_PH:%.*]], label [[OUTER_INC]]
@@ -294,7 +294,7 @@ define void @predicated_inside_loop_signed_neg(i32 %arg) nounwind #0 {
; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 0, [[SUB1]]
; CHECK-NEXT: br i1 [[CMP1]], label [[GUARDED:%.*]], label [[EXIT:%.*]]
; CHECK: guarded:
-; CHECK-NEXT: [[SUB2:%.*]] = sub nsw i32 [[ARG]], [[I]]
+; CHECK-NEXT: [[SUB2:%.*]] = sub nuw nsw i32 [[ARG]], [[I]]
; CHECK-NEXT: [[SUB3:%.*]] = sub nsw i32 [[SUB2]], 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 0, [[SUB3]]
; CHECK-NEXT: br i1 [[CMP2]], label [[INNER_PH:%.*]], label [[OUTER_INC]]
@@ -355,7 +355,7 @@ define void @predicated_inside_loop_signed_pos(i32 %arg) nounwind #0 {
; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 0, [[SUB1]]
; CHECK-NEXT: br i1 [[CMP1]], label [[GUARDED:%.*]], label [[EXIT:%.*]]
; CHECK: guarded:
-; CHECK-NEXT: [[SUB2:%.*]] = sub nsw i32 [[ARG]], [[I]]
+; CHECK-NEXT: [[SUB2:%.*]] = sub nuw nsw i32 [[ARG]], [[I]]
; CHECK-NEXT: [[SUB3:%.*]] = sub nsw i32 [[SUB2]], 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 0, [[SUB3]]
; CHECK-NEXT: br i1 [[CMP2]], label [[INNER_PH:%.*]], label [[OUTER_INC]]
@@ -415,7 +415,7 @@ define void @predicated_inside_loop_unsigned(i32 %arg) nounwind #0 {
; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 0, [[SUB1]]
; CHECK-NEXT: br i1 [[CMP1]], label [[GUARDED:%.*]], label [[EXIT:%.*]]
; CHECK: guarded:
-; CHECK-NEXT: [[SUB2:%.*]] = sub nsw i32 [[ARG]], [[I]]
+; CHECK-NEXT: [[SUB2:%.*]] = sub nuw nsw i32 [[ARG]], [[I]]
; CHECK-NEXT: [[SUB3:%.*]] = sub nsw i32 [[SUB2]], 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i32 0, [[SUB3]]
; CHECK-NEXT: br i1 [[CMP2]], label [[INNER_PH:%.*]], label [[OUTER_INC]]
diff --git a/llvm/test/Transforms/IndVarSimplify/strengthen-overflow.ll b/llvm/test/Transforms/IndVarSimplify/strengthen-overflow.ll
index 4a230b781d2db..47bad1f5f055e 100644
--- a/llvm/test/Transforms/IndVarSimplify/strengthen-overflow.ll
+++ b/llvm/test/Transforms/IndVarSimplify/strengthen-overflow.ll
@@ -402,7 +402,7 @@ define void @test_shl_unbounded(ptr %p, i64 %n) {
; CHECK-NEXT: [[OFF:%.*]] = shl i64 [[IV]], 2
; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 [[OFF]]
; CHECK-NEXT: store i8 0, ptr [[GEP]], align 1
-; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N:%.*]]
; CHECK-NEXT: br i1 [[EC]], label [[EXIT:%.*]], label [[LOOP]]
; CHECK: exit:
diff --git a/llvm/test/Transforms/IndVarSimplify/widen-nonnegative.ll b/llvm/test/Transforms/IndVarSimplify/widen-nonnegative.ll
index e00eaafa3f192..382e2ed1013ba 100644
--- a/llvm/test/Transforms/IndVarSimplify/widen-nonnegative.ll
+++ b/llvm/test/Transforms/IndVarSimplify/widen-nonnegative.ll
@@ -114,7 +114,7 @@ define void @sext_add_nsw(ptr %A, i32 %offset, i32 %M) {
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[INDVARS_IV]], [[TMP0]]
+; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[INDVARS_IV]], [[TMP0]]
; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[TMP1]]
; CHECK-NEXT: tail call void @use_ptr(ptr [[ARRAYIDX_US]])
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
@@ -180,13 +180,14 @@ exit:
define void @sext_add_noflags(ptr %A, i32 %offset, i32 %M) {
; CHECK-LABEL: @sext_add_noflags(
; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[OFFSET:%.*]] to i64
; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[M:%.*]], i32 1)
; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[SMAX]] to i64
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = trunc nuw nsw i64 [[INDVARS_IV]] to i32
-; CHECK-NEXT: [[ADD_US:%.*]] = add i32 [[TMP0]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[INDVARS_IV]], [[TMP0]]
+; CHECK-NEXT: [[ADD_US:%.*]] = trunc nuw i64 [[TMP1]] to i32
; CHECK-NEXT: [[IDXPROM_US:%.*]] = sext i32 [[ADD_US]] to i64
; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[IDXPROM_US]]
; CHECK-NEXT: tail call void @use_ptr(ptr [[ARRAYIDX_US]])
@@ -216,15 +217,13 @@ exit:
define void @zext_add_nsw(ptr %A, i32 %offset, i32 %M) {
; CHECK-LABEL: @zext_add_nsw(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[OFFSET:%.*]] to i64
+; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[OFFSET:%.*]] to i64
; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[M:%.*]], i32 1)
; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[SMAX]] to i64
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[INDVARS_IV]], [[TMP0]]
-; CHECK-NEXT: [[TMP2:%.*]] = trunc nsw i64 [[TMP1]] to i32
-; CHECK-NEXT: [[IDXPROM_US:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[IDXPROM_US:%.*]] = add nuw nsw i64 [[INDVARS_IV]], [[TMP0]]
; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[IDXPROM_US]]
; CHECK-NEXT: tail call void @use_ptr(ptr [[ARRAYIDX_US]])
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
@@ -288,14 +287,13 @@ exit:
define void @zext_add_noflags(ptr %A, i32 %offset, i32 %M) {
; CHECK-LABEL: @zext_add_noflags(
; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[OFFSET:%.*]] to i64
; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[M:%.*]], i32 1)
; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[SMAX]] to i64
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = trunc nuw nsw i64 [[INDVARS_IV]] to i32
-; CHECK-NEXT: [[ADD_US:%.*]] = add i32 [[TMP0]], [[OFFSET:%.*]]
-; CHECK-NEXT: [[IDXPROM_US:%.*]] = zext i32 [[ADD_US]] to i64
+; CHECK-NEXT: [[IDXPROM_US:%.*]] = add nuw nsw i64 [[INDVARS_IV]], [[TMP0]]
; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[IDXPROM_US]]
; CHECK-NEXT: tail call void @use_ptr(ptr [[ARRAYIDX_US]])
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
@@ -324,13 +322,13 @@ exit:
define void @zext_nneg_add_nsw(ptr %A, i32 %offset, i32 %M) {
; CHECK-LABEL: @zext_nneg_add_nsw(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[OFFSET:%.*]] to i64
+; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[OFFSET:%.*]] to i64
; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[M:%.*]], i32 1)
; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[SMAX]] to i64
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[INDVARS_IV]], [[TMP0]]
+; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[INDVARS_IV]], [[TMP0]]
; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[TMP1]]
; CHECK-NEXT: tail call void @use_ptr(ptr [[ARRAYIDX_US]])
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
@@ -394,14 +392,13 @@ exit:
define void @zext_nneg_add_noflags(ptr %A, i32 %offset, i32 %M) {
; CHECK-LABEL: @zext_nneg_add_noflags(
; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[OFFSET:%.*]] to i64
; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[M:%.*]], i32 1)
; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[SMAX]] to i64
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = trunc nuw nsw i64 [[INDVARS_IV]] to i32
-; CHECK-NEXT: [[ADD_US:%.*]] = add i32 [[TMP0]], [[OFFSET:%.*]]
-; CHECK-NEXT: [[IDXPROM_US:%.*]] = zext nneg i32 [[ADD_US]] to i64
+; CHECK-NEXT: [[IDXPROM_US:%.*]] = add nuw nsw i64 [[INDVARS_IV]], [[TMP0]]
; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[IDXPROM_US]]
; CHECK-NEXT: tail call void @use_ptr(ptr [[ARRAYIDX_US]])
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
diff --git a/llvm/test/Transforms/LoopFlatten/widen-iv.ll b/llvm/test/Transforms/LoopFlatten/widen-iv.ll
index ac42acb932fc3..8672c7b70db78 100644
--- a/llvm/test/Transforms/LoopFlatten/widen-iv.ll
+++ b/llvm/test/Transforms/LoopFlatten/widen-iv.ll
@@ -131,17 +131,24 @@ define void @foo2_sext(ptr nocapture readonly %A, i32 %N, i32 %M) {
; CHECK-NEXT: br label [[FOR_COND1_PREHEADER:%.*]]
; CHECK: for.cond1.preheader.us.preheader:
; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[M]] to i64
-; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[N]] to i64
-; CHECK-NEXT: [[FLATTEN_TRIPCOUNT:%.*]] = mul i64 [[TMP0]], [[TMP1]]
+; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[M]] to i64
+; CHECK-NEXT: [[FLATTEN_TRIPCOUNT:%.*]] = sext i32 [[N]] to i64
; CHECK-NEXT: br label [[FOR_COND1_PREHEADER_US:%.*]]
; CHECK: for.cond1.preheader.us:
; CHECK-NEXT: [[INDVAR2:%.*]] = phi i64 [ [[INDVAR_NEXT3:%.*]], [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US:%.*]] ], [ 0, [[FOR_COND1_PREHEADER_US_PREHEADER]] ]
+; CHECK-NEXT: [[TMP3:%.*]] = mul nsw i64 [[INDVAR2]], [[TMP1]]
+; CHECK-NEXT: [[TMP4:%.*]] = trunc nsw i64 [[TMP3]] to i32
+; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
; CHECK-NEXT: br label [[FOR_BODY4_US:%.*]]
; CHECK: for.body4.us:
-; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDVAR2]]
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ [[INDVAR_NEXT:%.*]], [[FOR_BODY4_US]] ], [ 0, [[FOR_COND1_PREHEADER_US]] ]
+; CHECK-NEXT: [[TMP6:%.*]] = add nsw i64 [[INDVAR]], [[TMP5]]
+; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[TMP6]]
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX_US]], align 4
; CHECK-NEXT: tail call void @g(i32 [[TMP2]])
-; CHECK-NEXT: br label [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US]]
+; CHECK-NEXT: [[INDVAR_NEXT]] = add nuw nsw i64 [[INDVAR]], 1
+; CHECK-NEXT: [[CMP2_US:%.*]] = icmp slt i64 [[INDVAR_NEXT]], [[TMP0]]
+; CHECK-NEXT: br i1 [[CMP2_US]], label [[FOR_BODY4_US]], label [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US]]
; CHECK: for.cond1.for.cond.cleanup3_crit_edge.us:
; CHECK-NEXT: [[INDVAR_NEXT3]] = add nuw nsw i64 [[INDVAR2]], 1
; CHECK-NEXT: [[CMP_US:%.*]] = icmp slt i64 [[INDVAR_NEXT3]], [[FLATTEN_TRIPCOUNT]]
@@ -268,23 +275,27 @@ define void @foo2_zext(ptr nocapture readonly %A, i32 %N, i32 %M) {
; CHECK: for.cond1.preheader.us.preheader:
; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[M]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[N]] to i64
-; CHECK-NEXT: [[FLATTEN_TRIPCOUNT:%.*]] = mul i64 [[TMP0]], [[TMP1]]
; CHECK-NEXT: br label [[FOR_COND1_PREHEADER_US:%.*]]
; CHECK: for.cond1.preheader.preheader:
; CHECK-NEXT: br label [[FOR_COND1_PREHEADER:%.*]]
; CHECK: for.cond1.preheader.us:
; CHECK-NEXT: [[INDVAR1:%.*]] = phi i64 [ [[INDVAR_NEXT2:%.*]], [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US:%.*]] ], [ 0, [[FOR_COND1_PREHEADER_US_PREHEADER]] ]
-; CHECK-NEXT: [[FLATTEN_TRUNCIV:%.*]] = trunc i64 [[INDVAR1]] to i32
+; CHECK-NEXT: [[TMP4:%.*]] = trunc nuw i64 [[INDVAR1]] to i32
+; CHECK-NEXT: [[MUL_US:%.*]] = mul i32 [[TMP4]], [[M]]
+; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[MUL_US]] to i64
; CHECK-NEXT: br label [[FOR_BODY4_US:%.*]]
; CHECK: for.body4.us:
-; CHECK-NEXT: [[IDXPROM_US:%.*]] = zext i32 [[FLATTEN_TRUNCIV]] to i64
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ [[INDVAR_NEXT:%.*]], [[FOR_BODY4_US]] ], [ 0, [[FOR_COND1_PREHEADER_US]] ]
+; CHECK-NEXT: [[IDXPROM_US:%.*]] = add i64 [[INDVAR]], [[TMP3]]
; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[IDXPROM_US]]
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX_US]], align 4
; CHECK-NEXT: tail call void @g(i32 [[TMP2]])
-; CHECK-NEXT: br label [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US]]
+; CHECK-NEXT: [[INDVAR_NEXT]] = add nuw i64 [[INDVAR]], 1
+; CHECK-NEXT: [[CMP2_US:%.*]] = icmp ult i64 [[INDVAR_NEXT]], [[TMP0]]
+; CHECK-NEXT: br i1 [[CMP2_US]], label [[FOR_BODY4_US]], label [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US]]
; CHECK: for.cond1.for.cond.cleanup3_crit_edge.us:
; CHECK-NEXT: [[INDVAR_NEXT2]] = add i64 [[INDVAR1]], 1
-; CHECK-NEXT: [[CMP_US:%.*]] = icmp ult i64 [[INDVAR_NEXT2]], [[FLATTEN_TRIPCOUNT]]
+; CHECK-NEXT: [[CMP_US:%.*]] = icmp ult i64 [[INDVAR_NEXT2]], [[TMP1]]
; CHECK-NEXT: br i1 [[CMP_US]], label [[FOR_COND1_PREHEADER_US]], label [[FOR_COND_CLEANUP_LOOPEXIT19:%.*]]
; CHECK: for.cond1.preheader:
; CHECK-NEXT: [[I_018:%.*]] = phi i32 [ [[INC6:%.*]], [[FOR_COND1_PREHEADER]] ], [ 0, [[FOR_COND1_PREHEADER_PREHEADER]] ]
@@ -398,22 +409,26 @@ define void @zext(i32 %N, ptr nocapture %A, i16 %val) {
; CHECK: for.cond1.preheader.us.preheader:
; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[N]] to i64
-; CHECK-NEXT: [[FLATTEN_TRIPCOUNT:%.*]] = mul i64 [[TMP0]], [[TMP1]]
; CHECK-NEXT: br label [[FOR_COND1_PREHEADER_US:%.*]]
; CHECK: for.cond1.preheader.us:
; CHECK-NEXT: [[INDVAR1:%.*]] = phi i64 [ [[INDVAR_NEXT2:%.*]], [[FOR_COND1_FOR_INC7_CRIT_EDGE_US:%.*]] ], [ 0, [[FOR_COND1_PREHEADER_US_PREHEADER]] ]
-; CHECK-NEXT: [[FLATTEN_TRUNCIV:%.*]] = trunc i64 [[INDVAR1]] to i32
+; CHECK-NEXT: [[TMP4:%.*]] = trunc nuw i64 [[INDVAR1]] to i32
+; CHECK-NEXT: [[MUL_US:%.*]] = mul i32 [[TMP4]], [[N]]
+; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[MUL_US]] to i64
; CHECK-NEXT: br label [[FOR_BODY3_US:%.*]]
; CHECK: for.body3.us:
-; CHECK-NEXT: [[IDXPROM_US:%.*]] = zext i32 [[FLATTEN_TRUNCIV]] to i64
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ [[INDVAR_NEXT:%.*]], [[FOR_BODY3_US]] ], [ 0, [[FOR_COND1_PREHEADER_US]] ]
+; CHECK-NEXT: [[IDXPROM_US:%.*]] = add i64 [[INDVAR]], [[TMP3]]
; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds i16, ptr [[A:%.*]], i64 [[IDXPROM_US]]
; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[ARRAYIDX_US]], align 2
; CHECK-NEXT: [[ADD5_US:%.*]] = add i16 [[TMP2]], [[VAL:%.*]]
; CHECK-NEXT: store i16 [[ADD5_US]], ptr [[ARRAYIDX_US]], align 2
-; CHECK-NEXT: br label [[FOR_COND1_FOR_INC7_CRIT_EDGE_US]]
+; CHECK-NEXT: [[INDVAR_NEXT]] = add nuw i64 [[INDVAR]], 1
+; CHECK-NEXT: [[CMP2_US:%.*]] = icmp ult i64 [[INDVAR_NEXT]], [[TMP0]]
+; CHECK-NEXT: br i1 [[CMP2_US]], label [[FOR_BODY3_US]], label [[FOR_COND1_FOR_INC7_CRIT_EDGE_US]]
; CHECK: for.cond1.for.inc7_crit_edge.us:
; CHECK-NEXT: [[INDVAR_NEXT2]] = add i64 [[INDVAR1]], 1
-; CHECK-NEXT: [[CMP_US:%.*]] = icmp ult i64 [[INDVAR_NEXT2]], [[FLATTEN_TRIPCOUNT]]
+; CHECK-NEXT: [[CMP_US:%.*]] = icmp ult i64 [[INDVAR_NEXT2]], [[TMP1]]
; CHECK-NEXT: br i1 [[CMP_US]], label [[FOR_COND1_PREHEADER_US]], label [[FOR_END9_LOOPEXIT:%.*]]
; CHECK: for.end9.loopexit:
; CHECK-NEXT: br label [[FOR_END9]]
@@ -509,19 +524,24 @@ define void @test(i8 %n, i8 %m) {
; CHECK: for.cond3.preheader.us.preheader:
; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[M]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[N]] to i64
-; CHECK-NEXT: [[FLATTEN_TRIPCOUNT:%.*]] = mul i64 [[TMP0]], [[TMP1]]
; CHECK-NEXT: br label [[FOR_COND3_PREHEADER_US:%.*]]
; CHECK: for.cond3.preheader.us:
; CHECK-NEXT: [[INDVAR2:%.*]] = phi i64 [ [[INDVAR_NEXT3:%.*]], [[FOR_COND3_FOR_COND_CLEANUP8_CRIT_EDGE_US:%.*]] ], [ 0, [[FOR_COND3_PREHEADER_US_PREHEADER]] ]
-; CHECK-NEXT: [[FLATTEN_TRUNCIV:%.*]] = trunc i64 [[INDVAR2]] to i8
+; CHECK-NEXT: [[TMP2:%.*]] = trunc nuw i64 [[INDVAR2]] to i8
+; CHECK-NEXT: [[MUL_US:%.*]] = mul i8 [[TMP2]], [[M]]
+; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[MUL_US]] to i64
; CHECK-NEXT: br label [[FOR_BODY9_US:%.*]]
; CHECK: for.body9.us:
-; CHECK-NEXT: [[CONV14_US:%.*]] = zext i8 [[FLATTEN_TRUNCIV]] to i32
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ [[INDVAR_NEXT:%.*]], [[FOR_BODY9_US]] ], [ 0, [[FOR_COND3_PREHEADER_US]] ]
+; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDVAR]], [[TMP3]]
+; CHECK-NEXT: [[CONV14_US:%.*]] = trunc nuw i64 [[TMP4]] to i32
; CHECK-NEXT: [[CALL_US:%.*]] = tail call i32 @use_32(i32 [[CONV14_US]])
-; CHECK-NEXT: br label [[FOR_COND3_FOR_COND_CLEANUP8_CRIT_EDGE_US]]
+; CHECK-NEXT: [[INDVAR_NEXT]] = add nuw i64 [[INDVAR]], 1
+; CHECK-NEXT: [[CMP6_US:%.*]] = icmp ult i64 [[INDVAR_NEXT]], [[TMP0]]
+; CHECK-NEXT: br i1 [[CMP6_US]], label [[FOR_BODY9_US]], label [[FOR_COND3_FOR_COND_CLEANUP8_CRIT_EDGE_US]]
; CHECK: for.cond3.for.cond.cleanup8_crit_edge.us:
; CHECK-NEXT: [[INDVAR_NEXT3]] = add i64 [[INDVAR2]], 1
-; CHECK-NEXT: [[CMP_US:%.*]] = icmp ult i64 [[INDVAR_NEXT3]], [[FLATTEN_TRIPCOUNT]]
+; CHECK-NEXT: [[CMP_US:%.*]] = icmp ult i64 [[INDVAR_NEXT3]], [[TMP1]]
; CHECK-NEXT: br i1 [[CMP_US]], label [[FOR_COND3_PREHEADER_US]], label [[FOR_COND_CLEANUP_LOOPEXIT1:%.*]]
; CHECK: for.cond3.preheader:
; CHECK-NEXT: [[I_026:%.*]] = phi i8 [ [[INC16:%.*]], [[FOR_COND3_PREHEADER]] ], [ 0, [[FOR_COND3_PREHEADER_PREHEADER]] ]
@@ -644,25 +664,29 @@ define void @test3(i8 %n, i8 %m) {
; CHECK: for.cond3.preheader.us.preheader:
; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[M]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[N]] to i64
-; CHECK-NEXT: [[FLATTEN_TRIPCOUNT:%.*]] = mul i64 [[TMP0]], [[TMP1]]
; CHECK-NEXT: br label [[FOR_COND3_PREHEADER_US:%.*]]
; CHECK: for.cond3.preheader.us:
; CHECK-NEXT: [[INDVAR2:%.*]] = phi i64 [ [[INDVAR_NEXT3:%.*]], [[FOR_COND3_FOR_COND_CLEANUP8_CRIT_EDGE_US:%.*]] ], [ 0, [[FOR_COND3_PREHEADER_US_PREHEADER]] ]
-; CHECK-NEXT: [[FLATTEN_TRUNCIV:%.*]] = trunc i64 [[INDVAR2]] to i8
+; CHECK-NEXT: [[TMP2:%.*]] = trunc nuw i64 [[INDVAR2]] to i8
+; CHECK-NEXT: [[MUL_US:%.*]] = mul i8 [[TMP2]], [[M]]
+; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[MUL_US]] to i64
; CHECK-NEXT: br label [[FOR_BODY9_US:%.*]]
; CHECK: for.body9.us:
-; CHECK-NEXT: [[CONV14_US:%.*]] = zext i8 [[FLATTEN_TRUNCIV]] to i32
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ [[INDVAR_NEXT:%.*]], [[FOR_BODY9_US]] ], [ 0, [[FOR_COND3_PREHEADER_US]] ]
+; CHECK-NEXT: [[CONV21_US:%.*]] = add i64 [[INDVAR]], [[TMP3]]
+; CHECK-NEXT: [[CONV14_US:%.*]] = trunc nuw i64 [[CONV21_US]] to i32
; CHECK-NEXT: [[CALL_US:%.*]] = tail call i32 @use_32(i32 [[CONV14_US]])
-; CHECK-NEXT: [[CONV15_US:%.*]] = zext i8 [[FLATTEN_TRUNCIV]] to i16
+; CHECK-NEXT: [[CONV15_US:%.*]] = trunc nuw i64 [[CONV21_US]] to i16
; CHECK-NEXT: [[CALL16_US:%.*]] = tail call i32 @use_16(i16 [[CONV15_US]])
; CHECK-NEXT: [[CALL18_US:%.*]] = tail call i32 @use_32(i32 [[CONV14_US]])
; CHECK-NEXT: [[CALL20_US:%.*]] = tail call i32 @use_16(i16 [[CONV15_US]])
-; CHECK-NEXT: [[CONV21_US:%.*]] = zext i8 [[FLATTEN_TRUNCIV]] to i64
; CHECK-NEXT: [[CALL22_US:%.*]] = tail call i32 @use_64(i64 [[CONV21_US]])
-; CHECK-NEXT: br label [[FOR_COND3_FOR_COND_CLEANUP8_CRIT_EDGE_US]]
+; CHECK-NEXT: [[INDVAR_NEXT]] = add nuw i64 [[INDVAR]], 1
+; CHECK-NEXT: [[CMP6_US:%.*]] = icmp ult i64 [[INDVAR_NEXT]], [[TMP0]]
+; CHECK-NEXT: br i1 [[CMP6_US]], label [[FOR_BODY9_US]], label [[FOR_COND3_FOR_COND_CLEANUP8_CRIT_EDGE_US]]
; CHECK: for.cond3.for.cond.cleanup8_crit_edge.us:
; CHECK-NEXT: [[INDVAR_NEXT3]] = add i64 [[INDVAR2]], 1
-; CHECK-NEXT: [[CMP_US:%.*]] = icmp ult i64 [[INDVAR_NEXT3]], [[FLATTEN_TRIPCOUNT]]
+; CHECK-NEXT: [[CMP_US:%.*]] = icmp ult i64 [[INDVAR_NEXT3]], [[TMP1]]
; CHECK-NEXT: br i1 [[CMP_US]], label [[FOR_COND3_PREHEADER_US]], label [[FOR_COND_CLEANUP_LOOPEXIT1:%.*]]
; CHECK: for.cond3.preheader:
; CHECK-NEXT: [[I_038:%.*]] = phi i8 [ [[INC24:%.*]], [[FOR_COND3_PREHEADER]] ], [ 0, [[FOR_COND3_PREHEADER_PREHEADER]] ]
@@ -797,24 +821,33 @@ define void @test4(i16 %n, i16 %m) {
; CHECK: for.cond3.preheader.us.preheader:
; CHECK-NEXT: [[TMP0:%.*]] = sext i16 [[M]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[N]] to i64
-; CHECK-NEXT: [[FLATTEN_TRIPCOUNT:%.*]] = mul i64 [[TMP0]], [[TMP1]]
; CHECK-NEXT: br label [[FOR_COND3_PREHEADER_US:%.*]]
; CHECK: for.cond3.preheader.us:
; CHECK-NEXT: [[INDVAR2:%.*]] = phi i64 [ [[INDVAR_NEXT3:%.*]], [[FOR_COND3_FOR_COND_CLEANUP8_CRIT_EDGE_US:%.*]] ], [ 0, [[FOR_COND3_PREHEADER_US_PREHEADER]] ]
-; CHECK-NEXT: [[FLATTEN_TRUNCIV:%.*]] = trunc i64 [[INDVAR2]] to i16
+; CHECK-NEXT: [[TMP2:%.*]] = trunc nuw nsw i64 [[INDVAR2]] to i16
+; CHECK-NEXT: [[MUL_US:%.*]] = mul i16 [[TMP2]], [[M]]
+; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[MUL_US]] to i64
; CHECK-NEXT: br label [[FOR_BODY9_US:%.*]]
; CHECK: for.body9.us:
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ [[INDVAR_NEXT:%.*]], [[FOR_BODY9_US]] ], [ 0, [[FOR_COND3_PREHEADER_US]] ]
+; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDVAR]], [[TMP3]]
+; CHECK-NEXT: [[FLATTEN_TRUNCIV:%.*]] = trunc nuw i64 [[TMP4]] to i16
; CHECK-NEXT: [[CONV14_US:%.*]] = sext i16 [[FLATTEN_TRUNCIV]] to i32
; CHECK-NEXT: [[CALL_US:%.*]] = tail call i32 @use_32(i32 [[CONV14_US]])
-; CHECK-NEXT: [[CALL15_US:%.*]] = tail call i32 @use_16(i16 [[FLATTEN_TRUNCIV]])
+; CHECK-NEXT: [[TMP6:%.*]] = trunc nuw i64 [[TMP4]] to i16
+; CHECK-NEXT: [[CALL15_US:%.*]] = tail call i32 @use_16(i16 [[TMP6]])
; CHECK-NEXT: [[CALL17_US:%.*]] = tail call i32 @use_32(i32 [[CONV14_US]])
-; CHECK-NEXT: [[CALL18_US:%.*]] = tail call i32 @use_16(i16 [[FLATTEN_TRUNCIV]])
-; CHECK-NEXT: [[CONV19_US:%.*]] = sext i16 [[FLATTEN_TRUNCIV]] to i64
+; CHECK-NEXT: [[TMP7:%.*]] = trunc nuw i64 [[TMP4]] to i16
+; CHECK-NEXT: [[CALL18_US:%.*]] = tail call i32 @use_16(i16 [[TMP7]])
+; CHECK-NEXT: [[TMP8:%.*]] = trunc nuw i64 [[TMP4]] to i16
+; CHECK-NEXT: [[CONV19_US:%.*]] = sext i16 [[TMP8]] to i64
; CHECK-NEXT: [[CALL20_US:%.*]] = tail call i32 @use_64(i64 [[CONV19_US]])
-; CHECK-NEXT: br label [[FOR_COND3_FOR_COND_CLEANUP8_CRIT_EDGE_US]]
+; CHECK-NEXT: [[INDVAR_NEXT]] = add nuw nsw i64 [[INDVAR]], 1
+; CHECK-NEXT: [[CMP6_US:%.*]] = icmp slt i64 [[INDVAR_NEXT]], [[TMP0]]
+; CHECK-NEXT: br i1 [[CMP6_US]], label [[FOR_BODY9_US]], label [[FOR_COND3_FOR_COND_CLEANUP8_CRIT_EDGE_US]]
; CHECK: for.cond3.for.cond.cleanup8_crit_edge.us:
; CHECK-NEXT: [[INDVAR_NEXT3]] = add i64 [[INDVAR2]], 1
-; CHECK-NEXT: [[CMP_US:%.*]] = icmp slt i64 [[INDVAR_NEXT3]], [[FLATTEN_TRIPCOUNT]]
+; CHECK-NEXT: [[CMP_US:%.*]] = icmp slt i64 [[INDVAR_NEXT3]], [[TMP1]]
; CHECK-NEXT: br i1 [[CMP_US]], label [[FOR_COND3_PREHEADER_US]], label [[FOR_COND_CLEANUP_LOOPEXIT:%.*]]
; CHECK: for.cond3.preheader:
; CHECK-NEXT: [[I_039:%.*]] = phi i16 [ [[INC22:%.*]], [[FOR_COND3_PREHEADER]] ], [ 0, [[FOR_COND3_PREHEADER_PREHEADER]] ]
diff --git a/llvm/test/Transforms/LoopFlatten/widen-iv2.ll b/llvm/test/Transforms/LoopFlatten/widen-iv2.ll
index 7b1caa70387fa..63483037c5b3e 100644
--- a/llvm/test/Transforms/LoopFlatten/widen-iv2.ll
+++ b/llvm/test/Transforms/LoopFlatten/widen-iv2.ll
@@ -33,12 +33,13 @@ define dso_local i32 @fn1() local_unnamed_addr #0 {
; CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr @c, align 8
; CHECK-NEXT: [[TMP5:%.*]] = mul nsw i64 [[INDVAR2]], [[TMP2]]
; CHECK-NEXT: [[MUL_US:%.*]] = mul nsw i32 [[I_016_US]], [[TMP0]]
-; CHECK-NEXT: [[TMP6:%.*]] = sext i32 [[MUL_US]] to i64
+; CHECK-NEXT: [[TMP6:%.*]] = trunc nsw i64 [[TMP5]] to i32
+; CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP6]] to i64
; CHECK-NEXT: br label [[FOR_BODY3_US:%.*]]
; CHECK: for.body3.us:
; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ [[INDVAR_NEXT:%.*]], [[FOR_BODY3_US]] ], [ 0, [[FOR_COND1_PREHEADER_US]] ]
; CHECK-NEXT: [[J_014_US:%.*]] = phi i32 [ 0, [[FOR_COND1_PREHEADER_US]] ], [ [[INC_US:%.*]], [[FOR_BODY3_US]] ]
-; CHECK-NEXT: [[TMP7:%.*]] = add nsw i64 [[INDVAR]], [[TMP5]]
+; CHECK-NEXT: [[TMP7:%.*]] = add nsw i64 [[INDVAR]], [[TMP10]]
; CHECK-NEXT: [[TMP8:%.*]] = sext i32 [[J_014_US]] to i64
; CHECK-NEXT: [[TMP9:%.*]] = add nsw i64 [[TMP8]], [[TMP5]]
; CHECK-NEXT: [[ADD_US:%.*]] = add nsw i32 [[J_014_US]], [[MUL_US]]
diff --git a/llvm/test/Transforms/LoopStrengthReduce/ARM/illegal-addr-modes.ll b/llvm/test/Transforms/LoopStrengthReduce/ARM/illegal-addr-modes.ll
index 3844e00ae0a4f..434ee01668fa4 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/ARM/illegal-addr-modes.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/ARM/illegal-addr-modes.ll
@@ -40,7 +40,7 @@ define ptr @negativeOneCase(ptr returned %a, ptr nocapture readonly %b, i32 %n)
; CHECK: while.body5:
; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[SCEVGEP1]], align 1
; CHECK-NEXT: store i8 [[TMP1]], ptr [[SCEVGEP2]], align 1
-; CHECK-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 1
+; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw i32 [[LSR_IV]], 1
; CHECK-NEXT: br label [[WHILE_COND2]]
; CHECK: while.end8:
; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[INCDEC_PTR]], i32 [[N]]
diff --git a/llvm/test/Transforms/LoopStrengthReduce/RISCV/term-fold-crash.ll b/llvm/test/Transforms/LoopStrengthReduce/RISCV/term-fold-crash.ll
index 9fb240684d232..e3d50308f1986 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/RISCV/term-fold-crash.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/RISCV/term-fold-crash.ll
@@ -7,16 +7,18 @@ define void @test(ptr %p, i8 %arg, i32 %start) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[ARG]] to i32
; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[CONV]], 1
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[START]], [[SHR]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 1
+; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[SHR]] to i64
+; CHECK-NEXT: [[IDXPROM2:%.*]] = zext i32 [[START]] to i64
+; CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr i8, ptr [[P]], i64 [[IDXPROM2]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[WIDE_TRIP_COUNT]], [[IDXPROM2]]
+; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 1
+; CHECK-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP2]]
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
-; CHECK-NEXT: [[ADD810:%.*]] = phi i32 [ [[START]], [[ENTRY:%.*]] ], [ [[ADD:%.*]], [[FOR_BODY]] ]
-; CHECK-NEXT: [[IDXPROM2:%.*]] = zext i32 [[ADD810]] to i64
-; CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr i8, ptr [[P]], i64 [[IDXPROM2]]
-; CHECK-NEXT: [[V:%.*]] = load i8, ptr [[ARRAYIDX3]], align 1
-; CHECK-NEXT: [[ADD]] = add i32 [[ADD810]], 1
-; CHECK-NEXT: [[LSR_FOLD_TERM_COND_REPLACED_TERM_COND:%.*]] = icmp eq i32 [[ADD]], [[TMP1]]
+; CHECK-NEXT: [[LSR_IV1:%.*]] = phi ptr [ [[SCEVGEP2:%.*]], [[FOR_BODY]] ], [ [[ARRAYIDX3]], [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[V:%.*]] = load i8, ptr [[LSR_IV1]], align 1
+; CHECK-NEXT: [[SCEVGEP2]] = getelementptr i8, ptr [[LSR_IV1]], i64 1
+; CHECK-NEXT: [[LSR_FOLD_TERM_COND_REPLACED_TERM_COND:%.*]] = icmp eq ptr [[SCEVGEP2]], [[SCEVGEP3]]
; CHECK-NEXT: br i1 [[LSR_FOLD_TERM_COND_REPLACED_TERM_COND]], label [[EXIT:%.*]], label [[FOR_BODY]]
; CHECK: exit:
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold-negative-testcase.ll b/llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold-negative-testcase.ll
index b16a981afdee0..8135e7862a586 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold-negative-testcase.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold-negative-testcase.ll
@@ -228,7 +228,7 @@ define void @TermCondMoreThanOneUse(ptr %a) {
; CHECK-NEXT: [[UGLYGEP2]] = getelementptr i8, ptr [[LSR_IV1]], i64 4
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[LSR_IV2]], 0
; CHECK-NEXT: [[DUMMY:%.*]] = select i1 [[EXITCOND_NOT]], i8 0, i8 1
-; CHECK-NEXT: [[LSR_IV_NEXT3]] = add nsw i64 [[LSR_IV2]], 1
+; CHECK-NEXT: [[LSR_IV_NEXT3]] = add nuw nsw i64 [[LSR_IV2]], 1
; CHECK-NEXT: [[LSR_FOLD_TERM_COND_REPLACED_TERM_COND:%.*]] = icmp eq ptr [[UGLYGEP2]], [[SCEVGEP]]
; CHECK-NEXT: br i1 [[LSR_FOLD_TERM_COND_REPLACED_TERM_COND]], label [[FOR_END:%.*]], label [[FOR_BODY]]
; CHECK: for.end:
diff --git a/llvm/test/Transforms/LoopStrengthReduce/scev-incorrect-nuw-inference.ll b/llvm/test/Transforms/LoopStrengthReduce/scev-incorrect-nuw-inference.ll
index 1b37b4cd2a2d8..37f25da1f9772 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/scev-incorrect-nuw-inference.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/scev-incorrect-nuw-inference.ll
@@ -13,25 +13,26 @@ define noundef i64 @test() {
; CHECK-NEXT: bb2:
; CHECK-NEXT: br label [[BB3:%.*]]
; CHECK: bb3:
-; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[BB10:%.*]] ], [ -1, [[BB2:%.*]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[LSR_IV]], 65536
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[TMP0]], 65535
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[AND]] to i64
-; CHECK-NEXT: [[ADD4:%.*]] = add nsw i64 [[ZEXT]], -128
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT1:%.*]], [[BB10:%.*]] ], [ 0, [[BB2:%.*]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[LSR_IV]], 65535
+; CHECK-NEXT: [[ADD4:%.*]] = add i64 [[LSR_IV]], 65407
; CHECK-NEXT: [[ICMP5:%.*]] = icmp ult i64 [[ADD4]], -256
+; CHECK-NEXT: [[AND:%.*]] = trunc i64 [[TMP0]] to i32
; CHECK-NEXT: [[ICMP6:%.*]] = icmp ult i32 [[AND]], 128
; CHECK-NEXT: [[OR:%.*]] = or i1 [[ICMP5]], [[ICMP6]]
; CHECK-NEXT: br i1 [[OR]], label [[BB10]], label [[BB7:%.*]]
; CHECK: bb7:
-; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[LSR_IV]], 1
-; CHECK-NEXT: call void @foo(i32 [[TMP1]])
+; CHECK-NEXT: [[ADD4:%.*]] = trunc i64 [[LSR_IV]] to i32
+; CHECK-NEXT: call void @foo(i32 [[ADD4]])
; CHECK-NEXT: unreachable
; CHECK: bb10:
-; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i32 [[LSR_IV]], 1
+; CHECK-NEXT: [[LSR_IV_NEXT1]] = add nuw nsw i64 [[LSR_IV]], 1
+; CHECK-NEXT: [[LSR_IV_NEXT:%.*]] = trunc i64 [[LSR_IV]] to i32
; CHECK-NEXT: [[ICMP12:%.*]] = icmp ult i32 [[LSR_IV_NEXT]], 1210
; CHECK-NEXT: br i1 [[ICMP12]], label [[BB3]], label [[BB13:%.*]]
; CHECK: bb13:
-; CHECK-NEXT: ret i64 [[ZEXT]]
+; CHECK-NEXT: [[AND:%.*]] = add i64 [[LSR_IV_NEXT1]], 65534
+; CHECK-NEXT: ret i64 [[AND]]
;
bb2:
br label %bb3
diff --git a/llvm/test/Transforms/LoopUnroll/AArch64/apple-unrolling.ll b/llvm/test/Transforms/LoopUnroll/AArch64/apple-unrolling.ll
index 10b22974080dc..9078db419e254 100644
--- a/llvm/test/Transforms/LoopUnroll/AArch64/apple-unrolling.ll
+++ b/llvm/test/Transforms/LoopUnroll/AArch64/apple-unrolling.ll
@@ -71,7 +71,7 @@ define void @small_load_store_loop(ptr %src, ptr %dst, i64 %N, i64 %scale) {
; APPLE-NEXT: [[GEP_DST_7:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV_NEXT_6]]
; APPLE-NEXT: store float [[L_7]], ptr [[GEP_DST_7]], align 4
; APPLE-NEXT: [[IV_NEXT_7]] = add nuw nsw i64 [[IV]], 8
-; APPLE-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; APPLE-NEXT: [[NITER_NEXT_7]] = add nuw i64 [[NITER]], 8
; APPLE-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; APPLE-NEXT: br i1 [[NITER_NCMP_7]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]]
; APPLE: [[EXIT_UNR_LCSSA]]:
@@ -126,7 +126,7 @@ define void @small_load_store_loop(ptr %src, ptr %dst, i64 %N, i64 %scale) {
; OTHER-NEXT: [[GEP_DST_1:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV_NEXT]]
; OTHER-NEXT: store float [[L_1]], ptr [[GEP_DST_1]], align 4
; OTHER-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; OTHER-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; OTHER-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; OTHER-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; OTHER-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]]
; OTHER: [[EXIT_UNR_LCSSA]]:
@@ -194,7 +194,7 @@ define void @load_op_store_loop(ptr %src, ptr %dst, i64 %N, i64 %scale, float %k
; APPLE-NEXT: [[GEP_DST_1:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV_NEXT]]
; APPLE-NEXT: store float [[O_1]], ptr [[GEP_DST_1]], align 4
; APPLE-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; APPLE-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; APPLE-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; APPLE-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; APPLE-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]]
; APPLE: [[EXIT_UNR_LCSSA]]:
@@ -244,7 +244,7 @@ define void @load_op_store_loop(ptr %src, ptr %dst, i64 %N, i64 %scale, float %k
; OTHER-NEXT: [[GEP_DST_1:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV_NEXT]]
; OTHER-NEXT: store float [[O_1]], ptr [[GEP_DST_1]], align 4
; OTHER-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; OTHER-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; OTHER-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; OTHER-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; OTHER-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]]
; OTHER: [[EXIT_UNR_LCSSA]]:
@@ -313,7 +313,7 @@ define void @load_op_store_loop_multiblock(ptr %src, ptr %dst, i64 %N, i64 %scal
; APPLE: [[EXIT]]:
; APPLE-NEXT: ret void
;
-; ; OTHER-LABEL: define void @load_op_store_loop_multiblock(
+; OTHER-LABEL: define void @load_op_store_loop_multiblock(
; OTHER-SAME: ptr [[SRC:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]], i64 [[SCALE:%.*]], float [[K:%.*]]) #[[ATTR0]] {
; OTHER-NEXT: [[ENTRY:.*]]:
; OTHER-NEXT: br label %[[LOOP:.*]]
@@ -321,12 +321,12 @@ define void @load_op_store_loop_multiblock(ptr %src, ptr %dst, i64 %N, i64 %scal
; OTHER-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOPCONT:.*]] ]
; OTHER-NEXT: [[SCALED_IV:%.*]] = mul nuw nsw i64 [[IV]], [[SCALE]]
; OTHER-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds float, ptr [[SRC]], i64 [[SCALED_IV]]
-; OTHER-NEXT: [[L:%.*]] = load float, ptr [[GEP_SRC]], align 4
+; OTHER-NEXT: [[L1:%.*]] = load float, ptr [[GEP_SRC]], align 4
; OTHER-NEXT: [[AND:%.*]] = and i64 [[IV]], 1
; OTHER-NEXT: [[ODD:%.*]] = icmp eq i64 [[AND]], 1
; OTHER-NEXT: br i1 [[ODD]], label %[[LOOPODD:.*]], label %[[LOOPCONT]]
; OTHER: [[LOOPCONT]]:
-; OTHER-NEXT: [[D:%.*]] = phi float [ [[L2:%.*]], %[[LOOPODD]] ], [ [[L]], %[[LOOP]] ]
+; OTHER-NEXT: [[D:%.*]] = phi float [ [[L2:%.*]], %[[LOOPODD]] ], [ [[L1]], %[[LOOP]] ]
; OTHER-NEXT: [[O:%.*]] = fadd float [[D]], [[K]]
; OTHER-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV]]
; OTHER-NEXT: store float [[O]], ptr [[GEP_DST]], align 4
@@ -334,7 +334,7 @@ define void @load_op_store_loop_multiblock(ptr %src, ptr %dst, i64 %N, i64 %scal
; OTHER-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; OTHER-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]
; OTHER: [[LOOPODD]]:
-; OTHER-NEXT: [[L2]] = fneg float [[L]]
+; OTHER-NEXT: [[L2]] = fneg float [[L1]]
; OTHER-NEXT: br label %[[LOOPCONT]]
; OTHER: [[EXIT]]:
; OTHER-NEXT: ret void
@@ -579,7 +579,7 @@ define void @early_continue_dep_on_load_large(ptr %p.1, ptr %p.2, i64 %N, i32 %x
; APPLE-NEXT: br label %[[LOOP_LATCH_3]]
; APPLE: [[LOOP_LATCH_3]]:
; APPLE-NEXT: [[IV_NEXT_3]] = add nuw nsw i64 [[IV]], 4
-; APPLE-NEXT: [[NITER_NEXT_3]] = add i64 [[NITER]], 4
+; APPLE-NEXT: [[NITER_NEXT_3]] = add nuw i64 [[NITER]], 4
; APPLE-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i64 [[NITER_NEXT_3]], [[UNROLL_ITER]]
; APPLE-NEXT: br i1 [[NITER_NCMP_3]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP_HEADER]]
; APPLE: [[EXIT_UNR_LCSSA]]:
@@ -1129,7 +1129,7 @@ define i32 @test_add_reduction_runtime(ptr %a, i64 noundef %n) {
; OTHER-NEXT: [[TMP5:%.*]] = load i32, ptr [[GEP_A_3]], align 2
; OTHER-NEXT: [[RDX_NEXT_3]] = add nuw nsw i32 [[RDX_NEXT_2]], [[TMP5]]
; OTHER-NEXT: [[IV_NEXT_3]] = add nuw nsw i64 [[IV]], 4
-; OTHER-NEXT: [[NITER_NEXT_3]] = add i64 [[NITER]], 4
+; OTHER-NEXT: [[NITER_NEXT_3]] = add nuw i64 [[NITER]], 4
; OTHER-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i64 [[NITER_NEXT_3]], [[UNROLL_ITER]]
; OTHER-NEXT: br i1 [[NITER_NCMP_3]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]]
; OTHER: [[EXIT_UNR_LCSSA]]:
diff --git a/llvm/test/Transforms/LoopUnroll/AArch64/runtime-unroll-generic.ll b/llvm/test/Transforms/LoopUnroll/AArch64/runtime-unroll-generic.ll
index 3411c997747d9..6ddb876f6ca53 100644
--- a/llvm/test/Transforms/LoopUnroll/AArch64/runtime-unroll-generic.ll
+++ b/llvm/test/Transforms/LoopUnroll/AArch64/runtime-unroll-generic.ll
@@ -67,7 +67,7 @@ define void @runtime_unroll_generic(i32 %arg_0, ptr %arg_1, ptr %arg_2, ptr %arg
; CHECK-A55-NEXT: [[ADD21_3:%.*]] = add nsw i32 [[MUL16_3]], [[TMP12]]
; CHECK-A55-NEXT: store i32 [[ADD21_3]], ptr [[ARRAYIDX20_3]], align 4
; CHECK-A55-NEXT: [[INDVARS_IV_NEXT_3]] = add nuw nsw i64 [[INDVARS_IV]], 4
-; CHECK-A55-NEXT: [[NITER_NEXT_3]] = add i64 [[NITER]], 4
+; CHECK-A55-NEXT: [[NITER_NEXT_3]] = add nuw i64 [[NITER]], 4
; CHECK-A55-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i64 [[NITER_NEXT_3]], [[UNROLL_ITER]]
; CHECK-A55-NEXT: br i1 [[NITER_NCMP_3]], label [[FOR_END_LOOPEXIT_UNR_LCSSA1:%.*]], label [[FOR_BODY6]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK-A55: for.end.loopexit.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/AArch64/vector.ll b/llvm/test/Transforms/LoopUnroll/AArch64/vector.ll
index 2bafa08a81c38..313dbb0dbae85 100644
--- a/llvm/test/Transforms/LoopUnroll/AArch64/vector.ll
+++ b/llvm/test/Transforms/LoopUnroll/AArch64/vector.ll
@@ -16,7 +16,7 @@ define void @reverse(ptr %dst, ptr %src, i64 %len) {
; APPLE: [[FOR_BODY]]:
; APPLE-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[IV_NEXT_7:%.*]], %[[FOR_BODY]] ]
; APPLE-NEXT: [[NITER:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[NITER_NEXT_7:%.*]], %[[FOR_BODY]] ]
-; APPLE-NEXT: [[TMP2:%.*]] = sub nsw i64 [[LEN]], [[IV]]
+; APPLE-NEXT: [[TMP2:%.*]] = sub nuw nsw i64 [[LEN]], [[IV]]
; APPLE-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds <4 x float>, ptr [[SRC]], i64 [[TMP2]]
; APPLE-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr [[ARRAYIDX]], align 16
; APPLE-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw <4 x float>, ptr [[DST]], i64 [[IV]]
@@ -64,7 +64,7 @@ define void @reverse(ptr %dst, ptr %src, i64 %len) {
; APPLE-NEXT: [[ARRAYIDX2_7:%.*]] = getelementptr inbounds nuw <4 x float>, ptr [[DST]], i64 [[IV_NEXT_6]]
; APPLE-NEXT: store <4 x float> [[TMP17]], ptr [[ARRAYIDX2_7]], align 16
; APPLE-NEXT: [[IV_NEXT_7]] = add nuw nsw i64 [[IV]], 8
-; APPLE-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; APPLE-NEXT: [[NITER_NEXT_7]] = add nuw i64 [[NITER]], 8
; APPLE-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; APPLE-NEXT: br i1 [[NITER_NCMP_7]], label %[[EXIT_UNR_LCSSA:.*]], label %[[FOR_BODY]]
; APPLE: [[EXIT_UNR_LCSSA]]:
@@ -107,7 +107,7 @@ define void @reverse(ptr %dst, ptr %src, i64 %len) {
; CORTEXA55: [[FOR_BODY]]:
; CORTEXA55-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[IV_NEXT_3:%.*]], %[[FOR_BODY]] ]
; CORTEXA55-NEXT: [[NITER:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[NITER_NEXT_3:%.*]], %[[FOR_BODY]] ]
-; CORTEXA55-NEXT: [[TMP2:%.*]] = sub nsw i64 [[LEN]], [[IV]]
+; CORTEXA55-NEXT: [[TMP2:%.*]] = sub nuw nsw i64 [[LEN]], [[IV]]
; CORTEXA55-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds <4 x float>, ptr [[SRC]], i64 [[TMP2]]
; CORTEXA55-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr [[ARRAYIDX]], align 16
; CORTEXA55-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw <4 x float>, ptr [[DST]], i64 [[IV]]
@@ -131,7 +131,7 @@ define void @reverse(ptr %dst, ptr %src, i64 %len) {
; CORTEXA55-NEXT: [[ARRAYIDX2_3:%.*]] = getelementptr inbounds nuw <4 x float>, ptr [[DST]], i64 [[IV_NEXT_2]]
; CORTEXA55-NEXT: store <4 x float> [[TMP9]], ptr [[ARRAYIDX2_3]], align 16
; CORTEXA55-NEXT: [[IV_NEXT_3]] = add nuw nsw i64 [[IV]], 4
-; CORTEXA55-NEXT: [[NITER_NEXT_3]] = add i64 [[NITER]], 4
+; CORTEXA55-NEXT: [[NITER_NEXT_3]] = add nuw i64 [[NITER]], 4
; CORTEXA55-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i64 [[NITER_NEXT_3]], [[UNROLL_ITER]]
; CORTEXA55-NEXT: br i1 [[NITER_NCMP_3]], label %[[EXIT_UNR_LCSSA:.*]], label %[[FOR_BODY]]
; CORTEXA55: [[EXIT_UNR_LCSSA]]:
diff --git a/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-convergent-uniform-tripcount.ll b/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-convergent-uniform-tripcount.ll
index d904fba1402d4..2750899e64815 100644
--- a/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-convergent-uniform-tripcount.ll
+++ b/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-convergent-uniform-tripcount.ll
@@ -77,8 +77,8 @@ define amdgpu_kernel void @runtime_unroll_uniform_trip_count(ptr addrspace(1) no
; CHECK-NEXT: call void @llvm.amdgcn.s.barrier() #4
; CHECK-NEXT: %add.7 = add i32 %load.7, %add.6
; CHECK-NEXT: store i32 %add.7, ptr addrspace(1) %arrayidx.out.7, align 4
-; CHECK-NEXT: %indvars.iv.next.7 = add i32 %indvars.iv, 8
-; CHECK-NEXT: %niter.next.7 = add i32 %niter, 8
+; CHECK-NEXT: %indvars.iv.next.7 = add nuw i32 %indvars.iv, 8
+; CHECK-NEXT: %niter.next.7 = add nuw i32 %niter, 8
; CHECK-NEXT: %niter.ncmp.7 = icmp eq i32 %niter.next.7, %unroll_iter
; CHECK-NEXT: br i1 %niter.ncmp.7, label %for.end.unr-lcssa, label %for.body
; CHECK: for.end.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/ARM/multi-blocks.ll b/llvm/test/Transforms/LoopUnroll/ARM/multi-blocks.ll
index 066a8b65bfce8..d2ccf8ee93db2 100644
--- a/llvm/test/Transforms/LoopUnroll/ARM/multi-blocks.ll
+++ b/llvm/test/Transforms/LoopUnroll/ARM/multi-blocks.ll
@@ -547,7 +547,7 @@ define void @test_four_blocks(ptr nocapture %Output, ptr nocapture readonly %Con
; CHECK: for.inc.3:
; CHECK-NEXT: [[TEMP_1_3]] = phi i32 [ [[ADD_3]], [[IF_THEN_3]] ], [ [[SUB13_3]], [[IF_ELSE_3]] ]
; CHECK-NEXT: [[INC_3]] = add nuw i32 [[J_027]], 4
-; CHECK-NEXT: [[NITER_NEXT_3]] = add i32 [[NITER]], 4
+; CHECK-NEXT: [[NITER_NEXT_3]] = add nuw i32 [[NITER]], 4
; CHECK-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i32 [[NITER_NEXT_3]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_3]], label [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]], label [[FOR_BODY]]
;
diff --git a/llvm/test/Transforms/LoopUnroll/NVPTX/unroll-convergent-uniform-tripcount.ll b/llvm/test/Transforms/LoopUnroll/NVPTX/unroll-convergent-uniform-tripcount.ll
index 4d7b96cfe5840..511063a980930 100644
--- a/llvm/test/Transforms/LoopUnroll/NVPTX/unroll-convergent-uniform-tripcount.ll
+++ b/llvm/test/Transforms/LoopUnroll/NVPTX/unroll-convergent-uniform-tripcount.ll
@@ -49,8 +49,8 @@ define void @runtime_unroll_uniform_trip_count(ptr %out, ptr %in, i32 %n) {
; CHECK-NEXT: %shfl.3 = call i32 @llvm.nvvm.shfl.down.i32(i32 %add.2, i32 1, i32 31)
; CHECK-NEXT: %add.3 = add i32 %load.3, %shfl.3
; CHECK-NEXT: store i32 %add.3, ptr %arrayidx.out.3, align 4
-; CHECK-NEXT: %indvars.iv.next.3 = add i32 %indvars.iv, 4
-; CHECK-NEXT: %niter.next.3 = add i32 %niter, 4
+; CHECK-NEXT: %indvars.iv.next.3 = add nuw i32 %indvars.iv, 4
+; CHECK-NEXT: %niter.next.3 = add nuw i32 %niter, 4
; CHECK-NEXT: %niter.ncmp.3 = icmp eq i32 %niter.next.3, %unroll_iter
; CHECK-NEXT: br i1 %niter.ncmp.3, label %for.end.unr-lcssa, label %for.body
; CHECK: for.end.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors-inseltpoison.ll b/llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors-inseltpoison.ll
index 5d08e9dea0889..64dd9ec246223 100644
--- a/llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors-inseltpoison.ll
+++ b/llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors-inseltpoison.ll
@@ -48,7 +48,7 @@ define ptr @f(ptr returned %s, i32 zeroext %x, i32 signext %k) local_unnamed_add
; CHECK-NEXT: store <16 x i8> [[TMP12]], ptr [[TMP13]], align 1
; CHECK-NEXT: [[INDEX_NEXT_1]] = add i64 [[INDEX]], 32
; CHECK-NEXT: [[VEC_IND_NEXT13_1]] = add <16 x i32> [[VEC_IND12]], splat (i32 32)
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[MIDDLE_BLOCK_UNR_LCSSA_LOOPEXIT:%.*]], label [[VECTOR_BODY]]
; CHECK: middle.block.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors.ll b/llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors.ll
index 03277fc8bb644..76b2c09183c3b 100644
--- a/llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors.ll
+++ b/llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors.ll
@@ -48,7 +48,7 @@ define ptr @f(ptr returned %s, i32 zeroext %x, i32 signext %k) local_unnamed_add
; CHECK-NEXT: store <16 x i8> [[TMP12]], ptr [[TMP13]], align 1
; CHECK-NEXT: [[INDEX_NEXT_1]] = add i64 [[INDEX]], 32
; CHECK-NEXT: [[VEC_IND_NEXT13_1]] = add <16 x i32> [[VEC_IND12]], splat (i32 32)
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[MIDDLE_BLOCK_UNR_LCSSA_LOOPEXIT:%.*]], label [[VECTOR_BODY]]
; CHECK: middle.block.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/RISCV/vector.ll b/llvm/test/Transforms/LoopUnroll/RISCV/vector.ll
index 2c834748c79d7..f6c8f5ef87876 100644
--- a/llvm/test/Transforms/LoopUnroll/RISCV/vector.ll
+++ b/llvm/test/Transforms/LoopUnroll/RISCV/vector.ll
@@ -33,7 +33,7 @@ define void @reverse(ptr %dst, ptr %src, i64 %len) {
; SIFIVE: [[FOR_BODY]]:
; SIFIVE-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[IV_NEXT_7:%.*]], %[[FOR_BODY]] ]
; SIFIVE-NEXT: [[NITER:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[NITER_NEXT_7:%.*]], %[[FOR_BODY]] ]
-; SIFIVE-NEXT: [[TMP0:%.*]] = sub nsw i64 [[LEN]], [[IV]]
+; SIFIVE-NEXT: [[TMP0:%.*]] = sub nuw nsw i64 [[LEN]], [[IV]]
; SIFIVE-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds <4 x float>, ptr [[SRC]], i64 [[TMP0]]
; SIFIVE-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[ARRAYIDX]], align 16
; SIFIVE-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw <4 x float>, ptr [[DST]], i64 [[IV]]
@@ -81,7 +81,7 @@ define void @reverse(ptr %dst, ptr %src, i64 %len) {
; SIFIVE-NEXT: [[ARRAYIDX2_7:%.*]] = getelementptr inbounds nuw <4 x float>, ptr [[DST]], i64 [[IV_NEXT_6]]
; SIFIVE-NEXT: store <4 x float> [[TMP17]], ptr [[ARRAYIDX2_7]], align 16
; SIFIVE-NEXT: [[IV_NEXT_7]] = add nuw nsw i64 [[IV]], 8
-; SIFIVE-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; SIFIVE-NEXT: [[NITER_NEXT_7]] = add nuw i64 [[NITER]], 8
; SIFIVE-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; SIFIVE-NEXT: br i1 [[NITER_NCMP_7]], label %[[EXIT_UNR_LCSSA:.*]], label %[[FOR_BODY]]
; SIFIVE: [[EXIT_UNR_LCSSA]]:
diff --git a/llvm/test/Transforms/LoopUnroll/convergent.controlled.ll b/llvm/test/Transforms/LoopUnroll/convergent.controlled.ll
index 5dc613e733f00..b1587269387fe 100644
--- a/llvm/test/Transforms/LoopUnroll/convergent.controlled.ll
+++ b/llvm/test/Transforms/LoopUnroll/convergent.controlled.ll
@@ -67,7 +67,7 @@ define i32 @runtime_unroll(i32 %n) {
; CHECK-NEXT: br label [[A_3]]
; CHECK: a.3:
; CHECK-NEXT: call void @f() [ "convergencectrl"(token [[TOK_LOOP]]) ]
-; CHECK-NEXT: [[INC_3]] = add nsw i32 [[X_0]], 4
+; CHECK-NEXT: [[INC_3]] = add nuw nsw i32 [[X_0]], 4
; CHECK-NEXT: [[EXITCOND_3:%.*]] = icmp eq i32 [[INC_3]], [[LOOP_CTL]]
; CHECK-NEXT: br i1 [[EXITCOND_3]], label [[EXIT:%.*]], label [[L3]]
; CHECK: exit:
@@ -129,7 +129,7 @@ define i32 @pragma_unroll(i32 %n) {
; CHECK-NEXT: br label [[A_7]]
; CHECK: a.7:
; CHECK-NEXT: call void @f() [ "convergencectrl"(token [[TOK_LOOP]]) ]
-; CHECK-NEXT: [[INC_7]] = add nsw i32 [[X_0]], 8
+; CHECK-NEXT: [[INC_7]] = add nuw nsw i32 [[X_0]], 8
; CHECK-NEXT: [[EXITCOND_7:%.*]] = icmp eq i32 [[INC_7]], [[LOOP_CTL]]
; CHECK-NEXT: br i1 [[EXITCOND_7]], label [[EXIT:%.*]], label [[L3]], !llvm.loop [[LOOP2:![0-9]+]]
; CHECK: exit:
@@ -202,7 +202,7 @@ define i32 @pragma_unroll_divisible_trip_multiple(i32 %n) {
; CHECK-NEXT: [[TOK_LOOP:%.*]] = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token [[ANCHOR]]) ]
; CHECK-NEXT: call void @f() [ "convergencectrl"(token [[TOK_LOOP]]) ]
; CHECK-NEXT: call void @f() [ "convergencectrl"(token [[TOK_LOOP]]) ]
-; CHECK-NEXT: [[INC_1]] = add nsw i32 [[X_0]], 2
+; CHECK-NEXT: [[INC_1]] = add nuw nsw i32 [[X_0]], 2
; CHECK-NEXT: [[EXITCOND_1:%.*]] = icmp eq i32 [[INC_1]], [[LOOP_CTL]]
; CHECK-NEXT: br i1 [[EXITCOND_1]], label [[EXIT:%.*]], label [[L3]], !llvm.loop [[LOOP7:![0-9]+]]
; CHECK: exit:
@@ -313,8 +313,8 @@ define i32 @pragma_unroll_with_remainder(i32 %n) {
; CHECK-NEXT: call void @f() [ "convergencectrl"(token [[TOK_LOOP]]) ]
; CHECK-NEXT: [[TOK_LOOP_1:%.*]] = call token @llvm.experimental.convergence.anchor()
; CHECK-NEXT: call void @f() [ "convergencectrl"(token [[TOK_LOOP_1]]) ]
-; CHECK-NEXT: [[INC_1]] = add nsw i32 [[X_0]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i32 [[NITER]], 2
+; CHECK-NEXT: [[INC_1]] = add nuw nsw i32 [[X_0]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i32 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i32 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[EXIT_UNR_LCSSA:%.*]], label [[L3]], !llvm.loop [[LOOP8:![0-9]+]]
; CHECK: exit.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/expensive-tripcount.ll b/llvm/test/Transforms/LoopUnroll/expensive-tripcount.ll
index d52d6ef1b60f2..8c4b19b9c7007 100644
--- a/llvm/test/Transforms/LoopUnroll/expensive-tripcount.ll
+++ b/llvm/test/Transforms/LoopUnroll/expensive-tripcount.ll
@@ -43,7 +43,7 @@ define dso_local void @complex_loop_unroll(i64 noundef %input_offset, i64 nounde
; CHECK-NEXT: [[INDVARS_IV_NEXT_6:%.*]] = add nsw i64 [[INDVARS_IV_NEXT_5]], [[STEP]]
; CHECK-NEXT: [[ADD_7]] = add i64 [[ADD_6]], [[INDVARS_IV_NEXT_6]]
; CHECK-NEXT: [[INDVARS_IV_NEXT_7]] = add nsw i64 [[INDVARS_IV_NEXT_6]], [[STEP]]
-; CHECK-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; CHECK-NEXT: [[NITER_NEXT_7]] = add nuw i64 [[NITER]], 8
; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp ne i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label %[[FOR_BODY]], label %[[FOR_END14_UNR_LCSSA:.*]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: [[FOR_END14_UNR_LCSSA]]:
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-exit-phi-scev-invalidation.ll b/llvm/test/Transforms/LoopUnroll/runtime-exit-phi-scev-invalidation.ll
index 047360178aa06..e5a8c5b75b9e8 100644
--- a/llvm/test/Transforms/LoopUnroll/runtime-exit-phi-scev-invalidation.ll
+++ b/llvm/test/Transforms/LoopUnroll/runtime-exit-phi-scev-invalidation.ll
@@ -60,7 +60,7 @@ define void @pr56282() {
; CHECK-NEXT: [[C_1_7:%.*]] = icmp ugt i32 [[V_7]], 0
; CHECK-NEXT: br i1 [[C_1_7]], label [[INNER_1_LATCH_7]], label [[EXIT_DEOPT_LOOPEXIT]]
; CHECK: inner.1.latch.7:
-; CHECK-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; CHECK-NEXT: [[NITER_NEXT_7]] = add nuw i64 [[NITER]], 8
; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp ne i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label [[INNER_1_HEADER]], label [[OUTER_MIDDLE_UNR_LCSSA:%.*]]
; CHECK: outer.middle.unr-lcssa:
@@ -188,7 +188,7 @@ define void @pr56286(i64 %x, ptr %src, ptr %dst, ptr %ptr.src) !prof !0 {
; CHECK-NEXT: [[L_1_LCSSA_UNR:%.*]] = phi i32 [ poison, [[OUTER_HEADER]] ], [ [[L_1_LCSSA_UNR_PH]], [[INNER_1_HEADER_PROL_LOOPEXIT_UNR_LCSSA]] ]
; CHECK-NEXT: [[INNER_1_IV_UNR:%.*]] = phi i64 [ [[X]], [[OUTER_HEADER]] ], [ [[INNER_1_IV_UNR_PH]], [[INNER_1_HEADER_PROL_LOOPEXIT_UNR_LCSSA]] ]
; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 7
-; CHECK-NEXT: br i1 [[TMP4]], label [[OUTER_MIDDLE:%.*]], label [[OUTER_HEADER_NEW:%.*]], !prof [[PROF6:![0-9]+]]
+; CHECK-NEXT: br i1 [[TMP4]], label [[OUTER_MIDDLE:%.*]], label [[OUTER_HEADER_NEW:%.*]], !prof [[PROF3]]
; CHECK: outer.header.new:
; CHECK-NEXT: br label [[INNER_1_HEADER:%.*]]
; CHECK: inner.1.header:
@@ -232,7 +232,7 @@ define void @pr56286(i64 %x, ptr %src, ptr %dst, ptr %ptr.src) !prof !0 {
; CHECK-NEXT: store i32 [[L_1_7]], ptr [[DST]], align 8
; CHECK-NEXT: [[INNER_1_IV_NEXT_7]] = add i64 [[INNER_1_IV]], 8
; CHECK-NEXT: [[CMP_2_7:%.*]] = icmp sgt i64 [[INNER_1_IV_NEXT_6]], 0
-; CHECK-NEXT: br i1 [[CMP_2_7]], label [[OUTER_MIDDLE_UNR_LCSSA:%.*]], label [[INNER_1_HEADER]], !prof [[PROF7:![0-9]+]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK-NEXT: br i1 [[CMP_2_7]], label [[OUTER_MIDDLE_UNR_LCSSA:%.*]], label [[INNER_1_HEADER]], !prof [[PROF6:![0-9]+]], !llvm.loop [[LOOP7:![0-9]+]]
; CHECK: outer.middle.unr-lcssa:
; CHECK-NEXT: [[L_1_LCSSA_PH:%.*]] = phi i32 [ [[L_1_7]], [[INNER_1_LATCH_7]] ]
; CHECK-NEXT: br label [[OUTER_MIDDLE]]
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-i128.ll b/llvm/test/Transforms/LoopUnroll/runtime-i128.ll
index fec8626e8c59c..bbe248ea4485c 100644
--- a/llvm/test/Transforms/LoopUnroll/runtime-i128.ll
+++ b/llvm/test/Transforms/LoopUnroll/runtime-i128.ll
@@ -26,8 +26,8 @@ define void @test(i128 %n, i128 %m) {
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: call void @foo()
-; CHECK-NEXT: [[IV_NEXT_7]] = add i128 [[IV]], 8
-; CHECK-NEXT: [[NITER_NEXT_7]] = add i128 [[NITER]], 8
+; CHECK-NEXT: [[IV_NEXT_7]] = add nuw i128 [[IV]], 8
+; CHECK-NEXT: [[NITER_NEXT_7]] = add nuw i128 [[NITER]], 8
; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp ne i128 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label [[LOOP]], label [[EXIT_UNR_LCSSA:%.*]]
; CHECK: exit.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-loop-at-most-two-exits.ll b/llvm/test/Transforms/LoopUnroll/runtime-loop-at-most-two-exits.ll
index 85de29de750fa..d05698510faad 100644
--- a/llvm/test/Transforms/LoopUnroll/runtime-loop-at-most-two-exits.ll
+++ b/llvm/test/Transforms/LoopUnroll/runtime-loop-at-most-two-exits.ll
@@ -68,8 +68,8 @@ define i32 @test(ptr nocapture %a, i64 %n) {
; ENABLED-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_6]]
; ENABLED-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4
; ENABLED-NEXT: [[ADD_7]] = add nsw i32 [[TMP10]], [[ADD_6]]
-; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add i64 [[INDVARS_IV]], 8
-; ENABLED-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add nuw i64 [[INDVARS_IV]], 8
+; ENABLED-NEXT: [[NITER_NEXT_7]] = add nuw i64 [[NITER]], 8
; ENABLED-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; ENABLED-NEXT: br i1 [[NITER_NCMP_7]], label [[FOR_END_UNR_LCSSA:%.*]], label [[HEADER]]
; ENABLED: for.end.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll b/llvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll
index c9d96dfd4179d..bdc5d7a39c84b 100644
--- a/llvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll
+++ b/llvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll
@@ -76,8 +76,8 @@ define void @test1(i64 %trip, i1 %cond) {
; EPILOG: loop_exiting_bb2.7:
; EPILOG-NEXT: br i1 false, label %loop_latch.7, label %exit3.loopexit
; EPILOG: loop_latch.7:
-; EPILOG-NEXT: %iv_next.7 = add i64 %iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %iv_next.7 = add nuw i64 %iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nuw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit2.loopexit.unr-lcssa
; EPILOG: exit1.loopexit:
@@ -143,8 +143,8 @@ define void @test1(i64 %trip, i1 %cond) {
; EPILOG-BLOCK: loop_exiting_bb2.1:
; EPILOG-BLOCK-NEXT: br i1 false, label %loop_latch.1, label %exit3.loopexit
; EPILOG-BLOCK: loop_latch.1:
-; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %iv_next.1 = add nuw i64 %iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nuw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit2.loopexit.unr-lcssa, !llvm.loop !0
; EPILOG-BLOCK: exit1.loopexit:
@@ -445,8 +445,8 @@ define i32 @test2(ptr nocapture %a, i64 %n) {
; EPILOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6
; EPILOG-NEXT: %10 = load i32, ptr %arrayidx.7, align 4
; EPILOG-NEXT: %add.7 = add nsw i32 %10, %add.6
-; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %indvars.iv.next.7 = add nuw i64 %indvars.iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nuw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %for.end.unr-lcssa, label %header
; EPILOG: for.end.unr-lcssa:
@@ -525,8 +525,8 @@ define i32 @test2(ptr nocapture %a, i64 %n) {
; EPILOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; EPILOG-BLOCK-NEXT: %4 = load i32, ptr %arrayidx.1, align 4
; EPILOG-BLOCK-NEXT: %add.1 = add nsw i32 %4, %add
-; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add nuw i64 %indvars.iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nuw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %for.end.unr-lcssa, label %header, !llvm.loop !2
; EPILOG-BLOCK: for.end.unr-lcssa:
@@ -873,7 +873,7 @@ define void @test3(i64 %trip, i64 %add, i1 %arg) {
; EPILOG: loop_latch.7:
; EPILOG-NEXT: %iv_next.7 = add nuw nsw i64 %iv, 8
; EPILOG-NEXT: %sum.next.7 = add i64 %sum.next.6, %add
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %niter.next.7 = add nuw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit2.loopexit.unr-lcssa
; EPILOG: exit1.loopexit:
@@ -950,7 +950,7 @@ define void @test3(i64 %trip, i64 %add, i1 %arg) {
; EPILOG-BLOCK: loop_latch.1:
; EPILOG-BLOCK-NEXT: %iv_next.1 = add nuw nsw i64 %iv, 2
; EPILOG-BLOCK-NEXT: %sum.next.1 = add i64 %sum.next, %add
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nuw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit2.loopexit.unr-lcssa, !llvm.loop !3
; EPILOG-BLOCK: exit1.loopexit:
@@ -1281,8 +1281,8 @@ define i32 @hdr_latch_same_exit(ptr nocapture %a, i64 %n, i1 %cond) {
; EPILOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6
; EPILOG-NEXT: %10 = load i32, ptr %arrayidx.7, align 4
; EPILOG-NEXT: %add.7 = add nsw i32 %10, %add.6
-; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %indvars.iv.next.7 = add nuw i64 %indvars.iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nuw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %latchExit.unr-lcssa, label %header
; EPILOG: latchExit.unr-lcssa:
@@ -1364,8 +1364,8 @@ define i32 @hdr_latch_same_exit(ptr nocapture %a, i64 %n, i1 %cond) {
; EPILOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; EPILOG-BLOCK-NEXT: %4 = load i32, ptr %arrayidx.1, align 4
; EPILOG-BLOCK-NEXT: %add.1 = add nsw i32 %4, %add
-; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add nuw i64 %indvars.iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nuw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %latchExit.unr-lcssa, label %header, !llvm.loop !4
; EPILOG-BLOCK: latchExit.unr-lcssa:
@@ -1719,8 +1719,8 @@ define i32 @otherblock_latch_same_exit(ptr nocapture %a, i64 %n, i1 %cond) {
; EPILOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6
; EPILOG-NEXT: %10 = load i32, ptr %arrayidx.7, align 4
; EPILOG-NEXT: %add.7 = add nsw i32 %10, %add.6
-; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %indvars.iv.next.7 = add nuw i64 %indvars.iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nuw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %latchExit.unr-lcssa, label %header
; EPILOG: latchExit.unr-lcssa:
@@ -1802,8 +1802,8 @@ define i32 @otherblock_latch_same_exit(ptr nocapture %a, i64 %n, i1 %cond) {
; EPILOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; EPILOG-BLOCK-NEXT: %4 = load i32, ptr %arrayidx.1, align 4
; EPILOG-BLOCK-NEXT: %add.1 = add nsw i32 %4, %add
-; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add nuw i64 %indvars.iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nuw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %latchExit.unr-lcssa, label %header, !llvm.loop !5
; EPILOG-BLOCK: latchExit.unr-lcssa:
@@ -2158,8 +2158,8 @@ define i32 @otherblock_latch_same_exit2(ptr nocapture %a, i64 %n, i1 %cond) {
; EPILOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6
; EPILOG-NEXT: %10 = load i32, ptr %arrayidx.7, align 4
; EPILOG-NEXT: %add.7 = add nsw i32 %10, %add.6
-; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %indvars.iv.next.7 = add nuw i64 %indvars.iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nuw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %latchExit.unr-lcssa, label %header
; EPILOG: latchExit.unr-lcssa:
@@ -2241,8 +2241,8 @@ define i32 @otherblock_latch_same_exit2(ptr nocapture %a, i64 %n, i1 %cond) {
; EPILOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; EPILOG-BLOCK-NEXT: %4 = load i32, ptr %arrayidx.1, align 4
; EPILOG-BLOCK-NEXT: %add.1 = add nsw i32 %4, %add
-; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add nuw i64 %indvars.iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nuw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %latchExit.unr-lcssa, label %header, !llvm.loop !6
; EPILOG-BLOCK: latchExit.unr-lcssa:
@@ -2598,8 +2598,8 @@ define i32 @otherblock_latch_same_exit3(ptr nocapture %a, i64 %n, i1 %cond) {
; EPILOG-NEXT: %cmp.7 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.7, label %latchExit.epilog-lcssa.loopexit, label %latch.7
; EPILOG: latch.7:
-; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %indvars.iv.next.7 = add nuw i64 %indvars.iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nuw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %latchExit.unr-lcssa, label %header
; EPILOG: latchExit.unr-lcssa:
@@ -2681,8 +2681,8 @@ define i32 @otherblock_latch_same_exit3(ptr nocapture %a, i64 %n, i1 %cond) {
; EPILOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42
; EPILOG-BLOCK-NEXT: br i1 %cmp.1, label %latchExit.epilog-lcssa.loopexit, label %latch.1
; EPILOG-BLOCK: latch.1:
-; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add nuw i64 %indvars.iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nuw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %latchExit.unr-lcssa, label %header, !llvm.loop !7
; EPILOG-BLOCK: latchExit.unr-lcssa:
@@ -3298,7 +3298,7 @@ define i64 @test5(i64 %trip, i64 %add, i1 %cond) {
; EPILOG-NEXT: %niter = phi i64 [ 0, %entry.new ], [ %niter.next.7, %loop_latch.7 ]
; EPILOG-NEXT: br i1 %cond, label %loop_latch, label %loop_exiting
; EPILOG: loop_exiting:
-; EPILOG-NEXT: %ivy = add i64 %iv, %add
+; EPILOG-NEXT: %ivy = add nuw i64 %iv, %add
; EPILOG-NEXT: switch i64 %sum, label %loop_latch [
; EPILOG-NEXT: i64 24, label %exit1.loopexit
; EPILOG-NEXT: i64 42, label %exit1.loopexit
@@ -3376,7 +3376,7 @@ define i64 @test5(i64 %trip, i64 %add, i1 %cond) {
; EPILOG: loop_latch.7:
; EPILOG-NEXT: %iv_next.7 = add nuw nsw i64 %iv, 8
; EPILOG-NEXT: %sum.next.7 = add i64 %sum.next.6, %add
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %niter.next.7 = add nuw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %latchexit.unr-lcssa
; EPILOG: exit1.loopexit:
@@ -3441,7 +3441,7 @@ define i64 @test5(i64 %trip, i64 %add, i1 %cond) {
; EPILOG-BLOCK-NEXT: %niter = phi i64 [ 0, %entry.new ], [ %niter.next.1, %loop_latch.1 ]
; EPILOG-BLOCK-NEXT: br i1 %cond, label %loop_latch, label %loop_exiting
; EPILOG-BLOCK: loop_exiting:
-; EPILOG-BLOCK-NEXT: %ivy = add i64 %iv, %add
+; EPILOG-BLOCK-NEXT: %ivy = add nuw i64 %iv, %add
; EPILOG-BLOCK-NEXT: switch i64 %sum, label %loop_latch [
; EPILOG-BLOCK-NEXT: i64 24, label %exit1.loopexit
; EPILOG-BLOCK-NEXT: i64 42, label %exit1.loopexit
@@ -3459,7 +3459,7 @@ define i64 @test5(i64 %trip, i64 %add, i1 %cond) {
; EPILOG-BLOCK: loop_latch.1:
; EPILOG-BLOCK-NEXT: %iv_next.1 = add nuw nsw i64 %iv, 2
; EPILOG-BLOCK-NEXT: %sum.next.1 = add i64 %sum.next, %add
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nuw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %latchexit.unr-lcssa, !llvm.loop !9
; EPILOG-BLOCK: exit1.loopexit:
@@ -3817,8 +3817,8 @@ define i32 @test6(ptr nocapture %a, i64 %n, i1 %cond, i32 %x) {
; EPILOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6
; EPILOG-NEXT: %load.7 = load i32, ptr %arrayidx.7, align 4
; EPILOG-NEXT: %add.7 = add nsw i32 %load.7, %add.6
-; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %indvars.iv.next.7 = add nuw i64 %indvars.iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nuw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %latch_exit.unr-lcssa, label %header
; EPILOG: latch_exit.unr-lcssa:
@@ -3902,8 +3902,8 @@ define i32 @test6(ptr nocapture %a, i64 %n, i1 %cond, i32 %x) {
; EPILOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; EPILOG-BLOCK-NEXT: %load.1 = load i32, ptr %arrayidx.1, align 4
; EPILOG-BLOCK-NEXT: %add.1 = add nsw i32 %load.1, %add
-; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add nuw i64 %indvars.iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nuw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %latch_exit.unr-lcssa, label %header, !llvm.loop !10
; EPILOG-BLOCK: latch_exit.unr-lcssa:
@@ -4221,7 +4221,7 @@ define i32 @test7(i32 %arg, i32 %arg1, i32 %arg2) {
; EPILOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.7
; EPILOG: latch.7:
; EPILOG-NEXT: %add.7 = add nuw nsw i64 %i6, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %niter.next.7 = add nuw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %header, label %latchexit.unr-lcssa
; EPILOG: latchexit.unr-lcssa:
@@ -4283,7 +4283,7 @@ define i32 @test7(i32 %arg, i32 %arg1, i32 %arg2) {
; EPILOG-BLOCK-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.1
; EPILOG-BLOCK: latch.1:
; EPILOG-BLOCK-NEXT: %add.1 = add nuw nsw i64 %i6, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nuw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %header, label %latchexit.unr-lcssa, !llvm.loop !11
; EPILOG-BLOCK: latchexit.unr-lcssa:
@@ -4801,7 +4801,7 @@ define ptr addrspace(1) @test9(ptr nocapture readonly %arg, i32 %n) {
; EPILOG-NEXT: br i1 true, label %latch.7, label %innerexit.loopexit
; EPILOG: latch.7:
; EPILOG-NEXT: %iv.next.7 = add nuw nsw i64 %phi, 8
-; EPILOG-NEXT: %niter.next.7 = add i32 %niter, 8
+; EPILOG-NEXT: %niter.next.7 = add nuw i32 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i32 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %header, label %outerLatch.loopexit.unr-lcssa
; EPILOG: outerLatch.loopexit.unr-lcssa:
@@ -4873,7 +4873,7 @@ define ptr addrspace(1) @test9(ptr nocapture readonly %arg, i32 %n) {
; EPILOG-BLOCK-NEXT: br i1 true, label %latch.1, label %innerexit.loopexit.loopexit
; EPILOG-BLOCK: latch.1:
; EPILOG-BLOCK-NEXT: %iv.next.1 = add nuw nsw i64 %phi, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i32 %niter, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nuw i32 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i32 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %header, label %outerLatch.loopexit.unr-lcssa, !llvm.loop !14
; EPILOG-BLOCK: outerLatch.loopexit.unr-lcssa:
@@ -4910,7 +4910,7 @@ define ptr addrspace(1) @test9(ptr nocapture readonly %arg, i32 %n) {
; EPILOG-BLOCK-NEXT: br i1 true, label %latch.1.1, label %innerexit.loopexit.loopexit5
; EPILOG-BLOCK: latch.1.1:
; EPILOG-BLOCK-NEXT: %iv.next.1.1 = add nuw nsw i64 %phi.1, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1.1 = add i32 %niter.1, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1.1 = add nuw i32 %niter.1, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1.1 = icmp ne i32 %niter.next.1.1, %unroll_iter.1
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1.1, label %header.1, label %outerLatch.loopexit.unr-lcssa.1, !llvm.loop !14
; EPILOG-BLOCK: outerLatch.loopexit.unr-lcssa.1:
@@ -5196,8 +5196,8 @@ define void @test10(i64 %trip, i64 %trip2) {
; EPILOG-NEXT: %cmp_early.7 = icmp ne i64 %iv_next.6, %trip2
; EPILOG-NEXT: br i1 %cmp_early.7, label %loop_latch.7, label %exit1.loopexit
; EPILOG: loop_latch.7:
-; EPILOG-NEXT: %iv_next.7 = add i64 %iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %iv_next.7 = add nuw i64 %iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nuw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit2.unr-lcssa
; EPILOG: exit1.loopexit:
@@ -5254,8 +5254,8 @@ define void @test10(i64 %trip, i64 %trip2) {
; EPILOG-BLOCK-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2
; EPILOG-BLOCK-NEXT: br i1 %cmp_early.1, label %loop_latch.1, label %exit1.loopexit
; EPILOG-BLOCK: loop_latch.1:
-; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %iv_next.1 = add nuw i64 %iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nuw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit2.unr-lcssa, !llvm.loop !16
; EPILOG-BLOCK: exit1.loopexit:
@@ -5470,8 +5470,8 @@ define void @test11(i64 %trip, i1 %cond) {
; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: br i1 %cond, label %loop_latch.7, label %exit1.loopexit
; EPILOG: loop_latch.7:
-; EPILOG-NEXT: %iv_next.7 = add i64 %iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %iv_next.7 = add nuw i64 %iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nuw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit2.unr-lcssa
; EPILOG: exit1.loopexit:
@@ -5524,8 +5524,8 @@ define void @test11(i64 %trip, i1 %cond) {
; EPILOG-BLOCK-NEXT: call void @bar()
; EPILOG-BLOCK-NEXT: br i1 %cond, label %loop_latch.1, label %exit1.loopexit
; EPILOG-BLOCK: loop_latch.1:
-; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %iv_next.1 = add nuw i64 %iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nuw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit2.unr-lcssa, !llvm.loop !17
; EPILOG-BLOCK: exit1.loopexit:
@@ -5747,8 +5747,8 @@ define void @test12(i64 %trip, i64 %trip2, i1 %cond) {
; EPILOG: loop_exiting_bb2.7:
; EPILOG-NEXT: br i1 %cond, label %loop_latch.7, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.7:
-; EPILOG-NEXT: %iv_next.7 = add i64 %iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %iv_next.7 = add nuw i64 %iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nuw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit1.unr-lcssa
; EPILOG: exit1.unr-lcssa:
@@ -5809,8 +5809,8 @@ define void @test12(i64 %trip, i64 %trip2, i1 %cond) {
; EPILOG-BLOCK: loop_exiting_bb2.1:
; EPILOG-BLOCK-NEXT: br i1 %cond, label %loop_latch.1, label %exit1.epilog-lcssa.loopexit
; EPILOG-BLOCK: loop_latch.1:
-; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %iv_next.1 = add nuw i64 %iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nuw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit1.unr-lcssa, !llvm.loop !18
; EPILOG-BLOCK: exit1.unr-lcssa:
@@ -6087,8 +6087,8 @@ define void @test13(i64 %trip, i64 %trip2) {
; EPILOG-NEXT: %unknown.7 = call i1 @unknown_cond()
; EPILOG-NEXT: br i1 %unknown.7, label %loop_latch.7, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.7:
-; EPILOG-NEXT: %iv_next.7 = add i64 %iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %iv_next.7 = add nuw i64 %iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nuw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit1.unr-lcssa
; EPILOG: exit1.unr-lcssa:
@@ -6152,8 +6152,8 @@ define void @test13(i64 %trip, i64 %trip2) {
; EPILOG-BLOCK-NEXT: %unknown.1 = call i1 @unknown_cond()
; EPILOG-BLOCK-NEXT: br i1 %unknown.1, label %loop_latch.1, label %exit1.epilog-lcssa.loopexit
; EPILOG-BLOCK: loop_latch.1:
-; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %iv_next.1 = add nuw i64 %iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nuw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit1.unr-lcssa, !llvm.loop !19
; EPILOG-BLOCK: exit1.unr-lcssa:
@@ -6427,8 +6427,8 @@ define void @test14(i64 %trip, i1 %cond) {
; EPILOG-NEXT: %unknown.7 = call i1 @unknown_cond()
; EPILOG-NEXT: br i1 %unknown.7, label %loop_latch.7, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.7:
-; EPILOG-NEXT: %iv_next.7 = add i64 %iv, 8
-; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
+; EPILOG-NEXT: %iv_next.7 = add nuw i64 %iv, 8
+; EPILOG-NEXT: %niter.next.7 = add nuw i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit1.unr-lcssa
; EPILOG: exit1.unr-lcssa:
@@ -6488,8 +6488,8 @@ define void @test14(i64 %trip, i1 %cond) {
; EPILOG-BLOCK-NEXT: %unknown.1 = call i1 @unknown_cond()
; EPILOG-BLOCK-NEXT: br i1 %unknown.1, label %loop_latch.1, label %exit1.epilog-lcssa.loopexit
; EPILOG-BLOCK: loop_latch.1:
-; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
-; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
+; EPILOG-BLOCK-NEXT: %iv_next.1 = add nuw i64 %iv, 2
+; EPILOG-BLOCK-NEXT: %niter.next.1 = add nuw i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit1.unr-lcssa, !llvm.loop !20
; EPILOG-BLOCK: exit1.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-multiexit-heuristic.ll b/llvm/test/Transforms/LoopUnroll/runtime-multiexit-heuristic.ll
index 99276e44095e6..c50f40a4b84a7 100644
--- a/llvm/test/Transforms/LoopUnroll/runtime-multiexit-heuristic.ll
+++ b/llvm/test/Transforms/LoopUnroll/runtime-multiexit-heuristic.ll
@@ -91,8 +91,8 @@ define i32 @test1(ptr nocapture %a, i64 %n) {
; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr i8, ptr [[TMP16]], i64 28
; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4
; CHECK-NEXT: [[ADD_7]] = add nsw i32 [[TMP10]], [[ADD_6]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_7]] = add i64 [[INDVARS_IV]], 8
-; CHECK-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; CHECK-NEXT: [[INDVARS_IV_NEXT_7]] = add nuw i64 [[INDVARS_IV]], 8
+; CHECK-NEXT: [[NITER_NEXT_7]] = add nuw i64 [[NITER]], 8
; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label [[LATCHEXIT_UNR_LCSSA:%.*]], label [[HEADER]]
; CHECK: latchexit.unr-lcssa:
@@ -244,8 +244,8 @@ define i32 @test1(ptr nocapture %a, i64 %n) {
; ENABLED-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_6]]
; ENABLED-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4
; ENABLED-NEXT: [[ADD_7]] = add nsw i32 [[TMP10]], [[ADD_6]]
-; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add i64 [[INDVARS_IV]], 8
-; ENABLED-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add nuw i64 [[INDVARS_IV]], 8
+; ENABLED-NEXT: [[NITER_NEXT_7]] = add nuw i64 [[NITER]], 8
; ENABLED-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; ENABLED-NEXT: br i1 [[NITER_NCMP_7]], label [[LATCHEXIT_UNR_LCSSA:%.*]], label [[HEADER]]
; ENABLED: latchexit.unr-lcssa:
@@ -457,8 +457,8 @@ define i32 @test2(ptr nocapture %a, i64 %n) {
; ENABLED-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_6]]
; ENABLED-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4
; ENABLED-NEXT: [[ADD_7]] = add nsw i32 [[TMP10]], [[ADD_6]]
-; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add i64 [[INDVARS_IV]], 8
-; ENABLED-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add nuw i64 [[INDVARS_IV]], 8
+; ENABLED-NEXT: [[NITER_NEXT_7]] = add nuw i64 [[NITER]], 8
; ENABLED-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; ENABLED-NEXT: br i1 [[NITER_NCMP_7]], label [[LATCHEXIT_UNR_LCSSA:%.*]], label [[HEADER]]
; ENABLED: latchexit.unr-lcssa:
@@ -816,8 +816,8 @@ define i32 @test5(ptr nocapture %a, i64 %n) {
; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr i8, ptr [[TMP16]], i64 28
; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4
; CHECK-NEXT: [[ADD_7]] = add nsw i32 [[TMP10]], [[ADD_6]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_7]] = add i64 [[INDVARS_IV]], 8
-; CHECK-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; CHECK-NEXT: [[INDVARS_IV_NEXT_7]] = add nuw i64 [[INDVARS_IV]], 8
+; CHECK-NEXT: [[NITER_NEXT_7]] = add nuw i64 [[NITER]], 8
; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label [[LATCHEXIT_UNR_LCSSA:%.*]], label [[HEADER]]
; CHECK: latchexit.unr-lcssa:
@@ -974,8 +974,8 @@ define i32 @test5(ptr nocapture %a, i64 %n) {
; ENABLED-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_6]]
; ENABLED-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4
; ENABLED-NEXT: [[ADD_7]] = add nsw i32 [[TMP10]], [[ADD_6]]
-; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add i64 [[INDVARS_IV]], 8
-; ENABLED-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add nuw i64 [[INDVARS_IV]], 8
+; ENABLED-NEXT: [[NITER_NEXT_7]] = add nuw i64 [[NITER]], 8
; ENABLED-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; ENABLED-NEXT: br i1 [[NITER_NCMP_7]], label [[LATCHEXIT_UNR_LCSSA:%.*]], label [[HEADER]]
; ENABLED: latchexit.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-unroll-assume-no-remainder.ll b/llvm/test/Transforms/LoopUnroll/runtime-unroll-assume-no-remainder.ll
index 73f7fd37a0099..9d08260ec4a3e 100644
--- a/llvm/test/Transforms/LoopUnroll/runtime-unroll-assume-no-remainder.ll
+++ b/llvm/test/Transforms/LoopUnroll/runtime-unroll-assume-no-remainder.ll
@@ -110,7 +110,7 @@ define dso_local void @cannotProveDivisibleTC(ptr noalias nocapture %a, ptr noal
; CHECK-NEXT: [[ARRAYIDX4_1:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 [[INC]]
; CHECK-NEXT: store i8 [[ADD_1]], ptr [[ARRAYIDX4_1]], align 1
; CHECK-NEXT: [[INC_1]] = add nuw nsw i32 [[I_011]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i32 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i32 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp ne i32 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[FOR_BODY]], label [[EXIT_LOOPEXIT_UNR_LCSSA:%.*]], !llvm.loop [[LOOP2:![0-9]+]]
; CHECK: exit.loopexit.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions-min-max.ll b/llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions-min-max.ll
index 203a99e8a7ffd..0732283566236 100644
--- a/llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions-min-max.ll
+++ b/llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions-min-max.ll
@@ -25,7 +25,7 @@ define i32 @test_smin_reduction(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[GEP_A_1]], align 4
; CHECK-NEXT: [[RDX_NEXT_1]] = call i32 @llvm.smin.i32(i32 [[MIN_1]], i32 [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -92,7 +92,7 @@ define i32 @test_smax_reduction(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[GEP_A_1]], align 4
; CHECK-NEXT: [[RDX_NEXT_1]] = call i32 @llvm.smax.i32(i32 [[MAX_1]], i32 [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP2:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -164,7 +164,7 @@ define float @test_fmin_reduction(ptr %a, i64 %n) {
; CHECK-NEXT: [[CMP_1:%.*]] = fcmp olt float [[RDX_NEXT]], [[TMP3]]
; CHECK-NEXT: [[RDX_NEXT_1]] = select i1 [[CMP_1]], float [[RDX_NEXT]], float [[TMP3]]
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -233,7 +233,7 @@ define float @test_fmax_reduction(ptr %a, i64 %n) {
; CHECK-NEXT: [[CMP_1:%.*]] = fcmp ogt float [[RDX_NEXT]], [[TMP3]]
; CHECK-NEXT: [[RDX_NEXT_1]] = select i1 [[CMP_1]], float [[RDX_NEXT]], float [[TMP3]]
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP4:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -306,7 +306,7 @@ define float @test_fast_math_fmin_reduction(ptr %a, i64 %n) {
; CHECK-NEXT: [[CMP_1:%.*]] = fcmp nnan ninf nsz olt float [[MIN_1]], [[TMP3]]
; CHECK-NEXT: [[RDX_NEXT_1]] = select nsz i1 [[CMP_1]], float [[MIN_1]], float [[TMP3]]
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -378,7 +378,7 @@ define float @test_fast_math_fmax_reduction(ptr %a, i64 %n) {
; CHECK-NEXT: [[CMP_1:%.*]] = fcmp nnan ninf nsz ogt float [[MAX_1]], [[TMP3]]
; CHECK-NEXT: [[RDX_NEXT_1]] = select nsz i1 [[CMP_1]], float [[MAX_1]], float [[TMP3]]
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP6:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -452,7 +452,7 @@ define float @test_fast_math_fmin_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[GEP_A_1]], align 4
; CHECK-NEXT: [[RDX_NEXT_1]] = call nsz float @llvm.minnum.f32(float [[MIN_1]], float [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -520,7 +520,7 @@ define float @test_fast_math_fmax_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[GEP_A_1]], align 4
; CHECK-NEXT: [[RDX_NEXT_1]] = call nsz float @llvm.maxnum.f32(float [[MAX_1]], float [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP8:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -588,9 +588,9 @@ define <4 x float> @test_vector_fmax_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr [[GEP_A_1]], align 16
; CHECK-NEXT: [[RDX_NEXT_1]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[RDX_1]], <4 x float> [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
-; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP14:![0-9]+]]
+; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
; CHECK-NEXT: [[RES_PH:%.*]] = phi <4 x float> [ [[RDX_NEXT_1]], %[[LOOP]] ]
; CHECK-NEXT: [[IV_UNR:%.*]] = phi i64 [ [[IV_NEXT_1]], %[[LOOP]] ]
@@ -655,9 +655,9 @@ define <4 x float> @test_vector_fmin_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr [[GEP_A_1]], align 16
; CHECK-NEXT: [[RDX_NEXT_1]] = call <4 x float> @llvm.minnum.v4f32(<4 x float> [[RDX_1]], <4 x float> [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
-; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]
+; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP10:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
; CHECK-NEXT: [[RES_PH:%.*]] = phi <4 x float> [ [[RDX_NEXT_1]], %[[LOOP]] ]
; CHECK-NEXT: [[IV_UNR:%.*]] = phi i64 [ [[IV_NEXT_1]], %[[LOOP]] ]
@@ -722,9 +722,9 @@ define <4 x i32> @test_vector_smax_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[GEP_A_1]], align 16
; CHECK-NEXT: [[RDX_NEXT_1]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[MAX_1]], <4 x i32> [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
-; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP10:![0-9]+]]
+; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP11:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
; CHECK-NEXT: [[RES_PH:%.*]] = phi <4 x i32> [ [[RDX_NEXT_1]], %[[LOOP]] ]
; CHECK-NEXT: [[IV_UNR:%.*]] = phi i64 [ [[IV_NEXT_1]], %[[LOOP]] ]
@@ -789,9 +789,9 @@ define <4 x i32> @test_vector_smin_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[GEP_A_1]], align 16
; CHECK-NEXT: [[RDX_NEXT_1]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[MIN_1]], <4 x i32> [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
-; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP11:![0-9]+]]
+; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP12:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
; CHECK-NEXT: [[RES_PH:%.*]] = phi <4 x i32> [ [[RDX_NEXT_1]], %[[LOOP]] ]
; CHECK-NEXT: [[IV_UNR:%.*]] = phi i64 [ [[IV_NEXT_1]], %[[LOOP]] ]
@@ -856,9 +856,9 @@ define <4 x i32> @test_vector_umax_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[GEP_A_1]], align 16
; CHECK-NEXT: [[RDX_NEXT_1]] = call <4 x i32> @llvm.umax.v4i32(<4 x i32> [[MAX_1]], <4 x i32> [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
-; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP12:![0-9]+]]
+; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP13:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
; CHECK-NEXT: [[RES_PH:%.*]] = phi <4 x i32> [ [[RDX_NEXT_1]], %[[LOOP]] ]
; CHECK-NEXT: [[IV_UNR:%.*]] = phi i64 [ [[IV_NEXT_1]], %[[LOOP]] ]
@@ -923,9 +923,9 @@ define <4 x i32> @test_vector_umin_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[GEP_A_1]], align 16
; CHECK-NEXT: [[RDX_NEXT_1]] = call <4 x i32> @llvm.umin.v4i32(<4 x i32> [[MIN_1]], <4 x i32> [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
-; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP13:![0-9]+]]
+; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP14:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
; CHECK-NEXT: [[RES_PH:%.*]] = phi <4 x i32> [ [[RDX_NEXT_1]], %[[LOOP]] ]
; CHECK-NEXT: [[IV_UNR:%.*]] = phi i64 [ [[IV_NEXT_1]], %[[LOOP]] ]
@@ -994,7 +994,7 @@ define i32 @test_smin_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[GEP_A_1]], align 4
; CHECK-NEXT: [[RDX_NEXT_1]] = call i32 @llvm.smin.i32(i32 [[MIN_1]], i32 [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP15:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -1062,7 +1062,7 @@ define i32 @test_smax_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[GEP_A_1]], align 4
; CHECK-NEXT: [[RDX_NEXT_1]] = call i32 @llvm.smax.i32(i32 [[MAX_1]], i32 [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP16:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -1130,7 +1130,7 @@ define i32 @test_umin_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[GEP_A_1]], align 4
; CHECK-NEXT: [[RDX_NEXT_1]] = call i32 @llvm.umin.i32(i32 [[MIN_1]], i32 [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP17:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -1198,7 +1198,7 @@ define i32 @test_umax_reduction_intrinsic(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[GEP_A_1]], align 4
; CHECK-NEXT: [[RDX_NEXT_1]] = call i32 @llvm.umax.i32(i32 [[MAX_1]], i32 [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP18:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions.ll b/llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions.ll
index 6492e01bd1fa7..bb3b8b3f27eab 100644
--- a/llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions.ll
+++ b/llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions.ll
@@ -25,7 +25,7 @@ define i32 @test_add_reduction(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[GEP_A_1]], align 2
; CHECK-NEXT: [[RDX_NEXT_1]] = add i32 [[RDX_1]], [[TMP3]]
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -85,7 +85,7 @@ define i32 @test_add_reduction_constant_op(ptr %a, i64 %n) {
; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[NITER_NEXT_1:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[RDX_NEXT_1]] = add nuw nsw i32 [[RDX]], 2
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP2:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -168,7 +168,7 @@ define i32 @test_add_reduction_8x_unroll(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[GEP_A_7]], align 2
; CHECK-NEXT: [[RDX_NEXT_7]] = add nuw nsw i32 [[RDX_NEXT_6]], [[TMP9]]
; CHECK-NEXT: [[IV_NEXT_7]] = add nuw nsw i64 [[IV]], 8
-; CHECK-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; CHECK-NEXT: [[NITER_NEXT_7]] = add nuw i64 [[NITER]], 8
; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -244,7 +244,7 @@ define <4 x i32> @test_vector_add_reduction(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[GEP_A_1]], align 16
; CHECK-NEXT: [[RDX_NEXT_1]] = add <4 x i32> [[RDX_1]], [[TMP3]]
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -311,7 +311,7 @@ define float @test_fadd_reduction(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[GEP_A_1]], align 16
; CHECK-NEXT: [[RDX_NEXT_1]] = fadd reassoc float [[RDX_1]], [[TMP3]]
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP6:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -377,7 +377,7 @@ define float @test_fadd_no_reassoc(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[GEP_A_1]], align 16
; CHECK-NEXT: [[RDX_NEXT_1]] = fadd float [[RDX_NEXT]], [[TMP3]]
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -442,7 +442,7 @@ define float @test_fadd_other_fastmath(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[GEP_A_1]], align 16
; CHECK-NEXT: [[RDX_NEXT_1]] = fadd contract float [[RDX_NEXT]], [[TMP3]]
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP8:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -512,7 +512,7 @@ define float @test_fmuladd_reduction(ptr %a, ptr %b, i64 %n) {
; CHECK-NEXT: [[Y_1:%.*]] = load float, ptr [[GEP_B_1]], align 4
; CHECK-NEXT: [[RDX_NEXT_1]] = call reassoc nsz float @llvm.fmuladd.f32(float [[X_1]], float [[Y_1]], float [[RDX_1]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
@@ -582,7 +582,7 @@ define float @test_fmuladd_reduction_constant_op(ptr %a, i64 %n) {
; CHECK-NEXT: [[X_1:%.*]] = load float, ptr [[GEP_A_1]], align 4
; CHECK-NEXT: [[RDX_NEXT_1]] = call reassoc nnan ninf nsz float @llvm.fmuladd.f32(float [[X_1]], float 1.000000e+00, float [[RDX_NEXT]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]], !llvm.loop [[LOOP10:![0-9]+]]
; CHECK: [[EXIT_UNR_LCSSA]]:
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-unroll-remainder.ll b/llvm/test/Transforms/LoopUnroll/runtime-unroll-remainder.ll
index 3c9c3bd10a93c..662f25ad3c5bf 100644
--- a/llvm/test/Transforms/LoopUnroll/runtime-unroll-remainder.ll
+++ b/llvm/test/Transforms/LoopUnroll/runtime-unroll-remainder.ll
@@ -93,7 +93,7 @@ define i32 @unroll(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N)
; CHECK-NEXT: [[MUL_3:%.*]] = mul nsw i32 [[TMP14]], [[TMP13]]
; CHECK-NEXT: [[ADD_3]] = add nsw i32 [[MUL_3]], [[ADD_2]]
; CHECK-NEXT: [[INDVARS_IV_NEXT_3]] = add nuw nsw i64 [[INDVARS_IV]], 4
-; CHECK-NEXT: [[NITER_NEXT_3]] = add i64 [[NITER]], 4
+; CHECK-NEXT: [[NITER_NEXT_3]] = add nuw i64 [[NITER]], 4
; CHECK-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i64 [[NITER_NEXT_3]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_3]], label [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]], label [[FOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
;
diff --git a/llvm/test/Transforms/LoopUnroll/scev-invalidation-lcssa.ll b/llvm/test/Transforms/LoopUnroll/scev-invalidation-lcssa.ll
index fd07238b16421..16fccd4245bda 100644
--- a/llvm/test/Transforms/LoopUnroll/scev-invalidation-lcssa.ll
+++ b/llvm/test/Transforms/LoopUnroll/scev-invalidation-lcssa.ll
@@ -37,8 +37,8 @@ define i32 @f(i1 %cond1) #0 !prof !0 {
; CHECK: loop2:
; CHECK-NEXT: [[PHI:%.*]] = phi i64 [ 0, [[ENTRY2_NEW]] ], [ [[INC_7:%.*]], [[LOOP2]] ]
; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[ENTRY2_NEW]] ], [ [[NITER_NEXT_7:%.*]], [[LOOP2]] ]
-; CHECK-NEXT: [[INC_7]] = add i64 [[PHI]], 8
-; CHECK-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
+; CHECK-NEXT: [[INC_7]] = add nuw i64 [[PHI]], 8
+; CHECK-NEXT: [[NITER_NEXT_7]] = add nuw i64 [[NITER]], 8
; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label [[EXIT2_UNR_LCSSA:%.*]], label [[LOOP2]]
; CHECK: exit2.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/shifted-tripcount.ll b/llvm/test/Transforms/LoopUnroll/shifted-tripcount.ll
index 4f3f861d308e9..37a1d8eded593 100644
--- a/llvm/test/Transforms/LoopUnroll/shifted-tripcount.ll
+++ b/llvm/test/Transforms/LoopUnroll/shifted-tripcount.ll
@@ -17,7 +17,7 @@ define void @latch_exit(ptr nocapture %p, i64 %n) nounwind {
; CHECK-NEXT: [[MUL9:%.*]] = fmul double [[TMP8]], [[TMP4]]
; CHECK-NEXT: store double [[MUL9]], ptr [[ARRAYIDX7]], align 8
; CHECK-NEXT: [[ARRAYIDX7_1:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16]]
-; CHECK-NEXT: [[TMP16_1]] = add i64 [[I_013]], 2
+; CHECK-NEXT: [[TMP16_1]] = add nuw i64 [[I_013]], 2
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16_1]]
; CHECK-NEXT: [[TMP4_1:%.*]] = load double, ptr [[ARRAYIDX_1]], align 8
; CHECK-NEXT: [[MUL9_1:%.*]] = fmul double [[TMP4]], [[TMP4_1]]
@@ -66,7 +66,7 @@ define void @non_latch_exit(ptr nocapture %p, i64 %n) nounwind {
; CHECK-NEXT: br label [[LATCH:%.*]]
; CHECK: latch:
; CHECK-NEXT: [[ARRAYIDX7_1:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16]]
-; CHECK-NEXT: [[TMP16_1]] = add i64 [[I_013]], 2
+; CHECK-NEXT: [[TMP16_1]] = add nuw i64 [[I_013]], 2
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16_1]]
; CHECK-NEXT: [[TMP4_1:%.*]] = load double, ptr [[ARRAYIDX_1]], align 8
; CHECK-NEXT: [[MUL9_1:%.*]] = fmul double [[TMP4]], [[TMP4_1]]
diff --git a/llvm/test/Transforms/LoopUnroll/tripcount-overflow.ll b/llvm/test/Transforms/LoopUnroll/tripcount-overflow.ll
index f839c88b93e54..f055692777a43 100644
--- a/llvm/test/Transforms/LoopUnroll/tripcount-overflow.ll
+++ b/llvm/test/Transforms/LoopUnroll/tripcount-overflow.ll
@@ -25,8 +25,8 @@ define i32 @foo(i32 %N) {
; EPILOG-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY_NEW]] ], [ [[INC_1:%.*]], [[WHILE_BODY]] ]
; EPILOG-NEXT: [[NITER:%.*]] = phi i32 [ 0, [[ENTRY_NEW]] ], [ [[NITER_NEXT_1:%.*]], [[WHILE_BODY]] ]
; EPILOG-NEXT: [[INC:%.*]] = add nuw nsw i32 [[I]], 1
-; EPILOG-NEXT: [[INC_1]] = add i32 [[I]], 2
-; EPILOG-NEXT: [[NITER_NEXT_1]] = add i32 [[NITER]], 2
+; EPILOG-NEXT: [[INC_1]] = add nuw i32 [[I]], 2
+; EPILOG-NEXT: [[NITER_NEXT_1]] = add nuw i32 [[NITER]], 2
; EPILOG-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i32 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; EPILOG-NEXT: br i1 [[NITER_NCMP_1]], label [[WHILE_END_UNR_LCSSA:%.*]], label [[WHILE_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; EPILOG: while.end.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopUnroll/unroll-loads-cse.ll b/llvm/test/Transforms/LoopUnroll/unroll-loads-cse.ll
index 4ae1518cf594d..8cdfb258fc510 100644
--- a/llvm/test/Transforms/LoopUnroll/unroll-loads-cse.ll
+++ b/llvm/test/Transforms/LoopUnroll/unroll-loads-cse.ll
@@ -33,7 +33,7 @@ define void @cse_matching_load_from_previous_unrolled_iteration(ptr %src, ptr no
; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IV_NEXT]]
; CHECK-NEXT: store i64 [[MUL_1]], ptr [[GEP_DST_1]], align 8
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[EXIT_UNR_LCSSA:%.*]], label [[LOOP]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: exit.unr-lcssa:
@@ -113,7 +113,7 @@ define void @cse_different_load_types(ptr %src, ptr noalias %dst, i64 %N) {
; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IV_NEXT]]
; CHECK-NEXT: store i64 [[MUL_1]], ptr [[GEP_DST_1]], align 8
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[EXIT_UNR_LCSSA:%.*]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: exit.unr-lcssa:
@@ -194,7 +194,7 @@ define void @cse_volatile_loads(ptr %src, ptr noalias %dst, i64 %N) {
; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IV_NEXT]]
; CHECK-NEXT: store i64 [[MUL_1]], ptr [[GEP_DST_1]], align 8
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[EXIT_UNR_LCSSA:%.*]], label [[LOOP]], !llvm.loop [[LOOP4:![0-9]+]]
; CHECK: exit.unr-lcssa:
@@ -272,7 +272,7 @@ define void @cse_atomic_loads(ptr %src, ptr noalias %dst, i64 %N) {
; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IV_NEXT]]
; CHECK-NEXT: store i64 [[MUL_1]], ptr [[GEP_DST_1]], align 8
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[EXIT_UNR_LCSSA:%.*]], label [[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK: exit.unr-lcssa:
@@ -350,7 +350,7 @@ define void @cse_load_may_be_clobbered(ptr %src, ptr %dst, i64 %N) {
; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IV_NEXT]]
; CHECK-NEXT: store i64 [[MUL_1]], ptr [[GEP_DST_1]], align 8
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[EXIT_UNR_LCSSA:%.*]], label [[LOOP]], !llvm.loop [[LOOP6:![0-9]+]]
; CHECK: exit.unr-lcssa:
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll b/llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
index a9206afcacdd7..ba6c943892fee 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
@@ -151,22 +151,13 @@ define void @vector_reverse_i64(ptr nocapture noundef writeonly %A, ptr nocaptur
; RV64-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64
; RV64-NEXT: br label %[[VECTOR_SCEVCHECK:.*]]
; RV64: [[VECTOR_SCEVCHECK]]:
-; RV64-NEXT: [[TMP3:%.*]] = add nsw i64 [[TMP0]], -1
-; RV64-NEXT: [[TMP4:%.*]] = add i32 [[N]], -1
-; RV64-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP3]] to i32
-; RV64-NEXT: [[TMP6:%.*]] = sub i32 [[TMP4]], [[TMP5]]
-; RV64-NEXT: [[TMP7:%.*]] = icmp ugt i32 [[TMP6]], [[TMP4]]
-; RV64-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[TMP3]], 4294967295
-; RV64-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP9]]
-; RV64-NEXT: br i1 [[TMP8]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
-; RV64: [[VECTOR_MEMCHECK]]:
; RV64-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
; RV64-NEXT: [[TMP10:%.*]] = shl i64 [[TMP11]], 4
; RV64-NEXT: [[TMP16:%.*]] = add i64 [[TMP10]], -1
; RV64-NEXT: [[TMP14:%.*]] = sub i64 [[B1]], [[A2]]
; RV64-NEXT: [[TMP15:%.*]] = sub i64 [[TMP14]], 1
; RV64-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP15]], [[TMP16]]
-; RV64-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; RV64-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; RV64: [[VECTOR_PH]]:
; RV64-NEXT: br label %[[VECTOR_BODY:.*]]
; RV64: [[VECTOR_BODY]]:
@@ -265,16 +256,7 @@ define void @vector_reverse_i64(ptr nocapture noundef writeonly %A, ptr nocaptur
; RV64-UF2-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; RV64-UF2-NEXT: [[TMP2:%.*]] = shl nuw i64 [[TMP1]], 3
; RV64-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], [[TMP2]]
-; RV64-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; RV64-UF2: [[VECTOR_SCEVCHECK]]:
-; RV64-UF2-NEXT: [[TMP3:%.*]] = add nsw i64 [[TMP0]], -1
-; RV64-UF2-NEXT: [[TMP4:%.*]] = add i32 [[N]], -1
-; RV64-UF2-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP3]] to i32
-; RV64-UF2-NEXT: [[TMP6:%.*]] = sub i32 [[TMP4]], [[TMP5]]
-; RV64-UF2-NEXT: [[TMP7:%.*]] = icmp ugt i32 [[TMP6]], [[TMP4]]
-; RV64-UF2-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[TMP3]], 4294967295
-; RV64-UF2-NEXT: [[TMP10:%.*]] = or i1 [[TMP7]], [[TMP9]]
-; RV64-UF2-NEXT: br i1 [[TMP10]], label %[[SCALAR_PH]], label %[[VECTOR_MEMCHECK:.*]]
+; RV64-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
; RV64-UF2: [[VECTOR_MEMCHECK]]:
; RV64-UF2-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
; RV64-UF2-NEXT: [[TMP12:%.*]] = shl i64 [[TMP11]], 5
@@ -319,8 +301,8 @@ define void @vector_reverse_i64(ptr nocapture noundef writeonly %A, ptr nocaptur
; RV64-UF2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[TMP20]]
; RV64-UF2-NEXT: br i1 [[CMP_N]], label %[[FOR_COND_CLEANUP_LOOPEXIT:.*]], label %[[SCALAR_PH]]
; RV64-UF2: [[SCALAR_PH]]:
-; RV64-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP48]], %[[MIDDLE_BLOCK]] ], [ [[TMP0]], %[[FOR_BODY_PREHEADER]] ], [ [[TMP0]], %[[VECTOR_SCEVCHECK]] ], [ [[TMP0]], %[[VECTOR_MEMCHECK]] ]
-; RV64-UF2-NEXT: [[BC_RESUME_VAL4:%.*]] = phi i32 [ [[TMP21]], %[[MIDDLE_BLOCK]] ], [ [[N]], %[[FOR_BODY_PREHEADER]] ], [ [[N]], %[[VECTOR_SCEVCHECK]] ], [ [[N]], %[[VECTOR_MEMCHECK]] ]
+; RV64-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP48]], %[[MIDDLE_BLOCK]] ], [ [[TMP0]], %[[FOR_BODY_PREHEADER]] ], [ [[TMP0]], %[[VECTOR_MEMCHECK]] ]
+; RV64-UF2-NEXT: [[BC_RESUME_VAL4:%.*]] = phi i32 [ [[TMP21]], %[[MIDDLE_BLOCK]] ], [ [[N]], %[[FOR_BODY_PREHEADER]] ], [ [[N]], %[[VECTOR_MEMCHECK]] ]
; RV64-UF2-NEXT: br label %[[FOR_BODY:.*]]
; RV64-UF2: [[FOR_COND_CLEANUP_LOOPEXIT]]:
; RV64-UF2-NEXT: br label %[[FOR_COND_CLEANUP]]
@@ -366,22 +348,13 @@ define void @vector_reverse_f32(ptr nocapture noundef writeonly %A, ptr nocaptur
; RV64-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64
; RV64-NEXT: br label %[[VECTOR_SCEVCHECK:.*]]
; RV64: [[VECTOR_SCEVCHECK]]:
-; RV64-NEXT: [[TMP3:%.*]] = add nsw i64 [[TMP0]], -1
-; RV64-NEXT: [[TMP4:%.*]] = add i32 [[N]], -1
-; RV64-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP3]] to i32
-; RV64-NEXT: [[TMP6:%.*]] = sub i32 [[TMP4]], [[TMP5]]
-; RV64-NEXT: [[TMP7:%.*]] = icmp ugt i32 [[TMP6]], [[TMP4]]
-; RV64-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[TMP3]], 4294967295
-; RV64-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP9]]
-; RV64-NEXT: br i1 [[TMP8]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
-; RV64: [[VECTOR_MEMCHECK]]:
; RV64-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
; RV64-NEXT: [[TMP10:%.*]] = shl i64 [[TMP11]], 4
; RV64-NEXT: [[TMP16:%.*]] = add i64 [[TMP10]], -1
; RV64-NEXT: [[TMP14:%.*]] = sub i64 [[B1]], [[A2]]
; RV64-NEXT: [[TMP15:%.*]] = sub i64 [[TMP14]], 1
; RV64-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP15]], [[TMP16]]
-; RV64-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; RV64-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; RV64: [[VECTOR_PH]]:
; RV64-NEXT: br label %[[VECTOR_BODY:.*]]
; RV64: [[VECTOR_BODY]]:
@@ -480,16 +453,7 @@ define void @vector_reverse_f32(ptr nocapture noundef writeonly %A, ptr nocaptur
; RV64-UF2-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; RV64-UF2-NEXT: [[TMP2:%.*]] = shl nuw i64 [[TMP1]], 3
; RV64-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], [[TMP2]]
-; RV64-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; RV64-UF2: [[VECTOR_SCEVCHECK]]:
-; RV64-UF2-NEXT: [[TMP3:%.*]] = add nsw i64 [[TMP0]], -1
-; RV64-UF2-NEXT: [[TMP4:%.*]] = add i32 [[N]], -1
-; RV64-UF2-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP3]] to i32
-; RV64-UF2-NEXT: [[TMP6:%.*]] = sub i32 [[TMP4]], [[TMP5]]
-; RV64-UF2-NEXT: [[TMP7:%.*]] = icmp ugt i32 [[TMP6]], [[TMP4]]
-; RV64-UF2-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[TMP3]], 4294967295
-; RV64-UF2-NEXT: [[TMP10:%.*]] = or i1 [[TMP7]], [[TMP9]]
-; RV64-UF2-NEXT: br i1 [[TMP10]], label %[[SCALAR_PH]], label %[[VECTOR_MEMCHECK:.*]]
+; RV64-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
; RV64-UF2: [[VECTOR_MEMCHECK]]:
; RV64-UF2-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
; RV64-UF2-NEXT: [[TMP12:%.*]] = shl i64 [[TMP11]], 5
@@ -534,8 +498,8 @@ define void @vector_reverse_f32(ptr nocapture noundef writeonly %A, ptr nocaptur
; RV64-UF2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[TMP20]]
; RV64-UF2-NEXT: br i1 [[CMP_N]], label %[[FOR_COND_CLEANUP_LOOPEXIT:.*]], label %[[SCALAR_PH]]
; RV64-UF2: [[SCALAR_PH]]:
-; RV64-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP48]], %[[MIDDLE_BLOCK]] ], [ [[TMP0]], %[[FOR_BODY_PREHEADER]] ], [ [[TMP0]], %[[VECTOR_SCEVCHECK]] ], [ [[TMP0]], %[[VECTOR_MEMCHECK]] ]
-; RV64-UF2-NEXT: [[BC_RESUME_VAL4:%.*]] = phi i32 [ [[TMP21]], %[[MIDDLE_BLOCK]] ], [ [[N]], %[[FOR_BODY_PREHEADER]] ], [ [[N]], %[[VECTOR_SCEVCHECK]] ], [ [[N]], %[[VECTOR_MEMCHECK]] ]
+; RV64-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP48]], %[[MIDDLE_BLOCK]] ], [ [[TMP0]], %[[FOR_BODY_PREHEADER]] ], [ [[TMP0]], %[[VECTOR_MEMCHECK]] ]
+; RV64-UF2-NEXT: [[BC_RESUME_VAL4:%.*]] = phi i32 [ [[TMP21]], %[[MIDDLE_BLOCK]] ], [ [[N]], %[[FOR_BODY_PREHEADER]] ], [ [[N]], %[[VECTOR_MEMCHECK]] ]
; RV64-UF2-NEXT: br label %[[FOR_BODY:.*]]
; RV64-UF2: [[FOR_COND_CLEANUP_LOOPEXIT]]:
; RV64-UF2-NEXT: br label %[[FOR_COND_CLEANUP]]
diff --git a/llvm/test/Transforms/LoopVectorize/X86/scev-checks-unprofitable.ll b/llvm/test/Transforms/LoopVectorize/X86/scev-checks-unprofitable.ll
index 16e65d3f1b352..36448c760ca96 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/scev-checks-unprofitable.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/scev-checks-unprofitable.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 5
; RUN: opt -p loop-vectorize -vectorizer-min-trip-count=8 -mcpu=skylake-avx512 -S %s | FileCheck %s
target triple = "x86_64-unknown-linux-gnu"
@@ -33,10 +33,31 @@ define void @value_defined_in_loop1_used_for_trip_counts(i32 %start, i1 %c, ptr
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: br label %[[EXIT_1_LOOPEXIT1:.*]]
; CHECK: [[LOOP_2_PREHEADER]]:
+; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[IV_1]], 1
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 8
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH2:.*]]
+; CHECK: [[VECTOR_PH2]]:
+; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[TMP1]], 7
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[TMP2]]
+; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[N_VEC]] to i32
+; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[START]], [[TMP3]]
; CHECK-NEXT: br label %[[LOOP_2:.*]]
; CHECK: [[LOOP_2]]:
-; CHECK-NEXT: [[IV_2:%.*]] = phi i64 [ [[IV_2_NEXT:%.*]], %[[LOOP_2]] ], [ 0, %[[LOOP_2_PREHEADER]] ]
-; CHECK-NEXT: [[IV_3:%.*]] = phi i32 [ [[IV_3_NEXT:%.*]], %[[LOOP_2]] ], [ [[START]], %[[LOOP_2_PREHEADER]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = shl i32 [[START]], 1
+; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP6]]
+; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr [[TMP7]], align 2
+; CHECK-NEXT: br label %[[MIDDLE_BLOCK4:.*]]
+; CHECK: [[MIDDLE_BLOCK4]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP1]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT_1_LOOPEXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK4]] ], [ 0, %[[LOOP_2_PREHEADER]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL5:%.*]] = phi i32 [ [[TMP4]], %[[MIDDLE_BLOCK4]] ], [ [[START]], %[[LOOP_2_PREHEADER]] ]
+; CHECK-NEXT: br label %[[LOOP_3:.*]]
+; CHECK: [[LOOP_3]]:
+; CHECK-NEXT: [[IV_2:%.*]] = phi i64 [ [[IV_2_NEXT:%.*]], %[[LOOP_3]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
+; CHECK-NEXT: [[IV_3:%.*]] = phi i32 [ [[IV_3_NEXT:%.*]], %[[LOOP_3]] ], [ [[BC_RESUME_VAL5]], %[[SCALAR_PH]] ]
; CHECK-NEXT: [[IV_3_NEXT]] = add i32 [[IV_3]], 1
; CHECK-NEXT: [[IV_2_NEXT]] = add i64 [[IV_2]], 1
; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[IV_3]], 1
@@ -44,7 +65,7 @@ define void @value_defined_in_loop1_used_for_trip_counts(i32 %start, i1 %c, ptr
; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr i8, ptr [[DST]], i64 [[ZEXT8]]
; CHECK-NEXT: store i16 0, ptr [[GEP_DST]], align 2
; CHECK-NEXT: [[EC_2:%.*]] = icmp ult i64 [[IV_2]], [[IV_1_LCSSA]]
-; CHECK-NEXT: br i1 [[EC_2]], label %[[LOOP_2]], label %[[EXIT_1_LOOPEXIT:.*]]
+; CHECK-NEXT: br i1 [[EC_2]], label %[[LOOP_3]], label %[[EXIT_1_LOOPEXIT]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: [[EXIT_1_LOOPEXIT]]:
; CHECK-NEXT: br label %[[EXIT_1:.*]]
; CHECK: [[EXIT_1_LOOPEXIT1]]:
diff --git a/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll b/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
index 16f53642aeae8..ae4d1f5c62161 100644
--- a/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
+++ b/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
@@ -8,11 +8,10 @@ define void @pr49538() {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: br label %[[LOOP_0:.*]]
; CHECK: [[LOOP_0]]:
-; CHECK-NEXT: [[IV_0:%.*]] = phi i16 [ -1, %[[ENTRY]] ], [ [[IV_0_NEXT:%.*]], %[[LOOP_0_LATCH:.*]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[IV_0]] to i32
-; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i32 [[TMP0]], 1
-; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP1]], 4
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], %[[LOOP_0_LATCH:.*]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[IV_0:%.*]] = phi i16 [ -1, %[[ENTRY]] ], [ [[IV_0_NEXT:%.*]], %[[LOOP_0_LATCH]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[INDVAR]], 65536
+; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i32 [[TMP1]], 3
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP1]], [[N_MOD_VF]]
@@ -26,12 +25,11 @@ define void @pr49538() {
; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP1]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[CMP_N]], label %[[LOOP_0_LATCH]], label %[[SCALAR_PH]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[LOOP_0_LATCH]], label %[[SCALAR_PH:.*]]
; CHECK: [[SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i16 [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ -1, %[[LOOP_0]] ]
; CHECK-NEXT: br label %[[LOOP_1:.*]]
; CHECK: [[LOOP_1]]:
-; CHECK-NEXT: [[IV_1:%.*]] = phi i16 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP_1]] ]
+; CHECK-NEXT: [[IV_1:%.*]] = phi i16 [ [[TMP2]], %[[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP_1]] ]
; CHECK-NEXT: [[IV_1_NEXT]] = add nsw i16 [[IV_1]], 1
; CHECK-NEXT: [[I6:%.*]] = icmp eq i16 [[IV_1_NEXT]], [[IV_0]]
; CHECK-NEXT: br i1 [[I6]], label %[[LOOP_0_LATCH]], label %[[LOOP_1]], !llvm.loop [[LOOP3:![0-9]+]]
@@ -39,6 +37,7 @@ define void @pr49538() {
; CHECK-NEXT: [[I8:%.*]] = phi i16 [ 1, %[[LOOP_1]] ], [ 1, %[[MIDDLE_BLOCK]] ]
; CHECK-NEXT: [[IV_0_NEXT]] = add nsw i16 [[IV_0]], 1
; CHECK-NEXT: [[EC_0:%.*]] = icmp eq i16 [[IV_0_NEXT]], [[I8]]
+; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
; CHECK-NEXT: br i1 [[EC_0]], label %[[EXIT:.*]], label %[[LOOP_0]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/LoopVectorize/optsize.ll b/llvm/test/Transforms/LoopVectorize/optsize.ll
index 294dbbbb3a5e2..e5312113b9186 100644
--- a/llvm/test/Transforms/LoopVectorize/optsize.ll
+++ b/llvm/test/Transforms/LoopVectorize/optsize.ll
@@ -254,22 +254,15 @@ define void @pr43371(i16 %val) optsize {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
-; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i16> poison, i16 [[VAL]], i64 0
-; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i16> [[BROADCAST_SPLATINSERT]], <2 x i16> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i16> [ <i16 0, i16 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = add <2 x i16> [[BROADCAST_SPLAT]], [[VEC_IND]]
-; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32>
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr [2592 x i16], ptr @cm_array, i32 0, i32 [[TMP4]]
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[INDEX]] to i16
+; CHECK-NEXT: [[TMP1:%.*]] = add i16 [[VAL]], [[TMP0]]
+; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[TMP1]] to i32
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr [2592 x i16], ptr @cm_array, i32 0, i32 [[TMP3]]
-; CHECK-NEXT: store i16 0, ptr [[TMP5]], align 1
-; CHECK-NEXT: store i16 0, ptr [[TMP7]], align 1
+; CHECK-NEXT: store <2 x i16> zeroinitializer, ptr [[TMP7]], align 1
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
-; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i16> [[VEC_IND]], splat (i16 2)
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 756
; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
@@ -282,22 +275,15 @@ define void @pr43371(i16 %val) optsize {
; PGSO-NEXT: [[ENTRY:.*:]]
; PGSO-NEXT: br label %[[VECTOR_PH:.*]]
; PGSO: [[VECTOR_PH]]:
-; PGSO-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i16> poison, i16 [[VAL]], i64 0
-; PGSO-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i16> [[BROADCAST_SPLATINSERT]], <2 x i16> poison, <2 x i32> zeroinitializer
; PGSO-NEXT: br label %[[VECTOR_BODY:.*]]
; PGSO: [[VECTOR_BODY]]:
; PGSO-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; PGSO-NEXT: [[VEC_IND:%.*]] = phi <2 x i16> [ <i16 0, i16 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; PGSO-NEXT: [[TMP0:%.*]] = add <2 x i16> [[BROADCAST_SPLAT]], [[VEC_IND]]
-; PGSO-NEXT: [[TMP1:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32>
-; PGSO-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
-; PGSO-NEXT: [[TMP5:%.*]] = getelementptr [2592 x i16], ptr @cm_array, i32 0, i32 [[TMP4]]
-; PGSO-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
+; PGSO-NEXT: [[TMP0:%.*]] = trunc i32 [[INDEX]] to i16
+; PGSO-NEXT: [[TMP1:%.*]] = add i16 [[VAL]], [[TMP0]]
+; PGSO-NEXT: [[TMP3:%.*]] = zext i16 [[TMP1]] to i32
; PGSO-NEXT: [[TMP7:%.*]] = getelementptr [2592 x i16], ptr @cm_array, i32 0, i32 [[TMP3]]
-; PGSO-NEXT: store i16 0, ptr [[TMP5]], align 1
-; PGSO-NEXT: store i16 0, ptr [[TMP7]], align 1
+; PGSO-NEXT: store <2 x i16> zeroinitializer, ptr [[TMP7]], align 1
; PGSO-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
-; PGSO-NEXT: [[VEC_IND_NEXT]] = add <2 x i16> [[VEC_IND]], splat (i16 2)
; PGSO-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 756
; PGSO-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
; PGSO: [[MIDDLE_BLOCK]]:
@@ -310,22 +296,15 @@ define void @pr43371(i16 %val) optsize {
; NPGSO-NEXT: [[ENTRY:.*:]]
; NPGSO-NEXT: br label %[[VECTOR_PH:.*]]
; NPGSO: [[VECTOR_PH]]:
-; NPGSO-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i16> poison, i16 [[VAL]], i64 0
-; NPGSO-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i16> [[BROADCAST_SPLATINSERT]], <2 x i16> poison, <2 x i32> zeroinitializer
; NPGSO-NEXT: br label %[[VECTOR_BODY:.*]]
; NPGSO: [[VECTOR_BODY]]:
; NPGSO-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; NPGSO-NEXT: [[VEC_IND:%.*]] = phi <2 x i16> [ <i16 0, i16 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; NPGSO-NEXT: [[TMP0:%.*]] = add <2 x i16> [[BROADCAST_SPLAT]], [[VEC_IND]]
-; NPGSO-NEXT: [[TMP1:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32>
-; NPGSO-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
-; NPGSO-NEXT: [[TMP5:%.*]] = getelementptr [2592 x i16], ptr @cm_array, i32 0, i32 [[TMP4]]
-; NPGSO-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
+; NPGSO-NEXT: [[TMP0:%.*]] = trunc i32 [[INDEX]] to i16
+; NPGSO-NEXT: [[TMP1:%.*]] = add i16 [[VAL]], [[TMP0]]
+; NPGSO-NEXT: [[TMP3:%.*]] = zext i16 [[TMP1]] to i32
; NPGSO-NEXT: [[TMP7:%.*]] = getelementptr [2592 x i16], ptr @cm_array, i32 0, i32 [[TMP3]]
-; NPGSO-NEXT: store i16 0, ptr [[TMP5]], align 1
-; NPGSO-NEXT: store i16 0, ptr [[TMP7]], align 1
+; NPGSO-NEXT: store <2 x i16> zeroinitializer, ptr [[TMP7]], align 1
; NPGSO-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
-; NPGSO-NEXT: [[VEC_IND_NEXT]] = add <2 x i16> [[VEC_IND]], splat (i16 2)
; NPGSO-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 756
; NPGSO-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP19:![0-9]+]]
; NPGSO: [[MIDDLE_BLOCK]]:
@@ -361,22 +340,15 @@ define void @pr43371_pgso(i16 %val) !prof !14 {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
-; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i16> poison, i16 [[VAL]], i64 0
-; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i16> [[BROADCAST_SPLATINSERT]], <2 x i16> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i16> [ <i16 0, i16 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = add <2 x i16> [[BROADCAST_SPLAT]], [[VEC_IND]]
-; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32>
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr [2592 x i16], ptr @cm_array, i32 0, i32 [[TMP4]]
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[INDEX]] to i16
+; CHECK-NEXT: [[TMP1:%.*]] = add i16 [[VAL]], [[TMP0]]
+; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[TMP1]] to i32
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr [2592 x i16], ptr @cm_array, i32 0, i32 [[TMP3]]
-; CHECK-NEXT: store i16 0, ptr [[TMP5]], align 1
-; CHECK-NEXT: store i16 0, ptr [[TMP7]], align 1
+; CHECK-NEXT: store <2 x i16> zeroinitializer, ptr [[TMP7]], align 1
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
-; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i16> [[VEC_IND]], splat (i16 2)
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 756
; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
@@ -389,22 +361,15 @@ define void @pr43371_pgso(i16 %val) !prof !14 {
; PGSO-NEXT: [[ENTRY:.*:]]
; PGSO-NEXT: br label %[[VECTOR_PH:.*]]
; PGSO: [[VECTOR_PH]]:
-; PGSO-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i16> poison, i16 [[VAL]], i64 0
-; PGSO-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i16> [[BROADCAST_SPLATINSERT]], <2 x i16> poison, <2 x i32> zeroinitializer
; PGSO-NEXT: br label %[[VECTOR_BODY:.*]]
; PGSO: [[VECTOR_BODY]]:
; PGSO-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; PGSO-NEXT: [[VEC_IND:%.*]] = phi <2 x i16> [ <i16 0, i16 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; PGSO-NEXT: [[TMP0:%.*]] = add <2 x i16> [[BROADCAST_SPLAT]], [[VEC_IND]]
-; PGSO-NEXT: [[TMP1:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32>
-; PGSO-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
-; PGSO-NEXT: [[TMP5:%.*]] = getelementptr [2592 x i16], ptr @cm_array, i32 0, i32 [[TMP4]]
-; PGSO-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
+; PGSO-NEXT: [[TMP0:%.*]] = trunc i32 [[INDEX]] to i16
+; PGSO-NEXT: [[TMP1:%.*]] = add i16 [[VAL]], [[TMP0]]
+; PGSO-NEXT: [[TMP3:%.*]] = zext i16 [[TMP1]] to i32
; PGSO-NEXT: [[TMP7:%.*]] = getelementptr [2592 x i16], ptr @cm_array, i32 0, i32 [[TMP3]]
-; PGSO-NEXT: store i16 0, ptr [[TMP5]], align 1
-; PGSO-NEXT: store i16 0, ptr [[TMP7]], align 1
+; PGSO-NEXT: store <2 x i16> zeroinitializer, ptr [[TMP7]], align 1
; PGSO-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
-; PGSO-NEXT: [[VEC_IND_NEXT]] = add <2 x i16> [[VEC_IND]], splat (i16 2)
; PGSO-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 756
; PGSO-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]
; PGSO: [[MIDDLE_BLOCK]]:
@@ -417,13 +382,9 @@ define void @pr43371_pgso(i16 %val) !prof !14 {
; NPGSO-NEXT: [[ENTRY:.*:]]
; NPGSO-NEXT: br label %[[VECTOR_SCEVCHECK:.*]]
; NPGSO: [[VECTOR_SCEVCHECK]]:
-; NPGSO-NEXT: [[TMP0:%.*]] = add i16 [[VAL]], 755
-; NPGSO-NEXT: [[TMP4:%.*]] = icmp ult i16 [[TMP0]], [[VAL]]
-; NPGSO-NEXT: br i1 [[TMP4]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
-; NPGSO: [[VECTOR_PH]]:
; NPGSO-NEXT: br label %[[VECTOR_BODY:.*]]
; NPGSO: [[VECTOR_BODY]]:
-; NPGSO-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; NPGSO-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_SCEVCHECK]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; NPGSO-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i16
; NPGSO-NEXT: [[TMP1:%.*]] = add i16 [[VAL]], [[OFFSET_IDX]]
; NPGSO-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32
@@ -431,22 +392,11 @@ define void @pr43371_pgso(i16 %val) !prof !14 {
; NPGSO-NEXT: store <2 x i16> zeroinitializer, ptr [[TMP3]], align 1
; NPGSO-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
; NPGSO-NEXT: [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], 756
-; NPGSO-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]]
-; NPGSO: [[MIDDLE_BLOCK]]:
-; NPGSO-NEXT: br label %[[FOR_COND_CLEANUP28:.*]]
+; NPGSO-NEXT: br i1 [[TMP5]], label %[[SCALAR_PH:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]]
; NPGSO: [[SCALAR_PH]]:
; NPGSO-NEXT: br label %[[FOR_BODY29:.*]]
-; NPGSO: [[FOR_COND_CLEANUP28]]:
-; NPGSO-NEXT: unreachable
; NPGSO: [[FOR_BODY29]]:
-; NPGSO-NEXT: [[I24_0170:%.*]] = phi i16 [ 0, %[[SCALAR_PH]] ], [ [[INC37:%.*]], %[[FOR_BODY29]] ]
-; NPGSO-NEXT: [[ADD33:%.*]] = add i16 [[VAL]], [[I24_0170]]
-; NPGSO-NEXT: [[IDXPROM34:%.*]] = zext i16 [[ADD33]] to i32
-; NPGSO-NEXT: [[ARRAYIDX35:%.*]] = getelementptr [2592 x i16], ptr @cm_array, i32 0, i32 [[IDXPROM34]]
-; NPGSO-NEXT: store i16 0, ptr [[ARRAYIDX35]], align 1
-; NPGSO-NEXT: [[INC37]] = add i16 [[I24_0170]], 1
-; NPGSO-NEXT: [[CMP26:%.*]] = icmp ult i16 [[INC37]], 756
-; NPGSO-NEXT: br i1 [[CMP26]], label %[[FOR_BODY29]], label %[[FOR_COND_CLEANUP28]], !llvm.loop [[LOOP21:![0-9]+]]
+; NPGSO-NEXT: unreachable
;
; We do not want to generate SCEV predicates when optimising for size, because
; that will lead to extra code generation such as the SCEV overflow runtime
@@ -538,7 +488,7 @@ define i32 @pr45526() optsize {
; NPGSO-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; NPGSO-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)
; NPGSO-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 512
-; NPGSO-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]]
+; NPGSO-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP21:![0-9]+]]
; NPGSO: [[MIDDLE_BLOCK]]:
; NPGSO-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[VECTOR_RECUR]], <4 x i32> [[TMP1]], <4 x i32> <i32 3, i32 4, i32 5, i32 6>
; NPGSO-NEXT: [[FIRST_INACTIVE_LANE:%.*]] = call i32 @llvm.experimental.cttz.elts.i32.v4i1(<4 x i1> [[TMP0]], i1 false)
@@ -624,7 +574,7 @@ define i32 @pr45526_pgso() !prof !14 {
; NPGSO-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; NPGSO-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; NPGSO-NEXT: [[TMP1:%.*]] = icmp eq i32 [[INDEX_NEXT]], 508
-; NPGSO-NEXT: br i1 [[TMP1]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP23:![0-9]+]]
+; NPGSO-NEXT: br i1 [[TMP1]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]]
; NPGSO: [[MIDDLE_BLOCK]]:
; NPGSO-NEXT: br label %[[SCALAR_PH:.*]]
; NPGSO: [[SCALAR_PH]]:
@@ -634,7 +584,7 @@ define i32 @pr45526_pgso() !prof !14 {
; NPGSO-NEXT: [[FOR:%.*]] = phi i32 [ 508, %[[SCALAR_PH]] ], [ [[PIVPLUS1]], %[[LOOP]] ]
; NPGSO-NEXT: [[PIVPLUS1]] = add nuw nsw i32 [[PIV]], 1
; NPGSO-NEXT: [[COND:%.*]] = icmp ult i32 [[PIV]], 510
-; NPGSO-NEXT: br i1 [[COND]], label %[[LOOP]], label %[[EXIT:.*]], !llvm.loop [[LOOP24:![0-9]+]]
+; NPGSO-NEXT: br i1 [[COND]], label %[[LOOP]], label %[[EXIT:.*]], !llvm.loop [[LOOP23:![0-9]+]]
; NPGSO: [[EXIT]]:
; NPGSO-NEXT: [[FOR_LCSSA:%.*]] = phi i32 [ [[FOR]], %[[LOOP]] ]
; NPGSO-NEXT: ret i32 [[FOR_LCSSA]]
@@ -766,7 +716,7 @@ define void @stride1(ptr noalias %B, i32 %BStride) optsize {
; NPGSO-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
; NPGSO-NEXT: [[VEC_IND_NEXT]] = add <2 x i32> [[VEC_IND]], splat (i32 2)
; NPGSO-NEXT: [[TMP8:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1026
-; NPGSO-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP25:![0-9]+]]
+; NPGSO-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP24:![0-9]+]]
; NPGSO: [[MIDDLE_BLOCK]]:
; NPGSO-NEXT: br label %[[FOR_END:.*]]
; NPGSO: [[FOR_END]]:
@@ -881,7 +831,7 @@ define void @stride1_pgso(ptr noalias %B, i32 %BStride) !prof !14 {
; NPGSO-NEXT: store <2 x i16> splat (i16 42), ptr [[TMP1]], align 4
; NPGSO-NEXT: [[INDEX_NEXT]] = add nuw i32 [[TMP0]], 2
; NPGSO-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1024
-; NPGSO-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP26:![0-9]+]]
+; NPGSO-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP25:![0-9]+]]
; NPGSO: [[MIDDLE_BLOCK]]:
; NPGSO-NEXT: br label %[[SCALAR_PH]]
; NPGSO: [[SCALAR_PH]]:
@@ -894,7 +844,7 @@ define void @stride1_pgso(ptr noalias %B, i32 %BStride) !prof !14 {
; NPGSO-NEXT: store i16 42, ptr [[GEPOFB]], align 4
; NPGSO-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; NPGSO-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[IV_NEXT]], 1025
-; NPGSO-NEXT: br i1 [[EXITCOND]], label %[[FOR_END:.*]], label %[[FOR_BODY]], !llvm.loop [[LOOP27:![0-9]+]]
+; NPGSO-NEXT: br i1 [[EXITCOND]], label %[[FOR_END:.*]], label %[[FOR_BODY]], !llvm.loop [[LOOP26:![0-9]+]]
; NPGSO: [[FOR_END]]:
; NPGSO-NEXT: ret void
;
@@ -1102,11 +1052,10 @@ exit:
; NPGSO: [[LOOP18]] = distinct !{[[LOOP18]], [[META17]], [[META16]]}
; NPGSO: [[LOOP19]] = distinct !{[[LOOP19]], [[META16]], [[META17]]}
; NPGSO: [[LOOP20]] = distinct !{[[LOOP20]], [[META16]], [[META17]]}
-; NPGSO: [[LOOP21]] = distinct !{[[LOOP21]], [[META16]]}
+; NPGSO: [[LOOP21]] = distinct !{[[LOOP21]], [[META16]], [[META17]]}
; NPGSO: [[LOOP22]] = distinct !{[[LOOP22]], [[META16]], [[META17]]}
-; NPGSO: [[LOOP23]] = distinct !{[[LOOP23]], [[META16]], [[META17]]}
-; NPGSO: [[LOOP24]] = distinct !{[[LOOP24]], [[META17]], [[META16]]}
+; NPGSO: [[LOOP23]] = distinct !{[[LOOP23]], [[META17]], [[META16]]}
+; NPGSO: [[LOOP24]] = distinct !{[[LOOP24]], [[META16]], [[META17]]}
; NPGSO: [[LOOP25]] = distinct !{[[LOOP25]], [[META16]], [[META17]]}
-; NPGSO: [[LOOP26]] = distinct !{[[LOOP26]], [[META16]], [[META17]]}
-; NPGSO: [[LOOP27]] = distinct !{[[LOOP27]], [[META16]]}
+; NPGSO: [[LOOP26]] = distinct !{[[LOOP26]], [[META16]]}
;.
diff --git a/llvm/test/Transforms/LoopVersioningLICM/loopversioningLICM1.ll b/llvm/test/Transforms/LoopVersioningLICM/loopversioningLICM1.ll
index 81b207d7ebd08..17a6d295f7ddd 100644
--- a/llvm/test/Transforms/LoopVersioningLICM/loopversioningLICM1.ll
+++ b/llvm/test/Transforms/LoopVersioningLICM/loopversioningLICM1.ll
@@ -28,7 +28,7 @@ define i32 @foo(ptr nocapture %var1, ptr nocapture readnone %var2, ptr nocapture
; CHECK-NEXT: [[CMP212:%.*]] = icmp ult i32 [[J_016]], [[ITR]]
; CHECK-NEXT: br i1 [[CMP212]], label [[FOR_BODY3_LVER_CHECK:%.*]], label [[FOR_INC11]]
; CHECK: for.body3.lver.check:
-; CHECK-NEXT: [[ADD:%.*]] = add i32 [[I_015]], [[ITR]]
+; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[I_015]], [[ITR]]
; CHECK-NEXT: [[IDXPROM6:%.*]] = zext i32 [[I_015]] to i64
; CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[VAR3]], i64 [[IDXPROM6]]
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[J_016]] to i64
diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll
index bfed4b193562f..903079635b32a 100644
--- a/llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll
@@ -33,7 +33,7 @@ define void @partial_unroll_forced(i32 %N, ptr %src, ptr noalias %dst) {
; CHECK-NEXT: [[ADD_1:%.*]] = fadd <8 x half> [[L_1]], [[L_1]]
; CHECK-NEXT: store <8 x half> [[ADD_1]], ptr [[DST_IDX_1]], align 16
; CHECK-NEXT: [[INDVARS_IV_NEXT_1]] = add nuw nsw i64 [[INDVARS_IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[EXIT_LOOPEXIT_UNR_LCSSA:%.*]], label [[LOOP_LATCH]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: exit.loopexit.unr-lcssa:
@@ -107,7 +107,7 @@ define void @cse_matching_load_from_previous_unrolled_iteration(i32 %N, ptr %src
; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr [8 x i8], ptr [[DST]], i64 [[INDVARS_IV_NEXT]]
; CHECK-NEXT: store <2 x i32> [[MUL_1]], ptr [[GEP_DST_1]], align 8
; CHECK-NEXT: [[INDVARS_IV_NEXT_1]] = add nuw nsw i64 [[INDVARS_IV]], 2
-; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
+; CHECK-NEXT: [[NITER_NEXT_1]] = add nuw i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[EXIT_LOOPEXIT_UNR_LCSSA:%.*]], label [[LOOP_LATCH]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: exit.loopexit.unr-lcssa:
diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/loopflatten.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/loopflatten.ll
index 8f106d720f758..81b83e678e814 100644
--- a/llvm/test/Transforms/PhaseOrdering/AArch64/loopflatten.ll
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/loopflatten.ll
@@ -14,18 +14,28 @@ define dso_local void @_Z3fooPiii(ptr %A, i32 %N, i32 %M) #0 {
; CHECK: for.cond1.preheader.lr.ph.split:
; CHECK-NEXT: [[TMP0:%.*]] = zext nneg i32 [[M]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[N]] to i64
-; CHECK-NEXT: [[FLATTEN_TRIPCOUNT:%.*]] = mul nuw nsw i64 [[TMP0]], [[TMP1]]
; CHECK-NEXT: br label [[FOR_COND1_PREHEADER_US:%.*]]
; CHECK: for.cond1.preheader:
-; CHECK-NEXT: [[INDVAR6:%.*]] = phi i64 [ 0, [[FOR_COND1_PREHEADER_LR_PH_SPLIT_US]] ], [ [[INDVAR_NEXT7:%.*]], [[FOR_COND1_PREHEADER_US]] ]
+; CHECK-NEXT: [[INDVAR7:%.*]] = phi i64 [ 0, [[FOR_COND1_PREHEADER_LR_PH_SPLIT_US]] ], [ [[INDVAR_NEXT7:%.*]], [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE:%.*]] ]
+; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[INDVAR7]] to i32
+; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[M]], [[TMP4]]
+; CHECK-NEXT: [[INDVAR6:%.*]] = zext i32 [[TMP3]] to i64
; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A:%.*]], i64 [[INDVAR6]]
-; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX_US]], align 4
-; CHECK-NEXT: tail call void @_Z1fi(i32 [[TMP2]])
-; CHECK-NEXT: [[INDVAR_NEXT7]] = add nuw i64 [[INDVAR6]], 1
-; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVAR_NEXT7]], [[FLATTEN_TRIPCOUNT]]
-; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_COND1_PREHEADER_US]]
+; CHECK-NEXT: br label [[FOR_BODY4:%.*]]
; CHECK: for.cond.cleanup:
; CHECK-NEXT: ret void
+; CHECK: for.cond1.for.cond.cleanup3_crit_edge:
+; CHECK-NEXT: [[INDVAR_NEXT7]] = add nuw nsw i64 [[INDVAR7]], 1
+; CHECK-NEXT: [[EXITCOND10_NOT:%.*]] = icmp eq i64 [[INDVAR_NEXT7]], [[TMP1]]
+; CHECK-NEXT: br i1 [[EXITCOND10_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_COND1_PREHEADER_US]]
+; CHECK: for.body4:
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ 0, [[FOR_COND1_PREHEADER_US]] ], [ [[INDVAR_NEXT:%.*]], [[FOR_BODY4]] ]
+; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[ARRAYIDX_US]], i64 [[INDVAR]]
+; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[GEP]], align 4
+; CHECK-NEXT: tail call void @_Z1fi(i32 [[TMP2]])
+; CHECK-NEXT: [[INDVAR_NEXT]] = add nuw nsw i64 [[INDVAR]], 1
+; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVAR_NEXT]], [[TMP0]]
+; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE]], label [[FOR_BODY4]]
;
entry:
br label %for.cond
diff --git a/llvm/test/Transforms/PhaseOrdering/SystemZ/sub-xor.ll b/llvm/test/Transforms/PhaseOrdering/SystemZ/sub-xor.ll
index 0ae3973daffad..618d9edfd4de1 100644
--- a/llvm/test/Transforms/PhaseOrdering/SystemZ/sub-xor.ll
+++ b/llvm/test/Transforms/PhaseOrdering/SystemZ/sub-xor.ll
@@ -14,133 +14,10 @@ target triple = "systemz"
define dso_local zeroext i32 @foo(ptr noundef %a) #0 {
; CHECK-LABEL: define dso_local zeroext i32 @foo(
; CHECK-SAME: ptr nofree noundef readnone captures(none) [[A:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
-; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[FOR_INC5_2:.*:]]
; CHECK-NEXT: tail call void @populate(ptr noundef nonnull @ARR) #[[ATTR2:[0-9]+]]
-; CHECK-NEXT: br label %[[FOR_BODY4:.*]]
-; CHECK: [[FOR_BODY4]]:
-; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[INDVARS_IV_NEXT_7:%.*]], %[[FOR_BODY4]] ]
-; CHECK-NEXT: [[SUM_11:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[ADD_7:%.*]], %[[FOR_BODY4]] ]
-; CHECK-NEXT: [[IDX_NEG:%.*]] = sub nsw i64 0, [[INDVARS_IV]]
-; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[IDX_NEG]]
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ADD_PTR]], align 4, !tbaa [[INT_TBAA3:![0-9]+]]
-; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP0]], [[SUM_11]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_NEG:%.*]] = xor i64 [[INDVARS_IV]], -1
-; CHECK-NEXT: [[ADD_PTR_110:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[INDVARS_IV_NEXT_NEG]]
-; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ADD_PTR_110]], align 4, !tbaa [[INT_TBAA3]]
-; CHECK-NEXT: [[ADD_111:%.*]] = add i32 [[TMP1]], [[ADD]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_112_NEG:%.*]] = sub nuw nsw i64 -2, [[INDVARS_IV]]
-; CHECK-NEXT: [[ADD_PTR_217:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[INDVARS_IV_NEXT_112_NEG]]
-; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ADD_PTR_217]], align 4, !tbaa [[INT_TBAA3]]
-; CHECK-NEXT: [[ADD_218:%.*]] = add i32 [[TMP2]], [[ADD_111]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_219_NEG:%.*]] = sub nuw nsw i64 -3, [[INDVARS_IV]]
-; CHECK-NEXT: [[ADD_PTR_3:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[INDVARS_IV_NEXT_219_NEG]]
-; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ADD_PTR_3]], align 4, !tbaa [[INT_TBAA3]]
-; CHECK-NEXT: [[ADD_3:%.*]] = add i32 [[TMP3]], [[ADD_218]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_3_NEG:%.*]] = sub nuw nsw i64 -4, [[INDVARS_IV]]
-; CHECK-NEXT: [[ADD_PTR_4:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[INDVARS_IV_NEXT_3_NEG]]
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ADD_PTR_4]], align 4, !tbaa [[INT_TBAA3]]
-; CHECK-NEXT: [[ADD_4:%.*]] = add i32 [[TMP4]], [[ADD_3]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_4_NEG:%.*]] = sub nuw nsw i64 -5, [[INDVARS_IV]]
-; CHECK-NEXT: [[ADD_PTR_5:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[INDVARS_IV_NEXT_4_NEG]]
-; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ADD_PTR_5]], align 4, !tbaa [[INT_TBAA3]]
-; CHECK-NEXT: [[ADD_5:%.*]] = add i32 [[TMP5]], [[ADD_4]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_5_NEG:%.*]] = sub nuw nsw i64 -6, [[INDVARS_IV]]
-; CHECK-NEXT: [[ADD_PTR_6:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[INDVARS_IV_NEXT_5_NEG]]
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[ADD_PTR_6]], align 4, !tbaa [[INT_TBAA3]]
-; CHECK-NEXT: [[ADD_6:%.*]] = add i32 [[TMP6]], [[ADD_5]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_6_NEG:%.*]] = sub nuw nsw i64 -7, [[INDVARS_IV]]
-; CHECK-NEXT: [[ADD_PTR_7:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[INDVARS_IV_NEXT_6_NEG]]
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ADD_PTR_7]], align 4, !tbaa [[INT_TBAA3]]
-; CHECK-NEXT: [[ADD_7]] = add i32 [[TMP7]], [[ADD_6]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_7]] = add nuw nsw i64 [[INDVARS_IV]], 8
-; CHECK-NEXT: [[EXITCOND_NOT_7:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT_7]], 32
-; CHECK-NEXT: br i1 [[EXITCOND_NOT_7]], label %[[FOR_BODY4_1:.*]], label %[[FOR_BODY4]], !llvm.loop [[LOOP7:![0-9]+]]
-; CHECK: [[FOR_BODY4_1]]:
-; CHECK-NEXT: [[INDVARS_IV_1:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_1_7:%.*]], %[[FOR_BODY4_1]] ], [ 0, %[[FOR_BODY4]] ]
-; CHECK-NEXT: [[SUM_11_1:%.*]] = phi i32 [ [[ADD_1_7:%.*]], %[[FOR_BODY4_1]] ], [ [[ADD_7]], %[[FOR_BODY4]] ]
-; CHECK-NEXT: [[IDX_NEG_1:%.*]] = sub nsw i64 0, [[INDVARS_IV_1]]
-; CHECK-NEXT: [[ADD_PTR_1:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[IDX_NEG_1]]
-; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[ADD_PTR_1]], align 4, !tbaa [[INT_TBAA3]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_1_NEG:%.*]] = xor i64 [[INDVARS_IV_1]], -1
-; CHECK-NEXT: [[ADD_PTR_1_1:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[INDVARS_IV_NEXT_1_NEG]]
-; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[ADD_PTR_1_1]], align 4, !tbaa [[INT_TBAA3]]
-; CHECK-NEXT: [[TMP10:%.*]] = add i32 [[TMP8]], [[TMP9]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_1_1_NEG:%.*]] = sub nuw nsw i64 -2, [[INDVARS_IV_1]]
-; CHECK-NEXT: [[ADD_PTR_1_2:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[INDVARS_IV_NEXT_1_1_NEG]]
-; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[ADD_PTR_1_2]], align 4, !tbaa [[INT_TBAA3]]
-; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_1_2_NEG:%.*]] = sub nuw nsw i64 -3, [[INDVARS_IV_1]]
-; CHECK-NEXT: [[ADD_PTR_1_3:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[INDVARS_IV_NEXT_1_2_NEG]]
-; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[ADD_PTR_1_3]], align 4, !tbaa [[INT_TBAA3]]
-; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_1_3_NEG:%.*]] = sub nuw nsw i64 -4, [[INDVARS_IV_1]]
-; CHECK-NEXT: [[ADD_PTR_1_4:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[INDVARS_IV_NEXT_1_3_NEG]]
-; CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[ADD_PTR_1_4]], align 4, !tbaa [[INT_TBAA3]]
-; CHECK-NEXT: [[TMP16:%.*]] = add i32 [[TMP14]], [[TMP15]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_1_4_NEG:%.*]] = sub nuw nsw i64 -5, [[INDVARS_IV_1]]
-; CHECK-NEXT: [[ADD_PTR_1_5:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[INDVARS_IV_NEXT_1_4_NEG]]
-; CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[ADD_PTR_1_5]], align 4, !tbaa [[INT_TBAA3]]
-; CHECK-NEXT: [[TMP18:%.*]] = add i32 [[TMP16]], [[TMP17]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_1_5_NEG:%.*]] = sub nuw nsw i64 -6, [[INDVARS_IV_1]]
-; CHECK-NEXT: [[ADD_PTR_1_6:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[INDVARS_IV_NEXT_1_5_NEG]]
-; CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[ADD_PTR_1_6]], align 4, !tbaa [[INT_TBAA3]]
-; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[TMP18]], [[TMP19]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_1_6_NEG:%.*]] = sub nuw nsw i64 -7, [[INDVARS_IV_1]]
-; CHECK-NEXT: [[ADD_PTR_1_7:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[INDVARS_IV_NEXT_1_6_NEG]]
-; CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[ADD_PTR_1_7]], align 4, !tbaa [[INT_TBAA3]]
-; CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP20]], [[TMP21]]
-; CHECK-NEXT: [[TMP23:%.*]] = shl i32 [[TMP22]], 1
-; CHECK-NEXT: [[ADD_1_7]] = add i32 [[TMP23]], [[SUM_11_1]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_1_7]] = add nuw nsw i64 [[INDVARS_IV_1]], 8
-; CHECK-NEXT: [[EXITCOND_1_NOT_7:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT_1_7]], 32
-; CHECK-NEXT: br i1 [[EXITCOND_1_NOT_7]], label %[[FOR_BODY4_2:.*]], label %[[FOR_BODY4_1]], !llvm.loop [[LOOP7]]
-; CHECK: [[FOR_BODY4_2]]:
-; CHECK-NEXT: [[INDVARS_IV_2:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_2_7:%.*]], %[[FOR_BODY4_2]] ], [ 0, %[[FOR_BODY4_1]] ]
-; CHECK-NEXT: [[SUM_11_2:%.*]] = phi i32 [ [[ADD_2_7:%.*]], %[[FOR_BODY4_2]] ], [ [[ADD_1_7]], %[[FOR_BODY4_1]] ]
-; CHECK-NEXT: [[IDX_NEG_2:%.*]] = sub nsw i64 0, [[INDVARS_IV_2]]
-; CHECK-NEXT: [[ADD_PTR_2:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[IDX_NEG_2]]
-; CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[ADD_PTR_2]], align 4, !tbaa [[INT_TBAA3]]
-; CHECK-NEXT: [[MUL_2:%.*]] = mul i32 [[TMP24]], 3
-; CHECK-NEXT: [[ADD_2:%.*]] = add i32 [[MUL_2]], [[SUM_11_2]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_2_NEG:%.*]] = xor i64 [[INDVARS_IV_2]], -1
-; CHECK-NEXT: [[ADD_PTR_2_1:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[INDVARS_IV_NEXT_2_NEG]]
-; CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[ADD_PTR_2_1]], align 4, !tbaa [[INT_TBAA3]]
-; CHECK-NEXT: [[MUL_2_1:%.*]] = mul i32 [[TMP25]], 3
-; CHECK-NEXT: [[ADD_2_1:%.*]] = add i32 [[MUL_2_1]], [[ADD_2]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_2_1_NEG:%.*]] = sub nuw nsw i64 -2, [[INDVARS_IV_2]]
-; CHECK-NEXT: [[ADD_PTR_2_2:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[INDVARS_IV_NEXT_2_1_NEG]]
-; CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[ADD_PTR_2_2]], align 4, !tbaa [[INT_TBAA3]]
-; CHECK-NEXT: [[MUL_2_2:%.*]] = mul i32 [[TMP26]], 3
-; CHECK-NEXT: [[ADD_2_2:%.*]] = add i32 [[MUL_2_2]], [[ADD_2_1]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_2_2_NEG:%.*]] = sub nuw nsw i64 -3, [[INDVARS_IV_2]]
-; CHECK-NEXT: [[ADD_PTR_2_3:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[INDVARS_IV_NEXT_2_2_NEG]]
-; CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[ADD_PTR_2_3]], align 4, !tbaa [[INT_TBAA3]]
-; CHECK-NEXT: [[MUL_2_3:%.*]] = mul i32 [[TMP27]], 3
-; CHECK-NEXT: [[ADD_2_3:%.*]] = add i32 [[MUL_2_3]], [[ADD_2_2]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_2_3_NEG:%.*]] = sub nuw nsw i64 -4, [[INDVARS_IV_2]]
-; CHECK-NEXT: [[ADD_PTR_2_4:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[INDVARS_IV_NEXT_2_3_NEG]]
-; CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[ADD_PTR_2_4]], align 4, !tbaa [[INT_TBAA3]]
-; CHECK-NEXT: [[MUL_2_4:%.*]] = mul i32 [[TMP28]], 3
-; CHECK-NEXT: [[ADD_2_4:%.*]] = add i32 [[MUL_2_4]], [[ADD_2_3]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_2_4_NEG:%.*]] = sub nuw nsw i64 -5, [[INDVARS_IV_2]]
-; CHECK-NEXT: [[ADD_PTR_2_5:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[INDVARS_IV_NEXT_2_4_NEG]]
-; CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[ADD_PTR_2_5]], align 4, !tbaa [[INT_TBAA3]]
-; CHECK-NEXT: [[MUL_2_5:%.*]] = mul i32 [[TMP29]], 3
-; CHECK-NEXT: [[ADD_2_5:%.*]] = add i32 [[MUL_2_5]], [[ADD_2_4]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_2_5_NEG:%.*]] = sub nuw nsw i64 -6, [[INDVARS_IV_2]]
-; CHECK-NEXT: [[ADD_PTR_2_6:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[INDVARS_IV_NEXT_2_5_NEG]]
-; CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[ADD_PTR_2_6]], align 4, !tbaa [[INT_TBAA3]]
-; CHECK-NEXT: [[MUL_2_6:%.*]] = mul i32 [[TMP30]], 3
-; CHECK-NEXT: [[ADD_2_6:%.*]] = add i32 [[MUL_2_6]], [[ADD_2_5]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_2_6_NEG:%.*]] = sub nuw nsw i64 -7, [[INDVARS_IV_2]]
-; CHECK-NEXT: [[ADD_PTR_2_7:%.*]] = getelementptr inbounds [4 x i8], ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), i64 [[INDVARS_IV_NEXT_2_6_NEG]]
-; CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[ADD_PTR_2_7]], align 4, !tbaa [[INT_TBAA3]]
-; CHECK-NEXT: [[MUL_2_7:%.*]] = mul i32 [[TMP31]], 3
-; CHECK-NEXT: [[ADD_2_7]] = add i32 [[MUL_2_7]], [[ADD_2_6]]
-; CHECK-NEXT: [[INDVARS_IV_NEXT_2_7]] = add nuw nsw i64 [[INDVARS_IV_2]], 8
-; CHECK-NEXT: [[EXITCOND_2_NOT_7:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT_2_7]], 32
-; CHECK-NEXT: br i1 [[EXITCOND_2_NOT_7]], label %[[FOR_INC5_2:.*]], label %[[FOR_BODY4_2]], !llvm.loop [[LOOP7]]
-; CHECK: [[FOR_INC5_2]]:
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr getelementptr inbounds nuw (i8, ptr @ARR, i64 396), align 4, !tbaa [[INT_TBAA3:![0-9]+]]
+; CHECK-NEXT: [[ADD_2_7:%.*]] = mul i32 [[TMP0]], 192
; CHECK-NEXT: ret i32 [[ADD_2_7]]
;
entry:
@@ -216,6 +93,4 @@ attributes #2 = { argmemonly nocallback nofree nosync nounwind willreturn }
; CHECK: [[META4]] = !{!"int", [[META5:![0-9]+]], i64 0}
; CHECK: [[META5]] = !{!"omnipotent char", [[META6:![0-9]+]], i64 0}
; CHECK: [[META6]] = !{!"Simple C/C++ TBAA"}
-; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META8:![0-9]+]]}
-; CHECK: [[META8]] = !{!"llvm.loop.mustprogress"}
;.
diff --git a/llvm/test/Transforms/PhaseOrdering/scev-custom-dl.ll b/llvm/test/Transforms/PhaseOrdering/scev-custom-dl.ll
index 60f2c30291eaa..bdcaaca9390c5 100644
--- a/llvm/test/Transforms/PhaseOrdering/scev-custom-dl.ll
+++ b/llvm/test/Transforms/PhaseOrdering/scev-custom-dl.ll
@@ -141,7 +141,7 @@ define i32 @test_loop_idiom_recogize(i32 %x, i32 %y, ptr %lam, ptr %alp) nounwin
; CHECK-NEXT: Classifying expressions for: @test_loop_idiom_recogize
; CHECK-NEXT: %indvar = phi i32 [ 0, %bb1.thread ], [ %indvar.next, %bb1 ]
; CHECK-NEXT: --> {0,+,1}<nuw><nsw><%bb1> U: [0,256) S: [0,256) Exits: 255 LoopDispositions: { %bb1: Computable }
-; CHECK-NEXT: %i.0.reg2mem.0 = sub nsw i32 255, %indvar
+; CHECK-NEXT: %i.0.reg2mem.0 = sub nuw nsw i32 255, %indvar
; CHECK-NEXT: --> {255,+,-1}<nsw><%bb1> U: [0,256) S: [0,256) Exits: 0 LoopDispositions: { %bb1: Computable }
; CHECK-NEXT: %0 = getelementptr [4 x i8], ptr %alp, i32 %i.0.reg2mem.0
; CHECK-NEXT: --> {(1020 + %alp),+,-4}<nw><%bb1> U: full-set S: full-set Exits: %alp LoopDispositions: { %bb1: Computable }
diff --git a/llvm/test/Transforms/PhaseOrdering/single-iteration-loop-sroa.ll b/llvm/test/Transforms/PhaseOrdering/single-iteration-loop-sroa.ll
index 98b44fa69d534..6fcd291efd762 100644
--- a/llvm/test/Transforms/PhaseOrdering/single-iteration-loop-sroa.ll
+++ b/llvm/test/Transforms/PhaseOrdering/single-iteration-loop-sroa.ll
@@ -12,17 +12,17 @@ define i16 @helper(i16 %0, i64 %x) {
; CHECK-NEXT: [[DATA:%.*]] = alloca [2 x i8], align 2
; CHECK-NEXT: store i16 [[TMP0:%.*]], ptr [[DATA]], align 2
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw i8, ptr [[DATA]], i64 1
+; CHECK-NEXT: [[TMP4:%.*]] = lshr i16 [[TMP0]], 8
+; CHECK-NEXT: [[TMP3:%.*]] = trunc nuw i16 [[TMP4]] to i8
; CHECK-NEXT: br label [[BB6_I_I:%.*]]
; CHECK: bb6.i.i:
-; CHECK-NEXT: [[ITER_SROA_0_07_I_I:%.*]] = phi i64 [ [[TMP2:%.*]], [[BB6_I_I]] ], [ 0, [[START:%.*]] ]
-; CHECK-NEXT: [[_40_I_I:%.*]] = sub nsw i64 0, [[ITER_SROA_0_07_I_I]]
+; CHECK-NEXT: [[TMP2_0_COPYLOAD_I_I_I_I:%.*]] = phi i8 [ [[TMP_0_COPYLOAD_I_I_I_I:%.*]], [[BB6_I_I]] ], [ [[TMP3]], [[START:%.*]] ]
+; CHECK-NEXT: [[ITER_SROA_0_07_I_I:%.*]] = phi i64 [ [[TMP2:%.*]], [[BB6_I_I]] ], [ 0, [[START]] ]
; CHECK-NEXT: [[TMP2]] = add nuw nsw i64 [[ITER_SROA_0_07_I_I]], 1
; CHECK-NEXT: [[_34_I_I:%.*]] = getelementptr inbounds nuw i8, ptr [[DATA]], i64 [[ITER_SROA_0_07_I_I]]
-; CHECK-NEXT: [[_39_I_I:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 [[_40_I_I]]
-; CHECK-NEXT: [[TMP_0_COPYLOAD_I_I_I_I:%.*]] = load i8, ptr [[_34_I_I]], align 1
-; CHECK-NEXT: [[TMP2_0_COPYLOAD_I_I_I_I:%.*]] = load i8, ptr [[_39_I_I]], align 1
+; CHECK-NEXT: [[TMP_0_COPYLOAD_I_I_I_I]] = load i8, ptr [[_34_I_I]], align 1
; CHECK-NEXT: store i8 [[TMP2_0_COPYLOAD_I_I_I_I]], ptr [[_34_I_I]], align 1
-; CHECK-NEXT: store i8 [[TMP_0_COPYLOAD_I_I_I_I]], ptr [[_39_I_I]], align 1
+; CHECK-NEXT: store i8 [[TMP_0_COPYLOAD_I_I_I_I]], ptr [[TMP1]], align 1
; CHECK-NEXT: [[EXITCOND_NOT_I_I:%.*]] = icmp eq i64 [[TMP2]], [[X:%.*]]
; CHECK-NEXT: br i1 [[EXITCOND_NOT_I_I]], label [[EXIT:%.*]], label [[BB6_I_I]]
; CHECK: exit:
diff --git a/llvm/test/Transforms/PhaseOrdering/swap-promotion.ll b/llvm/test/Transforms/PhaseOrdering/swap-promotion.ll
index 059a122262786..bc6142d18b2a0 100644
--- a/llvm/test/Transforms/PhaseOrdering/swap-promotion.ll
+++ b/llvm/test/Transforms/PhaseOrdering/swap-promotion.ll
@@ -24,7 +24,7 @@ define i32 @test(i32 %n) {
; CHECK: loop:
; CHECK-NEXT: [[P1_SROA_5_0:%.*]] = phi i32 [ 1, [[TMP0:%.*]] ], [ [[V2_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[P1_SROA_0_0:%.*]] = phi i32 [ 0, [[TMP0]] ], [ [[V1_INC:%.*]], [[LOOP]] ]
-; CHECK-NEXT: [[V1_INC]] = add i32 [[P1_SROA_0_0]], 1
+; CHECK-NEXT: [[V1_INC]] = add nuw i32 [[P1_SROA_0_0]], 1
; CHECK-NEXT: [[V2_NEXT]] = shl i32 [[P1_SROA_5_0]], 1
; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[V1_INC]], [[N:%.*]]
; CHECK-NEXT: br i1 [[C]], label [[EXIT:%.*]], label [[LOOP]]
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