[llvm] [SelectionDAG] Preserve CTTZ_ELTS lane count during expansion (PR #217982)

[Oscar Priego via llvm-commits]

https://github.com/Opriego created https://github.com/llvm/llvm-project/pull/217982

Fixes #216649.

`expandCttzElts` derives `VL` from its legalized auxiliary step vector. When that helper vector is widened for target legality, its lane count may differ from the logical lane count of the `CTTZ_ELTS` operand.

On X86 with AVX512F, the step vector for a semantic `<4 x i1>` mask is widened from `v4i8` to `v16i8`. As a result, an all-zero `llvm.experimental.cttz.elts` input returns 16 instead of the required result of 4.

Preserve the `ElementCount` from the `CTTZ_ELTS` operand and use it when materializing `VL`. Auxiliary step-vector legalization can still widen its representation without changing the logical lane domain of the operation.

Add AVX512F regression coverage for the affected `v4i1` and `v8i1` cases.

>From 6d0c1bb6428a1b642b746ec45742f7b17a9a5cf1 Mon Sep 17 00:00:00 2001
From: Oscar Priego Verdugo <oscar.priegov at gmail.com>
Date: Fri, 21 Aug 2026 10:57:35 -0600
Subject: [PATCH] [SelectionDAG] Preserve CTTZ_ELTS lane count during expansion

CTTZ_ELTS expansion derived VL from its legalized auxiliary step vector. On X86 with AVX512F, the step vector for a semantic v4i1 mask is widened from v4i8 to v16i8, causing an all-zero mask to return 16 instead of 4.

Derive VL from the CTTZ_ELTS operand's ElementCount instead. Auxiliary type legalization can still widen the step vector without changing the logical lane domain of the operation.
---
 .../lib/CodeGen/SelectionDAG/TargetLowering.cpp |  5 +++--
 llvm/test/CodeGen/X86/intrinsic-cttz-elts.ll    | 17 +++++++++++++++++
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index cca7cdad0e2c8..081d38dc136c0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -13859,6 +13859,8 @@ SDValue TargetLowering::expandVECTOR_COMPRESS(SDNode *Node,
 SDValue TargetLowering::expandCttzElts(SDNode *Node, SelectionDAG &DAG) const {
   SDLoc DL(Node);
   EVT VT = Node->getValueType(0);
+  ElementCount EC =
+      Node->getOperand(0).getValueType().getVectorElementCount();
 
   bool ZeroIsPoison = Node->getOpcode() == ISD::CTTZ_ELTS_ZERO_POISON;
   auto [Mask, StepVec] =
@@ -13893,8 +13895,7 @@ SDValue TargetLowering::expandCttzElts(SDNode *Node, SelectionDAG &DAG) const {
   if (getTypeAction(StepVT.getSimpleVT()) == TypePromoteInteger)
     StepVT = getTypeToTransformTo(*DAG.getContext(), StepVT);
 
-  SDValue VL =
-      DAG.getElementCount(DL, StepVT, StepVecVT.getVectorElementCount());
+  SDValue VL = DAG.getElementCount(DL, StepVT, EC);
   SDValue SplatVL = DAG.getSplat(StepVecVT, DL, VL);
   StepVec = DAG.getNode(ISD::SUB, DL, StepVecVT, SplatVL, StepVec);
   SDValue Zeroes = DAG.getConstant(0, DL, StepVecVT);
diff --git a/llvm/test/CodeGen/X86/intrinsic-cttz-elts.ll b/llvm/test/CodeGen/X86/intrinsic-cttz-elts.ll
index 65231c484db98..a0b494a6303dc 100644
--- a/llvm/test/CodeGen/X86/intrinsic-cttz-elts.ll
+++ b/llvm/test/CodeGen/X86/intrinsic-cttz-elts.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx512f < %s | FileCheck %s --check-prefix=AVX512
 
 define i8 @ctz_v8i16(<8 x i16> %a) {
 ; CHECK-LABEL: .LCPI0_0:
@@ -101,5 +102,21 @@ define i8 @ctz_v8i16_poison(<8 x i16> %a) {
   ret i8 %res
 }
 
+define i32 @ctz_zero_v4i1() {
+; AVX512-LABEL: ctz_zero_v4i1:
+; AVX512:         addb $5, %al
+  %res = call i32 @llvm.experimental.cttz.elts.i32.v4i1(<4 x i1> zeroinitializer, i1 false)
+  ret i32 %res
+}
+
+define i32 @ctz_zero_v8i1() {
+; AVX512-LABEL: ctz_zero_v8i1:
+; AVX512:         addb $9, %al
+  %res = call i32 @llvm.experimental.cttz.elts.i32.v8i1(<8 x i1> zeroinitializer, i1 false)
+  ret i32 %res
+}
+
 declare i8 @llvm.experimental.cttz.elts.i8.v8i16(<8 x i16>, i1)
 declare i16 @llvm.experimental.cttz.elts.i16.v4i32(<4 x i32>, i1)
+declare i32 @llvm.experimental.cttz.elts.i32.v4i1(<4 x i1>, i1)
+declare i32 @llvm.experimental.cttz.elts.i32.v8i1(<8 x i1>, i1)