[llvm] [SystemZ] Use scheduling model for load latency (PR #217617)

Jonas Paulsson via llvm-commits llvm-commits at lists.llvm.org
Fri Aug 21 09:56:34 PDT 2026


JonPsson1 wrote:

I see AArch64 implemented this on June 30. Is there any special thought behind duplicating this for SystemZ at this point?

```
/// There are several different cost models that can be customized by the
/// target. The normalization of each cost model may be target specific.
```
I am not sure exactly what TCK_Latency should mean on SystemZ - I don't think we have defined that yet. It doesn't seem to be used really - at least I see total NFC across SPEC using normal options (-O3 -march=arch15) with this patch.

In your test case you have only a single wide (8 x i32) vector test case, setting the cost to 8, which is treating the two VLs as strictly serial. This seems odd to me as loading two vectors from adjacent addresses really would always be pipelined. I can't imagine a strict sum-of-latencies usage during compile-time, but please fill me in if you are aware of the backgrounds here. Why is this relevant on AArch64 and not on SystemZ (benchmarks)?

As for the testing, I would have liked to see one narrow, one full, and one wide vector example, as in 2xi32, 4xi32 and 8xi32, for instance. The latency L in each case should be - I think - L, L and L + 1 (additional load).

Instead of using getTypeLegalizationCost(), we have a local getNumVectorRegs() that we use instead (see comment above it).

You have chosen zero-extending opcodes for i8 and i16 but sign-extending for i32 and i64. Not sure if it matters, but maybe better to be consistent. It would be possible to check for `*I `and it's possible only user being a sext or zext but that is probably not worth the trouble at this point.


https://github.com/llvm/llvm-project/pull/217617


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