[llvm] [AArch64][GISel] Allow import of DAG FCVT/CVTF patterns using fixedpoint immediate (PR #215812)
Kieran B via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 21 03:11:23 PDT 2026
https://github.com/kieroxide updated https://github.com/llvm/llvm-project/pull/215812
>From 50a3ffec6ffd380b454a84e91436edac5d6eab2e Mon Sep 17 00:00:00 2001
From: Kieran Bailey <kieran.bailey at arm.com>
Date: Wed, 12 Aug 2026 14:21:31 +0000
Subject: [PATCH 1/2] [AArch64][GISel] Allow import of DAG patterns using
fixedpoint immediate
Currently, fp_to_int(fmul) patterns only work for DAG, this is due to the use of fixedpoint immediate type which GISel could not import.
Add GlobalISel matchers and renderers for fixed-point immediates, allowing these patterns to be imported and used during instruction selection.
I originally created these to allow fp_to_int(fmul) fold patterns to import, but this does enable other existing patterns which use fixedpoint to work in GISel
---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 70 +-
.../GISel/AArch64InstructionSelector.cpp | 120 +-
llvm/test/CodeGen/AArch64/fcvt-fixed.ll | 1476 +++++------------
3 files changed, 516 insertions(+), 1150 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 962f6c9b13b8a..0e237389f8ecd 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -6858,35 +6858,55 @@ multiclass FPToIntegerIntPats<Intrinsic round, string INST> {
defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzs, "FCVTZS">;
defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzu, "FCVTZU">;
-// This thing just allows us to change the type of the node produced. The imm
-// value we want is already in V from SelectCVTFixedPointVec.
-def fixedpoint_vec_xform : SDNodeXForm<timm, [{
+// These are split by fixed-point width so GlobalISel can route each
+// transformed operand to a renderer that checks the correct #fbits range.
+def fixedpoint_xform32 : SDNodeXForm<timm, [{
+ (void)N;
+ return V;
+}]>;
+def gi_fixedpoint_xform32 : GICustomOperandRenderer<"renderFixedPointXForm32">,
+ GISDNodeXFormEquiv<fixedpoint_xform32>;
+
+def fixedpoint_xform64 : SDNodeXForm<timm, [{
(void)N;
return V;
}]>;
-def gi_fixedpoint_vec_xform : GICustomOperandRenderer<"renderFixedPointXForm">,
- GISDNodeXFormEquiv<fixedpoint_vec_xform>;
+def gi_fixedpoint_xform64 : GICustomOperandRenderer<"renderFixedPointXForm64">,
+ GISDNodeXFormEquiv<fixedpoint_xform64>;
+
+def gi_fixedpoint_f16_i32 : GIComplexOperandMatcher<s32, "selectCVTFixedPoint<32>">,
+ GIComplexPatternEquiv<fixedpoint_f16_i32>;
+def gi_fixedpoint_f16_i64 : GIComplexOperandMatcher<s32, "selectCVTFixedPoint<64>">,
+ GIComplexPatternEquiv<fixedpoint_f16_i64>;
+def gi_fixedpoint_f32_i32 : GIComplexOperandMatcher<s32, "selectCVTFixedPoint<32>">,
+ GIComplexPatternEquiv<fixedpoint_f32_i32>;
+def gi_fixedpoint_f32_i64 : GIComplexOperandMatcher<s32, "selectCVTFixedPoint<64>">,
+ GIComplexPatternEquiv<fixedpoint_f32_i64>;
+def gi_fixedpoint_f64_i32 : GIComplexOperandMatcher<s64, "selectCVTFixedPoint<32>">,
+ GIComplexPatternEquiv<fixedpoint_f64_i32>;
+def gi_fixedpoint_f64_i64 : GIComplexOperandMatcher<s64, "selectCVTFixedPoint<64>">,
+ GIComplexPatternEquiv<fixedpoint_f64_i64>;
multiclass FPToIntegerFmulPats<SDPatternOperator round, string INST> {
let Predicates = [HasFullFP16] in {
def : Pat<(i32 (round (fmul f16:$Rn, fixedpoint_f16_i32:$scale))),
- (!cast<Instruction>(INST # SWHri) $Rn, $scale)>;
+ (!cast<Instruction>(INST # SWHri) $Rn, fixedpoint_f16_i32:$scale)>;
def : Pat<(i64 (round (fmul f16:$Rn, fixedpoint_f16_i64:$scale))),
- (!cast<Instruction>(INST # SXHri) $Rn, $scale)>;
+ (!cast<Instruction>(INST # SXHri) $Rn, fixedpoint_f16_i64:$scale)>;
}
def : Pat<(i32 (round (fmul f32:$Rn, fixedpoint_f32_i32:$scale))),
- (!cast<Instruction>(INST # SWSri) $Rn, $scale)>;
+ (!cast<Instruction>(INST # SWSri) $Rn, fixedpoint_f32_i32:$scale)>;
def : Pat<(i64 (round (fmul f32:$Rn, fixedpoint_f32_i64:$scale))),
- (!cast<Instruction>(INST # SXSri) $Rn, $scale)>;
+ (!cast<Instruction>(INST # SXSri) $Rn, fixedpoint_f32_i64:$scale)>;
def : Pat<(i32 (round (fmul f64:$Rn, fixedpoint_f64_i32:$scale))),
- (!cast<Instruction>(INST # SWDri) $Rn, $scale)>;
+ (!cast<Instruction>(INST # SWDri) $Rn, fixedpoint_f64_i32:$scale)>;
def : Pat<(i64 (round (fmul f64:$Rn, fixedpoint_f64_i64:$scale))),
(!cast<Instruction>(INST # SXDri) $Rn, $scale)>;
def : Pat<(f32 (bitconvert (i32 (round (fmul FPR32:$Rn, fixedpoint_f32_i32:$scale))))),
- (!cast<Instruction>(INST # "s") FPR32:$Rn, (fixedpoint_vec_xform fixedpoint_f32_i32:$scale))>;
+ (!cast<Instruction>(INST # "s") FPR32:$Rn, (fixedpoint_xform32 fixedpoint_f32_i32:$scale))>;
def : Pat<(f64 (bitconvert (i64 (round (fmul FPR64:$Rn, fixedpoint_f64_i64:$scale))))),
- (!cast<Instruction>(INST # "d") FPR64:$Rn, (fixedpoint_vec_xform fixedpoint_f64_i64:$scale))>;
+ (!cast<Instruction>(INST # "d") FPR64:$Rn, (fixedpoint_xform64 fixedpoint_f64_i64:$scale))>;
}
defm : FPToIntegerFmulPats<any_fp_to_sint, "FCVTZS">;
@@ -6951,23 +6971,23 @@ multiclass FPToIntegerSatPats<SDNode to_int_sat, string INST> {
let Predicates = [HasFullFP16] in {
def : Pat<(i32 (to_int_sat (fmul f16:$Rn, fixedpoint_f16_i32:$scale), i32)),
- (!cast<Instruction>(INST # SWHri) $Rn, $scale)>;
+ (!cast<Instruction>(INST # SWHri) $Rn, fixedpoint_f16_i32:$scale)>;
def : Pat<(i64 (to_int_sat (fmul f16:$Rn, fixedpoint_f16_i64:$scale), i64)),
- (!cast<Instruction>(INST # SXHri) $Rn, $scale)>;
+ (!cast<Instruction>(INST # SXHri) $Rn, fixedpoint_f16_i64:$scale)>;
}
def : Pat<(i32 (to_int_sat (fmul f32:$Rn, fixedpoint_f32_i32:$scale), i32)),
- (!cast<Instruction>(INST # SWSri) $Rn, $scale)>;
+ (!cast<Instruction>(INST # SWSri) $Rn, fixedpoint_f32_i32:$scale)>;
def : Pat<(i64 (to_int_sat (fmul f32:$Rn, fixedpoint_f32_i64:$scale), i64)),
- (!cast<Instruction>(INST # SXSri) $Rn, $scale)>;
+ (!cast<Instruction>(INST # SXSri) $Rn, fixedpoint_f32_i64:$scale)>;
def : Pat<(i32 (to_int_sat (fmul f64:$Rn, fixedpoint_f64_i32:$scale), i32)),
- (!cast<Instruction>(INST # SWDri) $Rn, $scale)>;
+ (!cast<Instruction>(INST # SWDri) $Rn, fixedpoint_f64_i32:$scale)>;
def : Pat<(i64 (to_int_sat (fmul f64:$Rn, fixedpoint_f64_i64:$scale), i64)),
- (!cast<Instruction>(INST # SXDri) $Rn, $scale)>;
+ (!cast<Instruction>(INST # SXDri) $Rn, fixedpoint_f64_i64:$scale)>;
def : Pat<(f32 (bitconvert (i32 (to_int_sat (fmul FPR32:$Rn, fixedpoint_f32_i32:$scale), i32)))),
- (!cast<Instruction>(INST # "s") FPR32:$Rn, (fixedpoint_vec_xform fixedpoint_f32_i32:$scale))>;
+ (!cast<Instruction>(INST # "s") FPR32:$Rn, (fixedpoint_xform32 fixedpoint_f32_i32:$scale))>;
def : Pat<(f64 (bitconvert (i64 (to_int_sat (fmul FPR64:$Rn, fixedpoint_f64_i64:$scale), i64)))),
- (!cast<Instruction>(INST # "d") FPR64:$Rn, (fixedpoint_vec_xform fixedpoint_f64_i64:$scale))>;
+ (!cast<Instruction>(INST # "d") FPR64:$Rn, (fixedpoint_xform64 fixedpoint_f64_i64:$scale))>;
}
defm : FPToIntegerSatPats<fp_to_sint_sat, "FCVTZS">;
@@ -9324,6 +9344,14 @@ class fixedpoint_vec_f32<ValueType FloatVT>
: ComplexPattern<FloatVT, 1, "SelectCVTFixedPointVec<32>">;
class fixedpoint_vec_f16<ValueType FloatVT>
: ComplexPattern<FloatVT, 1, "SelectCVTFixedPointVec<16>">;
+// This thing just allows us to change the type of the node produced. The imm
+// value we want is already in V from SelectCVTFixedPointVec.
+def fixedpoint_vec_xform : SDNodeXForm<timm, [{
+ (void)N;
+ return V;
+}]>;
+def gi_fixedpoint_vec_xform : GICustomOperandRenderer<"renderFixedPointXFormVec">,
+ GISDNodeXFormEquiv<fixedpoint_vec_xform>;
def fixedpoint_v2f64 : fixedpoint_vec_f64<v2f64>;
def fixedpoint_v2f32 : fixedpoint_vec_f32<v2f32>;
@@ -9406,7 +9434,7 @@ def fixedpoint_recip_vec_xform : SDNodeXForm<timm, [{
return V;
}]>;
def gi_fixedpoint_recip_vec_xform
- : GICustomOperandRenderer<"renderFixedPointRecipXForm">,
+ : GICustomOperandRenderer<"renderFixedPointRecipXFormVec">,
GISDNodeXFormEquiv<fixedpoint_recip_vec_xform>;
def fixedpoint_recip_v2f64 : fixedpoint_recip_vec_f64<v2f64>;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index ad8c1eb728e7b..4af71cf942f02 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -481,19 +481,31 @@ class AArch64InstructionSelector : public InstructionSelector {
ComplexRendererFns selectArithExtendedRegister(MachineOperand &Root) const;
ComplexRendererFns selectExtractHigh(MachineOperand &Root) const;
-
+ template <unsigned Width>
+ ComplexRendererFns selectCVTFixedPoint(MachineOperand &Root) const;
+ ComplexRendererFns selectCVTFixedPointBase(const MachineOperand &Root,
+ unsigned width,
+ bool isReciprocal = false) const;
ComplexRendererFns selectCVTFixedPointVec(MachineOperand &Root) const;
ComplexRendererFns
selectCVTFixedPosRecipOperandVec(MachineOperand &Root) const;
- ComplexRendererFns
- selectCVTFixedPointVecBase(const MachineOperand &Root,
- bool isReciprocal = false) const;
void renderFixedPointScalarXForm(MachineInstrBuilder &MIB,
const MachineInstr &MI, int OpIdx) const;
+ unsigned getFixedPointWidthFromOperand(const MachineOperand &Root) const;
+ template <unsigned Width>
void renderFixedPointXForm(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx = -1) const;
- void renderFixedPointRecipXForm(MachineInstrBuilder &MIB,
- const MachineInstr &MI, int OpIdx = -1) const;
+ void renderFixedPointXForm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
+ int OpIdx = -1) const;
+ void renderFixedPointXForm64(MachineInstrBuilder &MIB, const MachineInstr &MI,
+ int OpIdx = -1) const;
+ void renderFixedPointXFormVec(MachineInstrBuilder &MIB,
+ const MachineInstr &MI, int OpIdx = -1) const;
+ void renderFixedPointRecipXFormVec(MachineInstrBuilder &MIB,
+ const MachineInstr &MI,
+ int OpIdx = -1) const;
+ void renderFixedPointImm(MachineInstrBuilder &MIB, const MachineOperand &Root,
+ unsigned Width, bool isReciprocal) const;
void renderTruncImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx = -1) const;
void renderLogicalImm32(MachineInstrBuilder &MIB, const MachineInstr &I,
@@ -7918,24 +7930,29 @@ AArch64InstructionSelector::selectExtractHigh(MachineOperand &Root) const {
}
InstructionSelector::ComplexRendererFns
-AArch64InstructionSelector::selectCVTFixedPointVecBase(
- const MachineOperand &Root, bool isReciprocal) const {
+AArch64InstructionSelector::selectCVTFixedPointBase(const MachineOperand &Root,
+ unsigned DstElementWidth,
+ bool isReciprocal) const {
if (!Root.isReg())
return std::nullopt;
const MachineRegisterInfo &MRI =
Root.getParent()->getParent()->getParent()->getRegInfo();
- MachineInstr *Dup = getDefIgnoringCopies(Root.getReg(), MRI);
- if (Dup->getOpcode() != AArch64::G_DUP)
- return std::nullopt;
+ Register Reg = Root.getReg();
+ MachineInstr *Dup = getDefIgnoringCopies(Reg, MRI);
+
+ if (Dup && Dup->getOpcode() == AArch64::G_DUP)
+ Reg = Dup->getOperand(1).getReg();
+
std::optional<ValueAndVReg> CstVal =
- getAnyConstantVRegValWithLookThrough(Dup->getOperand(1).getReg(), MRI);
+ getAnyConstantVRegValWithLookThrough(Reg, MRI);
+
if (!CstVal)
return std::nullopt;
- unsigned RegWidth = MRI.getType(Root.getReg()).getScalarSizeInBits();
+ unsigned SrcElementWidth = MRI.getType(Reg).getScalarSizeInBits();
APFloat FVal(0.0);
- switch (RegWidth) {
+ switch (SrcElementWidth) {
case 16:
FVal = APFloat(APFloat::IEEEhalf(), CstVal->Value);
break;
@@ -7949,21 +7966,38 @@ AArch64InstructionSelector::selectCVTFixedPointVecBase(
return std::nullopt;
};
if (unsigned FBits =
- CheckFixedPointOperandConstant(FVal, RegWidth, isReciprocal))
+ CheckFixedPointOperandConstant(FVal, DstElementWidth, isReciprocal))
return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(FBits); }}};
return std::nullopt;
}
+unsigned AArch64InstructionSelector::getFixedPointWidthFromOperand(
+ const MachineOperand &Root) const {
+ return Root.getParent()
+ ->getMF()
+ ->getRegInfo()
+ .getType(Root.getReg())
+ .getScalarSizeInBits();
+}
+
+template <unsigned Width>
+InstructionSelector::ComplexRendererFns
+AArch64InstructionSelector::selectCVTFixedPoint(MachineOperand &Root) const {
+ return selectCVTFixedPointBase(Root, Width, /*isReciprocal*/ false);
+}
+
InstructionSelector::ComplexRendererFns
AArch64InstructionSelector::selectCVTFixedPointVec(MachineOperand &Root) const {
- return selectCVTFixedPointVecBase(Root, /*isReciprocal*/ false);
+ return selectCVTFixedPointBase(Root, getFixedPointWidthFromOperand(Root),
+ /*isReciprocal*/ false);
}
InstructionSelector::ComplexRendererFns
AArch64InstructionSelector::selectCVTFixedPosRecipOperandVec(
MachineOperand &Root) const {
- return selectCVTFixedPointVecBase(Root, /*isReciprocal*/ true);
+ return selectCVTFixedPointBase(Root, getFixedPointWidthFromOperand(Root),
+ /*isReciprocal*/ true);
}
void AArch64InstructionSelector::renderFixedPointScalarXForm(
@@ -7973,26 +8007,54 @@ void AArch64InstructionSelector::renderFixedPointScalarXForm(
MIB.addImm(MI.getOperand(OpIdx).getImm());
}
-void AArch64InstructionSelector::renderFixedPointXForm(MachineInstrBuilder &MIB,
- const MachineInstr &MI,
- int OpIdx) const {
+void AArch64InstructionSelector::renderFixedPointImm(MachineInstrBuilder &MIB,
+ const MachineOperand &Root,
+ unsigned Width,
+ bool isReciprocal) const {
// FIXME: This is only needed to satisfy the type checking in tablegen, and
// should be able to reuse the Renderers already calculated by
- // selectCVTFixedPointVecBase.
+ // selectCVTFixedPointBase.
InstructionSelector::ComplexRendererFns Renderer =
- selectCVTFixedPointVecBase(MI.getOperand(OpIdx), /*isReciprocal*/ false);
+ selectCVTFixedPointBase(Root, Width, isReciprocal);
assert((Renderer && Renderer->size() == 1) &&
- "Expected selectCVTFixedPointVec to provide a function\n");
+ "Expected selectCVTFixedPointBase to provide a function\n");
(Renderer->front())(MIB);
}
-void AArch64InstructionSelector::renderFixedPointRecipXForm(
+template <unsigned Width>
+void AArch64InstructionSelector::renderFixedPointXForm(MachineInstrBuilder &MIB,
+ const MachineInstr &MI,
+ int OpIdx) const {
+ renderFixedPointImm(MIB, MI.getOperand(OpIdx), Width,
+ /*isReciprocal*/ false);
+}
+
+void AArch64InstructionSelector::renderFixedPointXForm32(
MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const {
- InstructionSelector::ComplexRendererFns Renderer =
- selectCVTFixedPointVecBase(MI.getOperand(OpIdx), /*isReciprocal*/ true);
- assert((Renderer && Renderer->size() == 1) &&
- "Expected selectCVTFixedPosRecipOperandVec to provide a function\n");
- (Renderer->front())(MIB);
+ // GIsel Renderers cannot use templates in .td so function name used to pass
+ // the width
+ renderFixedPointXForm<32>(MIB, MI, OpIdx);
+}
+
+void AArch64InstructionSelector::renderFixedPointXForm64(
+ MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const {
+ renderFixedPointXForm<64>(MIB, MI, OpIdx);
+}
+
+void AArch64InstructionSelector::renderFixedPointXFormVec(
+ MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const {
+ const MachineOperand &Root = MI.getOperand(OpIdx);
+ unsigned Width = getFixedPointWidthFromOperand(Root);
+
+ renderFixedPointImm(MIB, Root, Width, /*isReciprocal*/ false);
+}
+
+void AArch64InstructionSelector::renderFixedPointRecipXFormVec(
+ MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const {
+ const MachineOperand &Root = MI.getOperand(OpIdx);
+ unsigned Width = getFixedPointWidthFromOperand(Root);
+
+ renderFixedPointImm(MIB, Root, Width, /*isReciprocal*/ true);
}
void AArch64InstructionSelector::renderTruncImm(MachineInstrBuilder &MIB,
diff --git a/llvm/test/CodeGen/AArch64/fcvt-fixed.ll b/llvm/test/CodeGen/AArch64/fcvt-fixed.ll
index 7419d88ef6c8d..68abb738739a3 100644
--- a/llvm/test/CodeGen/AArch64/fcvt-fixed.ll
+++ b/llvm/test/CodeGen/AArch64/fcvt-fixed.ll
@@ -7,52 +7,30 @@
; fptoui
define i32 @fcvtzs_f32_i32_7(float %flt) {
-; CHECK-SD-LABEL: fcvtzs_f32_i32_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs w0, s0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_f32_i32_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2s, #67, lsl #24
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzs w0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_f32_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs w0, s0, #7
+; CHECK-NEXT: ret
%fix = fmul float %flt, 128.0
%cvt = fptosi float %fix to i32
ret i32 %cvt
}
define i32 @fcvtzs_f32_i32_32(float %flt) {
-; CHECK-SD-LABEL: fcvtzs_f32_i32_32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs w0, s0, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_f32_i32_32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #1333788672 // =0x4f800000
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzs w0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_f32_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs w0, s0, #32
+; CHECK-NEXT: ret
%fix = fmul float %flt, 4294967296.0
%cvt = fptosi float %fix to i32
ret i32 %cvt
}
define float @fcvtzs_f32_i32_7_fpr(float %flt) {
-; CHECK-SD-LABEL: fcvtzs_f32_i32_7_fpr:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs s0, s0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_f32_i32_7_fpr:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2s, #67, lsl #24
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzs s0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_f32_i32_7_fpr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs s0, s0, #7
+; CHECK-NEXT: ret
%fix = fmul float %flt, 128.0
%cvt = fptosi float %fix to i32
%bc = bitcast i32 %cvt to float
@@ -60,18 +38,10 @@ define float @fcvtzs_f32_i32_7_fpr(float %flt) {
}
define float @fcvtzs_f32_i32_32_fpr(float %flt) {
-; CHECK-SD-LABEL: fcvtzs_f32_i32_32_fpr:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs s0, s0, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_f32_i32_32_fpr:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #1333788672 // =0x4f800000
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzs s0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_f32_i32_32_fpr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs s0, s0, #32
+; CHECK-NEXT: ret
%fix = fmul float %flt, 4294967296.0
%cvt = fptosi float %fix to i32
%bc = bitcast i32 %cvt to float
@@ -79,125 +49,70 @@ define float @fcvtzs_f32_i32_32_fpr(float %flt) {
}
define i64 @fcvtzs_f32_i64_7(float %flt) {
-; CHECK-SD-LABEL: fcvtzs_f32_i64_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs x0, s0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_f32_i64_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2s, #67, lsl #24
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzs x0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_f32_i64_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs x0, s0, #7
+; CHECK-NEXT: ret
%fix = fmul float %flt, 128.0
%cvt = fptosi float %fix to i64
ret i64 %cvt
}
define i64 @fcvtzs_f32_i64_64(float %flt) {
-; CHECK-SD-LABEL: fcvtzs_f32_i64_64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs x0, s0, #64
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_f32_i64_64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #1602224128 // =0x5f800000
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzs x0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_f32_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs x0, s0, #64
+; CHECK-NEXT: ret
%fix = fmul float %flt, 18446744073709551616.0
%cvt = fptosi float %fix to i64
ret i64 %cvt
}
define i32 @fcvtzs_f64_i32_7(double %dbl) {
-; CHECK-SD-LABEL: fcvtzs_f64_i32_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs w0, d0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_f64_i32_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x4060000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmul d0, d0, d1
-; CHECK-GI-NEXT: fcvtzs w0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_f64_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs w0, d0, #7
+; CHECK-NEXT: ret
%fix = fmul double %dbl, 128.0
%cvt = fptosi double %fix to i32
ret i32 %cvt
}
define i32 @fcvtzs_f64_i32_32(double %dbl) {
-; CHECK-SD-LABEL: fcvtzs_f64_i32_32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs w0, d0, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_f64_i32_32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #4751297606875873280 // =0x41f0000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmul d0, d0, d1
-; CHECK-GI-NEXT: fcvtzs w0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_f64_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs w0, d0, #32
+; CHECK-NEXT: ret
%fix = fmul double %dbl, 4294967296.0
%cvt = fptosi double %fix to i32
ret i32 %cvt
}
define i64 @fcvtzs_f64_i64_7(double %dbl) {
-; CHECK-SD-LABEL: fcvtzs_f64_i64_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs x0, d0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_f64_i64_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x4060000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmul d0, d0, d1
-; CHECK-GI-NEXT: fcvtzs x0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_f64_i64_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs x0, d0, #7
+; CHECK-NEXT: ret
%fix = fmul double %dbl, 128.0
%cvt = fptosi double %fix to i64
ret i64 %cvt
}
define i64 @fcvtzs_f64_i64_64(double %dbl) {
-; CHECK-SD-LABEL: fcvtzs_f64_i64_64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs x0, d0, #64
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_f64_i64_64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #4895412794951729152 // =0x43f0000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmul d0, d0, d1
-; CHECK-GI-NEXT: fcvtzs x0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_f64_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs x0, d0, #64
+; CHECK-NEXT: ret
%fix = fmul double %dbl, 18446744073709551616.0
%cvt = fptosi double %fix to i64
ret i64 %cvt
}
define double @fcvtzs_f64_i64_7_fpr(double %dbl) {
-; CHECK-SD-LABEL: fcvtzs_f64_i64_7_fpr:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs d0, d0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_f64_i64_7_fpr:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x4060000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmul d0, d0, d1
-; CHECK-GI-NEXT: fcvtzs d0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_f64_i64_7_fpr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs d0, d0, #7
+; CHECK-NEXT: ret
%fix = fmul double %dbl, 128.0
%cvt = fptosi double %fix to i64
%bc = bitcast i64 %cvt to double
@@ -205,18 +120,10 @@ define double @fcvtzs_f64_i64_7_fpr(double %dbl) {
}
define double @fcvtzs_f64_i64_64_fpr(double %dbl) {
-; CHECK-SD-LABEL: fcvtzs_f64_i64_64_fpr:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs d0, d0, #64
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_f64_i64_64_fpr:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #4895412794951729152 // =0x43f0000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmul d0, d0, d1
-; CHECK-GI-NEXT: fcvtzs d0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_f64_i64_64_fpr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs d0, d0, #64
+; CHECK-NEXT: ret
%fix = fmul double %dbl, 18446744073709551616.0
%cvt = fptosi double %fix to i64
%bc = bitcast i64 %cvt to double
@@ -234,18 +141,10 @@ define i32 @fcvtzs_f16_i32_7(half %flt) {
; CHECK-NO16-NEXT: fcvtzs w0, s0
; CHECK-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: fcvtzs_f16_i32_7:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzs w0, h0, #7
-; CHECK-SD-FP16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: fcvtzs_f16_i32_7:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI12_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI12_0]
-; CHECK-GI-FP16-NEXT: fmul h0, h0, h1
-; CHECK-GI-FP16-NEXT: fcvtzs w0, h0
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: fcvtzs_f16_i32_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzs w0, h0, #7
+; CHECK-FP16-NEXT: ret
%fix = fmul half %flt, 128.0
%cvt = fptosi half %fix to i32
ret i32 %cvt
@@ -262,18 +161,10 @@ define i32 @fcvtzs_f16_i32_15(half %flt) {
; CHECK-NO16-NEXT: fcvtzs w0, s0
; CHECK-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: fcvtzs_f16_i32_15:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzs w0, h0, #15
-; CHECK-SD-FP16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: fcvtzs_f16_i32_15:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI13_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI13_0]
-; CHECK-GI-FP16-NEXT: fmul h0, h0, h1
-; CHECK-GI-FP16-NEXT: fcvtzs w0, h0
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: fcvtzs_f16_i32_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzs w0, h0, #15
+; CHECK-FP16-NEXT: ret
%fix = fmul half %flt, 32768.0
%cvt = fptosi half %fix to i32
ret i32 %cvt
@@ -290,18 +181,10 @@ define i64 @fcvtzs_f16_i64_7(half %flt) {
; CHECK-NO16-NEXT: fcvtzs x0, s0
; CHECK-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: fcvtzs_f16_i64_7:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzs x0, h0, #7
-; CHECK-SD-FP16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: fcvtzs_f16_i64_7:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI14_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI14_0]
-; CHECK-GI-FP16-NEXT: fmul h0, h0, h1
-; CHECK-GI-FP16-NEXT: fcvtzs x0, h0
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: fcvtzs_f16_i64_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzs x0, h0, #7
+; CHECK-FP16-NEXT: ret
%fix = fmul half %flt, 128.0
%cvt = fptosi half %fix to i64
ret i64 %cvt
@@ -318,18 +201,10 @@ define i64 @fcvtzs_f16_i64_15(half %flt) {
; CHECK-NO16-NEXT: fcvtzs x0, s0
; CHECK-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: fcvtzs_f16_i64_15:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzs x0, h0, #15
-; CHECK-SD-FP16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: fcvtzs_f16_i64_15:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI15_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI15_0]
-; CHECK-GI-FP16-NEXT: fmul h0, h0, h1
-; CHECK-GI-FP16-NEXT: fcvtzs x0, h0
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: fcvtzs_f16_i64_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzs x0, h0, #15
+; CHECK-FP16-NEXT: ret
%fix = fmul half %flt, 32768.0
%cvt = fptosi half %fix to i64
ret i64 %cvt
@@ -338,52 +213,30 @@ define i64 @fcvtzs_f16_i64_15(half %flt) {
; fptoui
define i32 @fcvtzu_f32_i32_7(float %flt) {
-; CHECK-SD-LABEL: fcvtzu_f32_i32_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu w0, s0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzu_f32_i32_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2s, #67, lsl #24
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzu w0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzu_f32_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu w0, s0, #7
+; CHECK-NEXT: ret
%fix = fmul float %flt, 128.0
%cvt = fptoui float %fix to i32
ret i32 %cvt
}
define i32 @fcvtzu_f32_i32_32(float %flt) {
-; CHECK-SD-LABEL: fcvtzu_f32_i32_32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu w0, s0, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzu_f32_i32_32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #1333788672 // =0x4f800000
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzu w0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzu_f32_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu w0, s0, #32
+; CHECK-NEXT: ret
%fix = fmul float %flt, 4294967296.0
%cvt = fptoui float %fix to i32
ret i32 %cvt
}
define float @fcvtzu_f32_i32_7_fpr(float %flt) {
-; CHECK-SD-LABEL: fcvtzu_f32_i32_7_fpr:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu s0, s0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzu_f32_i32_7_fpr:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2s, #67, lsl #24
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzu s0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzu_f32_i32_7_fpr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu s0, s0, #7
+; CHECK-NEXT: ret
%fix = fmul float %flt, 128.0
%cvt = fptoui float %fix to i32
%bc = bitcast i32 %cvt to float
@@ -391,18 +244,10 @@ define float @fcvtzu_f32_i32_7_fpr(float %flt) {
}
define float @fcvtzu_f32_i32_32_fpr(float %flt) {
-; CHECK-SD-LABEL: fcvtzu_f32_i32_32_fpr:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu s0, s0, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzu_f32_i32_32_fpr:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #1333788672 // =0x4f800000
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzu s0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzu_f32_i32_32_fpr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu s0, s0, #32
+; CHECK-NEXT: ret
%fix = fmul float %flt, 4294967296.0
%cvt = fptoui float %fix to i32
%bc = bitcast i32 %cvt to float
@@ -410,125 +255,70 @@ define float @fcvtzu_f32_i32_32_fpr(float %flt) {
}
define i64 @fcvtzu_f32_i64_7(float %flt) {
-; CHECK-SD-LABEL: fcvtzu_f32_i64_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu x0, s0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzu_f32_i64_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2s, #67, lsl #24
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzu x0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzu_f32_i64_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu x0, s0, #7
+; CHECK-NEXT: ret
%fix = fmul float %flt, 128.0
%cvt = fptoui float %fix to i64
ret i64 %cvt
}
define i64 @fcvtzu_f32_i64_64(float %flt) {
-; CHECK-SD-LABEL: fcvtzu_f32_i64_64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu x0, s0, #64
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzu_f32_i64_64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #1602224128 // =0x5f800000
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzu x0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzu_f32_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu x0, s0, #64
+; CHECK-NEXT: ret
%fix = fmul float %flt, 18446744073709551616.0
%cvt = fptoui float %fix to i64
ret i64 %cvt
}
define i32 @fcvtzu_f64_i32_7(double %dbl) {
-; CHECK-SD-LABEL: fcvtzu_f64_i32_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu w0, d0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzu_f64_i32_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x4060000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmul d0, d0, d1
-; CHECK-GI-NEXT: fcvtzu w0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzu_f64_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu w0, d0, #7
+; CHECK-NEXT: ret
%fix = fmul double %dbl, 128.0
%cvt = fptoui double %fix to i32
ret i32 %cvt
}
define i32 @fcvtzu_f64_i32_32(double %dbl) {
-; CHECK-SD-LABEL: fcvtzu_f64_i32_32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu w0, d0, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzu_f64_i32_32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #4751297606875873280 // =0x41f0000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmul d0, d0, d1
-; CHECK-GI-NEXT: fcvtzu w0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzu_f64_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu w0, d0, #32
+; CHECK-NEXT: ret
%fix = fmul double %dbl, 4294967296.0
%cvt = fptoui double %fix to i32
ret i32 %cvt
}
define i64 @fcvtzu_f64_i64_7(double %dbl) {
-; CHECK-SD-LABEL: fcvtzu_f64_i64_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu x0, d0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzu_f64_i64_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x4060000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmul d0, d0, d1
-; CHECK-GI-NEXT: fcvtzu x0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzu_f64_i64_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu x0, d0, #7
+; CHECK-NEXT: ret
%fix = fmul double %dbl, 128.0
%cvt = fptoui double %fix to i64
ret i64 %cvt
}
define i64 @fcvtzu_f64_i64_64(double %dbl) {
-; CHECK-SD-LABEL: fcvtzu_f64_i64_64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu x0, d0, #64
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzu_f64_i64_64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #4895412794951729152 // =0x43f0000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmul d0, d0, d1
-; CHECK-GI-NEXT: fcvtzu x0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzu_f64_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu x0, d0, #64
+; CHECK-NEXT: ret
%fix = fmul double %dbl, 18446744073709551616.0
%cvt = fptoui double %fix to i64
ret i64 %cvt
}
define double @fcvtzu_f64_i64_fpr(double %dbl) {
-; CHECK-SD-LABEL: fcvtzu_f64_i64_fpr:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu d0, d0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzu_f64_i64_fpr:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x4060000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmul d0, d0, d1
-; CHECK-GI-NEXT: fcvtzu d0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzu_f64_i64_fpr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu d0, d0, #7
+; CHECK-NEXT: ret
%fix = fmul double %dbl, 128.0
%cvt = fptoui double %fix to i64
%bc = bitcast i64 %cvt to double
@@ -546,18 +336,10 @@ define i32 @fcvtzu_f16_i32_7(half %flt) {
; CHECK-NO16-NEXT: fcvtzu w0, s0
; CHECK-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: fcvtzu_f16_i32_7:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzu w0, h0, #7
-; CHECK-SD-FP16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: fcvtzu_f16_i32_7:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI27_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI27_0]
-; CHECK-GI-FP16-NEXT: fmul h0, h0, h1
-; CHECK-GI-FP16-NEXT: fcvtzu w0, h0
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: fcvtzu_f16_i32_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzu w0, h0, #7
+; CHECK-FP16-NEXT: ret
%fix = fmul half %flt, 128.0
%cvt = fptoui half %fix to i32
ret i32 %cvt
@@ -574,18 +356,10 @@ define i32 @fcvtzu_f16_i32_15(half %flt) {
; CHECK-NO16-NEXT: fcvtzu w0, s0
; CHECK-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: fcvtzu_f16_i32_15:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzu w0, h0, #15
-; CHECK-SD-FP16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: fcvtzu_f16_i32_15:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI28_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI28_0]
-; CHECK-GI-FP16-NEXT: fmul h0, h0, h1
-; CHECK-GI-FP16-NEXT: fcvtzu w0, h0
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: fcvtzu_f16_i32_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzu w0, h0, #15
+; CHECK-FP16-NEXT: ret
%fix = fmul half %flt, 32768.0
%cvt = fptoui half %fix to i32
ret i32 %cvt
@@ -602,18 +376,10 @@ define i64 @fcvtzu_f16_i64_7(half %flt) {
; CHECK-NO16-NEXT: fcvtzu x0, s0
; CHECK-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: fcvtzu_f16_i64_7:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzu x0, h0, #7
-; CHECK-SD-FP16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: fcvtzu_f16_i64_7:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI29_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI29_0]
-; CHECK-GI-FP16-NEXT: fmul h0, h0, h1
-; CHECK-GI-FP16-NEXT: fcvtzu x0, h0
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: fcvtzu_f16_i64_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzu x0, h0, #7
+; CHECK-FP16-NEXT: ret
%fix = fmul half %flt, 128.0
%cvt = fptoui half %fix to i64
ret i64 %cvt
@@ -630,18 +396,10 @@ define i64 @fcvtzu_f16_i64_15(half %flt) {
; CHECK-NO16-NEXT: fcvtzu x0, s0
; CHECK-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: fcvtzu_f16_i64_15:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzu x0, h0, #15
-; CHECK-SD-FP16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: fcvtzu_f16_i64_15:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI30_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI30_0]
-; CHECK-GI-FP16-NEXT: fmul h0, h0, h1
-; CHECK-GI-FP16-NEXT: fcvtzu x0, h0
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: fcvtzu_f16_i64_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzu x0, h0, #15
+; CHECK-FP16-NEXT: ret
%fix = fmul half %flt, 32768.0
%cvt = fptoui half %fix to i64
ret i64 %cvt
@@ -650,142 +408,80 @@ define i64 @fcvtzu_f16_i64_15(half %flt) {
; sitofp
define float @scvtf_f32_i32_7(i32 %int) {
-; CHECK-SD-LABEL: scvtf_f32_i32_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: scvtf s0, w0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: scvtf_f32_i32_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v0.2s, #67, lsl #24
-; CHECK-GI-NEXT: scvtf s1, w0
-; CHECK-GI-NEXT: fdiv s0, s1, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: scvtf_f32_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf s0, w0, #7
+; CHECK-NEXT: ret
%cvt = sitofp i32 %int to float
%fix = fdiv float %cvt, 128.0
ret float %fix
}
define float @scvtf_f32_i32_32(i32 %int) {
-; CHECK-SD-LABEL: scvtf_f32_i32_32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: scvtf s0, w0, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: scvtf_f32_i32_32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: scvtf s0, w0
-; CHECK-GI-NEXT: mov w8, #1333788672 // =0x4f800000
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: fdiv s0, s0, s1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: scvtf_f32_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf s0, w0, #32
+; CHECK-NEXT: ret
%cvt = sitofp i32 %int to float
%fix = fdiv float %cvt, 4294967296.0
ret float %fix
}
define float @scvtf_f32_i64_7(i64 %long) {
-; CHECK-SD-LABEL: scvtf_f32_i64_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: scvtf s0, x0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: scvtf_f32_i64_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v0.2s, #67, lsl #24
-; CHECK-GI-NEXT: scvtf s1, x0
-; CHECK-GI-NEXT: fdiv s0, s1, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: scvtf_f32_i64_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf s0, x0, #7
+; CHECK-NEXT: ret
%cvt = sitofp i64 %long to float
%fix = fdiv float %cvt, 128.0
ret float %fix
}
define float @scvtf_f32_i64_64(i64 %long) {
-; CHECK-SD-LABEL: scvtf_f32_i64_64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: scvtf s0, x0, #64
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: scvtf_f32_i64_64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: scvtf s0, x0
-; CHECK-GI-NEXT: mov w8, #1602224128 // =0x5f800000
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: fdiv s0, s0, s1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: scvtf_f32_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf s0, x0, #64
+; CHECK-NEXT: ret
%cvt = sitofp i64 %long to float
%fix = fdiv float %cvt, 18446744073709551616.0
ret float %fix
}
define double @scvtf_f64_i32_7(i32 %int) {
-; CHECK-SD-LABEL: scvtf_f64_i32_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: scvtf d0, w0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: scvtf_f64_i32_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: scvtf d0, w0
-; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x4060000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fdiv d0, d0, d1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: scvtf_f64_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf d0, w0, #7
+; CHECK-NEXT: ret
%cvt = sitofp i32 %int to double
%fix = fdiv double %cvt, 128.0
ret double %fix
}
define double @scvtf_f64_i32_32(i32 %int) {
-; CHECK-SD-LABEL: scvtf_f64_i32_32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: scvtf d0, w0, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: scvtf_f64_i32_32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: scvtf d0, w0
-; CHECK-GI-NEXT: mov x8, #4751297606875873280 // =0x41f0000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fdiv d0, d0, d1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: scvtf_f64_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf d0, w0, #32
+; CHECK-NEXT: ret
%cvt = sitofp i32 %int to double
%fix = fdiv double %cvt, 4294967296.0
ret double %fix
}
define double @scvtf_f64_i64_7(i64 %long) {
-; CHECK-SD-LABEL: scvtf_f64_i64_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: scvtf d0, x0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: scvtf_f64_i64_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: scvtf d0, x0
-; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x4060000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fdiv d0, d0, d1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: scvtf_f64_i64_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf d0, x0, #7
+; CHECK-NEXT: ret
%cvt = sitofp i64 %long to double
%fix = fdiv double %cvt, 128.0
ret double %fix
}
define double @scvtf_f64_i64_64(i64 %long) {
-; CHECK-SD-LABEL: scvtf_f64_i64_64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: scvtf d0, x0, #64
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: scvtf_f64_i64_64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: scvtf d0, x0
-; CHECK-GI-NEXT: mov x8, #4895412794951729152 // =0x43f0000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fdiv d0, d0, d1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: scvtf_f64_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf d0, x0, #64
+; CHECK-NEXT: ret
%cvt = sitofp i64 %long to double
%fix = fdiv double %cvt, 18446744073709551616.0
ret double %fix
@@ -802,10 +498,10 @@ define half @scvtf_f16_i32_7(i32 %int) {
; CHECK-SD-NO16-NEXT: fcvt h0, s0
; CHECK-SD-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: scvtf_f16_i32_7:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: scvtf h0, w0, #7
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-FP16-LABEL: scvtf_f16_i32_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: scvtf h0, w0, #7
+; CHECK-FP16-NEXT: ret
;
; CHECK-GI-NO16-LABEL: scvtf_f16_i32_7:
; CHECK-GI-NO16: // %bb.0:
@@ -816,14 +512,6 @@ define half @scvtf_f16_i32_7(i32 %int) {
; CHECK-GI-NO16-NEXT: fdiv s0, s1, s0
; CHECK-GI-NO16-NEXT: fcvt h0, s0
; CHECK-GI-NO16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: scvtf_f16_i32_7:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: scvtf h0, w0
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI39_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI39_0]
-; CHECK-GI-FP16-NEXT: fdiv h0, h0, h1
-; CHECK-GI-FP16-NEXT: ret
%cvt = sitofp i32 %int to half
%fix = fdiv half %cvt, 128.0
ret half %fix
@@ -840,10 +528,10 @@ define half @scvtf_f16_i32_15(i32 %int) {
; CHECK-SD-NO16-NEXT: fcvt h0, s0
; CHECK-SD-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: scvtf_f16_i32_15:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: scvtf h0, w0, #15
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-FP16-LABEL: scvtf_f16_i32_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: scvtf h0, w0, #15
+; CHECK-FP16-NEXT: ret
;
; CHECK-GI-NO16-LABEL: scvtf_f16_i32_15:
; CHECK-GI-NO16: // %bb.0:
@@ -854,14 +542,6 @@ define half @scvtf_f16_i32_15(i32 %int) {
; CHECK-GI-NO16-NEXT: fdiv s0, s1, s0
; CHECK-GI-NO16-NEXT: fcvt h0, s0
; CHECK-GI-NO16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: scvtf_f16_i32_15:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: scvtf h0, w0
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI40_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI40_0]
-; CHECK-GI-FP16-NEXT: fdiv h0, h0, h1
-; CHECK-GI-FP16-NEXT: ret
%cvt = sitofp i32 %int to half
%fix = fdiv half %cvt, 32768.0
ret half %fix
@@ -878,10 +558,10 @@ define half @scvtf_f16_i64_7(i64 %long) {
; CHECK-SD-NO16-NEXT: fcvt h0, s0
; CHECK-SD-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: scvtf_f16_i64_7:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: scvtf h0, x0, #7
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-FP16-LABEL: scvtf_f16_i64_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: scvtf h0, x0, #7
+; CHECK-FP16-NEXT: ret
;
; CHECK-GI-NO16-LABEL: scvtf_f16_i64_7:
; CHECK-GI-NO16: // %bb.0:
@@ -892,14 +572,6 @@ define half @scvtf_f16_i64_7(i64 %long) {
; CHECK-GI-NO16-NEXT: fdiv s0, s1, s0
; CHECK-GI-NO16-NEXT: fcvt h0, s0
; CHECK-GI-NO16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: scvtf_f16_i64_7:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: scvtf h0, x0
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI41_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI41_0]
-; CHECK-GI-FP16-NEXT: fdiv h0, h0, h1
-; CHECK-GI-FP16-NEXT: ret
%cvt = sitofp i64 %long to half
%fix = fdiv half %cvt, 128.0
ret half %fix
@@ -916,10 +588,10 @@ define half @scvtf_f16_i64_15(i64 %long) {
; CHECK-SD-NO16-NEXT: fcvt h0, s0
; CHECK-SD-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: scvtf_f16_i64_15:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: scvtf h0, x0, #15
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-FP16-LABEL: scvtf_f16_i64_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: scvtf h0, x0, #15
+; CHECK-FP16-NEXT: ret
;
; CHECK-GI-NO16-LABEL: scvtf_f16_i64_15:
; CHECK-GI-NO16: // %bb.0:
@@ -930,14 +602,6 @@ define half @scvtf_f16_i64_15(i64 %long) {
; CHECK-GI-NO16-NEXT: fdiv s0, s1, s0
; CHECK-GI-NO16-NEXT: fcvt h0, s0
; CHECK-GI-NO16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: scvtf_f16_i64_15:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: scvtf h0, x0
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI42_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI42_0]
-; CHECK-GI-FP16-NEXT: fdiv h0, h0, h1
-; CHECK-GI-FP16-NEXT: ret
%cvt = sitofp i64 %long to half
%fix = fdiv half %cvt, 32768.0
ret half %fix
@@ -946,142 +610,80 @@ define half @scvtf_f16_i64_15(i64 %long) {
; uitofp
define float @ucvtf_f32_i32_7(i32 %int) {
-; CHECK-SD-LABEL: ucvtf_f32_i32_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ucvtf s0, w0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: ucvtf_f32_i32_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v0.2s, #67, lsl #24
-; CHECK-GI-NEXT: ucvtf s1, w0
-; CHECK-GI-NEXT: fdiv s0, s1, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: ucvtf_f32_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf s0, w0, #7
+; CHECK-NEXT: ret
%cvt = uitofp i32 %int to float
%fix = fdiv float %cvt, 128.0
ret float %fix
}
define float @ucvtf_f32_i32_32(i32 %int) {
-; CHECK-SD-LABEL: ucvtf_f32_i32_32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ucvtf s0, w0, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: ucvtf_f32_i32_32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ucvtf s0, w0
-; CHECK-GI-NEXT: mov w8, #1333788672 // =0x4f800000
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: fdiv s0, s0, s1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: ucvtf_f32_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf s0, w0, #32
+; CHECK-NEXT: ret
%cvt = uitofp i32 %int to float
%fix = fdiv float %cvt, 4294967296.0
ret float %fix
}
define float @ucvtf_f32_i64_7(i64 %long) {
-; CHECK-SD-LABEL: ucvtf_f32_i64_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ucvtf s0, x0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: ucvtf_f32_i64_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v0.2s, #67, lsl #24
-; CHECK-GI-NEXT: ucvtf s1, x0
-; CHECK-GI-NEXT: fdiv s0, s1, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: ucvtf_f32_i64_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf s0, x0, #7
+; CHECK-NEXT: ret
%cvt = uitofp i64 %long to float
%fix = fdiv float %cvt, 128.0
ret float %fix
}
define float @ucvtf_f32_i64_64(i64 %long) {
-; CHECK-SD-LABEL: ucvtf_f32_i64_64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ucvtf s0, x0, #64
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: ucvtf_f32_i64_64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ucvtf s0, x0
-; CHECK-GI-NEXT: mov w8, #1602224128 // =0x5f800000
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: fdiv s0, s0, s1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: ucvtf_f32_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf s0, x0, #64
+; CHECK-NEXT: ret
%cvt = uitofp i64 %long to float
%fix = fdiv float %cvt, 18446744073709551616.0
ret float %fix
}
define double @ucvtf_f64_i32_7(i32 %int) {
-; CHECK-SD-LABEL: ucvtf_f64_i32_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ucvtf d0, w0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: ucvtf_f64_i32_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ucvtf d0, w0
-; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x4060000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fdiv d0, d0, d1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: ucvtf_f64_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf d0, w0, #7
+; CHECK-NEXT: ret
%cvt = uitofp i32 %int to double
%fix = fdiv double %cvt, 128.0
ret double %fix
}
define double @ucvtf_f64_i32_32(i32 %int) {
-; CHECK-SD-LABEL: ucvtf_f64_i32_32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ucvtf d0, w0, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: ucvtf_f64_i32_32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ucvtf d0, w0
-; CHECK-GI-NEXT: mov x8, #4751297606875873280 // =0x41f0000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fdiv d0, d0, d1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: ucvtf_f64_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf d0, w0, #32
+; CHECK-NEXT: ret
%cvt = uitofp i32 %int to double
%fix = fdiv double %cvt, 4294967296.0
ret double %fix
}
define double @ucvtf_f64_i64_7(i64 %long) {
-; CHECK-SD-LABEL: ucvtf_f64_i64_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ucvtf d0, x0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: ucvtf_f64_i64_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ucvtf d0, x0
-; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x4060000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fdiv d0, d0, d1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: ucvtf_f64_i64_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf d0, x0, #7
+; CHECK-NEXT: ret
%cvt = uitofp i64 %long to double
%fix = fdiv double %cvt, 128.0
ret double %fix
}
define double @ucvtf_f64_i64_64(i64 %long) {
-; CHECK-SD-LABEL: ucvtf_f64_i64_64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ucvtf d0, x0, #64
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: ucvtf_f64_i64_64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ucvtf d0, x0
-; CHECK-GI-NEXT: mov x8, #4895412794951729152 // =0x43f0000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fdiv d0, d0, d1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: ucvtf_f64_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf d0, x0, #64
+; CHECK-NEXT: ret
%cvt = uitofp i64 %long to double
%fix = fdiv double %cvt, 18446744073709551616.0
ret double %fix
@@ -1098,10 +700,10 @@ define half @ucvtf_f16_i32_7(i32 %int) {
; CHECK-SD-NO16-NEXT: fcvt h0, s0
; CHECK-SD-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: ucvtf_f16_i32_7:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: ucvtf h0, w0, #7
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-FP16-LABEL: ucvtf_f16_i32_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: ucvtf h0, w0, #7
+; CHECK-FP16-NEXT: ret
;
; CHECK-GI-NO16-LABEL: ucvtf_f16_i32_7:
; CHECK-GI-NO16: // %bb.0:
@@ -1112,14 +714,6 @@ define half @ucvtf_f16_i32_7(i32 %int) {
; CHECK-GI-NO16-NEXT: fdiv s0, s1, s0
; CHECK-GI-NO16-NEXT: fcvt h0, s0
; CHECK-GI-NO16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: ucvtf_f16_i32_7:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: ucvtf h0, w0
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI51_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI51_0]
-; CHECK-GI-FP16-NEXT: fdiv h0, h0, h1
-; CHECK-GI-FP16-NEXT: ret
%cvt = uitofp i32 %int to half
%fix = fdiv half %cvt, 128.0
ret half %fix
@@ -1136,10 +730,10 @@ define half @ucvtf_f16_i32_15(i32 %int) {
; CHECK-SD-NO16-NEXT: fcvt h0, s0
; CHECK-SD-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: ucvtf_f16_i32_15:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: ucvtf h0, w0, #15
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-FP16-LABEL: ucvtf_f16_i32_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: ucvtf h0, w0, #15
+; CHECK-FP16-NEXT: ret
;
; CHECK-GI-NO16-LABEL: ucvtf_f16_i32_15:
; CHECK-GI-NO16: // %bb.0:
@@ -1150,14 +744,6 @@ define half @ucvtf_f16_i32_15(i32 %int) {
; CHECK-GI-NO16-NEXT: fdiv s0, s1, s0
; CHECK-GI-NO16-NEXT: fcvt h0, s0
; CHECK-GI-NO16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: ucvtf_f16_i32_15:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: ucvtf h0, w0
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI52_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI52_0]
-; CHECK-GI-FP16-NEXT: fdiv h0, h0, h1
-; CHECK-GI-FP16-NEXT: ret
%cvt = uitofp i32 %int to half
%fix = fdiv half %cvt, 32768.0
ret half %fix
@@ -1174,10 +760,10 @@ define half @ucvtf_f16_i64_7(i64 %long) {
; CHECK-SD-NO16-NEXT: fcvt h0, s0
; CHECK-SD-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: ucvtf_f16_i64_7:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: ucvtf h0, x0, #7
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-FP16-LABEL: ucvtf_f16_i64_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: ucvtf h0, x0, #7
+; CHECK-FP16-NEXT: ret
;
; CHECK-GI-NO16-LABEL: ucvtf_f16_i64_7:
; CHECK-GI-NO16: // %bb.0:
@@ -1188,14 +774,6 @@ define half @ucvtf_f16_i64_7(i64 %long) {
; CHECK-GI-NO16-NEXT: fdiv s0, s1, s0
; CHECK-GI-NO16-NEXT: fcvt h0, s0
; CHECK-GI-NO16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: ucvtf_f16_i64_7:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: ucvtf h0, x0
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI53_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI53_0]
-; CHECK-GI-FP16-NEXT: fdiv h0, h0, h1
-; CHECK-GI-FP16-NEXT: ret
%cvt = uitofp i64 %long to half
%fix = fdiv half %cvt, 128.0
ret half %fix
@@ -1212,10 +790,10 @@ define half @ucvtf_f16_i64_15(i64 %long) {
; CHECK-SD-NO16-NEXT: fcvt h0, s0
; CHECK-SD-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: ucvtf_f16_i64_15:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: ucvtf h0, x0, #15
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-FP16-LABEL: ucvtf_f16_i64_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: ucvtf h0, x0, #15
+; CHECK-FP16-NEXT: ret
;
; CHECK-GI-NO16-LABEL: ucvtf_f16_i64_15:
; CHECK-GI-NO16: // %bb.0:
@@ -1226,14 +804,6 @@ define half @ucvtf_f16_i64_15(i64 %long) {
; CHECK-GI-NO16-NEXT: fdiv s0, s1, s0
; CHECK-GI-NO16-NEXT: fcvt h0, s0
; CHECK-GI-NO16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: ucvtf_f16_i64_15:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: ucvtf h0, x0
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI54_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI54_0]
-; CHECK-GI-FP16-NEXT: fdiv h0, h0, h1
-; CHECK-GI-FP16-NEXT: ret
%cvt = uitofp i64 %long to half
%fix = fdiv half %cvt, 32768.0
ret half %fix
@@ -1250,52 +820,30 @@ declare i32 @llvm.fptosi.sat.i32.f16(half)
declare i64 @llvm.fptosi.sat.i64.f16(half)
define i32 @fcvtzs_sat_f32_i32_7(float %flt) {
-; CHECK-SD-LABEL: fcvtzs_sat_f32_i32_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs w0, s0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_sat_f32_i32_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2s, #67, lsl #24
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzs w0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_sat_f32_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs w0, s0, #7
+; CHECK-NEXT: ret
%fix = fmul float %flt, 128.0
%cvt = call i32 @llvm.fptosi.sat.i32.f32(float %fix)
ret i32 %cvt
}
define i32 @fcvtzs_sat_f32_i32_32(float %flt) {
-; CHECK-SD-LABEL: fcvtzs_sat_f32_i32_32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs w0, s0, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_sat_f32_i32_32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #1333788672 // =0x4f800000
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzs w0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_sat_f32_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs w0, s0, #32
+; CHECK-NEXT: ret
%fix = fmul float %flt, 4294967296.0
%cvt = call i32 @llvm.fptosi.sat.i32.f32(float %fix)
ret i32 %cvt
}
define float @fcvtzs_sat_f32_i32_7_fpr(float %flt) {
-; CHECK-SD-LABEL: fcvtzs_sat_f32_i32_7_fpr:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs s0, s0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_sat_f32_i32_7_fpr:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2s, #67, lsl #24
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzs s0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_sat_f32_i32_7_fpr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs s0, s0, #7
+; CHECK-NEXT: ret
%fix = fmul float %flt, 128.0
%cvt = call i32 @llvm.fptosi.sat.i32.f32(float %fix)
%bc = bitcast i32 %cvt to float
@@ -1303,18 +851,10 @@ define float @fcvtzs_sat_f32_i32_7_fpr(float %flt) {
}
define float @fcvtzs_sat_f32_i32_32_fpr(float %flt) {
-; CHECK-SD-LABEL: fcvtzs_sat_f32_i32_32_fpr:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs s0, s0, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_sat_f32_i32_32_fpr:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #1333788672 // =0x4f800000
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzs s0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_sat_f32_i32_32_fpr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs s0, s0, #32
+; CHECK-NEXT: ret
%fix = fmul float %flt, 4294967296.0
%cvt = call i32 @llvm.fptosi.sat.i32.f32(float %fix)
%bc = bitcast i32 %cvt to float
@@ -1322,108 +862,60 @@ define float @fcvtzs_sat_f32_i32_32_fpr(float %flt) {
}
define i64 @fcvtzs_sat_f32_i64_64(float %flt) {
-; CHECK-SD-LABEL: fcvtzs_sat_f32_i64_64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs x0, s0, #64
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_sat_f32_i64_64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #1602224128 // =0x5f800000
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzs x0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_sat_f32_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs x0, s0, #64
+; CHECK-NEXT: ret
%fix = fmul float %flt, 18446744073709551616.0
%cvt = call i64 @llvm.fptosi.sat.i64.f32(float %fix)
ret i64 %cvt
}
define i32 @fcvtzs_sat_f64_i32_7(double %dbl) {
-; CHECK-SD-LABEL: fcvtzs_sat_f64_i32_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs w0, d0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_sat_f64_i32_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x4060000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmul d0, d0, d1
-; CHECK-GI-NEXT: fcvtzs w0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_sat_f64_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs w0, d0, #7
+; CHECK-NEXT: ret
%fix = fmul double %dbl, 128.0
%cvt = call i32 @llvm.fptosi.sat.i32.f64(double %fix)
ret i32 %cvt
}
define i32 @fcvtzs_sat_f64_i32_32(double %dbl) {
-; CHECK-SD-LABEL: fcvtzs_sat_f64_i32_32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs w0, d0, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_sat_f64_i32_32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #4751297606875873280 // =0x41f0000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmul d0, d0, d1
-; CHECK-GI-NEXT: fcvtzs w0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_sat_f64_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs w0, d0, #32
+; CHECK-NEXT: ret
%fix = fmul double %dbl, 4294967296.0
%cvt = call i32 @llvm.fptosi.sat.i32.f64(double %fix)
ret i32 %cvt
}
define i64 @fcvtzs_sat_f64_i64_7(double %dbl) {
-; CHECK-SD-LABEL: fcvtzs_sat_f64_i64_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs x0, d0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_sat_f64_i64_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x4060000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmul d0, d0, d1
-; CHECK-GI-NEXT: fcvtzs x0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_sat_f64_i64_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs x0, d0, #7
+; CHECK-NEXT: ret
%fix = fmul double %dbl, 128.0
%cvt = call i64 @llvm.fptosi.sat.i64.f64(double %fix)
ret i64 %cvt
}
define i64 @fcvtzs_sat_f64_i64_64(double %dbl) {
-; CHECK-SD-LABEL: fcvtzs_sat_f64_i64_64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs x0, d0, #64
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_sat_f64_i64_64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #4895412794951729152 // =0x43f0000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmul d0, d0, d1
-; CHECK-GI-NEXT: fcvtzs x0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_sat_f64_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs x0, d0, #64
+; CHECK-NEXT: ret
%fix = fmul double %dbl, 18446744073709551616.0
%cvt = call i64 @llvm.fptosi.sat.i64.f64(double %fix)
ret i64 %cvt
}
define double @fcvtzs_sat_f64_i64_7_fpr(double %dbl) {
-; CHECK-SD-LABEL: fcvtzs_sat_f64_i64_7_fpr:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs d0, d0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_sat_f64_i64_7_fpr:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x4060000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmul d0, d0, d1
-; CHECK-GI-NEXT: fcvtzs d0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_sat_f64_i64_7_fpr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs d0, d0, #7
+; CHECK-NEXT: ret
%fix = fmul double %dbl, 128.0
%cvt = call i64 @llvm.fptosi.sat.i64.f64(double %fix)
%bc = bitcast i64 %cvt to double
@@ -1431,18 +923,10 @@ define double @fcvtzs_sat_f64_i64_7_fpr(double %dbl) {
}
define double @fcvtzs_sat_f64_i64_64_fpr(double %dbl) {
-; CHECK-SD-LABEL: fcvtzs_sat_f64_i64_64_fpr:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs d0, d0, #64
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_sat_f64_i64_64_fpr:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #4895412794951729152 // =0x43f0000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmul d0, d0, d1
-; CHECK-GI-NEXT: fcvtzs d0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_sat_f64_i64_64_fpr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs d0, d0, #64
+; CHECK-NEXT: ret
%fix = fmul double %dbl, 18446744073709551616.0
%cvt = call i64 @llvm.fptosi.sat.i64.f64(double %fix)
%bc = bitcast i64 %cvt to double
@@ -1461,18 +945,10 @@ define i32 @fcvtzs_sat_f16_i32_7(half %dbl) {
; CHECK-NO16-NEXT: fcvtzs w0, s0
; CHECK-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: fcvtzs_sat_f16_i32_7:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzs w0, h0, #7
-; CHECK-SD-FP16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: fcvtzs_sat_f16_i32_7:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI66_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI66_0]
-; CHECK-GI-FP16-NEXT: fmul h0, h0, h1
-; CHECK-GI-FP16-NEXT: fcvtzs w0, h0
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: fcvtzs_sat_f16_i32_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzs w0, h0, #7
+; CHECK-FP16-NEXT: ret
%fix = fmul half %dbl, 128.0
%cvt = call i32 @llvm.fptosi.sat.i32.f16(half %fix)
ret i32 %cvt
@@ -1489,18 +965,10 @@ define i32 @fcvtzs_sat_f16_i32_15(half %dbl) {
; CHECK-NO16-NEXT: fcvtzs w0, s0
; CHECK-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: fcvtzs_sat_f16_i32_15:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzs w0, h0, #15
-; CHECK-SD-FP16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: fcvtzs_sat_f16_i32_15:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI67_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI67_0]
-; CHECK-GI-FP16-NEXT: fmul h0, h0, h1
-; CHECK-GI-FP16-NEXT: fcvtzs w0, h0
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: fcvtzs_sat_f16_i32_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzs w0, h0, #15
+; CHECK-FP16-NEXT: ret
%fix = fmul half %dbl, 32768.0
%cvt = call i32 @llvm.fptosi.sat.i32.f16(half %fix)
ret i32 %cvt
@@ -1517,18 +985,10 @@ define i64 @fcvtzs_sat_f16_i64_7(half %dbl) {
; CHECK-NO16-NEXT: fcvtzs x0, s0
; CHECK-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: fcvtzs_sat_f16_i64_7:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzs x0, h0, #7
-; CHECK-SD-FP16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: fcvtzs_sat_f16_i64_7:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI68_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI68_0]
-; CHECK-GI-FP16-NEXT: fmul h0, h0, h1
-; CHECK-GI-FP16-NEXT: fcvtzs x0, h0
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: fcvtzs_sat_f16_i64_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzs x0, h0, #7
+; CHECK-FP16-NEXT: ret
%fix = fmul half %dbl, 128.0
%cvt = call i64 @llvm.fptosi.sat.i64.f16(half %fix)
ret i64 %cvt
@@ -1545,18 +1005,10 @@ define i64 @fcvtzs_sat_f16_i64_15(half %dbl) {
; CHECK-NO16-NEXT: fcvtzs x0, s0
; CHECK-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: fcvtzs_sat_f16_i64_15:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzs x0, h0, #15
-; CHECK-SD-FP16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: fcvtzs_sat_f16_i64_15:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI69_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI69_0]
-; CHECK-GI-FP16-NEXT: fmul h0, h0, h1
-; CHECK-GI-FP16-NEXT: fcvtzs x0, h0
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: fcvtzs_sat_f16_i64_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzs x0, h0, #15
+; CHECK-FP16-NEXT: ret
%fix = fmul half %dbl, 32768.0
%cvt = call i64 @llvm.fptosi.sat.i64.f16(half %fix)
ret i64 %cvt
@@ -1572,52 +1024,30 @@ declare i32 @llvm.fptoui.sat.i32.f16(half)
declare i64 @llvm.fptoui.sat.i64.f16(half)
define i32 @fcvtzu_sat_f32_i32_7(float %flt) {
-; CHECK-SD-LABEL: fcvtzu_sat_f32_i32_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu w0, s0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzu_sat_f32_i32_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2s, #67, lsl #24
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzu w0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzu_sat_f32_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu w0, s0, #7
+; CHECK-NEXT: ret
%fix = fmul float %flt, 128.0
%cvt = call i32 @llvm.fptoui.sat.i32.f32(float %fix)
ret i32 %cvt
}
define i32 @fcvtzu_sat_f32_i32_32(float %flt) {
-; CHECK-SD-LABEL: fcvtzu_sat_f32_i32_32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu w0, s0, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzu_sat_f32_i32_32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #1333788672 // =0x4f800000
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzu w0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzu_sat_f32_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu w0, s0, #32
+; CHECK-NEXT: ret
%fix = fmul float %flt, 4294967296.0
%cvt = call i32 @llvm.fptoui.sat.i32.f32(float %fix)
ret i32 %cvt
}
define float @fcvtzu_sat_f32_i32_7_fpr(float %flt) {
-; CHECK-SD-LABEL: fcvtzu_sat_f32_i32_7_fpr:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu s0, s0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzu_sat_f32_i32_7_fpr:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2s, #67, lsl #24
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzu s0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzu_sat_f32_i32_7_fpr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu s0, s0, #7
+; CHECK-NEXT: ret
%fix = fmul float %flt, 128.0
%cvt = call i32 @llvm.fptoui.sat.i32.f32(float %fix)
%bc = bitcast i32 %cvt to float
@@ -1625,18 +1055,10 @@ define float @fcvtzu_sat_f32_i32_7_fpr(float %flt) {
}
define float @fcvtzu_sat_f32_i32_32_fpr(float %flt) {
-; CHECK-SD-LABEL: fcvtzu_sat_f32_i32_32_fpr:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu s0, s0, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzu_sat_f32_i32_32_fpr:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #1333788672 // =0x4f800000
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzu s0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzu_sat_f32_i32_32_fpr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu s0, s0, #32
+; CHECK-NEXT: ret
%fix = fmul float %flt, 4294967296.0
%cvt = call i32 @llvm.fptoui.sat.i32.f32(float %fix)
%bc = bitcast i32 %cvt to float
@@ -1644,108 +1066,60 @@ define float @fcvtzu_sat_f32_i32_32_fpr(float %flt) {
}
define i64 @fcvtzu_sat_f32_i64_64(float %flt) {
-; CHECK-SD-LABEL: fcvtzu_sat_f32_i64_64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu x0, s0, #64
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzu_sat_f32_i64_64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #1602224128 // =0x5f800000
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzu x0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzu_sat_f32_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu x0, s0, #64
+; CHECK-NEXT: ret
%fix = fmul float %flt, 18446744073709551616.0
%cvt = call i64 @llvm.fptoui.sat.i64.f32(float %fix)
ret i64 %cvt
}
define i32 @fcvtzu_sat_f64_i32_7(double %dbl) {
-; CHECK-SD-LABEL: fcvtzu_sat_f64_i32_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu w0, d0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzu_sat_f64_i32_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x4060000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmul d0, d0, d1
-; CHECK-GI-NEXT: fcvtzu w0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzu_sat_f64_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu w0, d0, #7
+; CHECK-NEXT: ret
%fix = fmul double %dbl, 128.0
%cvt = call i32 @llvm.fptoui.sat.i32.f64(double %fix)
ret i32 %cvt
}
define i32 @fcvtzu_sat_f64_i32_32(double %dbl) {
-; CHECK-SD-LABEL: fcvtzu_sat_f64_i32_32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu w0, d0, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzu_sat_f64_i32_32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #4751297606875873280 // =0x41f0000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmul d0, d0, d1
-; CHECK-GI-NEXT: fcvtzu w0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzu_sat_f64_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu w0, d0, #32
+; CHECK-NEXT: ret
%fix = fmul double %dbl, 4294967296.0
%cvt = call i32 @llvm.fptoui.sat.i32.f64(double %fix)
ret i32 %cvt
}
define i64 @fcvtzu_sat_f64_i64_7(double %dbl) {
-; CHECK-SD-LABEL: fcvtzu_sat_f64_i64_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu x0, d0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzu_sat_f64_i64_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x4060000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmul d0, d0, d1
-; CHECK-GI-NEXT: fcvtzu x0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzu_sat_f64_i64_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu x0, d0, #7
+; CHECK-NEXT: ret
%fix = fmul double %dbl, 128.0
%cvt = call i64 @llvm.fptoui.sat.i64.f64(double %fix)
ret i64 %cvt
}
define i64 @fcvtzu_sat_f64_i64_64(double %dbl) {
-; CHECK-SD-LABEL: fcvtzu_sat_f64_i64_64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu x0, d0, #64
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzu_sat_f64_i64_64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #4895412794951729152 // =0x43f0000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmul d0, d0, d1
-; CHECK-GI-NEXT: fcvtzu x0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzu_sat_f64_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu x0, d0, #64
+; CHECK-NEXT: ret
%fix = fmul double %dbl, 18446744073709551616.0
%cvt = call i64 @llvm.fptoui.sat.i64.f64(double %fix)
ret i64 %cvt
}
define double @fcvtzu_sat_f64_i64_7_fpr(double %dbl) {
-; CHECK-SD-LABEL: fcvtzu_sat_f64_i64_7_fpr:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu d0, d0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzu_sat_f64_i64_7_fpr:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x4060000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmul d0, d0, d1
-; CHECK-GI-NEXT: fcvtzu d0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzu_sat_f64_i64_7_fpr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu d0, d0, #7
+; CHECK-NEXT: ret
%fix = fmul double %dbl, 128.0
%cvt = call i64 @llvm.fptoui.sat.i64.f64(double %fix)
%bc = bitcast i64 %cvt to double
@@ -1753,18 +1127,10 @@ define double @fcvtzu_sat_f64_i64_7_fpr(double %dbl) {
}
define double @fcvtzu_sat_f64_i64_64_fpr(double %dbl) {
-; CHECK-SD-LABEL: fcvtzu_sat_f64_i64_64_fpr:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu d0, d0, #64
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzu_sat_f64_i64_64_fpr:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #4895412794951729152 // =0x43f0000000000000
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmul d0, d0, d1
-; CHECK-GI-NEXT: fcvtzu d0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzu_sat_f64_i64_64_fpr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu d0, d0, #64
+; CHECK-NEXT: ret
%fix = fmul double %dbl, 18446744073709551616.0
%cvt = call i64 @llvm.fptoui.sat.i64.f64(double %fix)
%bc = bitcast i64 %cvt to double
@@ -1783,18 +1149,10 @@ define i32 @fcvtzu_sat_f16_i32_7(half %dbl) {
; CHECK-NO16-NEXT: fcvtzu w0, s0
; CHECK-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: fcvtzu_sat_f16_i32_7:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzu w0, h0, #7
-; CHECK-SD-FP16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: fcvtzu_sat_f16_i32_7:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI81_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI81_0]
-; CHECK-GI-FP16-NEXT: fmul h0, h0, h1
-; CHECK-GI-FP16-NEXT: fcvtzu w0, h0
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: fcvtzu_sat_f16_i32_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzu w0, h0, #7
+; CHECK-FP16-NEXT: ret
%fix = fmul half %dbl, 128.0
%cvt = call i32 @llvm.fptoui.sat.i32.f16(half %fix)
ret i32 %cvt
@@ -1811,18 +1169,10 @@ define i32 @fcvtzu_sat_f16_i32_15(half %dbl) {
; CHECK-NO16-NEXT: fcvtzu w0, s0
; CHECK-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: fcvtzu_sat_f16_i32_15:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzu w0, h0, #15
-; CHECK-SD-FP16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: fcvtzu_sat_f16_i32_15:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI82_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI82_0]
-; CHECK-GI-FP16-NEXT: fmul h0, h0, h1
-; CHECK-GI-FP16-NEXT: fcvtzu w0, h0
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: fcvtzu_sat_f16_i32_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzu w0, h0, #15
+; CHECK-FP16-NEXT: ret
%fix = fmul half %dbl, 32768.0
%cvt = call i32 @llvm.fptoui.sat.i32.f16(half %fix)
ret i32 %cvt
@@ -1839,18 +1189,10 @@ define i64 @fcvtzu_sat_f16_i64_7(half %dbl) {
; CHECK-NO16-NEXT: fcvtzu x0, s0
; CHECK-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: fcvtzu_sat_f16_i64_7:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzu x0, h0, #7
-; CHECK-SD-FP16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: fcvtzu_sat_f16_i64_7:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI83_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI83_0]
-; CHECK-GI-FP16-NEXT: fmul h0, h0, h1
-; CHECK-GI-FP16-NEXT: fcvtzu x0, h0
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: fcvtzu_sat_f16_i64_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzu x0, h0, #7
+; CHECK-FP16-NEXT: ret
%fix = fmul half %dbl, 128.0
%cvt = call i64 @llvm.fptoui.sat.i64.f16(half %fix)
ret i64 %cvt
@@ -1867,70 +1209,40 @@ define i64 @fcvtzu_sat_f16_i64_15(half %dbl) {
; CHECK-NO16-NEXT: fcvtzu x0, s0
; CHECK-NO16-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: fcvtzu_sat_f16_i64_15:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzu x0, h0, #15
-; CHECK-SD-FP16-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: fcvtzu_sat_f16_i64_15:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: adrp x8, .LCPI84_0
-; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI84_0]
-; CHECK-GI-FP16-NEXT: fmul h0, h0, h1
-; CHECK-GI-FP16-NEXT: fcvtzu x0, h0
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: fcvtzu_sat_f16_i64_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzu x0, h0, #15
+; CHECK-FP16-NEXT: ret
%fix = fmul half %dbl, 32768.0
%cvt = call i64 @llvm.fptoui.sat.i64.f16(half %fix)
ret i64 %cvt
}
define i32 @neon_fcvtzs_f32_i32_7(float %a) {
-; CHECK-SD-LABEL: neon_fcvtzs_f32_i32_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs w0, s0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: neon_fcvtzs_f32_i32_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2s, #67, lsl #24
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzs w0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: neon_fcvtzs_f32_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs w0, s0, #7
+; CHECK-NEXT: ret
%mul = fmul float %a, 128.0
%r = call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %mul)
ret i32 %r
}
define i32 @neon_fcvtzs_f32_i32_32(float %a) {
-; CHECK-SD-LABEL: neon_fcvtzs_f32_i32_32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs w0, s0, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: neon_fcvtzs_f32_i32_32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #1333788672 // =0x4f800000
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzs w0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: neon_fcvtzs_f32_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs w0, s0, #32
+; CHECK-NEXT: ret
%mul = fmul float %a, 4294967296.0
%r = call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %mul)
ret i32 %r
}
define float @neon_fcvtzs_f32_i32_7_bitcast(float %a) {
-; CHECK-SD-LABEL: neon_fcvtzs_f32_i32_7_bitcast:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs s0, s0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: neon_fcvtzs_f32_i32_7_bitcast:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2s, #67, lsl #24
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzs s0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: neon_fcvtzs_f32_i32_7_bitcast:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs s0, s0, #7
+; CHECK-NEXT: ret
%mul = fmul float %a, 128.0
%r = call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %mul)
%bc = bitcast i32 %r to float
@@ -1938,18 +1250,10 @@ define float @neon_fcvtzs_f32_i32_7_bitcast(float %a) {
}
define float @neon_fcvtzs_f32_i32_32_bitcast(float %a) {
-; CHECK-SD-LABEL: neon_fcvtzs_f32_i32_32_bitcast:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs s0, s0, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: neon_fcvtzs_f32_i32_32_bitcast:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #1333788672 // =0x4f800000
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzs s0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: neon_fcvtzs_f32_i32_32_bitcast:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs s0, s0, #32
+; CHECK-NEXT: ret
%mul = fmul float %a, 4294967296.0
%r = call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %mul)
%bc = bitcast i32 %r to float
@@ -1957,52 +1261,30 @@ define float @neon_fcvtzs_f32_i32_32_bitcast(float %a) {
}
define i32 @neon_fcvtzu_f32_i32_7(float %a) {
-; CHECK-SD-LABEL: neon_fcvtzu_f32_i32_7:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu w0, s0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: neon_fcvtzu_f32_i32_7:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2s, #67, lsl #24
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzu w0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: neon_fcvtzu_f32_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu w0, s0, #7
+; CHECK-NEXT: ret
%mul = fmul float %a, 128.0
%r = call i32 @llvm.aarch64.neon.fcvtzu.i32.f32(float %mul)
ret i32 %r
}
define i32 @neon_fcvtzu_f32_i32_32(float %a) {
-; CHECK-SD-LABEL: neon_fcvtzu_f32_i32_32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu w0, s0, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: neon_fcvtzu_f32_i32_32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #1333788672 // =0x4f800000
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzu w0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: neon_fcvtzu_f32_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu w0, s0, #32
+; CHECK-NEXT: ret
%mul = fmul float %a, 4294967296.0
%r = call i32 @llvm.aarch64.neon.fcvtzu.i32.f32(float %mul)
ret i32 %r
}
define float @neon_fcvtzu_f32_i32_7_bitcast(float %a) {
-; CHECK-SD-LABEL: neon_fcvtzu_f32_i32_7_bitcast:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu s0, s0, #7
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: neon_fcvtzu_f32_i32_7_bitcast:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2s, #67, lsl #24
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzu s0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: neon_fcvtzu_f32_i32_7_bitcast:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu s0, s0, #7
+; CHECK-NEXT: ret
%mul = fmul float %a, 128.0
%r = call i32 @llvm.aarch64.neon.fcvtzu.i32.f32(float %mul)
%bc = bitcast i32 %r to float
@@ -2010,18 +1292,10 @@ define float @neon_fcvtzu_f32_i32_7_bitcast(float %a) {
}
define float @neon_fcvtzu_f32_i32_32_bitcast(float %a) {
-; CHECK-SD-LABEL: neon_fcvtzu_f32_i32_32_bitcast:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu s0, s0, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: neon_fcvtzu_f32_i32_32_bitcast:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #1333788672 // =0x4f800000
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fcvtzu s0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: neon_fcvtzu_f32_i32_32_bitcast:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu s0, s0, #32
+; CHECK-NEXT: ret
%mul = fmul float %a, 4294967296.0
%r = call i32 @llvm.aarch64.neon.fcvtzu.i32.f32(float %mul)
%bc = bitcast i32 %r to float
@@ -2029,5 +1303,7 @@ define float @neon_fcvtzu_f32_i32_32_bitcast(float %a) {
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK: {{.*}}
-; CHECK-FP16: {{.*}}
+; CHECK-GI: {{.*}}
+; CHECK-GI-FP16: {{.*}}
+; CHECK-SD: {{.*}}
+; CHECK-SD-FP16: {{.*}}
>From ed654e1768d525beefcc0a3c5ff0689921f5a698 Mon Sep 17 00:00:00 2001
From: Kieran Bailey <kieran.bailey at arm.com>
Date: Fri, 21 Aug 2026 10:09:29 +0000
Subject: [PATCH 2/2] Remove redundant Renderers Refactor function/variable
names
---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 45 ++++++----------
.../GISel/AArch64InstructionSelector.cpp | 51 ++++---------------
llvm/test/CodeGen/AArch64/fcvt-fixed.ll | 14 ++---
3 files changed, 30 insertions(+), 80 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 0e237389f8ecd..14cddb7b8da75 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -6858,24 +6858,17 @@ multiclass FPToIntegerIntPats<Intrinsic round, string INST> {
defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzs, "FCVTZS">;
defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzu, "FCVTZU">;
-// These are split by fixed-point width so GlobalISel can route each
-// transformed operand to a renderer that checks the correct #fbits range.
-def fixedpoint_xform32 : SDNodeXForm<timm, [{
- (void)N;
- return V;
-}]>;
-def gi_fixedpoint_xform32 : GICustomOperandRenderer<"renderFixedPointXForm32">,
- GISDNodeXFormEquiv<fixedpoint_xform32>;
-
-def fixedpoint_xform64 : SDNodeXForm<timm, [{
+// This thing just allows us to change the type of the node produced. The imm
+// value we want is already in V from SelectCVTFixedPointVec.
+def fixedpoint_xform : SDNodeXForm<timm, [{
(void)N;
return V;
}]>;
-def gi_fixedpoint_xform64 : GICustomOperandRenderer<"renderFixedPointXForm64">,
- GISDNodeXFormEquiv<fixedpoint_xform64>;
+def gi_fixedpoint_xform : GICustomOperandRenderer<"renderFixedPointXForm">,
+ GISDNodeXFormEquiv<fixedpoint_xform>;
def gi_fixedpoint_f16_i32 : GIComplexOperandMatcher<s32, "selectCVTFixedPoint<32>">,
- GIComplexPatternEquiv<fixedpoint_f16_i32>;
+ GIComplexPatternEquiv<fixedpoint_f16_i32>;
def gi_fixedpoint_f16_i64 : GIComplexOperandMatcher<s32, "selectCVTFixedPoint<64>">,
GIComplexPatternEquiv<fixedpoint_f16_i64>;
def gi_fixedpoint_f32_i32 : GIComplexOperandMatcher<s32, "selectCVTFixedPoint<32>">,
@@ -6904,9 +6897,9 @@ multiclass FPToIntegerFmulPats<SDPatternOperator round, string INST> {
(!cast<Instruction>(INST # SXDri) $Rn, $scale)>;
def : Pat<(f32 (bitconvert (i32 (round (fmul FPR32:$Rn, fixedpoint_f32_i32:$scale))))),
- (!cast<Instruction>(INST # "s") FPR32:$Rn, (fixedpoint_xform32 fixedpoint_f32_i32:$scale))>;
+ (!cast<Instruction>(INST # "s") FPR32:$Rn, (fixedpoint_xform fixedpoint_f32_i32:$scale))>;
def : Pat<(f64 (bitconvert (i64 (round (fmul FPR64:$Rn, fixedpoint_f64_i64:$scale))))),
- (!cast<Instruction>(INST # "d") FPR64:$Rn, (fixedpoint_xform64 fixedpoint_f64_i64:$scale))>;
+ (!cast<Instruction>(INST # "d") FPR64:$Rn, (fixedpoint_xform fixedpoint_f64_i64:$scale))>;
}
defm : FPToIntegerFmulPats<any_fp_to_sint, "FCVTZS">;
@@ -6985,9 +6978,9 @@ multiclass FPToIntegerSatPats<SDNode to_int_sat, string INST> {
(!cast<Instruction>(INST # SXDri) $Rn, fixedpoint_f64_i64:$scale)>;
def : Pat<(f32 (bitconvert (i32 (to_int_sat (fmul FPR32:$Rn, fixedpoint_f32_i32:$scale), i32)))),
- (!cast<Instruction>(INST # "s") FPR32:$Rn, (fixedpoint_xform32 fixedpoint_f32_i32:$scale))>;
+ (!cast<Instruction>(INST # "s") FPR32:$Rn, (fixedpoint_xform fixedpoint_f32_i32:$scale))>;
def : Pat<(f64 (bitconvert (i64 (to_int_sat (fmul FPR64:$Rn, fixedpoint_f64_i64:$scale), i64)))),
- (!cast<Instruction>(INST # "d") FPR64:$Rn, (fixedpoint_xform64 fixedpoint_f64_i64:$scale))>;
+ (!cast<Instruction>(INST # "d") FPR64:$Rn, (fixedpoint_xform fixedpoint_f64_i64:$scale))>;
}
defm : FPToIntegerSatPats<fp_to_sint_sat, "FCVTZS">;
@@ -9344,14 +9337,6 @@ class fixedpoint_vec_f32<ValueType FloatVT>
: ComplexPattern<FloatVT, 1, "SelectCVTFixedPointVec<32>">;
class fixedpoint_vec_f16<ValueType FloatVT>
: ComplexPattern<FloatVT, 1, "SelectCVTFixedPointVec<16>">;
-// This thing just allows us to change the type of the node produced. The imm
-// value we want is already in V from SelectCVTFixedPointVec.
-def fixedpoint_vec_xform : SDNodeXForm<timm, [{
- (void)N;
- return V;
-}]>;
-def gi_fixedpoint_vec_xform : GICustomOperandRenderer<"renderFixedPointXFormVec">,
- GISDNodeXFormEquiv<fixedpoint_vec_xform>;
def fixedpoint_v2f64 : fixedpoint_vec_f64<v2f64>;
def fixedpoint_v2f32 : fixedpoint_vec_f32<v2f32>;
@@ -9401,15 +9386,15 @@ multiclass FCVTPat<ValueType FVT, ValueType IVT, ValueType ScalarVT, RegisterOpe
// fptosi(fmul(x, power2)) -> FCVTZS_shift x, log2(power2)
def : Pat<(IVT (fp_to_sint (FVT (fmul FVT:$Vn, fixedpoint:$scale)))),
- (!cast<Instruction>("FCVTZS"#IVT#"_shift") $Vn, (fixedpoint_vec_xform fixedpoint:$scale))>;
+ (!cast<Instruction>("FCVTZS"#IVT#"_shift") $Vn, (fixedpoint_xform fixedpoint:$scale))>;
def : Pat<(IVT (fp_to_sint_sat (FVT (fmul FVT:$Vn, fixedpoint:$scale)), ScalarVT)),
- (!cast<Instruction>("FCVTZS"#IVT#"_shift") $Vn, (fixedpoint_vec_xform fixedpoint:$scale))>;
+ (!cast<Instruction>("FCVTZS"#IVT#"_shift") $Vn, (fixedpoint_xform fixedpoint:$scale))>;
// fptoui(fmul(x, power2)) -> FCVTZU_shift x, log2(power2)
def : Pat<(IVT (fp_to_uint (FVT (fmul FVT:$Vn, fixedpoint:$scale)))),
- (!cast<Instruction>("FCVTZU"#IVT#"_shift") $Vn, (fixedpoint_vec_xform fixedpoint:$scale))>;
+ (!cast<Instruction>("FCVTZU"#IVT#"_shift") $Vn, (fixedpoint_xform fixedpoint:$scale))>;
def : Pat<(IVT (fp_to_uint_sat (FVT (fmul FVT:$Vn, fixedpoint:$scale)), ScalarVT)),
- (!cast<Instruction>("FCVTZU"#IVT#"_shift") $Vn, (fixedpoint_vec_xform fixedpoint:$scale))>;
+ (!cast<Instruction>("FCVTZU"#IVT#"_shift") $Vn, (fixedpoint_xform fixedpoint:$scale))>;
}
let Predicates = [HasNEON] in {
@@ -9434,7 +9419,7 @@ def fixedpoint_recip_vec_xform : SDNodeXForm<timm, [{
return V;
}]>;
def gi_fixedpoint_recip_vec_xform
- : GICustomOperandRenderer<"renderFixedPointRecipXFormVec">,
+ : GICustomOperandRenderer<"renderFixedPointRecipXForm">,
GISDNodeXFormEquiv<fixedpoint_recip_vec_xform>;
def fixedpoint_recip_v2f64 : fixedpoint_recip_vec_f64<v2f64>;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 4af71cf942f02..613945a563dd4 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -492,18 +492,10 @@ class AArch64InstructionSelector : public InstructionSelector {
void renderFixedPointScalarXForm(MachineInstrBuilder &MIB,
const MachineInstr &MI, int OpIdx) const;
unsigned getFixedPointWidthFromOperand(const MachineOperand &Root) const;
- template <unsigned Width>
void renderFixedPointXForm(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx = -1) const;
- void renderFixedPointXForm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
- int OpIdx = -1) const;
- void renderFixedPointXForm64(MachineInstrBuilder &MIB, const MachineInstr &MI,
- int OpIdx = -1) const;
- void renderFixedPointXFormVec(MachineInstrBuilder &MIB,
- const MachineInstr &MI, int OpIdx = -1) const;
- void renderFixedPointRecipXFormVec(MachineInstrBuilder &MIB,
- const MachineInstr &MI,
- int OpIdx = -1) const;
+ void renderFixedPointRecipXForm(MachineInstrBuilder &MIB,
+ const MachineInstr &MI, int OpIdx = -1) const;
void renderFixedPointImm(MachineInstrBuilder &MIB, const MachineOperand &Root,
unsigned Width, bool isReciprocal) const;
void renderTruncImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
@@ -7931,7 +7923,7 @@ AArch64InstructionSelector::selectExtractHigh(MachineOperand &Root) const {
InstructionSelector::ComplexRendererFns
AArch64InstructionSelector::selectCVTFixedPointBase(const MachineOperand &Root,
- unsigned DstElementWidth,
+ unsigned DstElemWidth,
bool isReciprocal) const {
if (!Root.isReg())
return std::nullopt;
@@ -7950,9 +7942,9 @@ AArch64InstructionSelector::selectCVTFixedPointBase(const MachineOperand &Root,
if (!CstVal)
return std::nullopt;
- unsigned SrcElementWidth = MRI.getType(Reg).getScalarSizeInBits();
+ unsigned CstElemWidth = MRI.getType(Reg).getScalarSizeInBits();
APFloat FVal(0.0);
- switch (SrcElementWidth) {
+ switch (CstElemWidth) {
case 16:
FVal = APFloat(APFloat::IEEEhalf(), CstVal->Value);
break;
@@ -7966,7 +7958,7 @@ AArch64InstructionSelector::selectCVTFixedPointBase(const MachineOperand &Root,
return std::nullopt;
};
if (unsigned FBits =
- CheckFixedPointOperandConstant(FVal, DstElementWidth, isReciprocal))
+ CheckFixedPointOperandConstant(FVal, DstElemWidth, isReciprocal))
return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(FBits); }}};
return std::nullopt;
@@ -8021,40 +8013,19 @@ void AArch64InstructionSelector::renderFixedPointImm(MachineInstrBuilder &MIB,
(Renderer->front())(MIB);
}
-template <unsigned Width>
void AArch64InstructionSelector::renderFixedPointXForm(MachineInstrBuilder &MIB,
const MachineInstr &MI,
int OpIdx) const {
- renderFixedPointImm(MIB, MI.getOperand(OpIdx), Width,
- /*isReciprocal*/ false);
-}
-
-void AArch64InstructionSelector::renderFixedPointXForm32(
- MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const {
- // GIsel Renderers cannot use templates in .td so function name used to pass
- // the width
- renderFixedPointXForm<32>(MIB, MI, OpIdx);
-}
-
-void AArch64InstructionSelector::renderFixedPointXForm64(
- MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const {
- renderFixedPointXForm<64>(MIB, MI, OpIdx);
-}
-
-void AArch64InstructionSelector::renderFixedPointXFormVec(
- MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const {
const MachineOperand &Root = MI.getOperand(OpIdx);
- unsigned Width = getFixedPointWidthFromOperand(Root);
-
- renderFixedPointImm(MIB, Root, Width, /*isReciprocal*/ false);
+ renderFixedPointImm(MIB, Root, getFixedPointWidthFromOperand(Root),
+ /*isReciprocal*/ false);
}
-void AArch64InstructionSelector::renderFixedPointRecipXFormVec(
+void AArch64InstructionSelector::renderFixedPointRecipXForm(
MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const {
const MachineOperand &Root = MI.getOperand(OpIdx);
- unsigned Width = getFixedPointWidthFromOperand(Root);
-
- renderFixedPointImm(MIB, Root, Width, /*isReciprocal*/ true);
+ renderFixedPointImm(MIB, Root, getFixedPointWidthFromOperand(Root),
+ /*isReciprocal*/ true);
}
void AArch64InstructionSelector::renderTruncImm(MachineInstrBuilder &MIB,
diff --git a/llvm/test/CodeGen/AArch64/fcvt-fixed.ll b/llvm/test/CodeGen/AArch64/fcvt-fixed.ll
index 68abb738739a3..f42071126df1b 100644
--- a/llvm/test/CodeGen/AArch64/fcvt-fixed.ll
+++ b/llvm/test/CodeGen/AArch64/fcvt-fixed.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-NO16,CHECK-SD-NO16
-; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-FP16,CHECK-SD-FP16
-; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-NO16,CHECK-GI-NO16
-; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=+fullfp16 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-FP16,CHECK-GI-FP16
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECK-NO16,CHECK-SD-NO16
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-NO16,CHECK-GI-NO16
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=+fullfp16 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
; fptoui
@@ -1301,9 +1301,3 @@ define float @neon_fcvtzu_f32_i32_32_bitcast(float %a) {
%bc = bitcast i32 %r to float
ret float %bc
}
-
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK-GI: {{.*}}
-; CHECK-GI-FP16: {{.*}}
-; CHECK-SD: {{.*}}
-; CHECK-SD-FP16: {{.*}}
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