[clang] [llvm] [Mips] Support reserving GPRs with -ffixed-N (PR #217013)

via llvm-commits llvm-commits at lists.llvm.org
Fri Aug 21 01:04:07 PDT 2026


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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


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``````````bash
git-clang-format --diff origin/main HEAD --extensions h,c,cpp -- clang/test/CodeGen/Mips/fixed-register-global.c clang/test/Driver/mips-fixed-register.c clang/lib/Driver/ToolChains/Arch/Mips.cpp llvm/lib/Target/Mips/MipsISelLowering.cpp llvm/lib/Target/Mips/MipsRegisterInfo.cpp llvm/lib/Target/Mips/MipsSubtarget.h --diff_from_common_commit
``````````

:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index a374cce44..8c5399da4 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -5001,8 +5001,7 @@ MipsTargetLowering::getRegisterByName(const char *RegName, LLT VT,
                                     ? MRI->getRegClass(Mips::GPR64RegClassID)
                                     : MRI->getRegClass(Mips::GPR32RegClassID);
     Register Reg = RC.getRegister(RegIdx);
-    BitVector ReservedRegs =
-        Subtarget.getRegisterInfo()->getReservedRegs(MF);
+    BitVector ReservedRegs = Subtarget.getRegisterInfo()->getReservedRegs(MF);
     if (!ReservedRegs.test(Reg))
       reportFatalUsageError(Twine("Trying to obtain non-reserved register \"" +
                                   StringRef(RegName) + "\"."));

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https://github.com/llvm/llvm-project/pull/217013


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