[llvm] [RISCV][GlobalISel] Legalize readcyclecounter/readsteadycounter (PR #217535)

[Matt Arsenault via llvm-commits]

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@@ -956,32 +956,31 @@ bool RISCVLegalizerInfo::legalizeReadCounter(
     MRI.setRegClass(R, &RISCV::GPRRegClass);
     return R;
   };
-  Register HiReg = CreateGPR();
   Register LoReg = CreateGPR();
+  Register HiReg = CreateGPR();
   Register ReadAgainReg = CreateGPR();
 
   // read:
   //   csrrs HiReg, counterh    # high word
   //   csrrs LoReg, counter     # low word
   //   csrrs ReadAgainReg, counterh
   //   bne   HiReg, ReadAgainReg, read
-  // Build the target instructions fully before inserting so the change
-  // observer (CSEInfo) and the legalizer worklist see their final form;
-  // raw BuildMI or chaining after insertInstr would bypass the observer.
-  MIRBuilder.setInsertPt(*LoopMBB, LoopMBB->begin());
-  MIRBuilder.setDebugLoc(DL);
-  auto BuildCSRRS = [&](Register Dst, int64_t Csr) {
-    MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(RISCV::CSRRS);
-    MIB.addReg(Dst, RegState::Define).addImm(Csr).addReg(RISCV::X0);
-    MIRBuilder.insertInstr(MIB);
-  };
-  BuildCSRRS(HiReg, HiCounter);
-  BuildCSRRS(LoReg, LoCounter);
-  BuildCSRRS(ReadAgainReg, HiCounter);
-
-  MachineInstrBuilder BNE = MIRBuilder.buildInstrNoInsert(RISCV::BNE);
-  BNE.addReg(HiReg).addReg(ReadAgainReg).addMBB(LoopMBB);
-  MIRBuilder.insertInstr(BNE);
+  // Emit the target instructions directly with BuildMI.
+  const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
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arsenm wrote:

Should never need a generic TargetInstrInfo in target code 

https://github.com/llvm/llvm-project/pull/217535