[llvm] [X86] Lower scalar integer div/rem to FP division (PR #216589)

[Ankit Kumar Tiwari via llvm-commits]

================
@@ -50710,28 +50785,34 @@ static SDValue combineIntDivRem(SDNode *N, SelectionDAG &DAG,
   MVT FPSclVT = MVT::f64;
   if (EltBits <= 16 || BothFitFP(APFloat::IEEEsingle()))
     FPSclVT = MVT::f32;
-  EVT FPVT = VT.changeVectorElementType(*DAG.getContext(), FPSclVT);
+  EVT FPVT = VT.isVector()
+                 ? VT.changeVectorElementType(*DAG.getContext(), FPSclVT)
+                 : EVT(FPSclVT);
 
   bool IsStrict = DAG.getMachineFunction().getFunction().hasFnAttribute(
       Attribute::StrictFP);
   if (IsStrict) {
+    // Scalar strictfp support is not implemented yet.
+    if (!VT.isVector())
+      return SDValue();
     // The SAE forms are 512-bit only. Inputs widen into a zmm below, which
     // requires 512-bit types to be legal and a power of 2 lane count.
     if (!Subtarget.useAVX512Regs() || !isPowerOf2_32(VT.getVectorNumElements()))
       return SDValue();
-  } else if (!IsSigned && VT.getScalarSizeInBits() == 32 &&
+  } else if (VT.isVector() && !IsSigned && VT.getScalarSizeInBits() == 32 &&
----------------
ankit-cybertron wrote:

Right now, since that scalar udiv also lowers to FP sequences, maybe scalarizing is worse than keeping it vectorized in vdivpd if I am thinking correctly, and we should remove the guard?

https://github.com/llvm/llvm-project/pull/216589