[llvm] [RISCV][P-ext] Select immediate forms for packed saturating shifts (PR #217688)
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Thu Aug 20 10:12:47 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: SiHuaN (sihuan)
<details>
<summary>Changes</summary>
pssha/psshar take a signed shift amount, so a constant selects an immediate
form: psslai when non-negative, psrai/psrari when negative. Only pssha with
a non-negative constant was handled. Magnitudes that do not fit the field
keep the register form, where the hardware clamps them to a full shift that
psrari does not reproduce.
---
Full diff: https://github.com/llvm/llvm-project/pull/217688.diff
3 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoP.td (+24-4)
- (modified) llvm/test/CodeGen/RISCV/rvp-simd-32.ll (+60-4)
- (modified) llvm/test/CodeGen/RISCV/rvp-simd-64.ll (+161-18)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index f09df843e0c40..e156287fc7706 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -118,6 +118,14 @@ def uimm4_plus1 : RISCVUImmPlus1Op<4>;
def uimm5_plus1 : RISCVUImmPlus1Op<5>;
def uimm6_plus1 : RISCVUImmPlus1Op<6>;
+// Matches the negation of an N-bit unsigned immediate, rendering the magnitude.
+class RISCVUImmNegLeaf<int bitsNum>
+ : ImmLeaf<XLenVT, "return Imm < 0 && isUInt<" # bitsNum # ">(-Imm);",
+ NegImm>;
+
+def uimm4_neg : RISCVUImmNegLeaf<4>;
+def uimm5_neg : RISCVUImmNegLeaf<5>;
+
//===----------------------------------------------------------------------===//
// Instruction class templates
//===----------------------------------------------------------------------===//
@@ -2144,8 +2152,11 @@ let Predicates = [HasStdExtP] in {
// 16-bit arithmetic shift right patterns
def : PatGprImm<riscv_psra, PSRAI_H, uimm4, XLenVecI16VT>;
- // 16-bit signed saturation shift left patterns
+ // 16-bit saturating shift patterns
def : PatGprImm<riscv_pssha, PSSLAI_H, uimm4, XLenVecI16VT>;
+ def : PatGprImm<riscv_psshar, PSSLAI_H, uimm4, XLenVecI16VT>;
+ def : PatGprImm<riscv_pssha, PSRAI_H, uimm4_neg, XLenVecI16VT>;
+ def : PatGprImm<riscv_psshar, PSRARI_H, uimm4_neg, XLenVecI16VT>;
def : PatGprShift<riscv_pssha, PSSHA_HS, XLenVecI16VT>;
def : PatGprShift<riscv_psshar, PSSHAR_HS, XLenVecI16VT>;
def : PatGprShift<riscv_psshl, PSSHL_HS, XLenVecI16VT>;
@@ -2500,15 +2511,21 @@ let append Predicates = [IsRV32] in {
// 32-bit arithmetic shift left/right patterns
def : PatGprPairImm<riscv_psra, PSRAI_DW, uimm5, v2i32>;
- // 16-bit signed saturation shift left patterns
+ // 16-bit saturating shift patterns
def : PatGprPairImm<riscv_pssha, PSSLAI_DH, uimm4, v4i16>;
+ def : PatGprPairImm<riscv_psshar, PSSLAI_DH, uimm4, v4i16>;
+ def : PatGprPairImm<riscv_pssha, PSRAI_DH, uimm4_neg, v4i16>;
+ def : PatGprPairImm<riscv_psshar, PSRARI_DH, uimm4_neg, v4i16>;
def : PatGprPairShift<riscv_pssha, PSSHA_DHS, v4i16>;
def : PatGprPairShift<riscv_psshar, PSSHAR_DHS, v4i16>;
def : PatGprPairShift<riscv_psshl, PSSHL_DHS, v4i16>;
def : PatGprPairShift<riscv_psshlr, PSSHLR_DHS, v4i16>;
- // 32-bit signed saturation shift left patterns
+ // 32-bit saturating shift patterns
def : PatGprPairImm<riscv_pssha, PSSLAI_DW, uimm5, v2i32>;
+ def : PatGprPairImm<riscv_psshar, PSSLAI_DW, uimm5, v2i32>;
+ def : PatGprPairImm<riscv_pssha, PSRAI_DW, uimm5_neg, v2i32>;
+ def : PatGprPairImm<riscv_psshar, PSRARI_DW, uimm5_neg, v2i32>;
def : PatGprPairShift<riscv_pssha, PSSHA_DWS, v2i32>;
def : PatGprPairShift<riscv_psshar, PSSHAR_DWS, v2i32>;
def : PatGprPairShift<riscv_psshl, PSSHL_DWS, v2i32>;
@@ -2810,8 +2827,11 @@ let append Predicates = [IsRV64] in {
// 32-bit arithmetic shift left/right patterns
def : PatGprImm<riscv_psra, PSRAI_W, uimm5, v2i32>;
- // 32-bit signed saturation shift left patterns
+ // 32-bit saturating shift patterns
def : PatGprImm<riscv_pssha, PSSLAI_W, uimm5, v2i32>;
+ def : PatGprImm<riscv_psshar, PSSLAI_W, uimm5, v2i32>;
+ def : PatGprImm<riscv_pssha, PSRAI_W, uimm5_neg, v2i32>;
+ def : PatGprImm<riscv_psshar, PSRARI_W, uimm5_neg, v2i32>;
def : PatGprShift<riscv_pssha, PSSHA_WS, v2i32>;
def : PatGprShift<riscv_psshar, PSSHAR_WS, v2i32>;
def : PatGprShift<riscv_psshl, PSSHL_WS, v2i32>;
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
index 8f96ec6e8a811..5961c4f4ce940 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
@@ -1300,6 +1300,62 @@ define <2 x i16> @test_psshlr_s_u16x2(<2 x i16> %a, i32 %shamt) {
ret <2 x i16> %res
}
+; Constant shift amounts select the immediate forms.
+define <2 x i16> @test_pssha_s_i16x2_imm(<2 x i16> %a) {
+; CHECK-LABEL: test_pssha_s_i16x2_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: psslai.h a0, a0, 3
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.pssha.v2i16.i32(<2 x i16> %a, i32 3)
+ ret <2 x i16> %res
+}
+
+define <2 x i16> @test_psshar_s_i16x2_imm(<2 x i16> %a) {
+; CHECK-LABEL: test_psshar_s_i16x2_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: psslai.h a0, a0, 3
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.psshar.v2i16.i32(<2 x i16> %a, i32 3)
+ ret <2 x i16> %res
+}
+
+define <2 x i16> @test_pssha_s_i16x2_neg_imm(<2 x i16> %a) {
+; CHECK-LABEL: test_pssha_s_i16x2_neg_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: psrai.h a0, a0, 3
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.pssha.v2i16.i32(<2 x i16> %a, i32 -3)
+ ret <2 x i16> %res
+}
+
+define <2 x i16> @test_psshar_s_i16x2_neg_imm(<2 x i16> %a) {
+; CHECK-LABEL: test_psshar_s_i16x2_neg_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: psrari.h a0, a0, 3
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.psshar.v2i16.i32(<2 x i16> %a, i32 -3)
+ ret <2 x i16> %res
+}
+
+define <2 x i16> @test_pssha_s_i16x2_neg_imm_max(<2 x i16> %a) {
+; CHECK-LABEL: test_pssha_s_i16x2_neg_imm_max:
+; CHECK: # %bb.0:
+; CHECK-NEXT: psrai.h a0, a0, 15
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.pssha.v2i16.i32(<2 x i16> %a, i32 -15)
+ ret <2 x i16> %res
+}
+
+define <2 x i16> @test_pssha_s_i16x2_neg_imm_too_large(<2 x i16> %a) {
+; CHECK-LABEL: test_pssha_s_i16x2_neg_imm_too_large:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a1, -16
+; CHECK-NEXT: pssha.hs a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.pssha.v2i16.i32(<2 x i16> %a, i32 -16)
+ ret <2 x i16> %res
+}
+
; Test packed multiply high signed for v4i8
define <4 x i8> @test_pmulh_b(<4 x i8> %a, <4 x i8> %b) {
; RV32-LABEL: test_pmulh_b:
@@ -2258,10 +2314,10 @@ define <2 x i16> @test_select_v2i16(i1 %cond, <2 x i16> %a, <2 x i16> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB158_2
+; CHECK-NEXT: bnez a3, .LBB164_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB158_2:
+; CHECK-NEXT: .LBB164_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <2 x i16> %a, <2 x i16> %b
ret <2 x i16> %res
@@ -2272,10 +2328,10 @@ define <4 x i8> @test_select_v4i8(i1 %cond, <4 x i8> %a, <4 x i8> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB159_2
+; CHECK-NEXT: bnez a3, .LBB165_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB159_2:
+; CHECK-NEXT: .LBB165_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <4 x i8> %a, <4 x i8> %b
ret <4 x i8> %res
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
index fe067d8225fc3..02ea76c17866e 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
@@ -2427,6 +2427,149 @@ define <2 x i32> @test_psshlr_s_u32x2(<2 x i32> %a, i32 %shamt) {
ret <2 x i32> %res
}
+; Constant shift amounts select the immediate forms.
+define <4 x i16> @test_pssha_s_i16x4_imm(<4 x i16> %a) {
+; RV32-LABEL: test_pssha_s_i16x4_imm:
+; RV32: # %bb.0:
+; RV32-NEXT: psslai.dh a0, a0, 3
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pssha_s_i16x4_imm:
+; RV64: # %bb.0:
+; RV64-NEXT: psslai.h a0, a0, 3
+; RV64-NEXT: ret
+ %res = call <4 x i16> @llvm.riscv.pssha.v4i16.i32(<4 x i16> %a, i32 3)
+ ret <4 x i16> %res
+}
+
+define <4 x i16> @test_psshar_s_i16x4_imm(<4 x i16> %a) {
+; RV32-LABEL: test_psshar_s_i16x4_imm:
+; RV32: # %bb.0:
+; RV32-NEXT: psslai.dh a0, a0, 3
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_psshar_s_i16x4_imm:
+; RV64: # %bb.0:
+; RV64-NEXT: psslai.h a0, a0, 3
+; RV64-NEXT: ret
+ %res = call <4 x i16> @llvm.riscv.psshar.v4i16.i32(<4 x i16> %a, i32 3)
+ ret <4 x i16> %res
+}
+
+define <4 x i16> @test_pssha_s_i16x4_neg_imm(<4 x i16> %a) {
+; RV32-LABEL: test_pssha_s_i16x4_neg_imm:
+; RV32: # %bb.0:
+; RV32-NEXT: psrai.dh a0, a0, 3
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pssha_s_i16x4_neg_imm:
+; RV64: # %bb.0:
+; RV64-NEXT: psrai.h a0, a0, 3
+; RV64-NEXT: ret
+ %res = call <4 x i16> @llvm.riscv.pssha.v4i16.i32(<4 x i16> %a, i32 -3)
+ ret <4 x i16> %res
+}
+
+define <4 x i16> @test_psshar_s_i16x4_neg_imm(<4 x i16> %a) {
+; RV32-LABEL: test_psshar_s_i16x4_neg_imm:
+; RV32: # %bb.0:
+; RV32-NEXT: psrari.dh a0, a0, 3
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_psshar_s_i16x4_neg_imm:
+; RV64: # %bb.0:
+; RV64-NEXT: psrari.h a0, a0, 3
+; RV64-NEXT: ret
+ %res = call <4 x i16> @llvm.riscv.psshar.v4i16.i32(<4 x i16> %a, i32 -3)
+ ret <4 x i16> %res
+}
+
+define <2 x i32> @test_pssha_s_i32x2_imm(<2 x i32> %a) {
+; RV32-LABEL: test_pssha_s_i32x2_imm:
+; RV32: # %bb.0:
+; RV32-NEXT: psslai.dw a0, a0, 3
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pssha_s_i32x2_imm:
+; RV64: # %bb.0:
+; RV64-NEXT: psslai.w a0, a0, 3
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.pssha.v2i32.i32(<2 x i32> %a, i32 3)
+ ret <2 x i32> %res
+}
+
+define <2 x i32> @test_psshar_s_i32x2_imm(<2 x i32> %a) {
+; RV32-LABEL: test_psshar_s_i32x2_imm:
+; RV32: # %bb.0:
+; RV32-NEXT: psslai.dw a0, a0, 3
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_psshar_s_i32x2_imm:
+; RV64: # %bb.0:
+; RV64-NEXT: psslai.w a0, a0, 3
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.psshar.v2i32.i32(<2 x i32> %a, i32 3)
+ ret <2 x i32> %res
+}
+
+define <2 x i32> @test_pssha_s_i32x2_neg_imm(<2 x i32> %a) {
+; RV32-LABEL: test_pssha_s_i32x2_neg_imm:
+; RV32: # %bb.0:
+; RV32-NEXT: psrai.dw a0, a0, 3
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pssha_s_i32x2_neg_imm:
+; RV64: # %bb.0:
+; RV64-NEXT: psrai.w a0, a0, 3
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.pssha.v2i32.i32(<2 x i32> %a, i32 -3)
+ ret <2 x i32> %res
+}
+
+define <2 x i32> @test_psshar_s_i32x2_neg_imm(<2 x i32> %a) {
+; RV32-LABEL: test_psshar_s_i32x2_neg_imm:
+; RV32: # %bb.0:
+; RV32-NEXT: psrari.dw a0, a0, 3
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_psshar_s_i32x2_neg_imm:
+; RV64: # %bb.0:
+; RV64-NEXT: psrari.w a0, a0, 3
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.psshar.v2i32.i32(<2 x i32> %a, i32 -3)
+ ret <2 x i32> %res
+}
+
+define <2 x i32> @test_pssha_s_i32x2_neg_imm_max(<2 x i32> %a) {
+; RV32-LABEL: test_pssha_s_i32x2_neg_imm_max:
+; RV32: # %bb.0:
+; RV32-NEXT: psrai.dw a0, a0, 31
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pssha_s_i32x2_neg_imm_max:
+; RV64: # %bb.0:
+; RV64-NEXT: psrai.w a0, a0, 31
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.pssha.v2i32.i32(<2 x i32> %a, i32 -31)
+ ret <2 x i32> %res
+}
+
+define <2 x i32> @test_pssha_s_i32x2_neg_imm_too_large(<2 x i32> %a) {
+; RV32-LABEL: test_pssha_s_i32x2_neg_imm_too_large:
+; RV32: # %bb.0:
+; RV32-NEXT: li a2, -32
+; RV32-NEXT: pssha.dws a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pssha_s_i32x2_neg_imm_too_large:
+; RV64: # %bb.0:
+; RV64-NEXT: li a1, -32
+; RV64-NEXT: pssha.ws a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.pssha.v2i32.i32(<2 x i32> %a, i32 -32)
+ ret <2 x i32> %res
+}
+
; Test packed multiply high signed
define <8 x i8> @test_pmulh_b(<8 x i8> %a, <8 x i8> %b) {
; RV32-LABEL: test_pmulh_b:
@@ -4534,12 +4677,12 @@ define <4 x i16> @test_select_v4i16(i1 %cond, <4 x i16> %a, <4 x i16> %b) {
; RV32-LABEL: test_select_v4i16:
; RV32: # %bb.0:
; RV32-NEXT: andi a5, a0, 1
-; RV32-NEXT: bnez a5, .LBB236_2
+; RV32-NEXT: bnez a5, .LBB246_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: mv a0, a3
; RV32-NEXT: mv a1, a4
; RV32-NEXT: ret
-; RV32-NEXT: .LBB236_2:
+; RV32-NEXT: .LBB246_2:
; RV32-NEXT: mv a0, a1
; RV32-NEXT: mv a1, a2
; RV32-NEXT: ret
@@ -4548,10 +4691,10 @@ define <4 x i16> @test_select_v4i16(i1 %cond, <4 x i16> %a, <4 x i16> %b) {
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
; RV64-NEXT: mv a0, a1
-; RV64-NEXT: bnez a3, .LBB236_2
+; RV64-NEXT: bnez a3, .LBB246_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: mv a0, a2
-; RV64-NEXT: .LBB236_2:
+; RV64-NEXT: .LBB246_2:
; RV64-NEXT: ret
%res = select i1 %cond, <4 x i16> %a, <4 x i16> %b
ret <4 x i16> %res
@@ -4561,12 +4704,12 @@ define <8 x i8> @test_select_v8i8(i1 %cond, <8 x i8> %a, <8 x i8> %b) {
; RV32-LABEL: test_select_v8i8:
; RV32: # %bb.0:
; RV32-NEXT: andi a5, a0, 1
-; RV32-NEXT: bnez a5, .LBB237_2
+; RV32-NEXT: bnez a5, .LBB247_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: mv a0, a3
; RV32-NEXT: mv a1, a4
; RV32-NEXT: ret
-; RV32-NEXT: .LBB237_2:
+; RV32-NEXT: .LBB247_2:
; RV32-NEXT: mv a0, a1
; RV32-NEXT: mv a1, a2
; RV32-NEXT: ret
@@ -4575,10 +4718,10 @@ define <8 x i8> @test_select_v8i8(i1 %cond, <8 x i8> %a, <8 x i8> %b) {
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
; RV64-NEXT: mv a0, a1
-; RV64-NEXT: bnez a3, .LBB237_2
+; RV64-NEXT: bnez a3, .LBB247_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: mv a0, a2
-; RV64-NEXT: .LBB237_2:
+; RV64-NEXT: .LBB247_2:
; RV64-NEXT: ret
%res = select i1 %cond, <8 x i8> %a, <8 x i8> %b
ret <8 x i8> %res
@@ -4588,12 +4731,12 @@ define <2 x i32> @test_select_v2i32(i1 %cond, <2 x i32> %a, <2 x i32> %b) {
; RV32-LABEL: test_select_v2i32:
; RV32: # %bb.0:
; RV32-NEXT: andi a5, a0, 1
-; RV32-NEXT: bnez a5, .LBB238_2
+; RV32-NEXT: bnez a5, .LBB248_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: mv a0, a3
; RV32-NEXT: mv a1, a4
; RV32-NEXT: ret
-; RV32-NEXT: .LBB238_2:
+; RV32-NEXT: .LBB248_2:
; RV32-NEXT: mv a0, a1
; RV32-NEXT: mv a1, a2
; RV32-NEXT: ret
@@ -4602,10 +4745,10 @@ define <2 x i32> @test_select_v2i32(i1 %cond, <2 x i32> %a, <2 x i32> %b) {
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
; RV64-NEXT: mv a0, a1
-; RV64-NEXT: bnez a3, .LBB238_2
+; RV64-NEXT: bnez a3, .LBB248_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: mv a0, a2
-; RV64-NEXT: .LBB238_2:
+; RV64-NEXT: .LBB248_2:
; RV64-NEXT: ret
%res = select i1 %cond, <2 x i32> %a, <2 x i32> %b
ret <2 x i32> %res
@@ -4653,16 +4796,16 @@ define <2 x i32> @test_vselect_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
; RV32: # %bb.0:
; RV32-NEXT: pmslt.dw a6, a2, a0
; RV32-NEXT: mv a0, a4
-; RV32-NEXT: beqz a7, .LBB241_3
+; RV32-NEXT: beqz a7, .LBB251_3
; RV32-NEXT: # %bb.1:
-; RV32-NEXT: beqz a6, .LBB241_4
-; RV32-NEXT: .LBB241_2:
+; RV32-NEXT: beqz a6, .LBB251_4
+; RV32-NEXT: .LBB251_2:
; RV32-NEXT: mv a1, a5
; RV32-NEXT: ret
-; RV32-NEXT: .LBB241_3:
+; RV32-NEXT: .LBB251_3:
; RV32-NEXT: mv a5, a3
-; RV32-NEXT: bnez a6, .LBB241_2
-; RV32-NEXT: .LBB241_4:
+; RV32-NEXT: bnez a6, .LBB251_2
+; RV32-NEXT: .LBB251_4:
; RV32-NEXT: mv a0, a2
; RV32-NEXT: mv a1, a5
; RV32-NEXT: ret
``````````
</details>
https://github.com/llvm/llvm-project/pull/217688
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