[llvm] [X86] Lower scalar integer div/rem to FP division (PR #216589)
Ankit Kumar Tiwari via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 20 10:02:30 PDT 2026
https://github.com/ankit-cybertron updated https://github.com/llvm/llvm-project/pull/216589
>From c8f026b79e8a20f01619622ee4a3eb91c7535227 Mon Sep 17 00:00:00 2001
From: Ankit Kumar Tiwari <ankit.cybertron at gmail.com>
Date: Sun, 16 Aug 2026 22:43:07 +0530
Subject: [PATCH 1/7] Baseline Test
---
llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll | 119 +++++++++++++++++++
1 file changed, 119 insertions(+)
create mode 100644 llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll
diff --git a/llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll b/llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll
new file mode 100644
index 0000000000000..10100c65cab3f
--- /dev/null
+++ b/llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll
@@ -0,0 +1,119 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s
+
+define i32 @sdiv_i32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: sdiv_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: cltd
+; CHECK-NEXT: idivl %esi
+; CHECK-NEXT: retq
+ %r = sdiv i32 %a, %b
+ ret i32 %r
+}
+
+define i16 @sdiv_i16(i16 %a, i16 %b) nounwind {
+; CHECK-LABEL: sdiv_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: cwtd
+; CHECK-NEXT: idivw %si
+; CHECK-NEXT: retq
+ %r = sdiv i16 %a, %b
+ ret i16 %r
+}
+
+define i8 @sdiv_i8(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: sdiv_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movsbl %dil, %eax
+; CHECK-NEXT: idivb %sil
+; CHECK-NEXT: retq
+ %r = sdiv i8 %a, %b
+ ret i8 %r
+}
+
+define i32 @udiv_i32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: udiv_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: divl %esi
+; CHECK-NEXT: retq
+ %r = udiv i32 %a, %b
+ ret i32 %r
+}
+
+define i16 @udiv_i16(i16 %a, i16 %b) nounwind {
+; CHECK-LABEL: udiv_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: divw %si
+; CHECK-NEXT: retq
+ %r = udiv i16 %a, %b
+ ret i16 %r
+}
+
+define i8 @udiv_i8(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: udiv_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movzbl %dil, %eax
+; CHECK-NEXT: divb %sil
+; CHECK-NEXT: retq
+ %r = udiv i8 %a, %b
+ ret i8 %r
+}
+
+define i32 @urem_i32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: urem_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: divl %esi
+; CHECK-NEXT: movl %edx, %eax
+; CHECK-NEXT: retq
+ %r = urem i32 %a, %b
+ ret i32 %r
+}
+
+define i64 @sdiv_i64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: sdiv_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: cqto
+; CHECK-NEXT: idivq %rsi
+; CHECK-NEXT: retq
+ %r = sdiv i64 %a, %b
+ ret i64 %r
+}
+
+define i32 @sdiv_i32_const(i32 %a) nounwind {
+; CHECK-LABEL: sdiv_i32_const:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movslq %edi, %rax
+; CHECK-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
+; CHECK-NEXT: shrq $32, %rcx
+; CHECK-NEXT: addl %ecx, %eax
+; CHECK-NEXT: movl %eax, %ecx
+; CHECK-NEXT: shrl $31, %ecx
+; CHECK-NEXT: sarl $2, %eax
+; CHECK-NEXT: addl %ecx, %eax
+; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
+; CHECK-NEXT: retq
+ %r = sdiv i32 %a, 7
+ ret i32 %r
+}
+
+define i32 @sdiv_i32_noimplicitfloat(i32 %a, i32 %b) nounwind noimplicitfloat {
+; CHECK-LABEL: sdiv_i32_noimplicitfloat:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: cltd
+; CHECK-NEXT: idivl %esi
+; CHECK-NEXT: retq
+ %r = sdiv i32 %a, %b
+ ret i32 %r
+}
>From 8ab252ee42ecbbce8d3db49d8f2fce6c1386a030 Mon Sep 17 00:00:00 2001
From: Ankit Kumar Tiwari <ankit.cybertron at gmail.com>
Date: Sun, 16 Aug 2026 23:12:51 +0530
Subject: [PATCH 2/7] [X86] Lower scalar i8/i16/i32 integer div/rem to FP
division
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 31 ++++++++---
llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll | 58 ++++++++++++++------
2 files changed, 64 insertions(+), 25 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 406761eec9721..4bd36d762c7b6 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -50720,8 +50720,8 @@ static SDValue combineIntDivRem(SDNode *N, SelectionDAG &DAG,
EVT VT = N->getValueType(0);
SDLoc DL(N);
- // Vector division never survives op legalization to reach later rounds.
- if (!VT.isVector() || !Subtarget.hasSSE2())
+
+ if (!Subtarget.hasSSE2())
return SDValue();
SDValue Dividend = N->getOperand(0);
@@ -50735,6 +50735,13 @@ static SDValue combineIntDivRem(SDNode *N, SelectionDAG &DAG,
bool IsRem = Opc == ISD::UREM || Opc == ISD::SREM;
bool IsSigned = Opc == ISD::SDIV || Opc == ISD::SREM;
+ // Scalar functions that do not use XMM registers must not get this combine.
+ if (!VT.isVector() &&
+ (Subtarget.useSoftFloat() ||
+ DAG.getMachineFunction().getFunction().hasFnAttribute(
+ Attribute::NoImplicitFloat)))
+ return SDValue();
+
// If the result is only read back as scalar extracts, scalarization computes
// just the demanded lanes. Keep the vector operation when every lane is
// extracted, which occurs when non-power-of-two vectors are returned.
@@ -50778,16 +50785,21 @@ static SDValue combineIntDivRem(SDNode *N, SelectionDAG &DAG,
MVT FPSclVT = MVT::f64;
if (EltBits <= 16 || BothFitFP(APFloat::IEEEsingle()))
FPSclVT = MVT::f32;
- EVT FPVT = VT.changeVectorElementType(*DAG.getContext(), FPSclVT);
+ EVT FPVT = VT.isVector()
+ ? VT.changeVectorElementType(*DAG.getContext(), FPSclVT)
+ : EVT(FPSclVT);
bool IsStrict = DAG.getMachineFunction().getFunction().hasFnAttribute(
Attribute::StrictFP);
if (IsStrict) {
+ // Scalar strictfp support is not implemented yet.
+ if (!VT.isVector())
+ return SDValue();
// The SAE forms are 512-bit only. Inputs widen into a zmm below, which
// requires 512-bit types to be legal and a power of 2 lane count.
if (!Subtarget.useAVX512Regs() || !isPowerOf2_32(VT.getVectorNumElements()))
return SDValue();
- } else if (!IsSigned && VT.getScalarSizeInBits() == 32 &&
+ } else if (VT.isVector() && !IsSigned && VT.getScalarSizeInBits() == 32 &&
!Subtarget.hasAVX2()) {
// Unsigned i32 needs FP_TO_UINT(f64->u32) which is emulated and a loss
// for latency and code size before AVX2.
@@ -50795,11 +50807,12 @@ static SDValue combineIntDivRem(SDNode *N, SelectionDAG &DAG,
}
// Nothing will split an illegal FP type after type legalization and the
- // strict SAE divide is 512-bit only.
- bool FPVTUsable = IsStrict
- ? FPVT.getSizeInBits() <= 512
- : DCI.isBeforeLegalize() ||
- DAG.getTargetLoweringInfo().isTypeLegal(FPVT);
+ // strict SAE divide is 512-bit only. Scalar f32/f64 are always legal.
+ bool FPVTUsable = !VT.isVector() ||
+ (IsStrict
+ ? FPVT.getSizeInBits() <= 512
+ : DCI.isBeforeLegalize() ||
+ DAG.getTargetLoweringInfo().isTypeLegal(FPVT));
// Halve the divide while the integer halves stay legal.
if (!FPVTUsable) {
diff --git a/llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll b/llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll
index 10100c65cab3f..c752a26703275 100644
--- a/llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll
+++ b/llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll
@@ -4,9 +4,10 @@
define i32 @sdiv_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: sdiv_i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: movl %edi, %eax
-; CHECK-NEXT: cltd
-; CHECK-NEXT: idivl %esi
+; CHECK-NEXT: vcvtsi2sd %esi, %xmm15, %xmm0
+; CHECK-NEXT: vcvtsi2sd %edi, %xmm15, %xmm1
+; CHECK-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vcvttsd2si %xmm0, %eax
; CHECK-NEXT: retq
%r = sdiv i32 %a, %b
ret i32 %r
@@ -15,10 +16,13 @@ define i32 @sdiv_i32(i32 %a, i32 %b) nounwind {
define i16 @sdiv_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: sdiv_i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: movswl %si, %eax
+; CHECK-NEXT: vcvtsi2ss %eax, %xmm15, %xmm0
+; CHECK-NEXT: movswl %di, %eax
+; CHECK-NEXT: vcvtsi2ss %eax, %xmm15, %xmm1
+; CHECK-NEXT: vdivss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
-; CHECK-NEXT: cwtd
-; CHECK-NEXT: idivw %si
; CHECK-NEXT: retq
%r = sdiv i16 %a, %b
ret i16 %r
@@ -27,8 +31,13 @@ define i16 @sdiv_i16(i16 %a, i16 %b) nounwind {
define i8 @sdiv_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: sdiv_i8:
; CHECK: # %bb.0:
+; CHECK-NEXT: movsbl %sil, %eax
+; CHECK-NEXT: vcvtsi2ss %eax, %xmm15, %xmm0
; CHECK-NEXT: movsbl %dil, %eax
-; CHECK-NEXT: idivb %sil
+; CHECK-NEXT: vcvtsi2ss %eax, %xmm15, %xmm1
+; CHECK-NEXT: vdivss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%r = sdiv i8 %a, %b
ret i8 %r
@@ -37,9 +46,13 @@ define i8 @sdiv_i8(i8 %a, i8 %b) nounwind {
define i32 @udiv_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: udiv_i32:
; CHECK: # %bb.0:
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: vcvtsi2sd %rax, %xmm15, %xmm0
; CHECK-NEXT: movl %edi, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %esi
+; CHECK-NEXT: vcvtsi2sd %rax, %xmm15, %xmm1
+; CHECK-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vcvttsd2si %xmm0, %rax
+; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
; CHECK-NEXT: retq
%r = udiv i32 %a, %b
ret i32 %r
@@ -48,10 +61,13 @@ define i32 @udiv_i32(i32 %a, i32 %b) nounwind {
define i16 @udiv_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: udiv_i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: movzwl %si, %eax
+; CHECK-NEXT: vcvtsi2ss %eax, %xmm15, %xmm0
+; CHECK-NEXT: movzwl %di, %eax
+; CHECK-NEXT: vcvtsi2ss %eax, %xmm15, %xmm1
+; CHECK-NEXT: vdivss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divw %si
; CHECK-NEXT: retq
%r = udiv i16 %a, %b
ret i16 %r
@@ -60,8 +76,13 @@ define i16 @udiv_i16(i16 %a, i16 %b) nounwind {
define i8 @udiv_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: udiv_i8:
; CHECK: # %bb.0:
+; CHECK-NEXT: movzbl %sil, %eax
+; CHECK-NEXT: vcvtsi2ss %eax, %xmm15, %xmm0
; CHECK-NEXT: movzbl %dil, %eax
-; CHECK-NEXT: divb %sil
+; CHECK-NEXT: vcvtsi2ss %eax, %xmm15, %xmm1
+; CHECK-NEXT: vdivss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%r = udiv i8 %a, %b
ret i8 %r
@@ -71,9 +92,14 @@ define i32 @urem_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: urem_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %esi
-; CHECK-NEXT: movl %edx, %eax
+; CHECK-NEXT: movl %esi, %ecx
+; CHECK-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm0
+; CHECK-NEXT: movl %edi, %ecx
+; CHECK-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm1
+; CHECK-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vcvttsd2si %xmm0, %rcx
+; CHECK-NEXT: imull %esi, %ecx
+; CHECK-NEXT: subl %ecx, %eax
; CHECK-NEXT: retq
%r = urem i32 %a, %b
ret i32 %r
>From cbc9e6641043df3efaccf470e2d9afb0cbaf6f7f Mon Sep 17 00:00:00 2001
From: Ankit Kumar Tiwari <ankit.cybertron at gmail.com>
Date: Tue, 18 Aug 2026 01:19:49 +0530
Subject: [PATCH 3/7] Fix scalar test parameter extensions
---
llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll | 112 +++++++++----------
1 file changed, 52 insertions(+), 60 deletions(-)
diff --git a/llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll b/llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll
index c752a26703275..d1b9d041944fa 100644
--- a/llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll
+++ b/llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll
@@ -13,36 +13,6 @@ define i32 @sdiv_i32(i32 %a, i32 %b) nounwind {
ret i32 %r
}
-define i16 @sdiv_i16(i16 %a, i16 %b) nounwind {
-; CHECK-LABEL: sdiv_i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: movswl %si, %eax
-; CHECK-NEXT: vcvtsi2ss %eax, %xmm15, %xmm0
-; CHECK-NEXT: movswl %di, %eax
-; CHECK-NEXT: vcvtsi2ss %eax, %xmm15, %xmm1
-; CHECK-NEXT: vdivss %xmm0, %xmm1, %xmm0
-; CHECK-NEXT: vcvttss2si %xmm0, %eax
-; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
-; CHECK-NEXT: retq
- %r = sdiv i16 %a, %b
- ret i16 %r
-}
-
-define i8 @sdiv_i8(i8 %a, i8 %b) nounwind {
-; CHECK-LABEL: sdiv_i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: movsbl %sil, %eax
-; CHECK-NEXT: vcvtsi2ss %eax, %xmm15, %xmm0
-; CHECK-NEXT: movsbl %dil, %eax
-; CHECK-NEXT: vcvtsi2ss %eax, %xmm15, %xmm1
-; CHECK-NEXT: vdivss %xmm0, %xmm1, %xmm0
-; CHECK-NEXT: vcvttss2si %xmm0, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
-; CHECK-NEXT: retq
- %r = sdiv i8 %a, %b
- ret i8 %r
-}
-
define i32 @udiv_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: udiv_i32:
; CHECK: # %bb.0:
@@ -58,36 +28,6 @@ define i32 @udiv_i32(i32 %a, i32 %b) nounwind {
ret i32 %r
}
-define i16 @udiv_i16(i16 %a, i16 %b) nounwind {
-; CHECK-LABEL: udiv_i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: movzwl %si, %eax
-; CHECK-NEXT: vcvtsi2ss %eax, %xmm15, %xmm0
-; CHECK-NEXT: movzwl %di, %eax
-; CHECK-NEXT: vcvtsi2ss %eax, %xmm15, %xmm1
-; CHECK-NEXT: vdivss %xmm0, %xmm1, %xmm0
-; CHECK-NEXT: vcvttss2si %xmm0, %eax
-; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
-; CHECK-NEXT: retq
- %r = udiv i16 %a, %b
- ret i16 %r
-}
-
-define i8 @udiv_i8(i8 %a, i8 %b) nounwind {
-; CHECK-LABEL: udiv_i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: movzbl %sil, %eax
-; CHECK-NEXT: vcvtsi2ss %eax, %xmm15, %xmm0
-; CHECK-NEXT: movzbl %dil, %eax
-; CHECK-NEXT: vcvtsi2ss %eax, %xmm15, %xmm1
-; CHECK-NEXT: vdivss %xmm0, %xmm1, %xmm0
-; CHECK-NEXT: vcvttss2si %xmm0, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
-; CHECK-NEXT: retq
- %r = udiv i8 %a, %b
- ret i8 %r
-}
-
define i32 @urem_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: urem_i32:
; CHECK: # %bb.0:
@@ -143,3 +83,55 @@ define i32 @sdiv_i32_noimplicitfloat(i32 %a, i32 %b) nounwind noimplicitfloat {
%r = sdiv i32 %a, %b
ret i32 %r
}
+
+define signext i8 @sdiv_i8(i8 signext %a, i8 signext %b) nounwind {
+; CHECK-LABEL: sdiv_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtsi2ss %esi, %xmm15, %xmm0
+; CHECK-NEXT: vcvtsi2ss %edi, %xmm15, %xmm1
+; CHECK-NEXT: vdivss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %r = sdiv i8 %a, %b
+ ret i8 %r
+}
+
+define zeroext i8 @udiv_i8(i8 zeroext %a, i8 zeroext %b) nounwind {
+; CHECK-LABEL: udiv_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtsi2ss %esi, %xmm15, %xmm0
+; CHECK-NEXT: vcvtsi2ss %edi, %xmm15, %xmm1
+; CHECK-NEXT: vdivss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %r = udiv i8 %a, %b
+ ret i8 %r
+}
+
+define signext i16 @sdiv_i16(i16 signext %a, i16 signext %b) nounwind {
+; CHECK-LABEL: sdiv_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtsi2ss %esi, %xmm15, %xmm0
+; CHECK-NEXT: vcvtsi2ss %edi, %xmm15, %xmm1
+; CHECK-NEXT: vdivss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+ %r = sdiv i16 %a, %b
+ ret i16 %r
+}
+
+define zeroext i16 @udiv_i16(i16 zeroext %a, i16 zeroext %b) nounwind {
+; CHECK-LABEL: udiv_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcvtsi2ss %esi, %xmm15, %xmm0
+; CHECK-NEXT: vcvtsi2ss %edi, %xmm15, %xmm1
+; CHECK-NEXT: vdivss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+ %r = udiv i16 %a, %b
+ ret i16 %r
+}
>From fa4f839ff71a8698e5fa89c7a0a217a70715c22f Mon Sep 17 00:00:00 2001
From: Ankit Kumar Tiwari <ankit.cybertron at gmail.com>
Date: Thu, 20 Aug 2026 09:40:07 +0530
Subject: [PATCH 4/7] add more div/rem test cases
---
llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll | 225 ++++++++++++++++---
1 file changed, 189 insertions(+), 36 deletions(-)
diff --git a/llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll b/llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll
index d1b9d041944fa..7a7b6f3c1f1c4 100644
--- a/llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll
+++ b/llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll
@@ -28,6 +28,21 @@ define i32 @udiv_i32(i32 %a, i32 %b) nounwind {
ret i32 %r
}
+define i32 @srem_i32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: srem_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: vcvtsi2sd %esi, %xmm15, %xmm0
+; CHECK-NEXT: vcvtsi2sd %edi, %xmm15, %xmm1
+; CHECK-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vcvttsd2si %xmm0, %ecx
+; CHECK-NEXT: imull %esi, %ecx
+; CHECK-NEXT: subl %ecx, %eax
+; CHECK-NEXT: retq
+ %r = srem i32 %a, %b
+ ret i32 %r
+}
+
define i32 @urem_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: urem_i32:
; CHECK: # %bb.0:
@@ -45,43 +60,62 @@ define i32 @urem_i32(i32 %a, i32 %b) nounwind {
ret i32 %r
}
-define i64 @sdiv_i64(i64 %a, i64 %b) nounwind {
-; CHECK-LABEL: sdiv_i64:
+define signext i16 @sdiv_i16(i16 signext %a, i16 signext %b) nounwind {
+; CHECK-LABEL: sdiv_i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: movq %rdi, %rax
-; CHECK-NEXT: cqto
-; CHECK-NEXT: idivq %rsi
+; CHECK-NEXT: vcvtsi2ss %esi, %xmm15, %xmm0
+; CHECK-NEXT: vcvtsi2ss %edi, %xmm15, %xmm1
+; CHECK-NEXT: vdivss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq
- %r = sdiv i64 %a, %b
- ret i64 %r
+ %r = sdiv i16 %a, %b
+ ret i16 %r
}
-define i32 @sdiv_i32_const(i32 %a) nounwind {
-; CHECK-LABEL: sdiv_i32_const:
+define zeroext i16 @udiv_i16(i16 zeroext %a, i16 zeroext %b) nounwind {
+; CHECK-LABEL: udiv_i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: movslq %edi, %rax
-; CHECK-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
-; CHECK-NEXT: shrq $32, %rcx
-; CHECK-NEXT: addl %ecx, %eax
-; CHECK-NEXT: movl %eax, %ecx
-; CHECK-NEXT: shrl $31, %ecx
-; CHECK-NEXT: sarl $2, %eax
-; CHECK-NEXT: addl %ecx, %eax
-; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
+; CHECK-NEXT: vcvtsi2ss %esi, %xmm15, %xmm0
+; CHECK-NEXT: vcvtsi2ss %edi, %xmm15, %xmm1
+; CHECK-NEXT: vdivss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq
- %r = sdiv i32 %a, 7
- ret i32 %r
+ %r = udiv i16 %a, %b
+ ret i16 %r
}
-define i32 @sdiv_i32_noimplicitfloat(i32 %a, i32 %b) nounwind noimplicitfloat {
-; CHECK-LABEL: sdiv_i32_noimplicitfloat:
+define signext i16 @srem_i16(i16 signext %a, i16 signext %b) nounwind {
+; CHECK-LABEL: srem_i16:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, %eax
-; CHECK-NEXT: cltd
-; CHECK-NEXT: idivl %esi
+; CHECK-NEXT: vcvtsi2ss %esi, %xmm15, %xmm0
+; CHECK-NEXT: vcvtsi2ss %edi, %xmm15, %xmm1
+; CHECK-NEXT: vdivss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %ecx
+; CHECK-NEXT: imull %esi, %ecx
+; CHECK-NEXT: subl %ecx, %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq
- %r = sdiv i32 %a, %b
- ret i32 %r
+ %r = srem i16 %a, %b
+ ret i16 %r
+}
+
+define zeroext i16 @urem_i16(i16 zeroext %a, i16 zeroext %b) nounwind {
+; CHECK-LABEL: urem_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: vcvtsi2ss %esi, %xmm15, %xmm0
+; CHECK-NEXT: vcvtsi2ss %edi, %xmm15, %xmm1
+; CHECK-NEXT: vdivss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %ecx
+; CHECK-NEXT: imull %esi, %ecx
+; CHECK-NEXT: subl %ecx, %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+ %r = urem i16 %a, %b
+ ret i16 %r
}
define signext i8 @sdiv_i8(i8 signext %a, i8 signext %b) nounwind {
@@ -110,28 +144,147 @@ define zeroext i8 @udiv_i8(i8 zeroext %a, i8 zeroext %b) nounwind {
ret i8 %r
}
-define signext i16 @sdiv_i16(i16 signext %a, i16 signext %b) nounwind {
-; CHECK-LABEL: sdiv_i16:
+define signext i8 @srem_i8(i8 signext %a, i8 signext %b) nounwind {
+; CHECK-LABEL: srem_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vcvtsi2ss %esi, %xmm15, %xmm0
; CHECK-NEXT: vcvtsi2ss %edi, %xmm15, %xmm1
; CHECK-NEXT: vdivss %xmm0, %xmm1, %xmm0
; CHECK-NEXT: vcvttss2si %xmm0, %eax
-; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: mulb %sil
+; CHECK-NEXT: subb %al, %dil
+; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
- %r = sdiv i16 %a, %b
- ret i16 %r
+ %r = srem i8 %a, %b
+ ret i8 %r
}
-define zeroext i16 @udiv_i16(i16 zeroext %a, i16 zeroext %b) nounwind {
-; CHECK-LABEL: udiv_i16:
+define zeroext i8 @urem_i8(i8 zeroext %a, i8 zeroext %b) nounwind {
+; CHECK-LABEL: urem_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vcvtsi2ss %esi, %xmm15, %xmm0
; CHECK-NEXT: vcvtsi2ss %edi, %xmm15, %xmm1
; CHECK-NEXT: vdivss %xmm0, %xmm1, %xmm0
; CHECK-NEXT: vcvttss2si %xmm0, %eax
-; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: mulb %sil
+; CHECK-NEXT: subb %al, %dil
+; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
- %r = udiv i16 %a, %b
- ret i16 %r
+ %r = urem i8 %a, %b
+ ret i8 %r
+}
+
+define i32 @sdiv_srem_pair(i32 %a, i32 %b, ptr %p) nounwind {
+; CHECK-LABEL: sdiv_srem_pair:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %rdx, %rcx
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: cltd
+; CHECK-NEXT: idivl %esi
+; CHECK-NEXT: movl %edx, (%rcx)
+; CHECK-NEXT: retq
+ %q = sdiv i32 %a, %b
+ %r = srem i32 %a, %b
+ store i32 %r, ptr %p
+ ret i32 %q
+}
+
+define i32 @udiv_urem_pair(i32 %a, i32 %b, ptr %p) nounwind {
+; CHECK-LABEL: udiv_urem_pair:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %rdx, %rcx
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: divl %esi
+; CHECK-NEXT: movl %edx, (%rcx)
+; CHECK-NEXT: retq
+ %q = udiv i32 %a, %b
+ %r = urem i32 %a, %b
+ store i32 %r, ptr %p
+ ret i32 %q
+}
+
+define i32 @udiv_i32_narrow(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: udiv_i32_narrow:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movzbl %dil, %eax
+; CHECK-NEXT: movzbl %sil, %ecx
+; CHECK-NEXT: vcvtsi2ss %ecx, %xmm15, %xmm0
+; CHECK-NEXT: vcvtsi2ss %eax, %xmm15, %xmm1
+; CHECK-NEXT: vdivss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
+; CHECK-NEXT: retq
+ %a2 = and i32 %a, 255
+ %b2 = and i32 %b, 255
+ %r = udiv i32 %a2, %b2
+ ret i32 %r
+}
+
+define i32 @sdiv_i32_narrow(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: sdiv_i32_narrow:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sarl $24, %edi
+; CHECK-NEXT: sarl $24, %esi
+; CHECK-NEXT: vcvtsi2ss %esi, %xmm15, %xmm0
+; CHECK-NEXT: vcvtsi2ss %edi, %xmm15, %xmm1
+; CHECK-NEXT: vdivss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: retq
+ %a2 = ashr i32 %a, 24
+ %b2 = ashr i32 %b, 24
+ %r = sdiv i32 %a2, %b2
+ ret i32 %r
+}
+
+define i32 @sdiv_i32_const(i32 %a) nounwind {
+; CHECK-LABEL: sdiv_i32_const:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movslq %edi, %rax
+; CHECK-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
+; CHECK-NEXT: shrq $32, %rcx
+; CHECK-NEXT: addl %ecx, %eax
+; CHECK-NEXT: movl %eax, %ecx
+; CHECK-NEXT: shrl $31, %ecx
+; CHECK-NEXT: sarl $2, %eax
+; CHECK-NEXT: addl %ecx, %eax
+; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
+; CHECK-NEXT: retq
+ %r = sdiv i32 %a, 7
+ ret i32 %r
+}
+
+define i64 @sdiv_i64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: sdiv_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: cqto
+; CHECK-NEXT: idivq %rsi
+; CHECK-NEXT: retq
+ %r = sdiv i64 %a, %b
+ ret i64 %r
+}
+
+define i32 @sdiv_i32_noimplicitfloat(i32 %a, i32 %b) nounwind noimplicitfloat {
+; CHECK-LABEL: sdiv_i32_noimplicitfloat:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: cltd
+; CHECK-NEXT: idivl %esi
+; CHECK-NEXT: retq
+ %r = sdiv i32 %a, %b
+ ret i32 %r
+}
+
+define i32 @sdiv_i32_strictfp(i32 %a, i32 %b) nounwind strictfp {
+; CHECK-LABEL: sdiv_i32_strictfp:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: cltd
+; CHECK-NEXT: idivl %esi
+; CHECK-NEXT: retq
+ %r = sdiv i32 %a, %b
+ ret i32 %r
}
>From 60d90ad746edfb5aa0243ad8cccedd106747ecdd Mon Sep 17 00:00:00 2001
From: Ankit Kumar Tiwari <ankit.cybertron at gmail.com>
Date: Thu, 20 Aug 2026 09:40:53 +0530
Subject: [PATCH 5/7] Regenerate test checks
---
.../X86/2007-08-09-IllegalX86-64Asm.ll | 85 +-
.../CodeGen/X86/2008-09-11-CoalescerBug2.ll | 34 +-
.../2010-09-01-RemoveCopyByCommutingDef.ll | 27 +-
.../CodeGen/X86/MachineSink-Issue98477.ll | 52 +-
llvm/test/CodeGen/X86/anyext.ll | 16 +-
llvm/test/CodeGen/X86/apx/ctest.ll | 103 ++-
llvm/test/CodeGen/X86/atomic-unordered.ll | 142 +--
llvm/test/CodeGen/X86/backpropmask.ll | 35 +-
llvm/test/CodeGen/X86/buildvec-insertvec.ll | 36 +-
.../CodeGen/X86/bypass-slow-division-64.ll | 119 +--
.../CodeGen/X86/bypass-slow-division-tune.ll | 319 ++++---
llvm/test/CodeGen/X86/combine-srem.ll | 85 +-
llvm/test/CodeGen/X86/copy-eflags.ll | 41 +-
.../X86/div-rem-pair-recomposition-signed.ll | 289 ++++---
.../div-rem-pair-recomposition-unsigned.ll | 544 ++++++++----
llvm/test/CodeGen/X86/div8.ll | 16 +-
llvm/test/CodeGen/X86/divrem8_ext.ll | 79 +-
llvm/test/CodeGen/X86/early-ifcvt.ll | 103 ++-
.../CodeGen/X86/expand-vp-int-intrinsics.ll | 398 ++++++---
llvm/test/CodeGen/X86/extractelement-load.ll | 128 +--
llvm/test/CodeGen/X86/fold-loop-of-urem.ll | 249 ++++--
llvm/test/CodeGen/X86/hoist-invariant-load.ll | 30 +-
llvm/test/CodeGen/X86/implicit-null-check.ll | 8 +-
.../CodeGen/X86/insertelement-var-index.ll | 72 +-
llvm/test/CodeGen/X86/isel-sdiv.ll | 21 -
llvm/test/CodeGen/X86/isel-srem.ll | 84 +-
llvm/test/CodeGen/X86/isel-udiv.ll | 21 -
llvm/test/CodeGen/X86/isel-urem.ll | 86 +-
llvm/test/CodeGen/X86/known-never-zero.ll | 242 ++++--
llvm/test/CodeGen/X86/known-pow2.ll | 50 +-
llvm/test/CodeGen/X86/knownbits-div.ll | 18 +-
.../test/CodeGen/X86/load-scalar-as-vector.ll | 58 +-
llvm/test/CodeGen/X86/machine-cp.ll | 26 +-
.../machine-trace-metrics-entryBB-critpath.ll | 17 +-
...of-two-or-zero-when-comparing-with-zero.ll | 51 +-
llvm/test/CodeGen/X86/pr32282.ll | 24 +-
llvm/test/CodeGen/X86/pr35316.ll | 29 +-
llvm/test/CodeGen/X86/shrink_vmul.ll | 809 +++++++++++++-----
.../CodeGen/X86/speculation-hardening-sls.ll | 137 ++-
llvm/test/CodeGen/X86/split-vector-rem.ll | 138 ++-
llvm/test/CodeGen/X86/udiv_fix.ll | 59 +-
llvm/test/CodeGen/X86/udiv_fix_sat.ll | 54 +-
llvm/test/CodeGen/X86/unknown-location.ll | 3 +
llvm/test/CodeGen/X86/urem-power-of-two.ll | 29 +-
llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll | 314 ++++---
llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll | 184 ++--
llvm/test/CodeGen/X86/vector-idiv-v2i32.ll | 188 ++--
llvm/test/CodeGen/X86/vector-rem.ll | 68 +-
llvm/test/CodeGen/X86/x86-cmov-converter.ll | 164 ++--
49 files changed, 3878 insertions(+), 2006 deletions(-)
diff --git a/llvm/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll b/llvm/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll
index 7bdc4e19a1cf6..038c464c2ada4 100644
--- a/llvm/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll
+++ b/llvm/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll
@@ -28,14 +28,11 @@ define ptr @ubyte_divmod(ptr %a, ptr %b) {
; CHECK-NEXT: .cfi_def_cfa_offset 24
; CHECK-NEXT: pushq %r14
; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: pushq %r12
-; CHECK-NEXT: .cfi_def_cfa_offset 40
; CHECK-NEXT: pushq %rbx
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: subq $32, %rsp
+; CHECK-NEXT: .cfi_def_cfa_offset 40
+; CHECK-NEXT: subq $40, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 80
-; CHECK-NEXT: .cfi_offset %rbx, -48
-; CHECK-NEXT: .cfi_offset %r12, -40
+; CHECK-NEXT: .cfi_offset %rbx, -40
; CHECK-NEXT: .cfi_offset %r14, -32
; CHECK-NEXT: .cfi_offset %r15, -24
; CHECK-NEXT: .cfi_offset %rbp, -16
@@ -72,16 +69,17 @@ define ptr @ubyte_divmod(ptr %a, ptr %b) {
; CHECK-NEXT: movq _PyUFunc_API at GOTPCREL(%rip), %r14
; CHECK-NEXT: movq (%r14), %rax
; CHECK-NEXT: callq *216(%rax)
-; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
-; CHECK-NEXT: testb %dl, %dl
+; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
+; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je LBB0_11
; CHECK-NEXT: ## %bb.7: ## %cond_false.i
-; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %esi
-; CHECK-NEXT: movzbl %sil, %ecx
-; CHECK-NEXT: movl %ecx, %eax
-; CHECK-NEXT: divb %dl
-; CHECK-NEXT: movl %eax, %r15d
-; CHECK-NEXT: testb %cl, %cl
+; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
+; CHECK-NEXT: cvtsi2ss %ecx, %xmm0
+; CHECK-NEXT: movzbl %al, %edx
+; CHECK-NEXT: cvtsi2ss %edx, %xmm1
+; CHECK-NEXT: divss %xmm1, %xmm0
+; CHECK-NEXT: cvttss2si %xmm0, %ebp
+; CHECK-NEXT: testl %ecx, %ecx
; CHECK-NEXT: jne LBB0_12
; CHECK-NEXT: jmp LBB0_14
; CHECK-NEXT: LBB0_8: ## %bb17
@@ -101,34 +99,42 @@ define ptr @ubyte_divmod(ptr %a, ptr %b) {
; CHECK-NEXT: LBB0_11: ## %cond_true.i
; CHECK-NEXT: movl $4, %edi
; CHECK-NEXT: callq _feraiseexcept
-; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
-; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %esi
-; CHECK-NEXT: xorl %r15d, %r15d
-; CHECK-NEXT: testb %sil, %sil
+; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
+; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
+; CHECK-NEXT: xorl %ebp, %ebp
+; CHECK-NEXT: testb %cl, %cl
; CHECK-NEXT: je LBB0_14
; CHECK-NEXT: LBB0_12: ## %cond_false.i
-; CHECK-NEXT: testb %dl, %dl
+; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je LBB0_14
; CHECK-NEXT: ## %bb.13: ## %cond_next17.i
-; CHECK-NEXT: movzbl %sil, %eax
-; CHECK-NEXT: divb %dl
-; CHECK-NEXT: movzbl %ah, %ebx
+; CHECK-NEXT: movzbl %al, %edx
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2ss %edx, %xmm0
+; CHECK-NEXT: movzbl %cl, %r15d
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: cvtsi2ss %r15d, %xmm1
+; CHECK-NEXT: divss %xmm0, %xmm1
+; CHECK-NEXT: cvttss2si %xmm1, %eax
+; CHECK-NEXT: ## kill: def $al killed $al killed $eax
+; CHECK-NEXT: mulb %dl
+; CHECK-NEXT: subb %al, %r15b
; CHECK-NEXT: jmp LBB0_18
; CHECK-NEXT: LBB0_14: ## %cond_true.i200
-; CHECK-NEXT: testb %dl, %dl
+; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne LBB0_17
; CHECK-NEXT: ## %bb.16: ## %cond_true14.i
; CHECK-NEXT: movl $4, %edi
; CHECK-NEXT: callq _feraiseexcept
; CHECK-NEXT: LBB0_17: ## %ubyte_ctype_remainder.exit
-; CHECK-NEXT: xorl %ebx, %ebx
+; CHECK-NEXT: xorl %r15d, %r15d
; CHECK-NEXT: LBB0_18: ## %ubyte_ctype_remainder.exit
; CHECK-NEXT: movq (%r14), %rax
; CHECK-NEXT: callq *224(%rax)
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: je LBB0_21
; CHECK-NEXT: ## %bb.19: ## %cond_true61
-; CHECK-NEXT: movl %eax, %ebp
+; CHECK-NEXT: movl %eax, %ebx
; CHECK-NEXT: movq (%r14), %rax
; CHECK-NEXT: movq _.str5 at GOTPCREL(%rip), %rdi
; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rsi
@@ -143,7 +149,7 @@ define ptr @ubyte_divmod(ptr %a, ptr %b) {
; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rsi
; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %edi
; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rcx
-; CHECK-NEXT: movl %ebp, %edx
+; CHECK-NEXT: movl %ebx, %edx
; CHECK-NEXT: callq *232(%rax)
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: jne LBB0_27
@@ -153,41 +159,40 @@ define ptr @ubyte_divmod(ptr %a, ptr %b) {
; CHECK-NEXT: testq %rax, %rax
; CHECK-NEXT: je LBB0_27
; CHECK-NEXT: ## %bb.22: ## %cond_next97
-; CHECK-NEXT: movq %rax, %r14
-; CHECK-NEXT: movq _PyArray_API at GOTPCREL(%rip), %r12
-; CHECK-NEXT: movq (%r12), %rax
+; CHECK-NEXT: movq %rax, %rbx
+; CHECK-NEXT: movq _PyArray_API at GOTPCREL(%rip), %r14
+; CHECK-NEXT: movq (%r14), %rax
; CHECK-NEXT: movq 200(%rax), %rdi
; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: callq *304(%rdi)
; CHECK-NEXT: testq %rax, %rax
; CHECK-NEXT: je LBB0_25
; CHECK-NEXT: ## %bb.23: ## %cond_next135
-; CHECK-NEXT: movb %r15b, 16(%rax)
-; CHECK-NEXT: movq %rax, 24(%r14)
-; CHECK-NEXT: movq (%r12), %rax
+; CHECK-NEXT: movb %bpl, 16(%rax)
+; CHECK-NEXT: movq %rax, 24(%rbx)
+; CHECK-NEXT: movq (%r14), %rax
; CHECK-NEXT: movq 200(%rax), %rdi
; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: callq *304(%rdi)
; CHECK-NEXT: testq %rax, %rax
; CHECK-NEXT: je LBB0_25
; CHECK-NEXT: ## %bb.24: ## %cond_next182
-; CHECK-NEXT: movb %bl, 16(%rax)
-; CHECK-NEXT: movq %rax, 32(%r14)
-; CHECK-NEXT: movq %r14, %rax
+; CHECK-NEXT: movb %r15b, 16(%rax)
+; CHECK-NEXT: movq %rax, 32(%rbx)
+; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_25: ## %cond_true113
-; CHECK-NEXT: decq (%r14)
+; CHECK-NEXT: decq (%rbx)
; CHECK-NEXT: jne LBB0_27
; CHECK-NEXT: ## %bb.26: ## %cond_true126
-; CHECK-NEXT: movq 8(%r14), %rax
-; CHECK-NEXT: movq %r14, %rdi
+; CHECK-NEXT: movq 8(%rbx), %rax
+; CHECK-NEXT: movq %rbx, %rdi
; CHECK-NEXT: callq *48(%rax)
; CHECK-NEXT: LBB0_27: ## %UnifiedReturnBlock
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: LBB0_28: ## %UnifiedReturnBlock
-; CHECK-NEXT: addq $32, %rsp
+; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: popq %rbx
-; CHECK-NEXT: popq %r12
; CHECK-NEXT: popq %r14
; CHECK-NEXT: popq %r15
; CHECK-NEXT: popq %rbp
diff --git a/llvm/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll b/llvm/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
index 53175413980f1..68d149606102d 100644
--- a/llvm/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
+++ b/llvm/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
@@ -9,31 +9,39 @@
define i32 @func_44(i16 signext %p_46) nounwind {
; SOURCE-SCHED-LABEL: func_44:
; SOURCE-SCHED: # %bb.0: # %entry
-; SOURCE-SCHED-NEXT: subl $12, %esp
+; SOURCE-SCHED-NEXT: pushl %ebx
+; SOURCE-SCHED-NEXT: subl $8, %esp
; SOURCE-SCHED-NEXT: movl g_5, %eax
; SOURCE-SCHED-NEXT: sarl %eax
; SOURCE-SCHED-NEXT: xorl %ecx, %ecx
; SOURCE-SCHED-NEXT: cmpl $2, %eax
; SOURCE-SCHED-NEXT: setge %cl
-; SOURCE-SCHED-NEXT: movzbl g_73, %edx
-; SOURCE-SCHED-NEXT: xorl %eax, %eax
-; SOURCE-SCHED-NEXT: subb {{[0-9]+}}(%esp), %al
-; SOURCE-SCHED-NEXT: testb %dl, %dl
+; SOURCE-SCHED-NEXT: movzbl g_73, %ebx
+; SOURCE-SCHED-NEXT: xorl %edx, %edx
+; SOURCE-SCHED-NEXT: subb {{[0-9]+}}(%esp), %dl
+; SOURCE-SCHED-NEXT: testb %bl, %bl
; SOURCE-SCHED-NEXT: jne .LBB0_2
; SOURCE-SCHED-NEXT: # %bb.1: # %bb11
-; SOURCE-SCHED-NEXT: movzbl %al, %eax
-; SOURCE-SCHED-NEXT: divb %dl
-; SOURCE-SCHED-NEXT: movzbl %ah, %eax
+; SOURCE-SCHED-NEXT: movzbl %bl, %eax
+; SOURCE-SCHED-NEXT: cvtsi2ss %eax, %xmm0
+; SOURCE-SCHED-NEXT: movzbl %dl, %eax
+; SOURCE-SCHED-NEXT: cvtsi2ss %eax, %xmm1
+; SOURCE-SCHED-NEXT: divss %xmm0, %xmm1
+; SOURCE-SCHED-NEXT: cvttss2si %xmm1, %eax
+; SOURCE-SCHED-NEXT: # kill: def $al killed $al killed $eax
+; SOURCE-SCHED-NEXT: mulb %bl
+; SOURCE-SCHED-NEXT: subb %al, %dl
; SOURCE-SCHED-NEXT: .LBB0_2: # %bb12
-; SOURCE-SCHED-NEXT: xorl %edx, %edx
-; SOURCE-SCHED-NEXT: testb %al, %al
-; SOURCE-SCHED-NEXT: setne %dl
+; SOURCE-SCHED-NEXT: xorl %eax, %eax
+; SOURCE-SCHED-NEXT: testb %dl, %dl
+; SOURCE-SCHED-NEXT: setne %al
; SOURCE-SCHED-NEXT: subl $4, %esp
; SOURCE-SCHED-NEXT: pushl $0
; SOURCE-SCHED-NEXT: pushl %ecx
-; SOURCE-SCHED-NEXT: pushl %edx
+; SOURCE-SCHED-NEXT: pushl %eax
; SOURCE-SCHED-NEXT: calll func_48 at PLT
-; SOURCE-SCHED-NEXT: addl $28, %esp
+; SOURCE-SCHED-NEXT: addl $24, %esp
+; SOURCE-SCHED-NEXT: popl %ebx
; SOURCE-SCHED-NEXT: retl
entry:
%0 = load i32, ptr @g_5, align 4
diff --git a/llvm/test/CodeGen/X86/2010-09-01-RemoveCopyByCommutingDef.ll b/llvm/test/CodeGen/X86/2010-09-01-RemoveCopyByCommutingDef.ll
index b68aaf5db615a..27f52a5df8be6 100644
--- a/llvm/test/CodeGen/X86/2010-09-01-RemoveCopyByCommutingDef.ll
+++ b/llvm/test/CodeGen/X86/2010-09-01-RemoveCopyByCommutingDef.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -verify-machineinstrs | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-apple-darwin10.0.0"
@@ -5,21 +6,39 @@ target triple = "x86_64-apple-darwin10.0.0"
; This test exercises the alias checking in SimpleRegisterCoalescing::RemoveCopyByCommutingDef.
define void @f(ptr %w, ptr %h, ptr %_this, ptr %image) nounwind ssp {
+; CHECK-LABEL: f:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: pushq %rax
+; CHECK-NEXT: movq %rsi, %rbx
+; CHECK-NEXT: movq %rdi, %r14
+; CHECK-NEXT: movq %rdx, %rdi
+; CHECK-NEXT: movq %rcx, %rsi
+; CHECK-NEXT: callq _g
+; CHECK-NEXT: movl (%rbx), %ecx
+; CHECK-NEXT: imull %eax, %ecx
+; CHECK-NEXT: shrq $32, %rax
+; CHECK-NEXT: cvtsi2sd %eax, %xmm0
+; CHECK-NEXT: cvtsi2sd %ecx, %xmm1
+; CHECK-NEXT: divsd %xmm0, %xmm1
+; CHECK-NEXT: cvttsd2si %xmm1, %eax
+; CHECK-NEXT: movl %eax, (%r14)
+; CHECK-NEXT: addq $8, %rsp
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: retq
%x1 = tail call i64 @g(ptr %_this, ptr %image) nounwind ; <i64> [#uses=3]
%tmp1 = trunc i64 %x1 to i32 ; <i32> [#uses=1]
-; CHECK: movl (%r{{.*}}), %
%x4 = load i32, ptr %h, align 4 ; <i32> [#uses=1]
; The imull clobbers a 32-bit register.
-; CHECK: imull %{{...}}, %e[[CLOBBER:..]]
%x5 = mul nsw i32 %x4, %tmp1 ; <i32> [#uses=1]
; So we cannot use the corresponding 64-bit register anymore.
-; CHECK-NOT: shrq $32, %r[[CLOBBER]]
%btmp3 = lshr i64 %x1, 32 ; <i64> [#uses=1]
%btmp4 = trunc i64 %btmp3 to i32 ; <i32> [#uses=1]
-; CHECK: idiv
%x6 = sdiv i32 %x5, %btmp4 ; <i32> [#uses=1]
store i32 %x6, ptr %w, align 4
ret void
diff --git a/llvm/test/CodeGen/X86/MachineSink-Issue98477.ll b/llvm/test/CodeGen/X86/MachineSink-Issue98477.ll
index 4abb1f8e1ca42..211f92b0b191a 100644
--- a/llvm/test/CodeGen/X86/MachineSink-Issue98477.ll
+++ b/llvm/test/CodeGen/X86/MachineSink-Issue98477.ll
@@ -7,42 +7,52 @@ target triple = "x86_64-unknown-linux-gnu"
define i32 @main(i1 %tobool.not, i32 %0) {
; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movl $1, %r8d
+; CHECK-NEXT: movl $1, %edx
; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: jne .LBB0_8
; CHECK-NEXT: .LBB0_1: # %j.preheader
-; CHECK-NEXT: xorl %r9d, %r9d
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2sd %esi, %xmm0
+; CHECK-NEXT: movsd {{.*#+}} xmm1 = [1.0E+0,0.0E+0]
+; CHECK-NEXT: divsd %xmm0, %xmm1
+; CHECK-NEXT: cvttsd2si %xmm1, %r8d
+; CHECK-NEXT: imull %esi, %r8d
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: subl %r8d, %eax
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2ss %edx, %xmm0
+; CHECK-NEXT: movss {{.*#+}} xmm1 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: divss %xmm0, %xmm1
+; CHECK-NEXT: cvttss2si %xmm1, %r8
+; CHECK-NEXT: imull %edx, %r8d
+; CHECK-NEXT: movl $1, %edx
+; CHECK-NEXT: subl %r8d, %edx
; CHECK-NEXT: jmp .LBB0_2
; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: .LBB0_5: # %if.then4
+; CHECK-NEXT: .LBB0_4: # %if.then4
; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1
-; CHECK-NEXT: movl $1, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %r8d
; CHECK-NEXT: testb $1, %dil
-; CHECK-NEXT: jne .LBB0_6
+; CHECK-NEXT: jne .LBB0_5
; CHECK-NEXT: .LBB0_2: # %j
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: movl $1, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: idivl %esi
-; CHECK-NEXT: movl %edx, %ecx
-; CHECK-NEXT: testb %r9b, %r9b
-; CHECK-NEXT: jne .LBB0_5
+; CHECK-NEXT: testb %cl, %cl
+; CHECK-NEXT: jne .LBB0_4
; CHECK-NEXT: # %bb.3: # %j
; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1
-; CHECK-NEXT: testl %r9d, %r9d
-; CHECK-NEXT: js .LBB0_5
-; CHECK-NEXT: # %bb.4:
-; CHECK-NEXT: movl %r9d, %edx
-; CHECK-NEXT: .LBB0_6: # %if.end9
-; CHECK-NEXT: testl %edx, %edx
+; CHECK-NEXT: testl %ecx, %ecx
+; CHECK-NEXT: js .LBB0_4
+; CHECK-NEXT: # %bb.6: # %if.end9
+; CHECK-NEXT: testl %ecx, %ecx
; CHECK-NEXT: jne .LBB0_7
; CHECK-NEXT: .LBB0_8: # %if.end13
-; CHECK-NEXT: xorl %r8d, %r8d
+; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: jmp .LBB0_1
+; CHECK-NEXT: .LBB0_5:
+; CHECK-NEXT: movl %edx, %ecx
+; CHECK-NEXT: testl %ecx, %ecx
+; CHECK-NEXT: je .LBB0_8
; CHECK-NEXT: .LBB0_7: # %while.body.lr.ph
-; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: retq
entry:
br i1 %tobool.not, label %if.end13, label %j.preheader
diff --git a/llvm/test/CodeGen/X86/anyext.ll b/llvm/test/CodeGen/X86/anyext.ll
index ec23948d1a431..d8d1e29acb088 100644
--- a/llvm/test/CodeGen/X86/anyext.ll
+++ b/llvm/test/CodeGen/X86/anyext.ll
@@ -15,9 +15,11 @@ define i32 @foo(i32 %p, i8 zeroext %x) nounwind {
;
; X64-LABEL: foo:
; X64: # %bb.0:
+; X64-NEXT: cvtsi2ss %esi, %xmm0
; X64-NEXT: movzbl %dil, %eax
-; X64-NEXT: divb %sil
-; X64-NEXT: movzbl %al, %eax
+; X64-NEXT: cvtsi2ss %eax, %xmm1
+; X64-NEXT: divss %xmm0, %xmm1
+; X64-NEXT: cvttss2si %xmm1, %eax
; X64-NEXT: andl $1, %eax
; X64-NEXT: retq
%q = trunc i32 %p to i8
@@ -39,11 +41,11 @@ define i32 @bar(i32 %p, i16 zeroext %x) nounwind {
;
; X64-LABEL: bar:
; X64: # %bb.0:
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: # kill: def $ax killed $ax killed $eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divw %si
-; X64-NEXT: # kill: def $ax killed $ax def $eax
+; X64-NEXT: cvtsi2ss %esi, %xmm0
+; X64-NEXT: movzwl %di, %eax
+; X64-NEXT: cvtsi2ss %eax, %xmm1
+; X64-NEXT: divss %xmm0, %xmm1
+; X64-NEXT: cvttss2si %xmm1, %eax
; X64-NEXT: andl $1, %eax
; X64-NEXT: retq
%q = trunc i32 %p to i16
diff --git a/llvm/test/CodeGen/X86/apx/ctest.ll b/llvm/test/CodeGen/X86/apx/ctest.ll
index c82431781c88f..a476308690c01 100644
--- a/llvm/test/CodeGen/X86/apx/ctest.ll
+++ b/llvm/test/CodeGen/X86/apx/ctest.ll
@@ -1489,75 +1489,84 @@ if.end: ; preds = %entry, %if.then
define void @cmp_srem(ptr %p, i32 %a, ptr %b) {
; CHECK-LABEL: cmp_srem:
; CHECK: # %bb.0: # %bb
-; CHECK-NEXT: movq %rdx, %rcx
-; CHECK-NEXT: movl %esi, %eax
-; CHECK-NEXT: subl $1, %eax
-; CHECK-NEXT: movl (%rdi), %edi
-; CHECK-NEXT: cltd
-; CHECK-NEXT: {nf} idivl %edi
-; CHECK-NEXT: ctestnel {dfv=} %edx, %edx
+; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
+; CHECK-NEXT: leal -1(%rsi), %eax
+; CHECK-NEXT: movl (%rdi), %ecx
+; CHECK-NEXT: cvtsi2sd %ecx, %xmm0
+; CHECK-NEXT: cvtsi2sd %eax, %xmm1
+; CHECK-NEXT: divsd %xmm0, %xmm1
+; CHECK-NEXT: cvttsd2si %xmm1, %eax
+; CHECK-NEXT: imull %ecx, %eax
+; CHECK-NEXT: movl %esi, %edi
+; CHECK-NEXT: subl $1, %edi
+; CHECK-NEXT: ccmpnel {dfv=} %eax, %edi
; CHECK-NEXT: sete %al
; CHECK-NEXT: cmpl $1, %esi
-; CHECK-NEXT: ccmpael {dfv=zf} $1, %edi
-; CHECK-NEXT: sete %dl
-; CHECK-NEXT: orb %al, %dl
-; CHECK-NEXT: movb %dl, (%rcx)
+; CHECK-NEXT: ccmpael {dfv=zf} $1, %ecx
+; CHECK-NEXT: sete %cl
+; CHECK-NEXT: orb %al, %cl
+; CHECK-NEXT: movb %cl, (%rdx)
; CHECK-NEXT: retq
;
; NDD-LABEL: cmp_srem:
; NDD: # %bb.0: # %bb
-; NDD-NEXT: movq %rdx, %rcx
-; NDD-NEXT: subl $1, %esi, %eax
-; NDD-NEXT: movl (%rdi), %edi
-; NDD-NEXT: cltd
-; NDD-NEXT: {nf} idivl %edi
-; NDD-NEXT: ctestnel {dfv=} %edx, %edx
+; NDD-NEXT: {nf} subl $1, %esi, %eax
+; NDD-NEXT: movl (%rdi), %ecx
+; NDD-NEXT: cvtsi2sd %ecx, %xmm0
+; NDD-NEXT: cvtsi2sd %eax, %xmm1
+; NDD-NEXT: divsd %xmm0, %xmm1
+; NDD-NEXT: cvttsd2si %xmm1, %eax
+; NDD-NEXT: imull %ecx, %eax
+; NDD-NEXT: subl $1, %esi, %edi
+; NDD-NEXT: ccmpnel {dfv=} %eax, %edi
; NDD-NEXT: sete %al
; NDD-NEXT: cmpl $1, %esi
-; NDD-NEXT: ccmpael {dfv=zf} $1, %edi
-; NDD-NEXT: sete %dl
-; NDD-NEXT: orb %dl, %al
-; NDD-NEXT: movb %al, (%rcx)
+; NDD-NEXT: ccmpael {dfv=zf} $1, %ecx
+; NDD-NEXT: sete %cl
+; NDD-NEXT: orb %cl, %al
+; NDD-NEXT: movb %al, (%rdx)
; NDD-NEXT: retq
;
; PREFER_NO_LEGACY_SETCC-LABEL: cmp_srem:
; PREFER_NO_LEGACY_SETCC: # %bb.0: # %bb
-; PREFER_NO_LEGACY_SETCC-NEXT: movq %rdx, %rcx # encoding: [0x48,0x89,0xd1]
-; PREFER_NO_LEGACY_SETCC-NEXT: movl %esi, %eax # encoding: [0x89,0xf0]
-; PREFER_NO_LEGACY_SETCC-NEXT: movl (%rdi), %esi # encoding: [0x8b,0x37]
-; PREFER_NO_LEGACY_SETCC-NEXT: cmpl $1, %esi # encoding: [0x83,0xfe,0x01]
-; PREFER_NO_LEGACY_SETCC-NEXT: setzue %dl # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc2]
-; PREFER_NO_LEGACY_SETCC-NEXT: subl $1, %eax # encoding: [0x83,0xe8,0x01]
+; PREFER_NO_LEGACY_SETCC-NEXT: movl (%rdi), %eax # encoding: [0x8b,0x07]
+; PREFER_NO_LEGACY_SETCC-NEXT: cmpl $1, %eax # encoding: [0x83,0xf8,0x01]
+; PREFER_NO_LEGACY_SETCC-NEXT: setzue %cl # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc1]
+; PREFER_NO_LEGACY_SETCC-NEXT: subl $1, %esi # encoding: [0x83,0xee,0x01]
; PREFER_NO_LEGACY_SETCC-NEXT: setzub %dil # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc7]
-; PREFER_NO_LEGACY_SETCC-NEXT: setzune %r8b # encoding: [0x62,0xd4,0x7f,0x18,0x45,0xc0]
-; PREFER_NO_LEGACY_SETCC-NEXT: orb %dl, %dil # encoding: [0x40,0x08,0xd7]
-; PREFER_NO_LEGACY_SETCC-NEXT: cltd # encoding: [0x99]
-; PREFER_NO_LEGACY_SETCC-NEXT: idivl %esi # encoding: [0xf7,0xfe]
-; PREFER_NO_LEGACY_SETCC-NEXT: testl %edx, %edx # encoding: [0x85,0xd2]
+; PREFER_NO_LEGACY_SETCC-NEXT: cvtsi2sd %eax, %xmm0 # encoding: [0xf2,0x0f,0x2a,0xc0]
+; PREFER_NO_LEGACY_SETCC-NEXT: cvtsi2sd %esi, %xmm1 # encoding: [0xf2,0x0f,0x2a,0xce]
+; PREFER_NO_LEGACY_SETCC-NEXT: divsd %xmm0, %xmm1 # encoding: [0xf2,0x0f,0x5e,0xc8]
+; PREFER_NO_LEGACY_SETCC-NEXT: cvttsd2si %xmm1, %r8d # encoding: [0xf2,0x44,0x0f,0x2c,0xc1]
+; PREFER_NO_LEGACY_SETCC-NEXT: setzune %r9b # encoding: [0x62,0xd4,0x7f,0x18,0x45,0xc1]
+; PREFER_NO_LEGACY_SETCC-NEXT: orb %cl, %dil # encoding: [0x40,0x08,0xcf]
+; PREFER_NO_LEGACY_SETCC-NEXT: imull %eax, %r8d # encoding: [0x44,0x0f,0xaf,0xc0]
+; PREFER_NO_LEGACY_SETCC-NEXT: cmpl %r8d, %esi # encoding: [0x44,0x39,0xc6]
; PREFER_NO_LEGACY_SETCC-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; PREFER_NO_LEGACY_SETCC-NEXT: andb %r8b, %al # encoding: [0x44,0x20,0xc0]
+; PREFER_NO_LEGACY_SETCC-NEXT: andb %r9b, %al # encoding: [0x44,0x20,0xc8]
; PREFER_NO_LEGACY_SETCC-NEXT: orb %dil, %al # encoding: [0x40,0x08,0xf8]
-; PREFER_NO_LEGACY_SETCC-NEXT: movb %al, (%rcx) # encoding: [0x88,0x01]
+; PREFER_NO_LEGACY_SETCC-NEXT: movb %al, (%rdx) # encoding: [0x88,0x02]
; PREFER_NO_LEGACY_SETCC-NEXT: retq # encoding: [0xc3]
;
; PREFER_LEGACY_SETCC-LABEL: cmp_srem:
; PREFER_LEGACY_SETCC: # %bb.0: # %bb
-; PREFER_LEGACY_SETCC-NEXT: movq %rdx, %rcx # encoding: [0x48,0x89,0xd1]
-; PREFER_LEGACY_SETCC-NEXT: movl %esi, %eax # encoding: [0x89,0xf0]
-; PREFER_LEGACY_SETCC-NEXT: movl (%rdi), %esi # encoding: [0x8b,0x37]
-; PREFER_LEGACY_SETCC-NEXT: cmpl $1, %esi # encoding: [0x83,0xfe,0x01]
-; PREFER_LEGACY_SETCC-NEXT: sete %dl # encoding: [0x0f,0x94,0xc2]
-; PREFER_LEGACY_SETCC-NEXT: subl $1, %eax # encoding: [0x83,0xe8,0x01]
+; PREFER_LEGACY_SETCC-NEXT: movl (%rdi), %eax # encoding: [0x8b,0x07]
+; PREFER_LEGACY_SETCC-NEXT: cmpl $1, %eax # encoding: [0x83,0xf8,0x01]
+; PREFER_LEGACY_SETCC-NEXT: sete %cl # encoding: [0x0f,0x94,0xc1]
+; PREFER_LEGACY_SETCC-NEXT: subl $1, %esi # encoding: [0x83,0xee,0x01]
; PREFER_LEGACY_SETCC-NEXT: setb %dil # encoding: [0x40,0x0f,0x92,0xc7]
-; PREFER_LEGACY_SETCC-NEXT: setne %r8b # encoding: [0x41,0x0f,0x95,0xc0]
-; PREFER_LEGACY_SETCC-NEXT: orb %dl, %dil # encoding: [0x40,0x08,0xd7]
-; PREFER_LEGACY_SETCC-NEXT: cltd # encoding: [0x99]
-; PREFER_LEGACY_SETCC-NEXT: idivl %esi # encoding: [0xf7,0xfe]
-; PREFER_LEGACY_SETCC-NEXT: testl %edx, %edx # encoding: [0x85,0xd2]
+; PREFER_LEGACY_SETCC-NEXT: cvtsi2sd %eax, %xmm0 # encoding: [0xf2,0x0f,0x2a,0xc0]
+; PREFER_LEGACY_SETCC-NEXT: cvtsi2sd %esi, %xmm1 # encoding: [0xf2,0x0f,0x2a,0xce]
+; PREFER_LEGACY_SETCC-NEXT: divsd %xmm0, %xmm1 # encoding: [0xf2,0x0f,0x5e,0xc8]
+; PREFER_LEGACY_SETCC-NEXT: cvttsd2si %xmm1, %r8d # encoding: [0xf2,0x44,0x0f,0x2c,0xc1]
+; PREFER_LEGACY_SETCC-NEXT: setne %r9b # encoding: [0x41,0x0f,0x95,0xc1]
+; PREFER_LEGACY_SETCC-NEXT: orb %cl, %dil # encoding: [0x40,0x08,0xcf]
+; PREFER_LEGACY_SETCC-NEXT: imull %eax, %r8d # encoding: [0x44,0x0f,0xaf,0xc0]
+; PREFER_LEGACY_SETCC-NEXT: cmpl %r8d, %esi # encoding: [0x44,0x39,0xc6]
; PREFER_LEGACY_SETCC-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
-; PREFER_LEGACY_SETCC-NEXT: andb %r8b, %al # encoding: [0x44,0x20,0xc0]
+; PREFER_LEGACY_SETCC-NEXT: andb %r9b, %al # encoding: [0x44,0x20,0xc8]
; PREFER_LEGACY_SETCC-NEXT: orb %dil, %al # encoding: [0x40,0x08,0xf8]
-; PREFER_LEGACY_SETCC-NEXT: movb %al, (%rcx) # encoding: [0x88,0x01]
+; PREFER_LEGACY_SETCC-NEXT: movb %al, (%rdx) # encoding: [0x88,0x02]
; PREFER_LEGACY_SETCC-NEXT: retq # encoding: [0xc3]
bb:
%i = icmp eq i32 %a, 0
diff --git a/llvm/test/CodeGen/X86/atomic-unordered.ll b/llvm/test/CodeGen/X86/atomic-unordered.ll
index edfdec37150c2..b54cb06a1a83b 100644
--- a/llvm/test/CodeGen/X86/atomic-unordered.ll
+++ b/llvm/test/CodeGen/X86/atomic-unordered.ll
@@ -640,10 +640,13 @@ define i64 @load_fold_sdiv2(ptr %p, i64 %v2) {
; CHECK-O3-NEXT: idivq %rsi
; CHECK-O3-NEXT: retq
; CHECK-O3-NEXT: .LBB35_1:
-; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-O3-NEXT: xorl %edx, %edx
-; CHECK-O3-NEXT: divl %esi
-; CHECK-O3-NEXT: # kill: def $eax killed $eax def $rax
+; CHECK-O3-NEXT: movl %esi, %ecx
+; CHECK-O3-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm0
+; CHECK-O3-NEXT: movl %eax, %eax
+; CHECK-O3-NEXT: vcvtsi2sd %rax, %xmm15, %xmm1
+; CHECK-O3-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; CHECK-O3-NEXT: vcvttsd2si %xmm0, %rax
+; CHECK-O3-NEXT: movl %eax, %eax
; CHECK-O3-NEXT: retq
%v = load atomic i64, ptr %p unordered, align 8
%ret = sdiv i64 %v, %v2
@@ -671,10 +674,13 @@ define i64 @load_fold_sdiv3(ptr %p1, ptr %p2) {
; CHECK-O3-NEXT: idivq %rcx
; CHECK-O3-NEXT: retq
; CHECK-O3-NEXT: .LBB36_1:
-; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-O3-NEXT: xorl %edx, %edx
-; CHECK-O3-NEXT: divl %ecx
-; CHECK-O3-NEXT: # kill: def $eax killed $eax def $rax
+; CHECK-O3-NEXT: movl %ecx, %ecx
+; CHECK-O3-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm0
+; CHECK-O3-NEXT: movl %eax, %eax
+; CHECK-O3-NEXT: vcvtsi2sd %rax, %xmm15, %xmm1
+; CHECK-O3-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; CHECK-O3-NEXT: vcvttsd2si %xmm0, %rax
+; CHECK-O3-NEXT: movl %eax, %eax
; CHECK-O3-NEXT: retq
%v = load atomic i64, ptr %p1 unordered, align 8
%v2 = load atomic i64, ptr %p2 unordered, align 8
@@ -726,10 +732,13 @@ define i64 @load_fold_udiv2(ptr %p, i64 %v2) {
; CHECK-O3-NEXT: divq %rsi
; CHECK-O3-NEXT: retq
; CHECK-O3-NEXT: .LBB38_1:
-; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-O3-NEXT: xorl %edx, %edx
-; CHECK-O3-NEXT: divl %esi
-; CHECK-O3-NEXT: # kill: def $eax killed $eax def $rax
+; CHECK-O3-NEXT: movl %esi, %ecx
+; CHECK-O3-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm0
+; CHECK-O3-NEXT: movl %eax, %eax
+; CHECK-O3-NEXT: vcvtsi2sd %rax, %xmm15, %xmm1
+; CHECK-O3-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; CHECK-O3-NEXT: vcvttsd2si %xmm0, %rax
+; CHECK-O3-NEXT: movl %eax, %eax
; CHECK-O3-NEXT: retq
%v = load atomic i64, ptr %p unordered, align 8
%ret = udiv i64 %v, %v2
@@ -758,10 +767,13 @@ define i64 @load_fold_udiv3(ptr %p1, ptr %p2) {
; CHECK-O3-NEXT: divq %rcx
; CHECK-O3-NEXT: retq
; CHECK-O3-NEXT: .LBB39_1:
-; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-O3-NEXT: xorl %edx, %edx
-; CHECK-O3-NEXT: divl %ecx
-; CHECK-O3-NEXT: # kill: def $eax killed $eax def $rax
+; CHECK-O3-NEXT: movl %ecx, %ecx
+; CHECK-O3-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm0
+; CHECK-O3-NEXT: movl %eax, %eax
+; CHECK-O3-NEXT: vcvtsi2sd %rax, %xmm15, %xmm1
+; CHECK-O3-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; CHECK-O3-NEXT: vcvttsd2si %xmm0, %rax
+; CHECK-O3-NEXT: movl %eax, %eax
; CHECK-O3-NEXT: retq
%v = load atomic i64, ptr %p1 unordered, align 8
%v2 = load atomic i64, ptr %p2 unordered, align 8
@@ -824,10 +836,14 @@ define i64 @load_fold_srem2(ptr %p, i64 %v2) {
; CHECK-O3-NEXT: movq %rdx, %rax
; CHECK-O3-NEXT: retq
; CHECK-O3-NEXT: .LBB41_1:
-; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-O3-NEXT: xorl %edx, %edx
-; CHECK-O3-NEXT: divl %esi
-; CHECK-O3-NEXT: movl %edx, %eax
+; CHECK-O3-NEXT: movl %esi, %ecx
+; CHECK-O3-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm0
+; CHECK-O3-NEXT: movl %eax, %ecx
+; CHECK-O3-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm1
+; CHECK-O3-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; CHECK-O3-NEXT: vcvttsd2si %xmm0, %rcx
+; CHECK-O3-NEXT: imull %esi, %ecx
+; CHECK-O3-NEXT: subl %ecx, %eax
; CHECK-O3-NEXT: retq
%v = load atomic i64, ptr %p unordered, align 8
%ret = srem i64 %v, %v2
@@ -857,10 +873,14 @@ define i64 @load_fold_srem3(ptr %p1, ptr %p2) {
; CHECK-O3-NEXT: movq %rdx, %rax
; CHECK-O3-NEXT: retq
; CHECK-O3-NEXT: .LBB42_1:
-; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-O3-NEXT: xorl %edx, %edx
-; CHECK-O3-NEXT: divl %ecx
-; CHECK-O3-NEXT: movl %edx, %eax
+; CHECK-O3-NEXT: movl %ecx, %edx
+; CHECK-O3-NEXT: vcvtsi2sd %rdx, %xmm15, %xmm0
+; CHECK-O3-NEXT: movl %eax, %edx
+; CHECK-O3-NEXT: vcvtsi2sd %rdx, %xmm15, %xmm1
+; CHECK-O3-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; CHECK-O3-NEXT: vcvttsd2si %xmm0, %rdx
+; CHECK-O3-NEXT: imull %ecx, %edx
+; CHECK-O3-NEXT: subl %edx, %eax
; CHECK-O3-NEXT: retq
%v = load atomic i64, ptr %p1 unordered, align 8
%v2 = load atomic i64, ptr %p2 unordered, align 8
@@ -920,10 +940,14 @@ define i64 @load_fold_urem2(ptr %p, i64 %v2) {
; CHECK-O3-NEXT: movq %rdx, %rax
; CHECK-O3-NEXT: retq
; CHECK-O3-NEXT: .LBB44_1:
-; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-O3-NEXT: xorl %edx, %edx
-; CHECK-O3-NEXT: divl %esi
-; CHECK-O3-NEXT: movl %edx, %eax
+; CHECK-O3-NEXT: movl %esi, %ecx
+; CHECK-O3-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm0
+; CHECK-O3-NEXT: movl %eax, %ecx
+; CHECK-O3-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm1
+; CHECK-O3-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; CHECK-O3-NEXT: vcvttsd2si %xmm0, %rcx
+; CHECK-O3-NEXT: imull %esi, %ecx
+; CHECK-O3-NEXT: subl %ecx, %eax
; CHECK-O3-NEXT: retq
%v = load atomic i64, ptr %p unordered, align 8
%ret = urem i64 %v, %v2
@@ -954,10 +978,14 @@ define i64 @load_fold_urem3(ptr %p1, ptr %p2) {
; CHECK-O3-NEXT: movq %rdx, %rax
; CHECK-O3-NEXT: retq
; CHECK-O3-NEXT: .LBB45_1:
-; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-O3-NEXT: xorl %edx, %edx
-; CHECK-O3-NEXT: divl %ecx
-; CHECK-O3-NEXT: movl %edx, %eax
+; CHECK-O3-NEXT: movl %ecx, %edx
+; CHECK-O3-NEXT: vcvtsi2sd %rdx, %xmm15, %xmm0
+; CHECK-O3-NEXT: movl %eax, %edx
+; CHECK-O3-NEXT: vcvtsi2sd %rdx, %xmm15, %xmm1
+; CHECK-O3-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; CHECK-O3-NEXT: vcvttsd2si %xmm0, %rdx
+; CHECK-O3-NEXT: imull %ecx, %edx
+; CHECK-O3-NEXT: subl %edx, %eax
; CHECK-O3-NEXT: retq
%v = load atomic i64, ptr %p1 unordered, align 8
%v2 = load atomic i64, ptr %p2 unordered, align 8
@@ -1477,10 +1505,13 @@ define void @rmw_fold_sdiv2(ptr %p, i64 %v) {
; CHECK-O3-NEXT: movq %rax, (%rdi)
; CHECK-O3-NEXT: retq
; CHECK-O3-NEXT: .LBB74_1:
-; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-O3-NEXT: xorl %edx, %edx
-; CHECK-O3-NEXT: divl %esi
-; CHECK-O3-NEXT: # kill: def $eax killed $eax def $rax
+; CHECK-O3-NEXT: movl %esi, %ecx
+; CHECK-O3-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm0
+; CHECK-O3-NEXT: movl %eax, %eax
+; CHECK-O3-NEXT: vcvtsi2sd %rax, %xmm15, %xmm1
+; CHECK-O3-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; CHECK-O3-NEXT: vcvttsd2si %xmm0, %rax
+; CHECK-O3-NEXT: movl %eax, %eax
; CHECK-O3-NEXT: movq %rax, (%rdi)
; CHECK-O3-NEXT: retq
%prev = load atomic i64, ptr %p unordered, align 8
@@ -1529,10 +1560,13 @@ define void @rmw_fold_udiv2(ptr %p, i64 %v) {
; CHECK-O3-NEXT: movq %rax, (%rdi)
; CHECK-O3-NEXT: retq
; CHECK-O3-NEXT: .LBB76_1:
-; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-O3-NEXT: xorl %edx, %edx
-; CHECK-O3-NEXT: divl %esi
-; CHECK-O3-NEXT: # kill: def $eax killed $eax def $rax
+; CHECK-O3-NEXT: movl %esi, %ecx
+; CHECK-O3-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm0
+; CHECK-O3-NEXT: movl %eax, %eax
+; CHECK-O3-NEXT: vcvtsi2sd %rax, %xmm15, %xmm1
+; CHECK-O3-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; CHECK-O3-NEXT: vcvttsd2si %xmm0, %rax
+; CHECK-O3-NEXT: movl %eax, %eax
; CHECK-O3-NEXT: movq %rax, (%rdi)
; CHECK-O3-NEXT: retq
%prev = load atomic i64, ptr %p unordered, align 8
@@ -1607,11 +1641,15 @@ define void @rmw_fold_srem2(ptr %p, i64 %v) {
; CHECK-O3-NEXT: movq %rdx, (%rdi)
; CHECK-O3-NEXT: retq
; CHECK-O3-NEXT: .LBB78_1:
-; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-O3-NEXT: xorl %edx, %edx
-; CHECK-O3-NEXT: divl %esi
-; CHECK-O3-NEXT: # kill: def $edx killed $edx def $rdx
-; CHECK-O3-NEXT: movq %rdx, (%rdi)
+; CHECK-O3-NEXT: movl %esi, %ecx
+; CHECK-O3-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm0
+; CHECK-O3-NEXT: movl %eax, %ecx
+; CHECK-O3-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm1
+; CHECK-O3-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; CHECK-O3-NEXT: vcvttsd2si %xmm0, %rcx
+; CHECK-O3-NEXT: imull %esi, %ecx
+; CHECK-O3-NEXT: subl %ecx, %eax
+; CHECK-O3-NEXT: movq %rax, (%rdi)
; CHECK-O3-NEXT: retq
%prev = load atomic i64, ptr %p unordered, align 8
%val = srem i64 %prev, %v
@@ -1675,11 +1713,15 @@ define void @rmw_fold_urem2(ptr %p, i64 %v) {
; CHECK-O3-NEXT: movq %rdx, (%rdi)
; CHECK-O3-NEXT: retq
; CHECK-O3-NEXT: .LBB80_1:
-; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-O3-NEXT: xorl %edx, %edx
-; CHECK-O3-NEXT: divl %esi
-; CHECK-O3-NEXT: # kill: def $edx killed $edx def $rdx
-; CHECK-O3-NEXT: movq %rdx, (%rdi)
+; CHECK-O3-NEXT: movl %esi, %ecx
+; CHECK-O3-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm0
+; CHECK-O3-NEXT: movl %eax, %ecx
+; CHECK-O3-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm1
+; CHECK-O3-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; CHECK-O3-NEXT: vcvttsd2si %xmm0, %rcx
+; CHECK-O3-NEXT: imull %esi, %ecx
+; CHECK-O3-NEXT: subl %ecx, %eax
+; CHECK-O3-NEXT: movq %rax, (%rdi)
; CHECK-O3-NEXT: retq
%prev = load atomic i64, ptr %p unordered, align 8
%val = urem i64 %prev, %v
diff --git a/llvm/test/CodeGen/X86/backpropmask.ll b/llvm/test/CodeGen/X86/backpropmask.ll
index 0e6b5fef7f064..041c6d25edaf4 100644
--- a/llvm/test/CodeGen/X86/backpropmask.ll
+++ b/llvm/test/CodeGen/X86/backpropmask.ll
@@ -13,12 +13,18 @@
define dso_local void @PR37667() {
; CHECK-LABEL: PR37667:
; CHECK: # %bb.0:
-; CHECK-NEXT: movl b(%rip), %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl d(%rip)
-; CHECK-NEXT: orl c(%rip), %edx
-; CHECK-NEXT: movzbl %dl, %eax
-; CHECK-NEXT: movl %eax, a(%rip)
+; CHECK-NEXT: movzbl c(%rip), %eax
+; CHECK-NEXT: movl b(%rip), %ecx
+; CHECK-NEXT: movl d(%rip), %edx
+; CHECK-NEXT: cvtsi2sd %rdx, %xmm0
+; CHECK-NEXT: cvtsi2sd %rcx, %xmm1
+; CHECK-NEXT: divsd %xmm0, %xmm1
+; CHECK-NEXT: cvttsd2si %xmm1, %rsi
+; CHECK-NEXT: imull %edx, %esi
+; CHECK-NEXT: subl %esi, %ecx
+; CHECK-NEXT: movzbl %cl, %ecx
+; CHECK-NEXT: orl %eax, %ecx
+; CHECK-NEXT: movl %ecx, a(%rip)
; CHECK-NEXT: retq
%t0 = load i32, ptr @c, align 4
%t1 = load i32, ptr @b, align 4
@@ -33,12 +39,17 @@ define dso_local void @PR37667() {
define dso_local void @PR37060() {
; CHECK-LABEL: PR37060:
; CHECK: # %bb.0:
-; CHECK-NEXT: movl $-1, %eax
-; CHECK-NEXT: cltd
-; CHECK-NEXT: idivl c(%rip)
-; CHECK-NEXT: xorl b(%rip), %edx
-; CHECK-NEXT: movzbl %dl, %eax
-; CHECK-NEXT: movl %eax, a(%rip)
+; CHECK-NEXT: movl c(%rip), %eax
+; CHECK-NEXT: cvtsi2sd %eax, %xmm0
+; CHECK-NEXT: movsd {{.*#+}} xmm1 = [-1.0E+0,0.0E+0]
+; CHECK-NEXT: divsd %xmm0, %xmm1
+; CHECK-NEXT: cvttsd2si %xmm1, %ecx
+; CHECK-NEXT: imull %eax, %ecx
+; CHECK-NEXT: movzbl %cl, %eax
+; CHECK-NEXT: movzbl b(%rip), %ecx
+; CHECK-NEXT: xorl %eax, %ecx
+; CHECK-NEXT: xorl $255, %ecx
+; CHECK-NEXT: movl %ecx, a(%rip)
; CHECK-NEXT: retq
%t0 = load i32, ptr @c, align 4
%rem = srem i32 -1, %t0
diff --git a/llvm/test/CodeGen/X86/buildvec-insertvec.ll b/llvm/test/CodeGen/X86/buildvec-insertvec.ll
index 4b0e5441b4abf..8024cbcf7c4b2 100644
--- a/llvm/test/CodeGen/X86/buildvec-insertvec.ll
+++ b/llvm/test/CodeGen/X86/buildvec-insertvec.ll
@@ -790,29 +790,43 @@ define i32 @PR46586(ptr %p, <4 x i32> %v) {
; SSE2-NEXT: pinsrw $6, %eax, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE2-NEXT: movd %xmm1, %eax
+; SSE2-NEXT: xorps %xmm1, %xmm1
+; SSE2-NEXT: cvtsi2sd %eax, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: movd %xmm0, %ecx
-; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divl %ecx
-; SSE2-NEXT: movl %edx, %eax
+; SSE2-NEXT: xorps %xmm0, %xmm0
+; SSE2-NEXT: cvtsi2sd %rcx, %xmm0
+; SSE2-NEXT: divsd %xmm0, %xmm1
+; SSE2-NEXT: cvttsd2si %xmm1, %rdx
+; SSE2-NEXT: imull %ecx, %edx
+; SSE2-NEXT: subl %edx, %eax
; SSE2-NEXT: retq
;
; SSE41-LABEL: PR46586:
; SSE41: # %bb.0:
-; SSE41-NEXT: movzbl 3(%rdi), %eax
+; SSE41-NEXT: movl (%rdi), %eax
; SSE41-NEXT: extractps $3, %xmm0, %ecx
-; SSE41-NEXT: xorl %edx, %edx
-; SSE41-NEXT: divl %ecx
-; SSE41-NEXT: movl %edx, %eax
+; SSE41-NEXT: xorps %xmm0, %xmm0
+; SSE41-NEXT: cvtsi2sd %rcx, %xmm0
+; SSE41-NEXT: shrl $24, %eax
+; SSE41-NEXT: cvtsi2sd %eax, %xmm1
+; SSE41-NEXT: divsd %xmm0, %xmm1
+; SSE41-NEXT: cvttsd2si %xmm1, %rdx
+; SSE41-NEXT: imull %ecx, %edx
+; SSE41-NEXT: subl %edx, %eax
; SSE41-NEXT: retq
;
; AVX-LABEL: PR46586:
; AVX: # %bb.0:
-; AVX-NEXT: movzbl 3(%rdi), %eax
+; AVX-NEXT: movl (%rdi), %eax
; AVX-NEXT: vextractps $3, %xmm0, %ecx
-; AVX-NEXT: xorl %edx, %edx
-; AVX-NEXT: divl %ecx
-; AVX-NEXT: movl %edx, %eax
+; AVX-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm0
+; AVX-NEXT: shrl $24, %eax
+; AVX-NEXT: vcvtsi2sd %eax, %xmm15, %xmm1
+; AVX-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; AVX-NEXT: vcvttsd2si %xmm0, %rdx
+; AVX-NEXT: imull %ecx, %edx
+; AVX-NEXT: subl %edx, %eax
; AVX-NEXT: retq
%p3 = getelementptr inbounds i8, ptr %p, i64 3
%t25 = load i8, ptr %p
diff --git a/llvm/test/CodeGen/X86/bypass-slow-division-64.ll b/llvm/test/CodeGen/X86/bypass-slow-division-64.ll
index fa7a216746b32..a100291f5eb70 100644
--- a/llvm/test/CodeGen/X86/bypass-slow-division-64.ll
+++ b/llvm/test/CodeGen/X86/bypass-slow-division-64.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; Check that 64-bit division is bypassed correctly.
; RUN: llc < %s -mtriple=x86_64-- -mattr=-idivq-to-divl | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ
; RUN: llc < %s -mtriple=x86_64-- -mattr=+idivq-to-divl | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
@@ -44,24 +45,6 @@ define i64 @sdiv_quotient(i64 %a, i64 %b) nounwind {
; FAST-DIVQ-NEXT: cqto
; FAST-DIVQ-NEXT: idivq %rsi
; FAST-DIVQ-NEXT: retq
-;
-; SLOW-DIVQ-LABEL: sdiv_quotient:
-; SLOW-DIVQ: # %bb.0:
-; SLOW-DIVQ-DAG: movq %rdi, %rax
-; SLOW-DIVQ-DAG: movq %rdi, %rcx
-; SLOW-DIVQ-DAG: orq %rsi, %rcx
-; SLOW-DIVQ-DAG: shrq $32, %rcx
-; SLOW-DIVQ-NEXT: je .LBB0_1
-; SLOW-DIVQ-NEXT: # %bb.2:
-; SLOW-DIVQ-NEXT: cqto
-; SLOW-DIVQ-NEXT: idivq %rsi
-; SLOW-DIVQ-NEXT: retq
-; SLOW-DIVQ-NEXT: .LBB0_1:
-; SLOW-DIVQ-DAG: # kill: def $eax killed $eax killed $rax
-; SLOW-DIVQ-DAG: xorl %edx, %edx
-; SLOW-DIVQ-NEXT: divl %esi
-; SLOW-DIVQ-NEXT: # kill: def $eax killed $eax def $rax
-; SLOW-DIVQ-NEXT: retq
%result = sdiv i64 %a, %b
ret i64 %result
}
@@ -96,25 +79,6 @@ define i64 @sdiv_remainder(i64 %a, i64 %b) nounwind {
; FAST-DIVQ-NEXT: idivq %rsi
; FAST-DIVQ-NEXT: movq %rdx, %rax
; FAST-DIVQ-NEXT: retq
-;
-; SLOW-DIVQ-LABEL: sdiv_remainder:
-; SLOW-DIVQ: # %bb.0:
-; SLOW-DIVQ-DAG: movq %rdi, %rax
-; SLOW-DIVQ-DAG: movq %rdi, %rcx
-; SLOW-DIVQ-DAG: orq %rsi, %rcx
-; SLOW-DIVQ-DAG: shrq $32, %rcx
-; SLOW-DIVQ-NEXT: je .LBB3_1
-; SLOW-DIVQ-NEXT: # %bb.2:
-; SLOW-DIVQ-NEXT: cqto
-; SLOW-DIVQ-NEXT: idivq %rsi
-; SLOW-DIVQ-NEXT: movq %rdx, %rax
-; SLOW-DIVQ-NEXT: retq
-; SLOW-DIVQ-NEXT: .LBB3_1:
-; SLOW-DIVQ-DAG: # kill: def $eax killed $eax killed $rax
-; SLOW-DIVQ-DAG: xorl %edx, %edx
-; SLOW-DIVQ-NEXT: divl %esi
-; SLOW-DIVQ-NEXT: movl %edx, %eax
-; SLOW-DIVQ-NEXT: retq
%result = srem i64 %a, %b
ret i64 %result
}
@@ -151,27 +115,6 @@ define i64 @sdiv_quotient_and_remainder(i64 %a, i64 %b) nounwind {
; FAST-DIVQ-NEXT: idivq %rsi
; FAST-DIVQ-NEXT: addq %rdx, %rax
; FAST-DIVQ-NEXT: retq
-;
-; SLOW-DIVQ-LABEL: sdiv_quotient_and_remainder:
-; SLOW-DIVQ: # %bb.0:
-; SLOW-DIVQ-DAG: movq %rdi, %rax
-; SLOW-DIVQ-DAG: movq %rdi, %rcx
-; SLOW-DIVQ-DAG: orq %rsi, %rcx
-; SLOW-DIVQ-DAG: shrq $32, %rcx
-; SLOW-DIVQ-NEXT: je .LBB6_1
-; SLOW-DIVQ-NEXT: # %bb.2:
-; SLOW-DIVQ-NEXT: cqto
-; SLOW-DIVQ-NEXT: idivq %rsi
-; SLOW-DIVQ-NEXT: addq %rdx, %rax
-; SLOW-DIVQ-NEXT: retq
-; SLOW-DIVQ-NEXT: .LBB6_1:
-; SLOW-DIVQ-DAG: # kill: def $eax killed $eax killed $rax
-; SLOW-DIVQ-DAG: xorl %edx, %edx
-; SLOW-DIVQ-NEXT: divl %esi
-; SLOW-DIVQ-NEXT: # kill: def $edx killed $edx def $rdx
-; SLOW-DIVQ-NEXT: # kill: def $eax killed $eax def $rax
-; SLOW-DIVQ-NEXT: addq %rdx, %rax
-; SLOW-DIVQ-NEXT: retq
%resultdiv = sdiv i64 %a, %b
%resultrem = srem i64 %a, %b
%result = add i64 %resultdiv, %resultrem
@@ -217,24 +160,6 @@ define i64 @udiv_quotient(i64 %a, i64 %b) nounwind {
; FAST-DIVQ-NEXT: xorl %edx, %edx
; FAST-DIVQ-NEXT: divq %rsi
; FAST-DIVQ-NEXT: retq
-;
-; SLOW-DIVQ-LABEL: udiv_quotient:
-; SLOW-DIVQ: # %bb.0:
-; SLOW-DIVQ-DAG: movq %rdi, %rax
-; SLOW-DIVQ-DAG: movq %rdi, %rcx
-; SLOW-DIVQ-DAG: orq %rsi, %rcx
-; SLOW-DIVQ-DAG: shrq $32, %rcx
-; SLOW-DIVQ-NEXT: je .LBB9_1
-; SLOW-DIVQ-NEXT: # %bb.2:
-; SLOW-DIVQ-NEXT: xorl %edx, %edx
-; SLOW-DIVQ-NEXT: divq %rsi
-; SLOW-DIVQ-NEXT: retq
-; SLOW-DIVQ-NEXT: .LBB9_1:
-; SLOW-DIVQ-DAG: # kill: def $eax killed $eax killed $rax
-; SLOW-DIVQ-DAG: xorl %edx, %edx
-; SLOW-DIVQ-NEXT: divl %esi
-; SLOW-DIVQ-NEXT: # kill: def $eax killed $eax def $rax
-; SLOW-DIVQ-NEXT: retq
%result = udiv i64 %a, %b
ret i64 %result
}
@@ -269,25 +194,6 @@ define i64 @udiv_remainder(i64 %a, i64 %b) nounwind {
; FAST-DIVQ-NEXT: divq %rsi
; FAST-DIVQ-NEXT: movq %rdx, %rax
; FAST-DIVQ-NEXT: retq
-;
-; SLOW-DIVQ-LABEL: udiv_remainder:
-; SLOW-DIVQ: # %bb.0:
-; SLOW-DIVQ-DAG: movq %rdi, %rax
-; SLOW-DIVQ-DAG: movq %rdi, %rcx
-; SLOW-DIVQ-DAG: orq %rsi, %rcx
-; SLOW-DIVQ-DAG: shrq $32, %rcx
-; SLOW-DIVQ-NEXT: je .LBB12_1
-; SLOW-DIVQ-NEXT: # %bb.2:
-; SLOW-DIVQ-NEXT: xorl %edx, %edx
-; SLOW-DIVQ-NEXT: divq %rsi
-; SLOW-DIVQ-NEXT: movq %rdx, %rax
-; SLOW-DIVQ-NEXT: retq
-; SLOW-DIVQ-NEXT: .LBB12_1:
-; SLOW-DIVQ-DAG: # kill: def $eax killed $eax killed $rax
-; SLOW-DIVQ-DAG: xorl %edx, %edx
-; SLOW-DIVQ-NEXT: divl %esi
-; SLOW-DIVQ-NEXT: movl %edx, %eax
-; SLOW-DIVQ-NEXT: retq
%result = urem i64 %a, %b
ret i64 %result
}
@@ -324,27 +230,6 @@ define i64 @udiv_quotient_and_remainder(i64 %a, i64 %b) nounwind {
; FAST-DIVQ-NEXT: divq %rsi
; FAST-DIVQ-NEXT: addq %rdx, %rax
; FAST-DIVQ-NEXT: retq
-;
-; SLOW-DIVQ-LABEL: udiv_quotient_and_remainder:
-; SLOW-DIVQ: # %bb.0:
-; SLOW-DIVQ-DAG: movq %rdi, %rax
-; SLOW-DIVQ-DAG: movq %rdi, %rcx
-; SLOW-DIVQ-DAG: orq %rsi, %rcx
-; SLOW-DIVQ-DAG: shrq $32, %rcx
-; SLOW-DIVQ-NEXT: je .LBB15_1
-; SLOW-DIVQ-NEXT: # %bb.2:
-; SLOW-DIVQ-NEXT: xorl %edx, %edx
-; SLOW-DIVQ-NEXT: divq %rsi
-; SLOW-DIVQ-NEXT: addq %rdx, %rax
-; SLOW-DIVQ-NEXT: retq
-; SLOW-DIVQ-NEXT: .LBB15_1:
-; SLOW-DIVQ-DAG: # kill: def $eax killed $eax killed $rax
-; SLOW-DIVQ-DAG: xorl %edx, %edx
-; SLOW-DIVQ-NEXT: divl %esi
-; SLOW-DIVQ-NEXT: # kill: def $edx killed $edx def $rdx
-; SLOW-DIVQ-NEXT: # kill: def $eax killed $eax def $rax
-; SLOW-DIVQ-NEXT: addq %rdx, %rax
-; SLOW-DIVQ-NEXT: retq
%resultdiv = udiv i64 %a, %b
%resultrem = urem i64 %a, %b
%result = add i64 %resultdiv, %resultrem
@@ -388,3 +273,5 @@ define void @PR43514(i32 %x, i32 %y) {
%s = srem i64 %z1, %z2
ret void
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; SLOW-DIVQ: {{.*}}
diff --git a/llvm/test/CodeGen/X86/bypass-slow-division-tune.ll b/llvm/test/CodeGen/X86/bypass-slow-division-tune.ll
index afecf00113a0a..4b4674dc177fd 100644
--- a/llvm/test/CodeGen/X86/bypass-slow-division-tune.ll
+++ b/llvm/test/CodeGen/X86/bypass-slow-division-tune.ll
@@ -17,28 +17,51 @@ define i32 @div32(i32 %a, i32 %b) {
; ATOM-NEXT: testl $-256, %eax
; ATOM-NEXT: je .LBB0_1
; ATOM-NEXT: # %bb.2:
-; ATOM-NEXT: movl %edi, %eax
-; ATOM-NEXT: cltd
-; ATOM-NEXT: idivl %esi
+; ATOM-NEXT: cvtsi2sd %esi, %xmm0
+; ATOM-NEXT: cvtsi2sd %edi, %xmm1
+; ATOM-NEXT: divsd %xmm0, %xmm1
+; ATOM-NEXT: cvttsd2si %xmm1, %eax
; ATOM-NEXT: retq
; ATOM-NEXT: .LBB0_1:
+; ATOM-NEXT: movzbl %sil, %eax
+; ATOM-NEXT: cvtsi2ss %eax, %xmm0
; ATOM-NEXT: movzbl %dil, %eax
-; ATOM-NEXT: divb %sil
+; ATOM-NEXT: cvtsi2ss %eax, %xmm1
+; ATOM-NEXT: divss %xmm0, %xmm1
+; ATOM-NEXT: cvttss2si %xmm1, %eax
; ATOM-NEXT: movzbl %al, %eax
; ATOM-NEXT: retq
;
-; REST-LABEL: div32:
-; REST: # %bb.0: # %entry
-; REST-NEXT: movl %edi, %eax
-; REST-NEXT: cltd
-; REST-NEXT: idivl %esi
-; REST-NEXT: retq
+; X64-LABEL: div32:
+; X64: # %bb.0: # %entry
+; X64-NEXT: cvtsi2sd %esi, %xmm0
+; X64-NEXT: cvtsi2sd %edi, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %eax
+; X64-NEXT: retq
+;
+; SLM-LABEL: div32:
+; SLM: # %bb.0: # %entry
+; SLM-NEXT: cvtsi2sd %esi, %xmm0
+; SLM-NEXT: cvtsi2sd %edi, %xmm1
+; SLM-NEXT: divsd %xmm0, %xmm1
+; SLM-NEXT: cvttsd2si %xmm1, %eax
+; SLM-NEXT: retq
+;
+; SKL-LABEL: div32:
+; SKL: # %bb.0: # %entry
+; SKL-NEXT: vcvtsi2sd %esi, %xmm15, %xmm0
+; SKL-NEXT: vcvtsi2sd %edi, %xmm15, %xmm1
+; SKL-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; SKL-NEXT: vcvttsd2si %xmm0, %eax
+; SKL-NEXT: retq
;
; HUGEWS-LABEL: div32:
; HUGEWS: # %bb.0: # %entry
-; HUGEWS-NEXT: movl %edi, %eax
-; HUGEWS-NEXT: cltd
-; HUGEWS-NEXT: idivl %esi
+; HUGEWS-NEXT: vcvtsi2sd %esi, %xmm15, %xmm0
+; HUGEWS-NEXT: vcvtsi2sd %edi, %xmm15, %xmm1
+; HUGEWS-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; HUGEWS-NEXT: vcvttsd2si %xmm0, %eax
; HUGEWS-NEXT: retq
entry:
%div = sdiv i32 %a, %b
@@ -49,74 +72,86 @@ entry:
define i64 @div64(i64 %a, i64 %b) {
; ATOM-LABEL: div64:
; ATOM: # %bb.0: # %entry
-; ATOM-NEXT: movq %rdi, %rcx
; ATOM-NEXT: movq %rdi, %rax
-; ATOM-NEXT: orq %rsi, %rcx
-; ATOM-NEXT: shrq $32, %rcx
+; ATOM-NEXT: orq %rsi, %rax
+; ATOM-NEXT: shrq $32, %rax
; ATOM-NEXT: je .LBB1_1
; ATOM-NEXT: # %bb.2:
+; ATOM-NEXT: movq %rdi, %rax
; ATOM-NEXT: cqto
; ATOM-NEXT: idivq %rsi
; ATOM-NEXT: retq
; ATOM-NEXT: .LBB1_1:
-; ATOM-NEXT: # kill: def $eax killed $eax killed $rax
-; ATOM-NEXT: xorl %edx, %edx
-; ATOM-NEXT: divl %esi
-; ATOM-NEXT: # kill: def $eax killed $eax def $rax
+; ATOM-NEXT: movl %esi, %eax
+; ATOM-NEXT: cvtsi2sd %rax, %xmm0
+; ATOM-NEXT: movl %edi, %eax
+; ATOM-NEXT: cvtsi2sd %rax, %xmm1
+; ATOM-NEXT: divsd %xmm0, %xmm1
+; ATOM-NEXT: cvttsd2si %xmm1, %rax
+; ATOM-NEXT: movl %eax, %eax
; ATOM-NEXT: retq
;
; X64-LABEL: div64:
; X64: # %bb.0: # %entry
; X64-NEXT: movq %rdi, %rax
-; X64-NEXT: movq %rdi, %rcx
-; X64-NEXT: orq %rsi, %rcx
-; X64-NEXT: shrq $32, %rcx
+; X64-NEXT: orq %rsi, %rax
+; X64-NEXT: shrq $32, %rax
; X64-NEXT: je .LBB1_1
; X64-NEXT: # %bb.2:
+; X64-NEXT: movq %rdi, %rax
; X64-NEXT: cqto
; X64-NEXT: idivq %rsi
; X64-NEXT: retq
; X64-NEXT: .LBB1_1:
-; X64-NEXT: # kill: def $eax killed $eax killed $rax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %esi
-; X64-NEXT: # kill: def $eax killed $eax def $rax
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: cvtsi2sd %rax, %xmm0
+; X64-NEXT: movl %edi, %eax
+; X64-NEXT: cvtsi2sd %rax, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %rax
+; X64-NEXT: movl %eax, %eax
; X64-NEXT: retq
;
; SLM-LABEL: div64:
; SLM: # %bb.0: # %entry
-; SLM-NEXT: movq %rdi, %rcx
; SLM-NEXT: movq %rdi, %rax
-; SLM-NEXT: orq %rsi, %rcx
-; SLM-NEXT: shrq $32, %rcx
+; SLM-NEXT: orq %rsi, %rax
+; SLM-NEXT: shrq $32, %rax
; SLM-NEXT: je .LBB1_1
; SLM-NEXT: # %bb.2:
+; SLM-NEXT: movq %rdi, %rax
; SLM-NEXT: cqto
; SLM-NEXT: idivq %rsi
; SLM-NEXT: retq
; SLM-NEXT: .LBB1_1:
-; SLM-NEXT: xorl %edx, %edx
-; SLM-NEXT: # kill: def $eax killed $eax killed $rax
-; SLM-NEXT: divl %esi
-; SLM-NEXT: # kill: def $eax killed $eax def $rax
+; SLM-NEXT: movl %esi, %eax
+; SLM-NEXT: cvtsi2sd %rax, %xmm0
+; SLM-NEXT: movl %edi, %eax
+; SLM-NEXT: cvtsi2sd %rax, %xmm1
+; SLM-NEXT: divsd %xmm0, %xmm1
+; SLM-NEXT: cvttsd2si %xmm1, %rax
+; SLM-NEXT: movl %eax, %eax
; SLM-NEXT: retq
;
; SKL-LABEL: div64:
; SKL: # %bb.0: # %entry
; SKL-NEXT: movq %rdi, %rax
-; SKL-NEXT: movq %rdi, %rcx
-; SKL-NEXT: orq %rsi, %rcx
-; SKL-NEXT: shrq $32, %rcx
+; SKL-NEXT: orq %rsi, %rax
+; SKL-NEXT: shrq $32, %rax
; SKL-NEXT: je .LBB1_1
; SKL-NEXT: # %bb.2:
+; SKL-NEXT: movq %rdi, %rax
; SKL-NEXT: cqto
; SKL-NEXT: idivq %rsi
; SKL-NEXT: retq
; SKL-NEXT: .LBB1_1:
-; SKL-NEXT: # kill: def $eax killed $eax killed $rax
-; SKL-NEXT: xorl %edx, %edx
-; SKL-NEXT: divl %esi
-; SKL-NEXT: # kill: def $eax killed $eax def $rax
+; SKL-NEXT: movl %esi, %eax
+; SKL-NEXT: vcvtsi2sd %rax, %xmm15, %xmm0
+; SKL-NEXT: movl %edi, %eax
+; SKL-NEXT: vcvtsi2sd %rax, %xmm15, %xmm1
+; SKL-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; SKL-NEXT: vcvttsd2si %xmm0, %rax
+; SKL-NEXT: movl %eax, %eax
; SKL-NEXT: retq
;
; GMT-LABEL: div64:
@@ -179,74 +214,86 @@ define i64 @div64_pgso(i64 %a, i64 %b) !prof !15 {
define i64 @div64_hugews(i64 %a, i64 %b) {
; ATOM-LABEL: div64_hugews:
; ATOM: # %bb.0:
-; ATOM-NEXT: movq %rdi, %rcx
; ATOM-NEXT: movq %rdi, %rax
-; ATOM-NEXT: orq %rsi, %rcx
-; ATOM-NEXT: shrq $32, %rcx
+; ATOM-NEXT: orq %rsi, %rax
+; ATOM-NEXT: shrq $32, %rax
; ATOM-NEXT: je .LBB4_1
; ATOM-NEXT: # %bb.2:
+; ATOM-NEXT: movq %rdi, %rax
; ATOM-NEXT: cqto
; ATOM-NEXT: idivq %rsi
; ATOM-NEXT: retq
; ATOM-NEXT: .LBB4_1:
-; ATOM-NEXT: # kill: def $eax killed $eax killed $rax
-; ATOM-NEXT: xorl %edx, %edx
-; ATOM-NEXT: divl %esi
-; ATOM-NEXT: # kill: def $eax killed $eax def $rax
+; ATOM-NEXT: movl %esi, %eax
+; ATOM-NEXT: cvtsi2sd %rax, %xmm0
+; ATOM-NEXT: movl %edi, %eax
+; ATOM-NEXT: cvtsi2sd %rax, %xmm1
+; ATOM-NEXT: divsd %xmm0, %xmm1
+; ATOM-NEXT: cvttsd2si %xmm1, %rax
+; ATOM-NEXT: movl %eax, %eax
; ATOM-NEXT: retq
;
; X64-LABEL: div64_hugews:
; X64: # %bb.0:
; X64-NEXT: movq %rdi, %rax
-; X64-NEXT: movq %rdi, %rcx
-; X64-NEXT: orq %rsi, %rcx
-; X64-NEXT: shrq $32, %rcx
+; X64-NEXT: orq %rsi, %rax
+; X64-NEXT: shrq $32, %rax
; X64-NEXT: je .LBB4_1
; X64-NEXT: # %bb.2:
+; X64-NEXT: movq %rdi, %rax
; X64-NEXT: cqto
; X64-NEXT: idivq %rsi
; X64-NEXT: retq
; X64-NEXT: .LBB4_1:
-; X64-NEXT: # kill: def $eax killed $eax killed $rax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %esi
-; X64-NEXT: # kill: def $eax killed $eax def $rax
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: cvtsi2sd %rax, %xmm0
+; X64-NEXT: movl %edi, %eax
+; X64-NEXT: cvtsi2sd %rax, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %rax
+; X64-NEXT: movl %eax, %eax
; X64-NEXT: retq
;
; SLM-LABEL: div64_hugews:
; SLM: # %bb.0:
-; SLM-NEXT: movq %rdi, %rcx
; SLM-NEXT: movq %rdi, %rax
-; SLM-NEXT: orq %rsi, %rcx
-; SLM-NEXT: shrq $32, %rcx
+; SLM-NEXT: orq %rsi, %rax
+; SLM-NEXT: shrq $32, %rax
; SLM-NEXT: je .LBB4_1
; SLM-NEXT: # %bb.2:
+; SLM-NEXT: movq %rdi, %rax
; SLM-NEXT: cqto
; SLM-NEXT: idivq %rsi
; SLM-NEXT: retq
; SLM-NEXT: .LBB4_1:
-; SLM-NEXT: xorl %edx, %edx
-; SLM-NEXT: # kill: def $eax killed $eax killed $rax
-; SLM-NEXT: divl %esi
-; SLM-NEXT: # kill: def $eax killed $eax def $rax
+; SLM-NEXT: movl %esi, %eax
+; SLM-NEXT: cvtsi2sd %rax, %xmm0
+; SLM-NEXT: movl %edi, %eax
+; SLM-NEXT: cvtsi2sd %rax, %xmm1
+; SLM-NEXT: divsd %xmm0, %xmm1
+; SLM-NEXT: cvttsd2si %xmm1, %rax
+; SLM-NEXT: movl %eax, %eax
; SLM-NEXT: retq
;
; SKL-LABEL: div64_hugews:
; SKL: # %bb.0:
; SKL-NEXT: movq %rdi, %rax
-; SKL-NEXT: movq %rdi, %rcx
-; SKL-NEXT: orq %rsi, %rcx
-; SKL-NEXT: shrq $32, %rcx
+; SKL-NEXT: orq %rsi, %rax
+; SKL-NEXT: shrq $32, %rax
; SKL-NEXT: je .LBB4_1
; SKL-NEXT: # %bb.2:
+; SKL-NEXT: movq %rdi, %rax
; SKL-NEXT: cqto
; SKL-NEXT: idivq %rsi
; SKL-NEXT: retq
; SKL-NEXT: .LBB4_1:
-; SKL-NEXT: # kill: def $eax killed $eax killed $rax
-; SKL-NEXT: xorl %edx, %edx
-; SKL-NEXT: divl %esi
-; SKL-NEXT: # kill: def $eax killed $eax def $rax
+; SKL-NEXT: movl %esi, %eax
+; SKL-NEXT: vcvtsi2sd %rax, %xmm15, %xmm0
+; SKL-NEXT: movl %edi, %eax
+; SKL-NEXT: vcvtsi2sd %rax, %xmm15, %xmm1
+; SKL-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; SKL-NEXT: vcvttsd2si %xmm0, %rax
+; SKL-NEXT: movl %eax, %eax
; SKL-NEXT: retq
;
; GMT-LABEL: div64_hugews:
@@ -267,54 +314,132 @@ define i64 @div64_hugews(i64 %a, i64 %b) {
}
define i32 @div32_optsize(i32 %a, i32 %b) optsize {
-; CHECK-LABEL: div32_optsize:
-; CHECK: # %bb.0:
-; CHECK-NEXT: movl %edi, %eax
-; CHECK-NEXT: cltd
-; CHECK-NEXT: idivl %esi
-; CHECK-NEXT: retq
+; ATOM-LABEL: div32_optsize:
+; ATOM: # %bb.0:
+; ATOM-NEXT: cvtsi2sd %esi, %xmm0
+; ATOM-NEXT: cvtsi2sd %edi, %xmm1
+; ATOM-NEXT: divsd %xmm0, %xmm1
+; ATOM-NEXT: cvttsd2si %xmm1, %eax
+; ATOM-NEXT: retq
+;
+; X64-LABEL: div32_optsize:
+; X64: # %bb.0:
+; X64-NEXT: cvtsi2sd %esi, %xmm0
+; X64-NEXT: cvtsi2sd %edi, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %eax
+; X64-NEXT: retq
+;
+; SLM-LABEL: div32_optsize:
+; SLM: # %bb.0:
+; SLM-NEXT: cvtsi2sd %esi, %xmm0
+; SLM-NEXT: cvtsi2sd %edi, %xmm1
+; SLM-NEXT: divsd %xmm0, %xmm1
+; SLM-NEXT: cvttsd2si %xmm1, %eax
+; SLM-NEXT: retq
+;
+; SKL-LABEL: div32_optsize:
+; SKL: # %bb.0:
+; SKL-NEXT: vcvtsi2sd %esi, %xmm15, %xmm0
+; SKL-NEXT: vcvtsi2sd %edi, %xmm15, %xmm1
+; SKL-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; SKL-NEXT: vcvttsd2si %xmm0, %eax
+; SKL-NEXT: retq
;
; HUGEWS-LABEL: div32_optsize:
; HUGEWS: # %bb.0:
-; HUGEWS-NEXT: movl %edi, %eax
-; HUGEWS-NEXT: cltd
-; HUGEWS-NEXT: idivl %esi
+; HUGEWS-NEXT: vcvtsi2sd %esi, %xmm15, %xmm0
+; HUGEWS-NEXT: vcvtsi2sd %edi, %xmm15, %xmm1
+; HUGEWS-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; HUGEWS-NEXT: vcvttsd2si %xmm0, %eax
; HUGEWS-NEXT: retq
%div = sdiv i32 %a, %b
ret i32 %div
}
define i32 @div32_pgso(i32 %a, i32 %b) !prof !15 {
-; CHECK-LABEL: div32_pgso:
-; CHECK: # %bb.0:
-; CHECK-NEXT: movl %edi, %eax
-; CHECK-NEXT: cltd
-; CHECK-NEXT: idivl %esi
-; CHECK-NEXT: retq
+; ATOM-LABEL: div32_pgso:
+; ATOM: # %bb.0:
+; ATOM-NEXT: cvtsi2sd %esi, %xmm0
+; ATOM-NEXT: cvtsi2sd %edi, %xmm1
+; ATOM-NEXT: divsd %xmm0, %xmm1
+; ATOM-NEXT: cvttsd2si %xmm1, %eax
+; ATOM-NEXT: retq
+;
+; X64-LABEL: div32_pgso:
+; X64: # %bb.0:
+; X64-NEXT: cvtsi2sd %esi, %xmm0
+; X64-NEXT: cvtsi2sd %edi, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %eax
+; X64-NEXT: retq
+;
+; SLM-LABEL: div32_pgso:
+; SLM: # %bb.0:
+; SLM-NEXT: cvtsi2sd %esi, %xmm0
+; SLM-NEXT: cvtsi2sd %edi, %xmm1
+; SLM-NEXT: divsd %xmm0, %xmm1
+; SLM-NEXT: cvttsd2si %xmm1, %eax
+; SLM-NEXT: retq
+;
+; SKL-LABEL: div32_pgso:
+; SKL: # %bb.0:
+; SKL-NEXT: vcvtsi2sd %esi, %xmm15, %xmm0
+; SKL-NEXT: vcvtsi2sd %edi, %xmm15, %xmm1
+; SKL-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; SKL-NEXT: vcvttsd2si %xmm0, %eax
+; SKL-NEXT: retq
;
; HUGEWS-LABEL: div32_pgso:
; HUGEWS: # %bb.0:
-; HUGEWS-NEXT: movl %edi, %eax
-; HUGEWS-NEXT: cltd
-; HUGEWS-NEXT: idivl %esi
+; HUGEWS-NEXT: vcvtsi2sd %esi, %xmm15, %xmm0
+; HUGEWS-NEXT: vcvtsi2sd %edi, %xmm15, %xmm1
+; HUGEWS-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; HUGEWS-NEXT: vcvttsd2si %xmm0, %eax
; HUGEWS-NEXT: retq
%div = sdiv i32 %a, %b
ret i32 %div
}
define i32 @div32_minsize(i32 %a, i32 %b) minsize {
-; CHECK-LABEL: div32_minsize:
-; CHECK: # %bb.0:
-; CHECK-NEXT: movl %edi, %eax
-; CHECK-NEXT: cltd
-; CHECK-NEXT: idivl %esi
-; CHECK-NEXT: retq
+; ATOM-LABEL: div32_minsize:
+; ATOM: # %bb.0:
+; ATOM-NEXT: cvtsi2sd %esi, %xmm0
+; ATOM-NEXT: cvtsi2sd %edi, %xmm1
+; ATOM-NEXT: divsd %xmm0, %xmm1
+; ATOM-NEXT: cvttsd2si %xmm1, %eax
+; ATOM-NEXT: retq
+;
+; X64-LABEL: div32_minsize:
+; X64: # %bb.0:
+; X64-NEXT: cvtsi2sd %esi, %xmm0
+; X64-NEXT: cvtsi2sd %edi, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %eax
+; X64-NEXT: retq
+;
+; SLM-LABEL: div32_minsize:
+; SLM: # %bb.0:
+; SLM-NEXT: cvtsi2sd %esi, %xmm0
+; SLM-NEXT: cvtsi2sd %edi, %xmm1
+; SLM-NEXT: divsd %xmm0, %xmm1
+; SLM-NEXT: cvttsd2si %xmm1, %eax
+; SLM-NEXT: retq
+;
+; SKL-LABEL: div32_minsize:
+; SKL: # %bb.0:
+; SKL-NEXT: vcvtsi2sd %esi, %xmm15, %xmm0
+; SKL-NEXT: vcvtsi2sd %edi, %xmm15, %xmm1
+; SKL-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; SKL-NEXT: vcvttsd2si %xmm0, %eax
+; SKL-NEXT: retq
;
; HUGEWS-LABEL: div32_minsize:
; HUGEWS: # %bb.0:
-; HUGEWS-NEXT: movl %edi, %eax
-; HUGEWS-NEXT: cltd
-; HUGEWS-NEXT: idivl %esi
+; HUGEWS-NEXT: vcvtsi2sd %esi, %xmm15, %xmm0
+; HUGEWS-NEXT: vcvtsi2sd %edi, %xmm15, %xmm1
+; HUGEWS-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; HUGEWS-NEXT: vcvttsd2si %xmm0, %eax
; HUGEWS-NEXT: retq
%div = sdiv i32 %a, %b
ret i32 %div
@@ -336,3 +461,5 @@ define i32 @div32_minsize(i32 %a, i32 %b) minsize {
!13 = !{i32 999000, i64 1000, i32 3}
!14 = !{i32 999999, i64 5, i32 3}
!15 = !{!"function_entry_count", i64 0}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; REST: {{.*}}
diff --git a/llvm/test/CodeGen/X86/combine-srem.ll b/llvm/test/CodeGen/X86/combine-srem.ll
index 82ac096353f06..3a1184aa551bf 100644
--- a/llvm/test/CodeGen/X86/combine-srem.ll
+++ b/llvm/test/CodeGen/X86/combine-srem.ll
@@ -390,30 +390,67 @@ declare <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32>, i32)
; OSS-Fuzz #6883
; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=6883
define i32 @ossfuzz6883() {
-; CHECK-LABEL: ossfuzz6883:
-; CHECK: # %bb.0:
-; CHECK-NEXT: movl (%rax), %ecx
-; CHECK-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: idivl %ecx
-; CHECK-NEXT: movl %eax, %esi
-; CHECK-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ecx
-; CHECK-NEXT: movl %eax, %edi
-; CHECK-NEXT: movl %esi, %eax
-; CHECK-NEXT: cltd
-; CHECK-NEXT: idivl %edi
-; CHECK-NEXT: movl %edx, %esi
-; CHECK-NEXT: movl %ecx, %eax
-; CHECK-NEXT: cltd
-; CHECK-NEXT: idivl %esi
-; CHECK-NEXT: movl %edx, %edi
-; CHECK-NEXT: movl %ecx, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %esi
-; CHECK-NEXT: andl %edi, %eax
-; CHECK-NEXT: retq
+; SSE-LABEL: ossfuzz6883:
+; SSE: # %bb.0:
+; SSE-NEXT: movl (%rax), %ecx
+; SSE-NEXT: cvtsi2sd %ecx, %xmm0
+; SSE-NEXT: movsd {{.*#+}} xmm1 = [2.147483647E+9,0.0E+0]
+; SSE-NEXT: movapd %xmm1, %xmm2
+; SSE-NEXT: divsd %xmm0, %xmm2
+; SSE-NEXT: cvttsd2si %xmm2, %eax
+; SSE-NEXT: cvtsi2sd %rcx, %xmm3
+; SSE-NEXT: divsd %xmm3, %xmm1
+; SSE-NEXT: cvttsd2si %xmm1, %rdx
+; SSE-NEXT: xorps %xmm1, %xmm1
+; SSE-NEXT: cvtsi2sd %edx, %xmm1
+; SSE-NEXT: cvttpd2dq %xmm2, %xmm2
+; SSE-NEXT: cvtdq2pd %xmm2, %xmm2
+; SSE-NEXT: divsd %xmm1, %xmm2
+; SSE-NEXT: cvttsd2si %xmm2, %esi
+; SSE-NEXT: imull %edx, %esi
+; SSE-NEXT: subl %esi, %eax
+; SSE-NEXT: xorps %xmm1, %xmm1
+; SSE-NEXT: cvtsi2sd %eax, %xmm1
+; SSE-NEXT: divsd %xmm1, %xmm0
+; SSE-NEXT: cvttsd2si %xmm0, %edx
+; SSE-NEXT: imull %eax, %edx
+; SSE-NEXT: subl %edx, %ecx
+; SSE-NEXT: xorps %xmm0, %xmm0
+; SSE-NEXT: cvtsi2sd %rax, %xmm0
+; SSE-NEXT: divsd %xmm0, %xmm3
+; SSE-NEXT: cvttsd2si %xmm3, %rax
+; SSE-NEXT: andl %ecx, %eax
+; SSE-NEXT: # kill: def $eax killed $eax killed $rax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: ossfuzz6883:
+; AVX: # %bb.0:
+; AVX-NEXT: movl (%rax), %ecx
+; AVX-NEXT: vcvtsi2sd %ecx, %xmm15, %xmm0
+; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [2.147483647E+9,0.0E+0]
+; AVX-NEXT: vdivsd %xmm0, %xmm1, %xmm2
+; AVX-NEXT: vcvttsd2si %xmm2, %eax
+; AVX-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm3
+; AVX-NEXT: vdivsd %xmm3, %xmm1, %xmm1
+; AVX-NEXT: vcvttsd2si %xmm1, %rdx
+; AVX-NEXT: vcvtsi2sd %edx, %xmm15, %xmm1
+; AVX-NEXT: vcvttpd2dq %xmm2, %xmm2
+; AVX-NEXT: vcvtdq2pd %xmm2, %xmm2
+; AVX-NEXT: vdivsd %xmm1, %xmm2, %xmm1
+; AVX-NEXT: vcvttsd2si %xmm1, %esi
+; AVX-NEXT: imull %edx, %esi
+; AVX-NEXT: subl %esi, %eax
+; AVX-NEXT: vcvtsi2sd %eax, %xmm15, %xmm1
+; AVX-NEXT: vdivsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vcvttsd2si %xmm0, %edx
+; AVX-NEXT: imull %eax, %edx
+; AVX-NEXT: subl %edx, %ecx
+; AVX-NEXT: vcvtsi2sd %rax, %xmm15, %xmm0
+; AVX-NEXT: vdivsd %xmm0, %xmm3, %xmm0
+; AVX-NEXT: vcvttsd2si %xmm0, %rax
+; AVX-NEXT: andl %ecx, %eax
+; AVX-NEXT: # kill: def $eax killed $eax killed $rax
+; AVX-NEXT: retq
%B17 = or i32 0, 2147483647
%L6 = load i32, ptr undef
%B11 = sdiv i32 %B17, %L6
diff --git a/llvm/test/CodeGen/X86/copy-eflags.ll b/llvm/test/CodeGen/X86/copy-eflags.ll
index e1711ccdbe13f..94a5f49597a1b 100644
--- a/llvm/test/CodeGen/X86/copy-eflags.ll
+++ b/llvm/test/CodeGen/X86/copy-eflags.ll
@@ -247,25 +247,20 @@ define dso_local void @PR37100(i8 %arg1, i16 %arg2, i64 %arg3, i8 %arg4, ptr %pt
;
; X64-LABEL: PR37100:
; X64: # %bb.0: # %bb
-; X64-NEXT: movq %rdx, %r10
-; X64-NEXT: movl {{[0-9]+}}(%rsp), %esi
-; X64-NEXT: movzbl %cl, %ecx
+; X64-NEXT: movzbl %cl, %eax
; X64-NEXT: .p2align 4
; X64-NEXT: .LBB3_1: # %bb1
; X64-NEXT: # =>This Inner Loop Header: Depth=1
-; X64-NEXT: movsbq %dil, %rax
-; X64-NEXT: xorl %r11d, %r11d
-; X64-NEXT: cmpq %rax, %r10
-; X64-NEXT: setl %r11b
-; X64-NEXT: negl %r11d
-; X64-NEXT: cmpq %rax, %r10
-; X64-NEXT: movzbl %al, %edi
-; X64-NEXT: cmovgel %ecx, %edi
+; X64-NEXT: movsbq %dil, %rcx
+; X64-NEXT: xorl %esi, %esi
+; X64-NEXT: cmpq %rcx, %rdx
+; X64-NEXT: setl %sil
+; X64-NEXT: negl %esi
+; X64-NEXT: cmpq %rcx, %rdx
+; X64-NEXT: movzbl %cl, %edi
+; X64-NEXT: cmovgel %eax, %edi
; X64-NEXT: movb %dil, (%r8)
-; X64-NEXT: cmovgel (%r9), %r11d
-; X64-NEXT: movl %esi, %eax
-; X64-NEXT: cltd
-; X64-NEXT: idivl %r11d
+; X64-NEXT: cmovgel (%r9), %esi
; X64-NEXT: jmp .LBB3_1
bb:
br label %bb1
@@ -321,16 +316,18 @@ define dso_local void @PR37431(ptr %arg1, ptr %arg2, ptr %arg3, i32 %arg4, i64 %
;
; X64-LABEL: PR37431:
; X64: # %bb.0: # %entry
-; X64-NEXT: movl %ecx, %eax
-; X64-NEXT: movq %rdx, %rcx
-; X64-NEXT: movslq (%rdi), %rdx
+; X64-NEXT: movslq (%rdi), %rax
; X64-NEXT: xorl %edi, %edi
-; X64-NEXT: cmpq %rdx, %r8
+; X64-NEXT: cmpq %rax, %r8
; X64-NEXT: sbbl %edi, %edi
; X64-NEXT: movb %dil, (%rsi)
-; X64-NEXT: cltd
-; X64-NEXT: idivl %edi
-; X64-NEXT: movb %dl, (%rcx)
+; X64-NEXT: cvtsi2sd %edi, %xmm0
+; X64-NEXT: cvtsi2sd %ecx, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %eax
+; X64-NEXT: imull %edi, %eax
+; X64-NEXT: subl %eax, %ecx
+; X64-NEXT: movb %cl, (%rdx)
; X64-NEXT: retq
entry:
%tmp = load i32, ptr %arg1
diff --git a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
index 5cfdbb7af38ad..b0f95688da646 100644
--- a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
+++ b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
@@ -11,20 +11,34 @@
define i8 @scalar_i8(i8 %x, i8 %y, ptr %divdst) nounwind {
; X86-LABEL: scalar_i8:
; X86: # %bb.0:
-; X86-NEXT: movsbl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: idivb {{[0-9]+}}(%esp)
-; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT: movsbl %ah, %ecx
-; X86-NEXT: movb %al, (%edx)
+; X86-NEXT: pushl %esi
+; X86-NEXT: movsbl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movsbl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: cvtsi2ss %edx, %xmm0
+; X86-NEXT: cvtsi2ss %ecx, %xmm1
+; X86-NEXT: divss %xmm0, %xmm1
+; X86-NEXT: cvttss2si %xmm1, %eax
+; X86-NEXT: movb %al, (%esi)
+; X86-NEXT: # kill: def $al killed $al killed $eax
+; X86-NEXT: mulb %dl
+; X86-NEXT: subb %al, %cl
; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: popl %esi
; X86-NEXT: retl
;
; X64-LABEL: scalar_i8:
; X64: # %bb.0:
-; X64-NEXT: movsbl %dil, %eax
-; X64-NEXT: idivb %sil
-; X64-NEXT: movsbl %ah, %ecx
+; X64-NEXT: movsbl %sil, %esi
+; X64-NEXT: cvtsi2ss %esi, %xmm0
+; X64-NEXT: movsbl %dil, %ecx
+; X64-NEXT: cvtsi2ss %ecx, %xmm1
+; X64-NEXT: divss %xmm0, %xmm1
+; X64-NEXT: cvttss2si %xmm1, %eax
; X64-NEXT: movb %al, (%rdx)
+; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: mulb %sil
+; X64-NEXT: subb %al, %cl
; X64-NEXT: movl %ecx, %eax
; X64-NEXT: retq
%div = sdiv i8 %x, %y
@@ -37,23 +51,34 @@ define i8 @scalar_i8(i8 %x, i8 %y, ptr %divdst) nounwind {
define i16 @scalar_i16(i16 %x, i16 %y, ptr %divdst) nounwind {
; X86-LABEL: scalar_i16:
; X86: # %bb.0:
-; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: cwtd
-; X86-NEXT: idivw {{[0-9]+}}(%esp)
+; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movw %ax, (%ecx)
-; X86-NEXT: movl %edx, %eax
+; X86-NEXT: movswl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movswl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: cvtsi2ss %edx, %xmm0
+; X86-NEXT: cvtsi2ss %eax, %xmm1
+; X86-NEXT: divss %xmm0, %xmm1
+; X86-NEXT: cvttss2si %xmm1, %esi
+; X86-NEXT: movw %si, (%ecx)
+; X86-NEXT: imull %edx, %esi
+; X86-NEXT: subl %esi, %eax
+; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: popl %esi
; X86-NEXT: retl
;
; X64-LABEL: scalar_i16:
; X64: # %bb.0:
-; X64-NEXT: movq %rdx, %rcx
; X64-NEXT: movl %edi, %eax
+; X64-NEXT: movswl %si, %ecx
+; X64-NEXT: cvtsi2ss %ecx, %xmm0
+; X64-NEXT: movswl %ax, %ecx
+; X64-NEXT: cvtsi2ss %ecx, %xmm1
+; X64-NEXT: divss %xmm0, %xmm1
+; X64-NEXT: cvttss2si %xmm1, %ecx
+; X64-NEXT: movw %cx, (%rdx)
+; X64-NEXT: imull %esi, %ecx
+; X64-NEXT: subl %ecx, %eax
; X64-NEXT: # kill: def $ax killed $ax killed $eax
-; X64-NEXT: cwtd
-; X64-NEXT: idivw %si
-; X64-NEXT: movw %ax, (%rcx)
-; X64-NEXT: movl %edx, %eax
; X64-NEXT: retq
%div = sdiv i16 %x, %y
store i16 %div, ptr %divdst, align 4
@@ -65,22 +90,30 @@ define i16 @scalar_i16(i16 %x, i16 %y, ptr %divdst) nounwind {
define i32 @scalar_i32(i32 %x, i32 %y, ptr %divdst) nounwind {
; X86-LABEL: scalar_i32:
; X86: # %bb.0:
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: cltd
-; X86-NEXT: idivl {{[0-9]+}}(%esp)
+; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl %eax, (%ecx)
-; X86-NEXT: movl %edx, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: cvtsi2sd %edx, %xmm0
+; X86-NEXT: cvtsi2sd %eax, %xmm1
+; X86-NEXT: divsd %xmm0, %xmm1
+; X86-NEXT: cvttsd2si %xmm1, %esi
+; X86-NEXT: movl %esi, (%ecx)
+; X86-NEXT: imull %edx, %esi
+; X86-NEXT: subl %esi, %eax
+; X86-NEXT: popl %esi
; X86-NEXT: retl
;
; X64-LABEL: scalar_i32:
; X64: # %bb.0:
-; X64-NEXT: movq %rdx, %rcx
; X64-NEXT: movl %edi, %eax
-; X64-NEXT: cltd
-; X64-NEXT: idivl %esi
-; X64-NEXT: movl %eax, (%rcx)
-; X64-NEXT: movl %edx, %eax
+; X64-NEXT: cvtsi2sd %esi, %xmm0
+; X64-NEXT: cvtsi2sd %edi, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %ecx
+; X64-NEXT: movl %ecx, (%rdx)
+; X64-NEXT: imull %esi, %ecx
+; X64-NEXT: subl %ecx, %eax
; X64-NEXT: retq
%div = sdiv i32 %x, %y
store i32 %div, ptr %divdst, align 4
@@ -938,23 +971,32 @@ define i32 @scalar_i32_const_pow2_divisor(i32 %0, ptr %1) minsize nounwind {
define i32 @scalar_i32_commutative(i32 %x, ptr %ysrc, ptr %divdst) nounwind {
; X86-LABEL: scalar_i32_commutative:
; X86: # %bb.0:
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: cltd
-; X86-NEXT: idivl (%ecx)
+; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl %eax, (%ecx)
-; X86-NEXT: movl %edx, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl (%edx), %edx
+; X86-NEXT: cvtsi2sd %eax, %xmm0
+; X86-NEXT: cvtsi2sd %edx, %xmm1
+; X86-NEXT: divsd %xmm1, %xmm0
+; X86-NEXT: cvttsd2si %xmm0, %esi
+; X86-NEXT: movl %esi, (%ecx)
+; X86-NEXT: imull %esi, %edx
+; X86-NEXT: subl %edx, %eax
+; X86-NEXT: popl %esi
; X86-NEXT: retl
;
; X64-LABEL: scalar_i32_commutative:
; X64: # %bb.0:
-; X64-NEXT: movq %rdx, %rcx
; X64-NEXT: movl %edi, %eax
-; X64-NEXT: cltd
-; X64-NEXT: idivl (%rsi)
-; X64-NEXT: movl %eax, (%rcx)
-; X64-NEXT: movl %edx, %eax
+; X64-NEXT: movl (%rsi), %ecx
+; X64-NEXT: cvtsi2sd %edi, %xmm0
+; X64-NEXT: cvtsi2sd %ecx, %xmm1
+; X64-NEXT: divsd %xmm1, %xmm0
+; X64-NEXT: cvttsd2si %xmm0, %esi
+; X64-NEXT: movl %esi, (%rdx)
+; X64-NEXT: imull %esi, %ecx
+; X64-NEXT: subl %ecx, %eax
; X64-NEXT: retq
%y = load i32, ptr %ysrc, align 4
%div = sdiv i32 %x, %y
@@ -970,30 +1012,33 @@ define i32 @extrause(i32 %x, i32 %y, ptr %divdst, ptr %t1dst) nounwind {
; X86: # %bb.0:
; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: cltd
-; X86-NEXT: idivl %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
-; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
-; X86-NEXT: movl %eax, (%edi)
-; X86-NEXT: imull %ecx, %eax
-; X86-NEXT: movl %eax, (%esi)
-; X86-NEXT: movl %edx, %eax
+; X86-NEXT: cvtsi2sd %esi, %xmm0
+; X86-NEXT: cvtsi2sd %eax, %xmm1
+; X86-NEXT: divsd %xmm0, %xmm1
+; X86-NEXT: cvttsd2si %xmm1, %edi
+; X86-NEXT: movl %edi, (%edx)
+; X86-NEXT: imull %esi, %edi
+; X86-NEXT: movl %edi, (%ecx)
+; X86-NEXT: subl %edi, %eax
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
; X86-NEXT: retl
;
; X64-LABEL: extrause:
; X64: # %bb.0:
-; X64-NEXT: movq %rdx, %r8
; X64-NEXT: movl %edi, %eax
-; X64-NEXT: cltd
-; X64-NEXT: idivl %esi
-; X64-NEXT: movl %eax, (%r8)
-; X64-NEXT: imull %esi, %eax
-; X64-NEXT: movl %eax, (%rcx)
-; X64-NEXT: movl %edx, %eax
+; X64-NEXT: cvtsi2sd %esi, %xmm0
+; X64-NEXT: cvtsi2sd %edi, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %edi
+; X64-NEXT: movl %edi, (%rdx)
+; X64-NEXT: imull %esi, %edi
+; X64-NEXT: movl %edi, (%rcx)
+; X64-NEXT: subl %edi, %eax
; X64-NEXT: retq
%div = sdiv i32 %x, %y
store i32 %div, ptr %divdst, align 4
@@ -1008,43 +1053,40 @@ define i32 @multiple_bb(i32 %x, i32 %y, ptr %divdst, i1 zeroext %store_srem, ptr
; X86-LABEL: multiple_bb:
; X86: # %bb.0:
; X86-NEXT: pushl %ebx
-; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi
-; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ebx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
-; X86-NEXT: movl %ecx, %eax
-; X86-NEXT: cltd
-; X86-NEXT: idivl %esi
-; X86-NEXT: movl %eax, (%edi)
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: cvtsi2sd %ecx, %xmm0
+; X86-NEXT: cvtsi2sd %edx, %xmm1
+; X86-NEXT: divsd %xmm0, %xmm1
+; X86-NEXT: cvttsd2si %xmm1, %eax
+; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: testb %bl, %bl
; X86-NEXT: je .LBB12_2
; X86-NEXT: # %bb.1: # %do_srem
-; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT: movl %eax, %edi
-; X86-NEXT: imull %esi, %edi
-; X86-NEXT: subl %edi, %ecx
-; X86-NEXT: movl %ecx, (%edx)
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: imull %eax, %ecx
+; X86-NEXT: subl %ecx, %edx
+; X86-NEXT: movl %edx, (%esi)
; X86-NEXT: .LBB12_2: # %end
; X86-NEXT: popl %esi
-; X86-NEXT: popl %edi
; X86-NEXT: popl %ebx
; X86-NEXT: retl
;
; X64-LABEL: multiple_bb:
; X64: # %bb.0:
-; X64-NEXT: movq %rdx, %r9
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: cltd
-; X64-NEXT: idivl %esi
-; X64-NEXT: movl %eax, (%r9)
+; X64-NEXT: cvtsi2sd %esi, %xmm0
+; X64-NEXT: cvtsi2sd %edi, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %eax
+; X64-NEXT: movl %eax, (%rdx)
; X64-NEXT: testl %ecx, %ecx
; X64-NEXT: je .LBB12_2
; X64-NEXT: # %bb.1: # %do_srem
-; X64-NEXT: movl %eax, %ecx
-; X64-NEXT: imull %esi, %ecx
-; X64-NEXT: subl %ecx, %edi
+; X64-NEXT: imull %eax, %esi
+; X64-NEXT: subl %esi, %edi
; X64-NEXT: movl %edi, (%r8)
; X64-NEXT: .LBB12_2: # %end
; X64-NEXT: retq
@@ -1063,32 +1105,30 @@ end:
define i32 @negative_different_x(i32 %x0, i32 %x1, i32 %y, ptr %divdst) nounwind {
; X86-LABEL: negative_different_x:
; X86: # %bb.0:
-; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
-; X86-NEXT: cltd
-; X86-NEXT: idivl %edi
-; X86-NEXT: movl %eax, (%esi)
-; X86-NEXT: imull %edi, %eax
-; X86-NEXT: subl %eax, %ecx
-; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: cvtsi2sd %edx, %xmm0
+; X86-NEXT: cvtsi2sdl {{[0-9]+}}(%esp), %xmm1
+; X86-NEXT: divsd %xmm0, %xmm1
+; X86-NEXT: cvttsd2si %xmm1, %esi
+; X86-NEXT: movl %esi, (%ecx)
+; X86-NEXT: imull %edx, %esi
+; X86-NEXT: subl %esi, %eax
; X86-NEXT: popl %esi
-; X86-NEXT: popl %edi
; X86-NEXT: retl
;
; X64-LABEL: negative_different_x:
; X64: # %bb.0:
-; X64-NEXT: movl %edx, %r8d
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: cltd
-; X64-NEXT: idivl %r8d
-; X64-NEXT: movl %eax, (%rcx)
-; X64-NEXT: imull %r8d, %eax
-; X64-NEXT: subl %eax, %esi
; X64-NEXT: movl %esi, %eax
+; X64-NEXT: cvtsi2sd %edx, %xmm0
+; X64-NEXT: cvtsi2sd %edi, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %esi
+; X64-NEXT: movl %esi, (%rcx)
+; X64-NEXT: imull %edx, %esi
+; X64-NEXT: subl %esi, %eax
; X64-NEXT: retq
%div = sdiv i32 %x0, %y ; not %x1
store i32 %div, ptr %divdst, align 4
@@ -1100,29 +1140,27 @@ define i32 @negative_different_x(i32 %x0, i32 %x1, i32 %y, ptr %divdst) nounwind
define i32 @negative_different_y(i32 %x0, i32 %x1, i32 %y, i32 %z, ptr %divdst) nounwind {
; X86-LABEL: negative_different_y:
; X86: # %bb.0:
-; X86-NEXT: pushl %esi
-; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl %ecx, %eax
-; X86-NEXT: cltd
-; X86-NEXT: idivl {{[0-9]+}}(%esp)
-; X86-NEXT: movl %eax, (%esi)
-; X86-NEXT: imull {{[0-9]+}}(%esp), %eax
-; X86-NEXT: subl %eax, %ecx
-; X86-NEXT: movl %ecx, %eax
-; X86-NEXT: popl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cvtsi2sd %eax, %xmm0
+; X86-NEXT: cvtsi2sdl {{[0-9]+}}(%esp), %xmm1
+; X86-NEXT: divsd %xmm1, %xmm0
+; X86-NEXT: cvttsd2si %xmm0, %edx
+; X86-NEXT: movl %edx, (%ecx)
+; X86-NEXT: imull {{[0-9]+}}(%esp), %edx
+; X86-NEXT: subl %edx, %eax
; X86-NEXT: retl
;
; X64-LABEL: negative_different_y:
; X64: # %bb.0:
-; X64-NEXT: movl %edx, %edi
-; X64-NEXT: movl %esi, %eax
-; X64-NEXT: cltd
-; X64-NEXT: idivl %ecx
-; X64-NEXT: movl %eax, (%r8)
-; X64-NEXT: imull %eax, %edi
-; X64-NEXT: subl %edi, %esi
; X64-NEXT: movl %esi, %eax
+; X64-NEXT: cvtsi2sd %ecx, %xmm0
+; X64-NEXT: cvtsi2sd %esi, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %ecx
+; X64-NEXT: movl %ecx, (%r8)
+; X64-NEXT: imull %ecx, %edx
+; X64-NEXT: subl %edx, %eax
; X64-NEXT: retq
%div = sdiv i32 %x1, %z ; not %x0
store i32 %div, ptr %divdst, align 4
@@ -1134,28 +1172,27 @@ define i32 @negative_different_y(i32 %x0, i32 %x1, i32 %y, i32 %z, ptr %divdst)
define i32 @negative_inverted_division(i32 %x0, i32 %x1, i32 %y, ptr %divdst) nounwind {
; X86-LABEL: negative_inverted_division:
; X86: # %bb.0:
-; X86-NEXT: pushl %esi
-; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: cltd
-; X86-NEXT: idivl %ecx
-; X86-NEXT: movl %eax, (%esi)
-; X86-NEXT: imull %ecx, %eax
-; X86-NEXT: subl %eax, %ecx
-; X86-NEXT: movl %ecx, %eax
-; X86-NEXT: popl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cvtsi2sd %eax, %xmm0
+; X86-NEXT: cvtsi2sdl {{[0-9]+}}(%esp), %xmm1
+; X86-NEXT: divsd %xmm0, %xmm1
+; X86-NEXT: cvttsd2si %xmm1, %edx
+; X86-NEXT: movl %edx, (%ecx)
+; X86-NEXT: imull %eax, %edx
+; X86-NEXT: subl %edx, %eax
; X86-NEXT: retl
;
; X64-LABEL: negative_inverted_division:
; X64: # %bb.0:
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: cltd
-; X64-NEXT: idivl %esi
-; X64-NEXT: movl %eax, (%rcx)
-; X64-NEXT: imull %esi, %eax
-; X64-NEXT: subl %eax, %esi
; X64-NEXT: movl %esi, %eax
+; X64-NEXT: cvtsi2sd %esi, %xmm0
+; X64-NEXT: cvtsi2sd %edi, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %edx
+; X64-NEXT: movl %edx, (%rcx)
+; X64-NEXT: imull %esi, %edx
+; X64-NEXT: subl %edx, %eax
; X64-NEXT: retq
%div = sdiv i32 %x0, %x1 ; inverted division
store i32 %div, ptr %divdst, align 4
diff --git a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
index 488a6d5860c40..c232156b6e15d 100644
--- a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
+++ b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
@@ -11,20 +11,34 @@
define i8 @scalar_i8(i8 %x, i8 %y, ptr %divdst) nounwind {
; X86-LABEL: scalar_i8:
; X86: # %bb.0:
-; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: divb {{[0-9]+}}(%esp)
-; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT: movzbl %ah, %ecx
-; X86-NEXT: movb %al, (%edx)
+; X86-NEXT: pushl %esi
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: cvtsi2ss %edx, %xmm0
+; X86-NEXT: cvtsi2ss %ecx, %xmm1
+; X86-NEXT: divss %xmm0, %xmm1
+; X86-NEXT: cvttss2si %xmm1, %eax
+; X86-NEXT: movb %al, (%esi)
+; X86-NEXT: # kill: def $al killed $al killed $eax
+; X86-NEXT: mulb %dl
+; X86-NEXT: subb %al, %cl
; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: popl %esi
; X86-NEXT: retl
;
; X64-LABEL: scalar_i8:
; X64: # %bb.0:
-; X64-NEXT: movzbl %dil, %eax
-; X64-NEXT: divb %sil
-; X64-NEXT: movzbl %ah, %ecx
+; X64-NEXT: movzbl %sil, %esi
+; X64-NEXT: cvtsi2ss %esi, %xmm0
+; X64-NEXT: movzbl %dil, %ecx
+; X64-NEXT: cvtsi2ss %ecx, %xmm1
+; X64-NEXT: divss %xmm0, %xmm1
+; X64-NEXT: cvttss2si %xmm1, %eax
; X64-NEXT: movb %al, (%rdx)
+; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: mulb %sil
+; X64-NEXT: subb %al, %cl
; X64-NEXT: movl %ecx, %eax
; X64-NEXT: retq
%div = udiv i8 %x, %y
@@ -37,23 +51,34 @@ define i8 @scalar_i8(i8 %x, i8 %y, ptr %divdst) nounwind {
define i16 @scalar_i16(i16 %x, i16 %y, ptr %divdst) nounwind {
; X86-LABEL: scalar_i16:
; X86: # %bb.0:
-; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divw {{[0-9]+}}(%esp)
+; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movw %ax, (%ecx)
-; X86-NEXT: movl %edx, %eax
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: cvtsi2ss %edx, %xmm0
+; X86-NEXT: cvtsi2ss %eax, %xmm1
+; X86-NEXT: divss %xmm0, %xmm1
+; X86-NEXT: cvttss2si %xmm1, %esi
+; X86-NEXT: movw %si, (%ecx)
+; X86-NEXT: imull %edx, %esi
+; X86-NEXT: subl %esi, %eax
+; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: popl %esi
; X86-NEXT: retl
;
; X64-LABEL: scalar_i16:
; X64: # %bb.0:
-; X64-NEXT: movq %rdx, %rcx
; X64-NEXT: movl %edi, %eax
+; X64-NEXT: movzwl %si, %ecx
+; X64-NEXT: cvtsi2ss %ecx, %xmm0
+; X64-NEXT: movzwl %ax, %ecx
+; X64-NEXT: cvtsi2ss %ecx, %xmm1
+; X64-NEXT: divss %xmm0, %xmm1
+; X64-NEXT: cvttss2si %xmm1, %ecx
+; X64-NEXT: movw %cx, (%rdx)
+; X64-NEXT: imull %esi, %ecx
+; X64-NEXT: subl %ecx, %eax
; X64-NEXT: # kill: def $ax killed $ax killed $eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divw %si
-; X64-NEXT: movw %ax, (%rcx)
-; X64-NEXT: movl %edx, %eax
; X64-NEXT: retq
%div = udiv i16 %x, %y
store i16 %div, ptr %divdst, align 4
@@ -65,22 +90,44 @@ define i16 @scalar_i16(i16 %x, i16 %y, ptr %divdst) nounwind {
define i32 @scalar_i32(i32 %x, i32 %y, ptr %divdst) nounwind {
; X86-LABEL: scalar_i32:
; X86: # %bb.0:
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl {{[0-9]+}}(%esp)
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl %eax, (%ecx)
-; X86-NEXT: movl %edx, %eax
+; X86-NEXT: movsd {{.*#+}} xmm0 = [4.503599627370496E+15,0.0E+0]
+; X86-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X86-NEXT: orpd %xmm0, %xmm1
+; X86-NEXT: subsd %xmm0, %xmm1
+; X86-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; X86-NEXT: orpd %xmm0, %xmm2
+; X86-NEXT: subsd %xmm0, %xmm2
+; X86-NEXT: divsd %xmm1, %xmm2
+; X86-NEXT: cvttsd2si %xmm2, %edx
+; X86-NEXT: movl %edx, %esi
+; X86-NEXT: sarl $31, %esi
+; X86-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
+; X86-NEXT: cvttsd2si %xmm2, %edi
+; X86-NEXT: andl %esi, %edi
+; X86-NEXT: orl %edx, %edi
+; X86-NEXT: movl %edi, (%ecx)
+; X86-NEXT: imull {{[0-9]+}}(%esp), %edi
+; X86-NEXT: subl %edi, %eax
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
; X86-NEXT: retl
;
; X64-LABEL: scalar_i32:
; X64: # %bb.0:
-; X64-NEXT: movq %rdx, %rcx
; X64-NEXT: movl %edi, %eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %esi
-; X64-NEXT: movl %eax, (%rcx)
-; X64-NEXT: movl %edx, %eax
+; X64-NEXT: movl %esi, %ecx
+; X64-NEXT: cvtsi2sd %rcx, %xmm0
+; X64-NEXT: movl %edi, %ecx
+; X64-NEXT: cvtsi2sd %rcx, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %rcx
+; X64-NEXT: movl %ecx, (%rdx)
+; X64-NEXT: imull %esi, %ecx
+; X64-NEXT: subl %ecx, %eax
; X64-NEXT: retq
%div = udiv i32 %x, %y
store i32 %div, ptr %divdst, align 4
@@ -734,77 +781,136 @@ define <8 x i16> @vector_i128_i16(<8 x i16> %x, <8 x i16> %y, ptr %divdst) nounw
define <4 x i32> @vector_i128_i32(<4 x i32> %x, <4 x i32> %y, ptr %divdst) nounwind {
; X86-LABEL: vector_i128_i32:
; X86: # %bb.0:
-; X86-NEXT: pushl %esi
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,3,3,3]
-; X86-NEXT: movd %xmm2, %eax
-; X86-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,3,3,3]
-; X86-NEXT: movd %xmm2, %esi
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %esi
-; X86-NEXT: movd %eax, %xmm3
-; X86-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,2,3]
-; X86-NEXT: movd %xmm2, %eax
-; X86-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,2,3]
-; X86-NEXT: movd %xmm2, %esi
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %esi
+; X86-NEXT: pxor %xmm4, %xmm4
+; X86-NEXT: movq {{.*#+}} xmm2 = [4.503599627370496E+15,0.0E+0]
+; X86-NEXT: movdqa %xmm1, %xmm3
+; X86-NEXT: psrldq {{.*#+}} xmm3 = xmm3[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; X86-NEXT: por %xmm2, %xmm3
+; X86-NEXT: subsd %xmm2, %xmm3
+; X86-NEXT: movdqa %xmm0, %xmm5
+; X86-NEXT: psrldq {{.*#+}} xmm5 = xmm5[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; X86-NEXT: por %xmm2, %xmm5
+; X86-NEXT: subsd %xmm2, %xmm5
+; X86-NEXT: divsd %xmm3, %xmm5
+; X86-NEXT: cvttsd2si %xmm5, %eax
+; X86-NEXT: movl %eax, %ecx
+; X86-NEXT: sarl $31, %ecx
+; X86-NEXT: movsd {{.*#+}} xmm3 = [2.147483648E+9,0.0E+0]
+; X86-NEXT: subsd %xmm3, %xmm5
+; X86-NEXT: cvttsd2si %xmm5, %edx
+; X86-NEXT: andl %ecx, %edx
+; X86-NEXT: orl %eax, %edx
+; X86-NEXT: movdqa %xmm1, %xmm6
+; X86-NEXT: punpckhdq {{.*#+}} xmm6 = xmm6[2],xmm4[2],xmm6[3],xmm4[3]
+; X86-NEXT: movdqa %xmm0, %xmm7
+; X86-NEXT: punpckhdq {{.*#+}} xmm7 = xmm7[2],xmm4[2],xmm7[3],xmm4[3]
+; X86-NEXT: movd %edx, %xmm5
+; X86-NEXT: por %xmm2, %xmm6
+; X86-NEXT: subsd %xmm2, %xmm6
+; X86-NEXT: por %xmm2, %xmm7
+; X86-NEXT: subsd %xmm2, %xmm7
+; X86-NEXT: divsd %xmm6, %xmm7
+; X86-NEXT: cvttsd2si %xmm7, %eax
+; X86-NEXT: movl %eax, %ecx
+; X86-NEXT: sarl $31, %ecx
+; X86-NEXT: subsd %xmm3, %xmm7
+; X86-NEXT: cvttsd2si %xmm7, %edx
+; X86-NEXT: andl %ecx, %edx
+; X86-NEXT: orl %eax, %edx
+; X86-NEXT: movd %edx, %xmm4
+; X86-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
+; X86-NEXT: movdqa %xmm1, %xmm5
+; X86-NEXT: psrlq $32, %xmm5
+; X86-NEXT: por %xmm2, %xmm5
+; X86-NEXT: subsd %xmm2, %xmm5
+; X86-NEXT: movdqa %xmm0, %xmm6
+; X86-NEXT: psrlq $32, %xmm6
+; X86-NEXT: por %xmm2, %xmm6
+; X86-NEXT: subsd %xmm2, %xmm6
+; X86-NEXT: divsd %xmm5, %xmm6
+; X86-NEXT: xorpd %xmm5, %xmm5
+; X86-NEXT: movss {{.*#+}} xmm5 = xmm0[0],xmm5[1,2,3]
+; X86-NEXT: cvttsd2si %xmm6, %ecx
+; X86-NEXT: subsd %xmm3, %xmm6
+; X86-NEXT: cvttsd2si %xmm6, %eax
+; X86-NEXT: xorpd %xmm6, %xmm6
+; X86-NEXT: movss {{.*#+}} xmm6 = xmm1[0],xmm6[1,2,3]
+; X86-NEXT: orps %xmm2, %xmm6
+; X86-NEXT: subsd %xmm2, %xmm6
+; X86-NEXT: orps %xmm2, %xmm5
+; X86-NEXT: subsd %xmm2, %xmm5
+; X86-NEXT: divsd %xmm6, %xmm5
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: sarl $31, %edx
+; X86-NEXT: andl %edx, %eax
+; X86-NEXT: orl %ecx, %eax
+; X86-NEXT: cvttsd2si %xmm5, %ecx
+; X86-NEXT: subsd %xmm3, %xmm5
; X86-NEXT: movd %eax, %xmm2
-; X86-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
-; X86-NEXT: movd %xmm0, %eax
-; X86-NEXT: movd %xmm1, %esi
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %esi
-; X86-NEXT: movd %eax, %xmm3
-; X86-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,1,1]
-; X86-NEXT: movd %xmm4, %eax
-; X86-NEXT: pshufd {{.*#+}} xmm4 = xmm1[1,1,1,1]
-; X86-NEXT: movd %xmm4, %esi
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %esi
-; X86-NEXT: movd %eax, %xmm4
-; X86-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1]
-; X86-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm2[0]
-; X86-NEXT: movdqa %xmm3, (%ecx)
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: sarl $31, %eax
+; X86-NEXT: cvttsd2si %xmm5, %edx
+; X86-NEXT: andl %eax, %edx
+; X86-NEXT: orl %ecx, %edx
+; X86-NEXT: movd %edx, %xmm3
+; X86-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm4[0]
+; X86-NEXT: movdqa %xmm3, (%eax)
; X86-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,1,3,3]
; X86-NEXT: pmuludq %xmm1, %xmm3
-; X86-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
; X86-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X86-NEXT: pmuludq %xmm2, %xmm1
+; X86-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3]
; X86-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
-; X86-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
-; X86-NEXT: psubd %xmm3, %xmm0
-; X86-NEXT: popl %esi
+; X86-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
+; X86-NEXT: psubd %xmm2, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: vector_i128_i32:
; X64: # %bb.0:
-; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,3,3,3]
-; X64-NEXT: movd %xmm2, %eax
; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,3,3,3]
-; X64-NEXT: movd %xmm2, %ecx
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %ecx
-; X64-NEXT: movd %eax, %xmm2
-; X64-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,2,3]
+; X64-NEXT: movd %xmm2, %eax
+; X64-NEXT: xorps %xmm2, %xmm2
+; X64-NEXT: cvtsi2sd %rax, %xmm2
+; X64-NEXT: pshufd {{.*#+}} xmm3 = xmm0[3,3,3,3]
; X64-NEXT: movd %xmm3, %eax
+; X64-NEXT: xorps %xmm3, %xmm3
+; X64-NEXT: cvtsi2sd %rax, %xmm3
+; X64-NEXT: divsd %xmm2, %xmm3
+; X64-NEXT: cvttsd2si %xmm3, %rax
+; X64-NEXT: movd %eax, %xmm2
; X64-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
-; X64-NEXT: movd %xmm3, %ecx
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %ecx
+; X64-NEXT: movd %xmm3, %eax
+; X64-NEXT: xorps %xmm3, %xmm3
+; X64-NEXT: cvtsi2sd %rax, %xmm3
+; X64-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,2,3]
+; X64-NEXT: movd %xmm4, %eax
+; X64-NEXT: xorps %xmm4, %xmm4
+; X64-NEXT: cvtsi2sd %rax, %xmm4
+; X64-NEXT: divsd %xmm3, %xmm4
+; X64-NEXT: cvttsd2si %xmm4, %rax
; X64-NEXT: movd %eax, %xmm3
; X64-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
+; X64-NEXT: movd %xmm1, %eax
+; X64-NEXT: xorps %xmm2, %xmm2
+; X64-NEXT: cvtsi2sd %rax, %xmm2
; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: movd %xmm1, %ecx
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %ecx
+; X64-NEXT: xorps %xmm4, %xmm4
+; X64-NEXT: cvtsi2sd %rax, %xmm4
+; X64-NEXT: divsd %xmm2, %xmm4
+; X64-NEXT: cvttsd2si %xmm4, %rax
; X64-NEXT: movd %eax, %xmm2
-; X64-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,1,1]
-; X64-NEXT: movd %xmm4, %eax
; X64-NEXT: pshufd {{.*#+}} xmm4 = xmm1[1,1,1,1]
-; X64-NEXT: movd %xmm4, %ecx
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %ecx
+; X64-NEXT: movd %xmm4, %eax
+; X64-NEXT: xorps %xmm4, %xmm4
+; X64-NEXT: cvtsi2sd %rax, %xmm4
+; X64-NEXT: pshufd {{.*#+}} xmm5 = xmm0[1,1,1,1]
+; X64-NEXT: movd %xmm5, %eax
+; X64-NEXT: xorps %xmm5, %xmm5
+; X64-NEXT: cvtsi2sd %rax, %xmm5
+; X64-NEXT: divsd %xmm4, %xmm5
+; X64-NEXT: cvttsd2si %xmm5, %rax
; X64-NEXT: movd %eax, %xmm4
; X64-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
; X64-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
@@ -918,23 +1024,48 @@ define <2 x i64> @vector_i128_i64(<2 x i64> %x, <2 x i64> %y, ptr %divdst) nounw
define i32 @scalar_i32_commutative(i32 %x, ptr %ysrc, ptr %divdst) nounwind {
; X86-LABEL: scalar_i32_commutative:
; X86: # %bb.0:
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl (%ecx)
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl %eax, (%ecx)
-; X86-NEXT: movl %edx, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movsd {{.*#+}} xmm0 = [4.503599627370496E+15,0.0E+0]
+; X86-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X86-NEXT: orpd %xmm0, %xmm1
+; X86-NEXT: subsd %xmm0, %xmm1
+; X86-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; X86-NEXT: orpd %xmm0, %xmm2
+; X86-NEXT: subsd %xmm0, %xmm2
+; X86-NEXT: divsd %xmm1, %xmm2
+; X86-NEXT: cvttsd2si %xmm2, %esi
+; X86-NEXT: movl %esi, %edi
+; X86-NEXT: sarl $31, %edi
+; X86-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
+; X86-NEXT: cvttsd2si %xmm2, %ebx
+; X86-NEXT: andl %edi, %ebx
+; X86-NEXT: orl %esi, %ebx
+; X86-NEXT: movl (%edx), %edx
+; X86-NEXT: imull %ebx, %edx
+; X86-NEXT: subl %edx, %eax
+; X86-NEXT: movl %ebx, (%ecx)
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
; X86-NEXT: retl
;
; X64-LABEL: scalar_i32_commutative:
; X64: # %bb.0:
-; X64-NEXT: movq %rdx, %rcx
; X64-NEXT: movl %edi, %eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl (%rsi)
-; X64-NEXT: movl %eax, (%rcx)
-; X64-NEXT: movl %edx, %eax
+; X64-NEXT: movl (%rsi), %ecx
+; X64-NEXT: cvtsi2sd %rcx, %xmm0
+; X64-NEXT: movl %edi, %esi
+; X64-NEXT: cvtsi2sd %rsi, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %rsi
+; X64-NEXT: movl %esi, (%rdx)
+; X64-NEXT: imull %ecx, %esi
+; X64-NEXT: subl %esi, %eax
; X64-NEXT: retq
%y = load i32, ptr %ysrc, align 4
%div = udiv i32 %x, %y
@@ -948,32 +1079,49 @@ define i32 @scalar_i32_commutative(i32 %x, ptr %ysrc, ptr %divdst) nounwind {
define i32 @extrause(i32 %x, i32 %y, ptr %divdst, ptr %t1dst) nounwind {
; X86-LABEL: extrause:
; X86: # %bb.0:
+; X86-NEXT: pushl %ebx
; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %ecx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
-; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
-; X86-NEXT: movl %eax, (%edi)
-; X86-NEXT: imull %ecx, %eax
-; X86-NEXT: movl %eax, (%esi)
-; X86-NEXT: movl %edx, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movsd {{.*#+}} xmm0 = [4.503599627370496E+15,0.0E+0]
+; X86-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X86-NEXT: orpd %xmm0, %xmm1
+; X86-NEXT: subsd %xmm0, %xmm1
+; X86-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; X86-NEXT: orpd %xmm0, %xmm2
+; X86-NEXT: subsd %xmm0, %xmm2
+; X86-NEXT: divsd %xmm1, %xmm2
+; X86-NEXT: cvttsd2si %xmm2, %esi
+; X86-NEXT: movl %esi, %edi
+; X86-NEXT: sarl $31, %edi
+; X86-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
+; X86-NEXT: cvttsd2si %xmm2, %ebx
+; X86-NEXT: andl %edi, %ebx
+; X86-NEXT: orl %esi, %ebx
+; X86-NEXT: movl %ebx, (%edx)
+; X86-NEXT: imull {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl %ebx, (%ecx)
+; X86-NEXT: subl %ebx, %eax
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
; X86-NEXT: retl
;
; X64-LABEL: extrause:
; X64: # %bb.0:
-; X64-NEXT: movq %rdx, %r8
; X64-NEXT: movl %edi, %eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %esi
-; X64-NEXT: movl %eax, (%r8)
-; X64-NEXT: imull %esi, %eax
-; X64-NEXT: movl %eax, (%rcx)
-; X64-NEXT: movl %edx, %eax
+; X64-NEXT: movl %esi, %edi
+; X64-NEXT: cvtsi2sd %rdi, %xmm0
+; X64-NEXT: movl %eax, %edi
+; X64-NEXT: cvtsi2sd %rdi, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %rdi
+; X64-NEXT: movl %edi, (%rdx)
+; X64-NEXT: imull %esi, %edi
+; X64-NEXT: movl %edi, (%rcx)
+; X64-NEXT: subl %edi, %eax
; X64-NEXT: retq
%div = udiv i32 %x, %y
store i32 %div, ptr %divdst, align 4
@@ -987,46 +1135,57 @@ define i32 @extrause(i32 %x, i32 %y, ptr %divdst, ptr %t1dst) nounwind {
define i32 @multiple_bb(i32 %x, i32 %y, ptr %divdst, i1 zeroext %store_urem, ptr %uremdst) nounwind {
; X86-LABEL: multiple_bb:
; X86: # %bb.0:
-; X86-NEXT: pushl %ebx
; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi
-; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ebx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
-; X86-NEXT: movl %ecx, %eax
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %esi
-; X86-NEXT: movl %eax, (%edi)
-; X86-NEXT: testb %bl, %bl
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movsd {{.*#+}} xmm0 = [4.503599627370496E+15,0.0E+0]
+; X86-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X86-NEXT: orpd %xmm0, %xmm1
+; X86-NEXT: subsd %xmm0, %xmm1
+; X86-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; X86-NEXT: orpd %xmm0, %xmm2
+; X86-NEXT: subsd %xmm0, %xmm2
+; X86-NEXT: divsd %xmm1, %xmm2
+; X86-NEXT: cvttsd2si %xmm2, %esi
+; X86-NEXT: movl %esi, %edi
+; X86-NEXT: sarl $31, %edi
+; X86-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
+; X86-NEXT: cvttsd2si %xmm2, %eax
+; X86-NEXT: andl %edi, %eax
+; X86-NEXT: orl %esi, %eax
+; X86-NEXT: movl %eax, (%edx)
+; X86-NEXT: testb %cl, %cl
; X86-NEXT: je .LBB11_2
; X86-NEXT: # %bb.1: # %do_urem
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT: movl %eax, %edi
-; X86-NEXT: imull %esi, %edi
-; X86-NEXT: subl %edi, %ecx
-; X86-NEXT: movl %ecx, (%edx)
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: imull %eax, %esi
+; X86-NEXT: subl %esi, %edx
+; X86-NEXT: movl %edx, (%ecx)
; X86-NEXT: .LBB11_2: # %end
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
-; X86-NEXT: popl %ebx
; X86-NEXT: retl
;
; X64-LABEL: multiple_bb:
; X64: # %bb.0:
-; X64-NEXT: movq %rdx, %r9
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: cvtsi2sd %rax, %xmm0
; X64-NEXT: movl %edi, %eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %esi
-; X64-NEXT: movl %eax, (%r9)
+; X64-NEXT: cvtsi2sd %rax, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %rax
+; X64-NEXT: movl %eax, (%rdx)
; X64-NEXT: testl %ecx, %ecx
; X64-NEXT: je .LBB11_2
; X64-NEXT: # %bb.1: # %do_urem
-; X64-NEXT: movl %eax, %ecx
-; X64-NEXT: imull %esi, %ecx
-; X64-NEXT: subl %ecx, %edi
+; X64-NEXT: imull %eax, %esi
+; X64-NEXT: subl %esi, %edi
; X64-NEXT: movl %edi, (%r8)
; X64-NEXT: .LBB11_2: # %end
+; X64-NEXT: # kill: def $eax killed $eax killed $rax
; X64-NEXT: retq
%div = udiv i32 %x, %y
store i32 %div, ptr %divdst, align 4
@@ -1045,30 +1204,42 @@ define i32 @negative_different_x(i32 %x0, i32 %x1, i32 %y, ptr %divdst) nounwind
; X86: # %bb.0:
; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %edi
-; X86-NEXT: movl %eax, (%esi)
-; X86-NEXT: imull %edi, %eax
-; X86-NEXT: subl %eax, %ecx
-; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movsd {{.*#+}} xmm0 = [4.503599627370496E+15,0.0E+0]
+; X86-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X86-NEXT: orpd %xmm0, %xmm1
+; X86-NEXT: subsd %xmm0, %xmm1
+; X86-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; X86-NEXT: orpd %xmm0, %xmm2
+; X86-NEXT: subsd %xmm0, %xmm2
+; X86-NEXT: divsd %xmm1, %xmm2
+; X86-NEXT: cvttsd2si %xmm2, %edx
+; X86-NEXT: movl %edx, %esi
+; X86-NEXT: sarl $31, %esi
+; X86-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
+; X86-NEXT: cvttsd2si %xmm2, %edi
+; X86-NEXT: andl %esi, %edi
+; X86-NEXT: orl %edx, %edi
+; X86-NEXT: movl %edi, (%ecx)
+; X86-NEXT: imull {{[0-9]+}}(%esp), %edi
+; X86-NEXT: subl %edi, %eax
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
; X86-NEXT: retl
;
; X64-LABEL: negative_different_x:
; X64: # %bb.0:
-; X64-NEXT: movl %edx, %r8d
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %r8d
-; X64-NEXT: movl %eax, (%rcx)
-; X64-NEXT: imull %r8d, %eax
-; X64-NEXT: subl %eax, %esi
; X64-NEXT: movl %esi, %eax
+; X64-NEXT: movl %edx, %esi
+; X64-NEXT: cvtsi2sd %rsi, %xmm0
+; X64-NEXT: movl %edi, %esi
+; X64-NEXT: cvtsi2sd %rsi, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %rsi
+; X64-NEXT: movl %esi, (%rcx)
+; X64-NEXT: imull %edx, %esi
+; X64-NEXT: subl %esi, %eax
; X64-NEXT: retq
%div = udiv i32 %x0, %y ; not %x1
store i32 %div, ptr %divdst, align 4
@@ -1080,29 +1251,44 @@ define i32 @negative_different_x(i32 %x0, i32 %x1, i32 %y, ptr %divdst) nounwind
define i32 @negative_different_y(i32 %x0, i32 %x1, i32 %y, i32 %z, ptr %divdst) nounwind {
; X86-LABEL: negative_different_y:
; X86: # %bb.0:
+; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi
-; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl %ecx, %eax
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl {{[0-9]+}}(%esp)
-; X86-NEXT: movl %eax, (%esi)
-; X86-NEXT: imull {{[0-9]+}}(%esp), %eax
-; X86-NEXT: subl %eax, %ecx
-; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: movsd {{.*#+}} xmm0 = [4.503599627370496E+15,0.0E+0]
+; X86-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X86-NEXT: orpd %xmm0, %xmm1
+; X86-NEXT: subsd %xmm0, %xmm1
+; X86-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; X86-NEXT: orpd %xmm0, %xmm2
+; X86-NEXT: subsd %xmm0, %xmm2
+; X86-NEXT: divsd %xmm1, %xmm2
+; X86-NEXT: cvttsd2si %xmm2, %edx
+; X86-NEXT: movl %edx, %esi
+; X86-NEXT: sarl $31, %esi
+; X86-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
+; X86-NEXT: cvttsd2si %xmm2, %edi
+; X86-NEXT: andl %esi, %edi
+; X86-NEXT: orl %edx, %edi
+; X86-NEXT: movl %edi, (%ecx)
+; X86-NEXT: imull {{[0-9]+}}(%esp), %edi
+; X86-NEXT: subl %edi, %eax
; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
; X86-NEXT: retl
;
; X64-LABEL: negative_different_y:
; X64: # %bb.0:
-; X64-NEXT: movl %edx, %edi
-; X64-NEXT: movl %esi, %eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %ecx
-; X64-NEXT: movl %eax, (%r8)
-; X64-NEXT: imull %eax, %edi
-; X64-NEXT: subl %edi, %esi
; X64-NEXT: movl %esi, %eax
+; X64-NEXT: movl %ecx, %ecx
+; X64-NEXT: cvtsi2sd %rcx, %xmm0
+; X64-NEXT: movl %esi, %ecx
+; X64-NEXT: cvtsi2sd %rcx, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %rcx
+; X64-NEXT: movl %ecx, (%r8)
+; X64-NEXT: imull %ecx, %edx
+; X64-NEXT: subl %edx, %eax
; X64-NEXT: retq
%div = udiv i32 %x1, %z ; not %x0
store i32 %div, ptr %divdst, align 4
@@ -1114,28 +1300,44 @@ define i32 @negative_different_y(i32 %x0, i32 %x1, i32 %y, i32 %z, ptr %divdst)
define i32 @negative_inverted_division(i32 %x0, i32 %x1, i32 %y, ptr %divdst) nounwind {
; X86-LABEL: negative_inverted_division:
; X86: # %bb.0:
+; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi
-; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %ecx
-; X86-NEXT: movl %eax, (%esi)
-; X86-NEXT: imull %ecx, %eax
-; X86-NEXT: subl %eax, %ecx
-; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: movsd {{.*#+}} xmm0 = [4.503599627370496E+15,0.0E+0]
+; X86-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X86-NEXT: orpd %xmm0, %xmm1
+; X86-NEXT: subsd %xmm0, %xmm1
+; X86-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; X86-NEXT: orpd %xmm0, %xmm2
+; X86-NEXT: subsd %xmm0, %xmm2
+; X86-NEXT: divsd %xmm1, %xmm2
+; X86-NEXT: cvttsd2si %xmm2, %edx
+; X86-NEXT: movl %edx, %esi
+; X86-NEXT: sarl $31, %esi
+; X86-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
+; X86-NEXT: cvttsd2si %xmm2, %edi
+; X86-NEXT: andl %esi, %edi
+; X86-NEXT: orl %edx, %edi
+; X86-NEXT: movl %edi, (%ecx)
+; X86-NEXT: imull %eax, %edi
+; X86-NEXT: subl %edi, %eax
; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
; X86-NEXT: retl
;
; X64-LABEL: negative_inverted_division:
; X64: # %bb.0:
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %esi
-; X64-NEXT: movl %eax, (%rcx)
-; X64-NEXT: imull %esi, %eax
-; X64-NEXT: subl %eax, %esi
; X64-NEXT: movl %esi, %eax
+; X64-NEXT: movl %esi, %edx
+; X64-NEXT: cvtsi2sd %rdx, %xmm0
+; X64-NEXT: movl %edi, %edx
+; X64-NEXT: cvtsi2sd %rdx, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %rdx
+; X64-NEXT: movl %edx, (%rcx)
+; X64-NEXT: imull %esi, %edx
+; X64-NEXT: subl %edx, %eax
; X64-NEXT: retq
%div = udiv i32 %x0, %x1 ; inverted division
store i32 %div, ptr %divdst, align 4
diff --git a/llvm/test/CodeGen/X86/div8.ll b/llvm/test/CodeGen/X86/div8.ll
index 44ce72ab8e03e..0061a9492561b 100644
--- a/llvm/test/CodeGen/X86/div8.ll
+++ b/llvm/test/CodeGen/X86/div8.ll
@@ -1,9 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s | FileCheck %s
; ModuleID = '8div.c'
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-apple-macosx10.6.6"
define signext i8 @test_div(i8 %dividend, i8 %divisor) nounwind ssp {
+; CHECK-LABEL: test_div:
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movb %sil, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movzbl %sil, %eax
+; CHECK-NEXT: cvtsi2ss %eax, %xmm0
+; CHECK-NEXT: movzbl %dil, %eax
+; CHECK-NEXT: cvtsi2ss %eax, %xmm1
+; CHECK-NEXT: divss %xmm0, %xmm1
+; CHECK-NEXT: cvttss2si %xmm1, %eax
+; CHECK-NEXT: movb %al, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movsbl %al, %eax
+; CHECK-NEXT: retq
entry:
%dividend.addr = alloca i8, align 2
%divisor.addr = alloca i8, align 1
@@ -13,8 +27,6 @@ entry:
%tmp = load i8, ptr %dividend.addr, align 2
%tmp1 = load i8, ptr %divisor.addr, align 1
; Insist on i8->i32 zero extension, even though divb demands only i16:
-; CHECK: movzbl {{.*}}%eax
-; CHECK: divb
%div = udiv i8 %tmp, %tmp1
store i8 %div, ptr %quotient, align 1
%tmp4 = load i8, ptr %quotient, align 1
diff --git a/llvm/test/CodeGen/X86/divrem8_ext.ll b/llvm/test/CodeGen/X86/divrem8_ext.ll
index bfc982d2def5d..3241d7aa7eae3 100644
--- a/llvm/test/CodeGen/X86/divrem8_ext.ll
+++ b/llvm/test/CodeGen/X86/divrem8_ext.ll
@@ -37,10 +37,16 @@ define zeroext i8 @test_urem_zext_ah(i8 %x, i8 %y) {
;
; X64-LABEL: test_urem_zext_ah:
; X64: # %bb.0:
-; X64-NEXT: movzbl %dil, %eax
-; X64-NEXT: divb %sil
-; X64-NEXT: movzbl %ah, %eax
+; X64-NEXT: movzbl %sil, %edx
+; X64-NEXT: cvtsi2ss %edx, %xmm0
+; X64-NEXT: movzbl %dil, %ecx
+; X64-NEXT: cvtsi2ss %ecx, %xmm1
+; X64-NEXT: divss %xmm0, %xmm1
+; X64-NEXT: cvttss2si %xmm1, %eax
; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: mulb %dl
+; X64-NEXT: subb %al, %cl
+; X64-NEXT: movl %ecx, %eax
; X64-NEXT: retq
%1 = urem i8 %x, %y
ret i8 %1
@@ -59,11 +65,17 @@ define i8 @test_urem_noext_ah(i8 %x, i8 %y) {
;
; X64-LABEL: test_urem_noext_ah:
; X64: # %bb.0:
-; X64-NEXT: movzbl %dil, %eax
-; X64-NEXT: divb %sil
-; X64-NEXT: movzbl %ah, %eax
-; X64-NEXT: addb %sil, %al
+; X64-NEXT: movzbl %sil, %edx
+; X64-NEXT: cvtsi2ss %edx, %xmm0
+; X64-NEXT: movzbl %dil, %ecx
+; X64-NEXT: cvtsi2ss %ecx, %xmm1
+; X64-NEXT: divss %xmm0, %xmm1
+; X64-NEXT: cvttss2si %xmm1, %eax
; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: mulb %dl
+; X64-NEXT: subb %al, %cl
+; X64-NEXT: addb %dl, %cl
+; X64-NEXT: movl %ecx, %eax
; X64-NEXT: retq
%1 = urem i8 %x, %y
%2 = add i8 %1, %y
@@ -81,9 +93,16 @@ define i64 @test_urem_zext64_ah(i8 %x, i8 %y) {
;
; X64-LABEL: test_urem_zext64_ah:
; X64: # %bb.0:
-; X64-NEXT: movzbl %dil, %eax
-; X64-NEXT: divb %sil
-; X64-NEXT: movzbl %ah, %eax
+; X64-NEXT: movzbl %sil, %ecx
+; X64-NEXT: cvtsi2ss %ecx, %xmm0
+; X64-NEXT: movzbl %dil, %edx
+; X64-NEXT: cvtsi2ss %edx, %xmm1
+; X64-NEXT: divss %xmm0, %xmm1
+; X64-NEXT: cvttss2si %xmm1, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: mulb %cl
+; X64-NEXT: subb %al, %dl
+; X64-NEXT: movzbl %dl, %eax
; X64-NEXT: retq
%1 = urem i8 %x, %y
%2 = zext i8 %1 to i64
@@ -125,10 +144,16 @@ define signext i8 @test_srem_sext_ah(i8 %x, i8 %y) {
;
; X64-LABEL: test_srem_sext_ah:
; X64: # %bb.0:
-; X64-NEXT: movsbl %dil, %eax
-; X64-NEXT: idivb %sil
-; X64-NEXT: movsbl %ah, %eax
+; X64-NEXT: movsbl %sil, %edx
+; X64-NEXT: cvtsi2ss %edx, %xmm0
+; X64-NEXT: movsbl %dil, %ecx
+; X64-NEXT: cvtsi2ss %ecx, %xmm1
+; X64-NEXT: divss %xmm0, %xmm1
+; X64-NEXT: cvttss2si %xmm1, %eax
; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: mulb %dl
+; X64-NEXT: subb %al, %cl
+; X64-NEXT: movl %ecx, %eax
; X64-NEXT: retq
%1 = srem i8 %x, %y
ret i8 %1
@@ -147,11 +172,17 @@ define i8 @test_srem_noext_ah(i8 %x, i8 %y) {
;
; X64-LABEL: test_srem_noext_ah:
; X64: # %bb.0:
-; X64-NEXT: movsbl %dil, %eax
-; X64-NEXT: idivb %sil
-; X64-NEXT: movsbl %ah, %eax
-; X64-NEXT: addb %sil, %al
+; X64-NEXT: movsbl %sil, %edx
+; X64-NEXT: cvtsi2ss %edx, %xmm0
+; X64-NEXT: movsbl %dil, %ecx
+; X64-NEXT: cvtsi2ss %ecx, %xmm1
+; X64-NEXT: divss %xmm0, %xmm1
+; X64-NEXT: cvttss2si %xmm1, %eax
; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: mulb %dl
+; X64-NEXT: subb %al, %cl
+; X64-NEXT: addb %dl, %cl
+; X64-NEXT: movl %ecx, %eax
; X64-NEXT: retq
%1 = srem i8 %x, %y
%2 = add i8 %1, %y
@@ -170,10 +201,16 @@ define i64 @test_srem_sext64_ah(i8 %x, i8 %y) {
;
; X64-LABEL: test_srem_sext64_ah:
; X64: # %bb.0:
-; X64-NEXT: movsbl %dil, %eax
-; X64-NEXT: idivb %sil
-; X64-NEXT: movsbl %ah, %eax
-; X64-NEXT: cltq
+; X64-NEXT: movsbl %sil, %ecx
+; X64-NEXT: cvtsi2ss %ecx, %xmm0
+; X64-NEXT: movsbl %dil, %edx
+; X64-NEXT: cvtsi2ss %edx, %xmm1
+; X64-NEXT: divss %xmm0, %xmm1
+; X64-NEXT: cvttss2si %xmm1, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: mulb %cl
+; X64-NEXT: subb %al, %dl
+; X64-NEXT: movsbq %dl, %rax
; X64-NEXT: retq
%1 = srem i8 %x, %y
%2 = sext i8 %1 to i64
diff --git a/llvm/test/CodeGen/X86/early-ifcvt.ll b/llvm/test/CodeGen/X86/early-ifcvt.ll
index d50f7e9e392a8..8603a7d402005 100644
--- a/llvm/test/CodeGen/X86/early-ifcvt.ll
+++ b/llvm/test/CodeGen/X86/early-ifcvt.ll
@@ -1,14 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -x86-early-ifcvt -stress-early-ifcvt | FileCheck %s
target triple = "x86_64-apple-macosx10.8.0"
; CHECK: mm2
define i32 @mm2(ptr nocapture %p, i32 %n) nounwind uwtable readonly ssp {
+; CHECK-LABEL: mm2:
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: LBB0_1: ## %do.body
+; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: movl %ecx, %edx
+; CHECK-NEXT: movl (%rdi), %r8d
+; CHECK-NEXT: addq $4, %rdi
+; CHECK-NEXT: cmpl %ecx, %r8d
+; CHECK-NEXT: cmovll %r8d, %ecx
+; CHECK-NEXT: cmpl %eax, %r8d
+; CHECK-NEXT: cmovgl %r8d, %eax
+; CHECK-NEXT: cmovgl %edx, %ecx
+; CHECK-NEXT: decl %esi
+; CHECK-NEXT: jne LBB0_1
+; CHECK-NEXT: ## %bb.2: ## %do.end
+; CHECK-NEXT: subl %ecx, %eax
+; CHECK-NEXT: retq
entry:
br label %do.body
-; CHECK: do.body
; Loop body has no branches before the backedge.
-; CHECK-NOT: LBB
do.body:
%max.0 = phi i32 [ 0, %entry ], [ %max.1, %do.cond ]
%min.0 = phi i32 [ 0, %entry ], [ %min.1, %do.cond ]
@@ -27,8 +46,6 @@ if.else:
do.cond:
%max.1 = phi i32 [ %0, %do.body ], [ %max.0, %if.else ]
%min.1 = phi i32 [ %min.0, %do.body ], [ %.min.0, %if.else ]
-; CHECK: decl %esi
-; CHECK: jne LBB
%dec = add i32 %n.addr.0, -1
%tobool = icmp eq i32 %dec, 0
br i1 %tobool, label %do.end, label %do.body
@@ -48,6 +65,21 @@ do.end:
; CHECK: fprintf
define void @multipreds(i32 %sw) nounwind uwtable ssp {
+; CHECK-LABEL: multipreds:
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: pushq %rax
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: movl $66, %ecx
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpl $127, %edi
+; CHECK-NEXT: movl $2, %eax
+; CHECK-NEXT: cmovel %ecx, %eax
+; CHECK-NEXT: testl %edi, %edi
+; CHECK-NEXT: cmovel %edx, %eax
+; CHECK-NEXT: movl %eax, %edi
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: callq _fprintf
+; CHECK-NEXT: ud2
entry:
switch i32 %sw, label %if.then29 [
i32 0, label %if.then37
@@ -72,6 +104,48 @@ declare void @fprintf(...) nounwind
; This test case contains irreducible control flow, so MachineLoopInfo doesn't
; recognize the cycle in the CFG. This would confuse MachineTraceMetrics.
define void @BZ2_decompress(ptr %s) nounwind ssp {
+; CHECK-LABEL: BZ2_decompress:
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: xorl %ebx, %ebx
+; CHECK-NEXT: testb %bl, %bl
+; CHECK-NEXT: jne LBB2_8
+; CHECK-NEXT: ## %bb.1: ## %entry
+; CHECK-NEXT: movabsq $18897856102400, %rax ## imm = 0x113000000000
+; CHECK-NEXT: btq %rbx, %rax
+; CHECK-NEXT: jae LBB2_2
+; CHECK-NEXT: LBB2_9: ## %save_state_and_return
+; CHECK-NEXT: movl %ebx, (%rax)
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB2_2: ## %entry
+; CHECK-NEXT: cmpq $38, %rbx
+; CHECK-NEXT: je LBB2_5
+; CHECK-NEXT: ## %bb.3: ## %entry
+; CHECK-NEXT: cmpq $39, %rbx
+; CHECK-NEXT: jne LBB2_8
+; CHECK-NEXT: ## %bb.4: ## %if.end.sw.bb2050_crit_edge
+; CHECK-NEXT: xorl %ebx, %ebx
+; CHECK-NEXT: jmp LBB2_6
+; CHECK-NEXT: LBB2_8: ## %sw.default
+; CHECK-NEXT: callq _BZ2_bz__AssertH__fail
+; CHECK-NEXT: jmp LBB2_9
+; CHECK-NEXT: LBB2_5: ## %sw.bb1983
+; CHECK-NEXT: xorl %ebx, %ebx
+; CHECK-NEXT: testb %bl, %bl
+; CHECK-NEXT: jne LBB2_9
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: LBB2_6: ## %while.body2038
+; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: testb %al, %al
+; CHECK-NEXT: jne LBB2_9
+; CHECK-NEXT: ## %bb.7: ## %if.end2042
+; CHECK-NEXT: ## in Loop: Header=BB2_6 Depth=1
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: testb %al, %al
+; CHECK-NEXT: je LBB2_6
+; CHECK-NEXT: jmp LBB2_9
entry:
switch i32 undef, label %sw.default [
i32 39, label %if.end.sw.bb2050_crit_edge
@@ -147,6 +221,15 @@ declare void @BZ2_bz__AssertH__fail()
; CHECK: test_idiv
; CHECK-NOT: cmov
define i32 @test_idiv(i32 %a, i32 %b) nounwind uwtable readnone ssp {
+; CHECK-LABEL: test_idiv:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: testl %esi, %esi
+; CHECK-NEXT: cvtsi2sd %esi, %xmm0
+; CHECK-NEXT: cvtsi2sd %edi, %xmm1
+; CHECK-NEXT: divsd %xmm0, %xmm1
+; CHECK-NEXT: cvttsd2si %xmm1, %eax
+; CHECK-NEXT: cmovel %edi, %eax
+; CHECK-NEXT: retq
%1 = icmp eq i32 %b, 0
br i1 %1, label %4, label %2
@@ -162,6 +245,18 @@ define i32 @test_idiv(i32 %a, i32 %b) nounwind uwtable readnone ssp {
; CHECK: test_div
; CHECK-NOT: cmov
define i32 @test_div(i32 %a, i32 %b) nounwind uwtable readnone ssp {
+; CHECK-LABEL: test_div:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: testl %esi, %esi
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: cvtsi2sd %rax, %xmm1
+; CHECK-NEXT: divsd %xmm0, %xmm1
+; CHECK-NEXT: cvttsd2si %xmm1, %rax
+; CHECK-NEXT: cmovel %edi, %eax
+; CHECK-NEXT: ## kill: def $eax killed $eax killed $rax
+; CHECK-NEXT: retq
%1 = icmp eq i32 %b, 0
br i1 %1, label %4, label %2
diff --git a/llvm/test/CodeGen/X86/expand-vp-int-intrinsics.ll b/llvm/test/CodeGen/X86/expand-vp-int-intrinsics.ll
index b63e0cadad8ef..4eb2a1afe0a2e 100644
--- a/llvm/test/CodeGen/X86/expand-vp-int-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/expand-vp-int-intrinsics.ll
@@ -184,34 +184,76 @@ define void @vp_udiv_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) noun
; X86: # %bb.0:
; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi
-; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: vpmovzxdq {{.*#+}} xmm4 = xmm0[0],zero,xmm0[1],zero
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: vbroadcastss {{[0-9]+}}(%esp), %xmm2
; X86-NEXT: vpmovsxbd {{.*#+}} xmm3 = [0,1,2,3]
; X86-NEXT: vpmaxud %xmm3, %xmm2, %xmm2
; X86-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2
; X86-NEXT: vblendvps %xmm2, {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
-; X86-NEXT: vextractps $1, %xmm1, %ecx
-; X86-NEXT: vpextrd $1, %xmm0, %eax
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %ecx
-; X86-NEXT: movl %eax, %ecx
-; X86-NEXT: vmovd %xmm1, %edi
-; X86-NEXT: vmovd %xmm0, %eax
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %edi
-; X86-NEXT: vmovd %eax, %xmm2
-; X86-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2
-; X86-NEXT: vpextrd $2, %xmm1, %ecx
-; X86-NEXT: vpextrd $2, %xmm0, %eax
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %ecx
-; X86-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2
-; X86-NEXT: vpextrd $3, %xmm1, %ecx
-; X86-NEXT: vpextrd $3, %xmm0, %eax
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %ecx
-; X86-NEXT: vpinsrd $3, %eax, %xmm2, %xmm0
-; X86-NEXT: vmovdqa %xmm0, (%esi)
+; X86-NEXT: vpmovzxdq {{.*#+}} xmm5 = xmm1[0],zero,xmm1[1],zero
+; X86-NEXT: vmovq {{.*#+}} xmm2 = [4.503599627370496E+15,0.0E+0]
+; X86-NEXT: vpsrlq $32, %xmm0, %xmm3
+; X86-NEXT: vpor %xmm2, %xmm3, %xmm3
+; X86-NEXT: vsubsd %xmm2, %xmm3, %xmm3
+; X86-NEXT: vpsrlq $32, %xmm1, %xmm6
+; X86-NEXT: vpor %xmm2, %xmm6, %xmm6
+; X86-NEXT: vsubsd %xmm2, %xmm6, %xmm6
+; X86-NEXT: vdivsd %xmm6, %xmm3, %xmm6
+; X86-NEXT: vcvttsd2si %xmm6, %edx
+; X86-NEXT: movl %edx, %esi
+; X86-NEXT: sarl $31, %esi
+; X86-NEXT: vmovsd {{.*#+}} xmm3 = [2.147483648E+9,0.0E+0]
+; X86-NEXT: vsubsd %xmm3, %xmm6, %xmm6
+; X86-NEXT: vcvttsd2si %xmm6, %ecx
+; X86-NEXT: andl %esi, %ecx
+; X86-NEXT: orl %edx, %ecx
+; X86-NEXT: vpor %xmm2, %xmm4, %xmm4
+; X86-NEXT: vsubsd %xmm2, %xmm4, %xmm4
+; X86-NEXT: vpor %xmm2, %xmm5, %xmm5
+; X86-NEXT: vsubsd %xmm2, %xmm5, %xmm5
+; X86-NEXT: vdivsd %xmm5, %xmm4, %xmm4
+; X86-NEXT: vcvttsd2si %xmm4, %edx
+; X86-NEXT: movl %edx, %esi
+; X86-NEXT: sarl $31, %esi
+; X86-NEXT: vsubsd %xmm3, %xmm4, %xmm4
+; X86-NEXT: vcvttsd2si %xmm4, %edi
+; X86-NEXT: andl %esi, %edi
+; X86-NEXT: orl %edx, %edi
+; X86-NEXT: vmovd %edi, %xmm4
+; X86-NEXT: vpinsrd $1, %ecx, %xmm4, %xmm4
+; X86-NEXT: vxorpd %xmm5, %xmm5, %xmm5
+; X86-NEXT: vpunpckhdq {{.*#+}} xmm6 = xmm0[2],xmm5[2],xmm0[3],xmm5[3]
+; X86-NEXT: vpor %xmm2, %xmm6, %xmm6
+; X86-NEXT: vsubsd %xmm2, %xmm6, %xmm6
+; X86-NEXT: vpunpckhdq {{.*#+}} xmm5 = xmm1[2],xmm5[2],xmm1[3],xmm5[3]
+; X86-NEXT: vpor %xmm2, %xmm5, %xmm5
+; X86-NEXT: vsubsd %xmm2, %xmm5, %xmm5
+; X86-NEXT: vdivsd %xmm5, %xmm6, %xmm5
+; X86-NEXT: vcvttsd2si %xmm5, %ecx
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: sarl $31, %edx
+; X86-NEXT: vsubsd %xmm3, %xmm5, %xmm5
+; X86-NEXT: vcvttsd2si %xmm5, %esi
+; X86-NEXT: andl %edx, %esi
+; X86-NEXT: orl %ecx, %esi
+; X86-NEXT: vpinsrd $2, %esi, %xmm4, %xmm4
+; X86-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; X86-NEXT: vpor %xmm2, %xmm0, %xmm0
+; X86-NEXT: vsubsd %xmm2, %xmm0, %xmm0
+; X86-NEXT: vpsrldq {{.*#+}} xmm1 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; X86-NEXT: vpor %xmm2, %xmm1, %xmm1
+; X86-NEXT: vsubsd %xmm2, %xmm1, %xmm1
+; X86-NEXT: vdivsd %xmm1, %xmm0, %xmm0
+; X86-NEXT: vcvttsd2si %xmm0, %ecx
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: sarl $31, %edx
+; X86-NEXT: vsubsd %xmm3, %xmm0, %xmm0
+; X86-NEXT: vcvttsd2si %xmm0, %esi
+; X86-NEXT: andl %edx, %esi
+; X86-NEXT: orl %ecx, %esi
+; X86-NEXT: vpinsrd $3, %esi, %xmm4, %xmm0
+; X86-NEXT: vmovdqa %xmm0, (%eax)
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
; X86-NEXT: retl
@@ -227,31 +269,47 @@ define void @vp_udiv_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) noun
; SSE-NEXT: pcmpeqd %xmm2, %xmm2
; SSE-NEXT: psubd %xmm2, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,3,3,3]
-; SSE-NEXT: movd %xmm2, %ecx
-; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,3,3,3]
; SSE-NEXT: movd %xmm2, %eax
-; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: divl %ecx
+; SSE-NEXT: xorps %xmm2, %xmm2
+; SSE-NEXT: cvtsi2sd %rax, %xmm2
+; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[3,3,3,3]
+; SSE-NEXT: movd %xmm3, %eax
+; SSE-NEXT: xorps %xmm3, %xmm3
+; SSE-NEXT: cvtsi2sd %rax, %xmm3
+; SSE-NEXT: divsd %xmm2, %xmm3
+; SSE-NEXT: cvttsd2si %xmm3, %rax
; SSE-NEXT: movd %eax, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
-; SSE-NEXT: movd %xmm3, %ecx
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,2,3]
; SSE-NEXT: movd %xmm3, %eax
-; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: divl %ecx
+; SSE-NEXT: xorps %xmm3, %xmm3
+; SSE-NEXT: cvtsi2sd %rax, %xmm3
+; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,2,3]
+; SSE-NEXT: movd %xmm4, %eax
+; SSE-NEXT: xorps %xmm4, %xmm4
+; SSE-NEXT: cvtsi2sd %rax, %xmm4
+; SSE-NEXT: divsd %xmm3, %xmm4
+; SSE-NEXT: cvttsd2si %xmm4, %rax
; SSE-NEXT: movd %eax, %xmm3
; SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
-; SSE-NEXT: movd %xmm1, %ecx
+; SSE-NEXT: movd %xmm1, %eax
+; SSE-NEXT: xorps %xmm2, %xmm2
+; SSE-NEXT: cvtsi2sd %rax, %xmm2
; SSE-NEXT: movd %xmm0, %eax
-; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: divl %ecx
+; SSE-NEXT: xorps %xmm4, %xmm4
+; SSE-NEXT: cvtsi2sd %rax, %xmm4
+; SSE-NEXT: divsd %xmm2, %xmm4
+; SSE-NEXT: cvttsd2si %xmm4, %rax
; SSE-NEXT: movd %eax, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
-; SSE-NEXT: movd %xmm1, %ecx
+; SSE-NEXT: movd %xmm1, %eax
+; SSE-NEXT: xorps %xmm1, %xmm1
+; SSE-NEXT: cvtsi2sd %rax, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE-NEXT: movd %xmm0, %eax
-; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: divl %ecx
+; SSE-NEXT: xorps %xmm0, %xmm0
+; SSE-NEXT: cvtsi2sd %rax, %xmm0
+; SSE-NEXT: divsd %xmm1, %xmm0
+; SSE-NEXT: cvttsd2si %xmm0, %rax
; SSE-NEXT: movd %eax, %xmm0
; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
@@ -266,26 +324,33 @@ define void @vp_udiv_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) noun
; AVX1-NEXT: vpmaxud %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vblendvps %xmm2, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vextractps $1, %xmm1, %ecx
-; AVX1-NEXT: vpextrd $1, %xmm0, %eax
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
-; AVX1-NEXT: movl %eax, %ecx
-; AVX1-NEXT: vmovd %xmm1, %esi
-; AVX1-NEXT: vmovd %xmm0, %eax
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %esi
-; AVX1-NEXT: vmovd %eax, %xmm2
-; AVX1-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2
-; AVX1-NEXT: vpextrd $2, %xmm1, %ecx
+; AVX1-NEXT: vextractps $1, %xmm0, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm2
+; AVX1-NEXT: vextractps $1, %xmm1, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm3
+; AVX1-NEXT: vdivsd %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vcvttsd2si %xmm2, %rax
+; AVX1-NEXT: vmovd %xmm0, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm2
+; AVX1-NEXT: vmovd %xmm1, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm3
+; AVX1-NEXT: vdivsd %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vcvttsd2si %xmm2, %rcx
+; AVX1-NEXT: vmovd %ecx, %xmm2
+; AVX1-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2
; AVX1-NEXT: vpextrd $2, %xmm0, %eax
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm3
+; AVX1-NEXT: vpextrd $2, %xmm1, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm4
+; AVX1-NEXT: vdivsd %xmm4, %xmm3, %xmm3
+; AVX1-NEXT: vcvttsd2si %xmm3, %rax
; AVX1-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2
-; AVX1-NEXT: vpextrd $3, %xmm1, %ecx
; AVX1-NEXT: vpextrd $3, %xmm0, %eax
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm0
+; AVX1-NEXT: vpextrd $3, %xmm1, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm1
+; AVX1-NEXT: vdivsd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vcvttsd2si %xmm0, %rax
; AVX1-NEXT: vpinsrd $3, %eax, %xmm2, %xmm0
; AVX1-NEXT: vmovdqa %xmm0, (%rdi)
; AVX1-NEXT: retq
@@ -451,34 +516,92 @@ define void @vp_urem_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) noun
; X86: # %bb.0:
; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi
-; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: vpmovzxdq {{.*#+}} xmm4 = xmm0[0],zero,xmm0[1],zero
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: vbroadcastss {{[0-9]+}}(%esp), %xmm2
; X86-NEXT: vpmovsxbd {{.*#+}} xmm3 = [0,1,2,3]
; X86-NEXT: vpmaxud %xmm3, %xmm2, %xmm2
; X86-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2
; X86-NEXT: vblendvps %xmm2, {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
-; X86-NEXT: vextractps $1, %xmm1, %ecx
-; X86-NEXT: vpextrd $1, %xmm0, %eax
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %ecx
-; X86-NEXT: movl %edx, %ecx
-; X86-NEXT: vmovd %xmm1, %edi
-; X86-NEXT: vmovd %xmm0, %eax
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %edi
-; X86-NEXT: vmovd %edx, %xmm2
-; X86-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2
+; X86-NEXT: vpmovzxdq {{.*#+}} xmm5 = xmm1[0],zero,xmm1[1],zero
+; X86-NEXT: vmovq {{.*#+}} xmm2 = [4.503599627370496E+15,0.0E+0]
+; X86-NEXT: vpsrlq $32, %xmm0, %xmm3
+; X86-NEXT: vpor %xmm2, %xmm3, %xmm3
+; X86-NEXT: vsubsd %xmm2, %xmm3, %xmm3
+; X86-NEXT: vpsrlq $32, %xmm1, %xmm6
+; X86-NEXT: vpor %xmm2, %xmm6, %xmm6
+; X86-NEXT: vsubsd %xmm2, %xmm6, %xmm6
+; X86-NEXT: vdivsd %xmm6, %xmm3, %xmm6
+; X86-NEXT: vcvttsd2si %xmm6, %ecx
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: sarl $31, %edx
+; X86-NEXT: vmovsd {{.*#+}} xmm3 = [2.147483648E+9,0.0E+0]
+; X86-NEXT: vsubsd %xmm3, %xmm6, %xmm6
+; X86-NEXT: vcvttsd2si %xmm6, %esi
+; X86-NEXT: andl %edx, %esi
+; X86-NEXT: orl %ecx, %esi
+; X86-NEXT: vpextrd $1, %xmm1, %edx
+; X86-NEXT: imull %esi, %edx
+; X86-NEXT: vpextrd $1, %xmm0, %ecx
+; X86-NEXT: subl %edx, %ecx
+; X86-NEXT: vpor %xmm2, %xmm4, %xmm4
+; X86-NEXT: vsubsd %xmm2, %xmm4, %xmm4
+; X86-NEXT: vpor %xmm2, %xmm5, %xmm5
+; X86-NEXT: vsubsd %xmm2, %xmm5, %xmm5
+; X86-NEXT: vdivsd %xmm5, %xmm4, %xmm4
+; X86-NEXT: vcvttsd2si %xmm4, %edx
+; X86-NEXT: movl %edx, %esi
+; X86-NEXT: sarl $31, %esi
+; X86-NEXT: vsubsd %xmm3, %xmm4, %xmm4
+; X86-NEXT: vcvttsd2si %xmm4, %edi
+; X86-NEXT: andl %esi, %edi
+; X86-NEXT: orl %edx, %edi
+; X86-NEXT: vmovd %xmm1, %edx
+; X86-NEXT: imull %edi, %edx
+; X86-NEXT: vmovd %xmm0, %esi
+; X86-NEXT: subl %edx, %esi
+; X86-NEXT: vmovd %esi, %xmm4
+; X86-NEXT: vpinsrd $1, %ecx, %xmm4, %xmm4
+; X86-NEXT: vxorpd %xmm5, %xmm5, %xmm5
+; X86-NEXT: vpunpckhdq {{.*#+}} xmm6 = xmm0[2],xmm5[2],xmm0[3],xmm5[3]
+; X86-NEXT: vpor %xmm2, %xmm6, %xmm6
+; X86-NEXT: vsubsd %xmm2, %xmm6, %xmm6
+; X86-NEXT: vpunpckhdq {{.*#+}} xmm5 = xmm1[2],xmm5[2],xmm1[3],xmm5[3]
+; X86-NEXT: vpor %xmm2, %xmm5, %xmm5
+; X86-NEXT: vsubsd %xmm2, %xmm5, %xmm5
+; X86-NEXT: vdivsd %xmm5, %xmm6, %xmm5
+; X86-NEXT: vcvttsd2si %xmm5, %ecx
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: sarl $31, %edx
+; X86-NEXT: vsubsd %xmm3, %xmm5, %xmm5
+; X86-NEXT: vcvttsd2si %xmm5, %esi
+; X86-NEXT: andl %edx, %esi
+; X86-NEXT: orl %ecx, %esi
; X86-NEXT: vpextrd $2, %xmm1, %ecx
-; X86-NEXT: vpextrd $2, %xmm0, %eax
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %ecx
-; X86-NEXT: vpinsrd $2, %edx, %xmm2, %xmm2
+; X86-NEXT: imull %esi, %ecx
+; X86-NEXT: vpextrd $2, %xmm0, %edx
+; X86-NEXT: subl %ecx, %edx
+; X86-NEXT: vpinsrd $2, %edx, %xmm4, %xmm4
+; X86-NEXT: vpsrldq {{.*#+}} xmm5 = xmm0[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; X86-NEXT: vpor %xmm2, %xmm5, %xmm5
+; X86-NEXT: vsubsd %xmm2, %xmm5, %xmm5
+; X86-NEXT: vpsrldq {{.*#+}} xmm6 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; X86-NEXT: vpor %xmm2, %xmm6, %xmm6
+; X86-NEXT: vsubsd %xmm2, %xmm6, %xmm2
+; X86-NEXT: vdivsd %xmm2, %xmm5, %xmm2
+; X86-NEXT: vcvttsd2si %xmm2, %ecx
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: sarl $31, %edx
+; X86-NEXT: vsubsd %xmm3, %xmm2, %xmm2
+; X86-NEXT: vcvttsd2si %xmm2, %esi
+; X86-NEXT: andl %edx, %esi
+; X86-NEXT: orl %ecx, %esi
; X86-NEXT: vpextrd $3, %xmm1, %ecx
-; X86-NEXT: vpextrd $3, %xmm0, %eax
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %ecx
-; X86-NEXT: vpinsrd $3, %edx, %xmm2, %xmm0
-; X86-NEXT: vmovdqa %xmm0, (%esi)
+; X86-NEXT: imull %esi, %ecx
+; X86-NEXT: vpextrd $3, %xmm0, %edx
+; X86-NEXT: subl %ecx, %edx
+; X86-NEXT: vpinsrd $3, %edx, %xmm4, %xmm0
+; X86-NEXT: vmovdqa %xmm0, (%eax)
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
; X86-NEXT: retl
@@ -494,35 +617,59 @@ define void @vp_urem_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) noun
; SSE-NEXT: pcmpeqd %xmm2, %xmm2
; SSE-NEXT: psubd %xmm2, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,3,3,3]
-; SSE-NEXT: movd %xmm2, %ecx
-; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,3,3,3]
; SSE-NEXT: movd %xmm2, %eax
-; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: divl %ecx
-; SSE-NEXT: movd %edx, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
+; SSE-NEXT: xorps %xmm2, %xmm2
+; SSE-NEXT: cvtsi2sd %rax, %xmm2
+; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[3,3,3,3]
; SSE-NEXT: movd %xmm3, %ecx
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,2,3]
-; SSE-NEXT: movd %xmm3, %eax
-; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: divl %ecx
-; SSE-NEXT: movd %edx, %xmm3
-; SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
-; SSE-NEXT: movd %xmm1, %ecx
-; SSE-NEXT: movd %xmm0, %eax
-; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: divl %ecx
-; SSE-NEXT: movd %edx, %xmm2
+; SSE-NEXT: xorps %xmm3, %xmm3
+; SSE-NEXT: cvtsi2sd %rcx, %xmm3
+; SSE-NEXT: divsd %xmm2, %xmm3
+; SSE-NEXT: cvttsd2si %xmm3, %rdx
+; SSE-NEXT: imull %eax, %edx
+; SSE-NEXT: subl %edx, %ecx
+; SSE-NEXT: movd %ecx, %xmm3
+; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,2,3]
+; SSE-NEXT: movd %xmm2, %eax
+; SSE-NEXT: xorps %xmm2, %xmm2
+; SSE-NEXT: cvtsi2sd %rax, %xmm2
+; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,2,3]
+; SSE-NEXT: movd %xmm4, %ecx
+; SSE-NEXT: xorps %xmm4, %xmm4
+; SSE-NEXT: cvtsi2sd %rcx, %xmm4
+; SSE-NEXT: divsd %xmm2, %xmm4
+; SSE-NEXT: cvttsd2si %xmm4, %rdx
+; SSE-NEXT: imull %eax, %edx
+; SSE-NEXT: subl %edx, %ecx
+; SSE-NEXT: movd %ecx, %xmm2
+; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
+; SSE-NEXT: movd %xmm1, %eax
+; SSE-NEXT: xorps %xmm3, %xmm3
+; SSE-NEXT: cvtsi2sd %rax, %xmm3
+; SSE-NEXT: movd %xmm0, %ecx
+; SSE-NEXT: xorps %xmm4, %xmm4
+; SSE-NEXT: cvtsi2sd %rcx, %xmm4
+; SSE-NEXT: divsd %xmm3, %xmm4
+; SSE-NEXT: cvttsd2si %xmm4, %rdx
+; SSE-NEXT: imull %eax, %edx
+; SSE-NEXT: subl %edx, %ecx
+; SSE-NEXT: movd %ecx, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
-; SSE-NEXT: movd %xmm1, %ecx
+; SSE-NEXT: movd %xmm1, %eax
+; SSE-NEXT: xorps %xmm1, %xmm1
+; SSE-NEXT: cvtsi2sd %rax, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; SSE-NEXT: movd %xmm0, %eax
-; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: divl %ecx
-; SSE-NEXT: movd %edx, %xmm0
-; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; SSE-NEXT: movdqa %xmm2, (%rdi)
+; SSE-NEXT: movd %xmm0, %ecx
+; SSE-NEXT: xorps %xmm0, %xmm0
+; SSE-NEXT: cvtsi2sd %rcx, %xmm0
+; SSE-NEXT: divsd %xmm1, %xmm0
+; SSE-NEXT: cvttsd2si %xmm0, %rdx
+; SSE-NEXT: imull %eax, %edx
+; SSE-NEXT: subl %edx, %ecx
+; SSE-NEXT: movd %ecx, %xmm0
+; SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1]
+; SSE-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm2[0]
+; SSE-NEXT: movdqa %xmm3, (%rdi)
; SSE-NEXT: retq
;
; AVX1-LABEL: vp_urem_v4i32:
@@ -533,27 +680,42 @@ define void @vp_urem_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) noun
; AVX1-NEXT: vpmaxud %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vblendvps %xmm2, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vextractps $1, %xmm0, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm2
; AVX1-NEXT: vextractps $1, %xmm1, %ecx
-; AVX1-NEXT: vpextrd $1, %xmm0, %eax
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
-; AVX1-NEXT: movl %edx, %ecx
-; AVX1-NEXT: vmovd %xmm1, %esi
-; AVX1-NEXT: vmovd %xmm0, %eax
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %esi
-; AVX1-NEXT: vmovd %edx, %xmm2
-; AVX1-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2
-; AVX1-NEXT: vpextrd $2, %xmm1, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm3
+; AVX1-NEXT: vdivsd %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vcvttsd2si %xmm2, %rdx
+; AVX1-NEXT: imull %ecx, %edx
+; AVX1-NEXT: subl %edx, %eax
+; AVX1-NEXT: vmovd %xmm0, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm2
+; AVX1-NEXT: vmovd %xmm1, %edx
+; AVX1-NEXT: vcvtsi2sd %rdx, %xmm15, %xmm3
+; AVX1-NEXT: vdivsd %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vcvttsd2si %xmm2, %rsi
+; AVX1-NEXT: imull %edx, %esi
+; AVX1-NEXT: subl %esi, %ecx
+; AVX1-NEXT: vmovd %ecx, %xmm2
+; AVX1-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2
; AVX1-NEXT: vpextrd $2, %xmm0, %eax
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
-; AVX1-NEXT: vpinsrd $2, %edx, %xmm2, %xmm2
-; AVX1-NEXT: vpextrd $3, %xmm1, %ecx
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm3
+; AVX1-NEXT: vpextrd $2, %xmm1, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm4
+; AVX1-NEXT: vdivsd %xmm4, %xmm3, %xmm3
+; AVX1-NEXT: vcvttsd2si %xmm3, %rdx
+; AVX1-NEXT: imull %ecx, %edx
+; AVX1-NEXT: subl %edx, %eax
+; AVX1-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2
; AVX1-NEXT: vpextrd $3, %xmm0, %eax
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
-; AVX1-NEXT: vpinsrd $3, %edx, %xmm2, %xmm0
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm0
+; AVX1-NEXT: vpextrd $3, %xmm1, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm1
+; AVX1-NEXT: vdivsd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vcvttsd2si %xmm0, %rdx
+; AVX1-NEXT: imull %ecx, %edx
+; AVX1-NEXT: subl %edx, %eax
+; AVX1-NEXT: vpinsrd $3, %eax, %xmm2, %xmm0
; AVX1-NEXT: vmovdqa %xmm0, (%rdi)
; AVX1-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/extractelement-load.ll b/llvm/test/CodeGen/X86/extractelement-load.ll
index ce68eebd5b752..1815e1ea1fd55 100644
--- a/llvm/test/CodeGen/X86/extractelement-load.ll
+++ b/llvm/test/CodeGen/X86/extractelement-load.ll
@@ -424,35 +424,55 @@ define i32 @main() nounwind {
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pushl %ebp
; X86-SSE2-NEXT: movl %esp, %ebp
-; X86-SSE2-NEXT: pushl %edi
; X86-SSE2-NEXT: pushl %esi
; X86-SSE2-NEXT: andl $-32, %esp
; X86-SSE2-NEXT: subl $64, %esp
-; X86-SSE2-NEXT: movaps n1+16, %xmm0
-; X86-SSE2-NEXT: movaps n1, %xmm1
-; X86-SSE2-NEXT: movl zero+4, %ecx
-; X86-SSE2-NEXT: movl zero+8, %eax
-; X86-SSE2-NEXT: movaps %xmm1, zero
-; X86-SSE2-NEXT: movaps %xmm0, zero+16
-; X86-SSE2-NEXT: movaps {{.*#+}} xmm0 = [2,2,2,2]
-; X86-SSE2-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
-; X86-SSE2-NEXT: movaps %xmm0, (%esp)
-; X86-SSE2-NEXT: movdqa (%esp), %xmm0
-; X86-SSE2-NEXT: movaps {{[0-9]+}}(%esp), %xmm1
-; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X86-SSE2-NEXT: movd %xmm1, %esi
-; X86-SSE2-NEXT: xorl %edx, %edx
-; X86-SSE2-NEXT: divl %esi
-; X86-SSE2-NEXT: movl %eax, %esi
-; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; X86-SSE2-NEXT: movd %xmm0, %edi
-; X86-SSE2-NEXT: movl %ecx, %eax
-; X86-SSE2-NEXT: xorl %edx, %edx
-; X86-SSE2-NEXT: divl %edi
-; X86-SSE2-NEXT: addl %esi, %eax
-; X86-SSE2-NEXT: leal -8(%ebp), %esp
+; X86-SSE2-NEXT: movapd zero, %xmm0
+; X86-SSE2-NEXT: movaps n1+16, %xmm1
+; X86-SSE2-NEXT: movaps n1, %xmm2
+; X86-SSE2-NEXT: movaps %xmm2, zero
+; X86-SSE2-NEXT: movaps %xmm1, zero+16
+; X86-SSE2-NEXT: movaps {{.*#+}} xmm1 = [2,2,2,2]
+; X86-SSE2-NEXT: movaps %xmm1, {{[0-9]+}}(%esp)
+; X86-SSE2-NEXT: movaps %xmm1, (%esp)
+; X86-SSE2-NEXT: movapd (%esp), %xmm1
+; X86-SSE2-NEXT: movaps {{[0-9]+}}(%esp), %xmm2
+; X86-SSE2-NEXT: xorpd %xmm3, %xmm3
+; X86-SSE2-NEXT: movapd %xmm0, %xmm4
+; X86-SSE2-NEXT: unpckhps {{.*#+}} xmm4 = xmm4[2],xmm3[2],xmm4[3],xmm3[3]
+; X86-SSE2-NEXT: movsd {{.*#+}} xmm2 = [4.503599627370496E+15,0.0E+0]
+; X86-SSE2-NEXT: orpd %xmm2, %xmm4
+; X86-SSE2-NEXT: subsd %xmm2, %xmm4
+; X86-SSE2-NEXT: movapd %xmm1, %xmm5
+; X86-SSE2-NEXT: unpckhps {{.*#+}} xmm5 = xmm5[2],xmm3[2],xmm5[3],xmm3[3]
+; X86-SSE2-NEXT: orpd %xmm2, %xmm5
+; X86-SSE2-NEXT: subsd %xmm2, %xmm5
+; X86-SSE2-NEXT: divsd %xmm5, %xmm4
+; X86-SSE2-NEXT: cvttsd2si %xmm4, %eax
+; X86-SSE2-NEXT: movl %eax, %edx
+; X86-SSE2-NEXT: sarl $31, %edx
+; X86-SSE2-NEXT: movsd {{.*#+}} xmm3 = [2.147483648E+9,0.0E+0]
+; X86-SSE2-NEXT: subsd %xmm3, %xmm4
+; X86-SSE2-NEXT: cvttsd2si %xmm4, %ecx
+; X86-SSE2-NEXT: andl %edx, %ecx
+; X86-SSE2-NEXT: orl %eax, %ecx
+; X86-SSE2-NEXT: psrlq $32, %xmm0
+; X86-SSE2-NEXT: por %xmm2, %xmm0
+; X86-SSE2-NEXT: subsd %xmm2, %xmm0
+; X86-SSE2-NEXT: psrlq $32, %xmm1
+; X86-SSE2-NEXT: por %xmm2, %xmm1
+; X86-SSE2-NEXT: subsd %xmm2, %xmm1
+; X86-SSE2-NEXT: divsd %xmm1, %xmm0
+; X86-SSE2-NEXT: cvttsd2si %xmm0, %edx
+; X86-SSE2-NEXT: movl %edx, %esi
+; X86-SSE2-NEXT: sarl $31, %esi
+; X86-SSE2-NEXT: subsd %xmm3, %xmm0
+; X86-SSE2-NEXT: cvttsd2si %xmm0, %eax
+; X86-SSE2-NEXT: andl %esi, %eax
+; X86-SSE2-NEXT: orl %edx, %eax
+; X86-SSE2-NEXT: addl %ecx, %eax
+; X86-SSE2-NEXT: leal -4(%ebp), %esp
; X86-SSE2-NEXT: popl %esi
-; X86-SSE2-NEXT: popl %edi
; X86-SSE2-NEXT: popl %ebp
; X86-SSE2-NEXT: retl
;
@@ -465,8 +485,8 @@ define i32 @main() nounwind {
; X64-SSSE3-NEXT: movq n1 at GOTPCREL(%rip), %rax
; X64-SSSE3-NEXT: movaps (%rax), %xmm0
; X64-SSSE3-NEXT: movaps 16(%rax), %xmm1
-; X64-SSSE3-NEXT: movl zero+4(%rip), %ecx
-; X64-SSSE3-NEXT: movl zero+8(%rip), %eax
+; X64-SSSE3-NEXT: movl zero+4(%rip), %eax
+; X64-SSSE3-NEXT: movl zero+8(%rip), %ecx
; X64-SSSE3-NEXT: movaps %xmm0, zero(%rip)
; X64-SSSE3-NEXT: movaps %xmm1, zero+16(%rip)
; X64-SSSE3-NEXT: movaps {{.*#+}} xmm0 = [2,2,2,2]
@@ -474,17 +494,24 @@ define i32 @main() nounwind {
; X64-SSSE3-NEXT: movaps %xmm0, (%rsp)
; X64-SSSE3-NEXT: movdqa (%rsp), %xmm0
; X64-SSSE3-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1
-; X64-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X64-SSSE3-NEXT: movd %xmm1, %esi
-; X64-SSSE3-NEXT: xorl %edx, %edx
-; X64-SSSE3-NEXT: divl %esi
-; X64-SSSE3-NEXT: movl %eax, %esi
+; X64-SSSE3-NEXT: xorps %xmm1, %xmm1
+; X64-SSSE3-NEXT: cvtsi2sd %rcx, %xmm1
+; X64-SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,2,3]
+; X64-SSSE3-NEXT: movd %xmm2, %ecx
+; X64-SSSE3-NEXT: xorps %xmm2, %xmm2
+; X64-SSSE3-NEXT: cvtsi2sd %rcx, %xmm2
+; X64-SSSE3-NEXT: divsd %xmm2, %xmm1
+; X64-SSSE3-NEXT: cvttsd2si %xmm1, %rcx
+; X64-SSSE3-NEXT: xorps %xmm1, %xmm1
+; X64-SSSE3-NEXT: cvtsi2sd %rax, %xmm1
; X64-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; X64-SSSE3-NEXT: movd %xmm0, %edi
-; X64-SSSE3-NEXT: movl %ecx, %eax
-; X64-SSSE3-NEXT: xorl %edx, %edx
-; X64-SSSE3-NEXT: divl %edi
-; X64-SSSE3-NEXT: addl %esi, %eax
+; X64-SSSE3-NEXT: movd %xmm0, %eax
+; X64-SSSE3-NEXT: xorps %xmm0, %xmm0
+; X64-SSSE3-NEXT: cvtsi2sd %rax, %xmm0
+; X64-SSSE3-NEXT: divsd %xmm0, %xmm1
+; X64-SSSE3-NEXT: cvttsd2si %xmm1, %rax
+; X64-SSSE3-NEXT: addl %ecx, %eax
+; X64-SSSE3-NEXT: # kill: def $eax killed $eax killed $rax
; X64-SSSE3-NEXT: movq %rbp, %rsp
; X64-SSSE3-NEXT: popq %rbp
; X64-SSSE3-NEXT: retq
@@ -497,21 +524,24 @@ define i32 @main() nounwind {
; X64-AVX-NEXT: subq $64, %rsp
; X64-AVX-NEXT: movq n1 at GOTPCREL(%rip), %rax
; X64-AVX-NEXT: vmovaps (%rax), %ymm0
-; X64-AVX-NEXT: movl zero+4(%rip), %ecx
-; X64-AVX-NEXT: movl zero+8(%rip), %eax
+; X64-AVX-NEXT: movl zero+4(%rip), %eax
+; X64-AVX-NEXT: movl zero+8(%rip), %ecx
; X64-AVX-NEXT: vmovaps %ymm0, zero(%rip)
; X64-AVX-NEXT: vbroadcastss {{.*#+}} ymm0 = [2,2,2,2,2,2,2,2]
; X64-AVX-NEXT: vmovaps %ymm0, (%rsp)
-; X64-AVX-NEXT: vmovaps (%rsp), %ymm0
-; X64-AVX-NEXT: vextractps $2, %xmm0, %esi
-; X64-AVX-NEXT: xorl %edx, %edx
-; X64-AVX-NEXT: divl %esi
-; X64-AVX-NEXT: movl %eax, %esi
-; X64-AVX-NEXT: vextractps $1, %xmm0, %edi
-; X64-AVX-NEXT: movl %ecx, %eax
-; X64-AVX-NEXT: xorl %edx, %edx
-; X64-AVX-NEXT: divl %edi
-; X64-AVX-NEXT: addl %esi, %eax
+; X64-AVX-NEXT: vmovapd (%rsp), %ymm0
+; X64-AVX-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm1
+; X64-AVX-NEXT: vextractps $2, %xmm0, %ecx
+; X64-AVX-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm2
+; X64-AVX-NEXT: vdivsd %xmm2, %xmm1, %xmm1
+; X64-AVX-NEXT: vcvttsd2si %xmm1, %rcx
+; X64-AVX-NEXT: vcvtsi2sd %rax, %xmm15, %xmm1
+; X64-AVX-NEXT: vextractps $1, %xmm0, %eax
+; X64-AVX-NEXT: vcvtsi2sd %rax, %xmm15, %xmm0
+; X64-AVX-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; X64-AVX-NEXT: vcvttsd2si %xmm0, %rax
+; X64-AVX-NEXT: addl %ecx, %eax
+; X64-AVX-NEXT: # kill: def $eax killed $eax killed $rax
; X64-AVX-NEXT: movq %rbp, %rsp
; X64-AVX-NEXT: popq %rbp
; X64-AVX-NEXT: vzeroupper
diff --git a/llvm/test/CodeGen/X86/fold-loop-of-urem.ll b/llvm/test/CodeGen/X86/fold-loop-of-urem.ll
index f3b9af4eb08e8..0c24eced35655 100644
--- a/llvm/test/CodeGen/X86/fold-loop-of-urem.ll
+++ b/llvm/test/CodeGen/X86/fold-loop-of-urem.ll
@@ -83,10 +83,15 @@ define void @simple_urem_to_sel_fail_not_in_loop(i32 %N, i32 %rem_amt) nounwind
; CHECK-NEXT: .LBB1_1:
; CHECK-NEXT: xorl %ebp, %ebp
; CHECK-NEXT: .LBB1_2: # %for.cond.cleanup
+; CHECK-NEXT: movl %ebx, %eax
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
; CHECK-NEXT: movl %ebp, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ebx
-; CHECK-NEXT: movl %edx, %edi
+; CHECK-NEXT: cvtsi2sd %rax, %xmm1
+; CHECK-NEXT: divsd %xmm0, %xmm1
+; CHECK-NEXT: cvttsd2si %xmm1, %rax
+; CHECK-NEXT: imull %ebx, %eax
+; CHECK-NEXT: subl %eax, %ebp
+; CHECK-NEXT: movl %ebp, %edi
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %r14
; CHECK-NEXT: popq %rbp
@@ -206,13 +211,13 @@ define void @simple_urem_to_sel_inner_loop_fail_not_invariant(i32 %N, i32 %M) no
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: movl %esi, %ebx
; CHECK-NEXT: movl %edi, %ebp
-; CHECK-NEXT: xorl %r14d, %r14d
+; CHECK-NEXT: xorl %r15d, %r15d
; CHECK-NEXT: jmp .LBB3_2
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB3_5: # %for.inner.cond.cleanup
; CHECK-NEXT: # in Loop: Header=BB3_2 Depth=1
-; CHECK-NEXT: incl %r14d
-; CHECK-NEXT: cmpl %ebp, %r14d
+; CHECK-NEXT: incl %r15d
+; CHECK-NEXT: cmpl %ebp, %r15d
; CHECK-NEXT: je .LBB3_6
; CHECK-NEXT: .LBB3_2: # %for.body
; CHECK-NEXT: # =>This Loop Header: Depth=1
@@ -222,16 +227,23 @@ define void @simple_urem_to_sel_inner_loop_fail_not_invariant(i32 %N, i32 %M) no
; CHECK-NEXT: je .LBB3_5
; CHECK-NEXT: # %bb.3: # %for.inner.body.preheader
; CHECK-NEXT: # in Loop: Header=BB3_2 Depth=1
-; CHECK-NEXT: movl %eax, %r15d
+; CHECK-NEXT: movl %eax, %ecx
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2sd %rcx, %xmm0
+; CHECK-NEXT: movl %r15d, %ecx
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: cvtsi2sd %rcx, %xmm1
+; CHECK-NEXT: divsd %xmm0, %xmm1
+; CHECK-NEXT: cvttsd2si %xmm1, %rcx
+; CHECK-NEXT: imull %eax, %ecx
+; CHECK-NEXT: movl %r15d, %r14d
+; CHECK-NEXT: subl %ecx, %r14d
; CHECK-NEXT: movl %ebx, %r12d
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB3_4: # %for.inner.body
; CHECK-NEXT: # Parent Loop BB3_2 Depth=1
; CHECK-NEXT: # => This Inner Loop Header: Depth=2
-; CHECK-NEXT: movl %r14d, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %r15d
-; CHECK-NEXT: movl %edx, %edi
+; CHECK-NEXT: movl %r14d, %edi
; CHECK-NEXT: callq use.i32 at PLT
; CHECK-NEXT: decl %r12d
; CHECK-NEXT: jne .LBB3_4
@@ -361,15 +373,23 @@ define void @simple_urem_fail_bad_incr3(i32 %N, i32 %rem_amt) nounwind {
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: pushq %r14
; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $16, %rsp
; CHECK-NEXT: movl %esi, %ebx
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: jmp .LBB5_2
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB5_6: # %for.body1
; CHECK-NEXT: # in Loop: Header=BB5_2 Depth=1
; CHECK-NEXT: movl %ebp, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ebx
-; CHECK-NEXT: movl %edx, %edi
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: divsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Folded Reload
+; CHECK-NEXT: cvttsd2si %xmm0, %rax
+; CHECK-NEXT: imull %ebx, %eax
+; CHECK-NEXT: subl %eax, %ebp
+; CHECK-NEXT: movl %ebp, %edi
; CHECK-NEXT: callq use.i32 at PLT
; CHECK-NEXT: .LBB5_7: # %for.body.tail
; CHECK-NEXT: # in Loop: Header=BB5_2 Depth=1
@@ -401,6 +421,7 @@ define void @simple_urem_fail_bad_incr3(i32 %N, i32 %rem_amt) nounwind {
; CHECK-NEXT: jne .LBB5_6
; CHECK-NEXT: jmp .LBB5_7
; CHECK-NEXT: .LBB5_8:
+; CHECK-NEXT: addq $16, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %r14
; CHECK-NEXT: popq %rbp
@@ -492,17 +513,25 @@ define void @simple_urem_fail_bad_incr(i32 %N, i32 %rem_amt) nounwind {
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: pushq %r14
; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $16, %rsp
; CHECK-NEXT: movl %esi, %ebx
; CHECK-NEXT: movl %edi, %ebp
; CHECK-NEXT: xorl %r14d, %r14d
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: jmp .LBB7_2
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB7_4: # %for.body.tail
; CHECK-NEXT: # in Loop: Header=BB7_2 Depth=1
; CHECK-NEXT: movl %r14d, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ebx
-; CHECK-NEXT: movl %edx, %edi
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: divsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Folded Reload
+; CHECK-NEXT: cvttsd2si %xmm0, %rax
+; CHECK-NEXT: imull %ebx, %eax
+; CHECK-NEXT: movl %r14d, %edi
+; CHECK-NEXT: subl %eax, %edi
; CHECK-NEXT: callq use.i32 at PLT
; CHECK-NEXT: incl %r14d
; CHECK-NEXT: cmpl %ebp, %r14d
@@ -518,6 +547,7 @@ define void @simple_urem_fail_bad_incr(i32 %N, i32 %rem_amt) nounwind {
; CHECK-NEXT: movl %eax, %r14d
; CHECK-NEXT: jmp .LBB7_4
; CHECK-NEXT: .LBB7_5:
+; CHECK-NEXT: addq $16, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %r14
; CHECK-NEXT: popq %rbp
@@ -615,21 +645,28 @@ define void @simple_urem_fail_srem(i32 %N, i32 %rem_amt) nounwind {
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: pushq %r14
; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $16, %rsp
; CHECK-NEXT: movl %esi, %ebx
; CHECK-NEXT: movl %edi, %ebp
; CHECK-NEXT: xorl %r14d, %r14d
+; CHECK-NEXT: cvtsi2sd %esi, %xmm0
+; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB9_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: movl %r14d, %eax
-; CHECK-NEXT: cltd
-; CHECK-NEXT: idivl %ebx
-; CHECK-NEXT: movl %edx, %edi
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2sd %r14d, %xmm0
+; CHECK-NEXT: divsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Folded Reload
+; CHECK-NEXT: cvttsd2si %xmm0, %eax
+; CHECK-NEXT: imull %ebx, %eax
+; CHECK-NEXT: movl %r14d, %edi
+; CHECK-NEXT: subl %eax, %edi
; CHECK-NEXT: callq use.i32 at PLT
; CHECK-NEXT: incl %r14d
; CHECK-NEXT: cmpl %r14d, %ebp
; CHECK-NEXT: jne .LBB9_2
; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: addq $16, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %r14
; CHECK-NEXT: popq %rbp
@@ -660,21 +697,30 @@ define void @simple_urem_fail_missing_nuw(i32 %N, i32 %rem_amt) nounwind {
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: pushq %r14
; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $16, %rsp
; CHECK-NEXT: movl %esi, %ebx
; CHECK-NEXT: movl %edi, %ebp
; CHECK-NEXT: xorl %r14d, %r14d
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB10_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl %r14d, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ebx
-; CHECK-NEXT: movl %edx, %edi
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: divsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Folded Reload
+; CHECK-NEXT: cvttsd2si %xmm0, %rax
+; CHECK-NEXT: imull %ebx, %eax
+; CHECK-NEXT: movl %r14d, %edi
+; CHECK-NEXT: subl %eax, %edi
; CHECK-NEXT: callq use.i32 at PLT
; CHECK-NEXT: incl %r14d
; CHECK-NEXT: cmpl %r14d, %ebp
; CHECK-NEXT: jne .LBB10_2
; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: addq $16, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %r14
; CHECK-NEXT: popq %rbp
@@ -705,21 +751,30 @@ define void @simple_urem_fail_bad_incr2(i32 %N, i32 %rem_amt) nounwind {
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: pushq %r14
; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $16, %rsp
; CHECK-NEXT: movl %esi, %ebx
; CHECK-NEXT: movl %edi, %ebp
; CHECK-NEXT: xorl %r14d, %r14d
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB11_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl %r14d, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ebx
-; CHECK-NEXT: movl %edx, %edi
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: divsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Folded Reload
+; CHECK-NEXT: cvttsd2si %xmm0, %rax
+; CHECK-NEXT: imull %ebx, %eax
+; CHECK-NEXT: movl %r14d, %edi
+; CHECK-NEXT: subl %eax, %edi
; CHECK-NEXT: callq use.i32 at PLT
; CHECK-NEXT: addl $2, %r14d
; CHECK-NEXT: cmpl %r14d, %ebp
; CHECK-NEXT: jne .LBB11_2
; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: addq $16, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %r14
; CHECK-NEXT: popq %rbp
@@ -750,21 +805,30 @@ define void @simple_urem_non_zero_entry4(i32 %N, i32 %rem_amt) nounwind {
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: pushq %r14
; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $16, %rsp
; CHECK-NEXT: movl %esi, %ebx
; CHECK-NEXT: movl %edi, %ebp
; CHECK-NEXT: movl $4, %r14d
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB12_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl %r14d, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ebx
-; CHECK-NEXT: movl %edx, %edi
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: divsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Folded Reload
+; CHECK-NEXT: cvttsd2si %xmm0, %rax
+; CHECK-NEXT: imull %ebx, %eax
+; CHECK-NEXT: movl %r14d, %edi
+; CHECK-NEXT: subl %eax, %edi
; CHECK-NEXT: callq use.i32 at PLT
; CHECK-NEXT: incl %r14d
; CHECK-NEXT: cmpl %r14d, %ebp
; CHECK-NEXT: jne .LBB12_2
; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: addq $16, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %r14
; CHECK-NEXT: popq %rbp
@@ -840,6 +904,7 @@ define void @simple_urem_fail_no_preheader_non_canonical(i32 %N, i32 %rem_amt) n
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: pushq %r14
; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $16, %rsp
; CHECK-NEXT: movl %esi, %ebx
; CHECK-NEXT: movl %edi, %ebp
; CHECK-NEXT: testl %edi, %edi
@@ -849,18 +914,27 @@ define void @simple_urem_fail_no_preheader_non_canonical(i32 %N, i32 %rem_amt) n
; CHECK-NEXT: jmp .LBB14_3
; CHECK-NEXT: .LBB14_1:
; CHECK-NEXT: xorl %r14d, %r14d
+; CHECK-NEXT: .LBB14_3: # %for.body.preheader
+; CHECK-NEXT: movl %ebx, %eax
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: .LBB14_3: # %for.body
+; CHECK-NEXT: .LBB14_4: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl %r14d, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ebx
-; CHECK-NEXT: movl %edx, %edi
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: divsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Folded Reload
+; CHECK-NEXT: cvttsd2si %xmm0, %rax
+; CHECK-NEXT: imull %ebx, %eax
+; CHECK-NEXT: movl %r14d, %edi
+; CHECK-NEXT: subl %eax, %edi
; CHECK-NEXT: callq use.i32 at PLT
; CHECK-NEXT: incl %r14d
; CHECK-NEXT: cmpl %r14d, %ebp
-; CHECK-NEXT: jne .LBB14_3
-; CHECK-NEXT: # %bb.4: # %for.cond.cleanup
+; CHECK-NEXT: jne .LBB14_4
+; CHECK-NEXT: # %bb.5: # %for.cond.cleanup
+; CHECK-NEXT: addq $16, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %r14
; CHECK-NEXT: popq %rbp
@@ -985,10 +1059,17 @@ define void @simple_urem_fail_bad_loop(i32 %N, i32 %rem_amt) nounwind {
; CHECK-NEXT: xorl $1, %edi
; CHECK-NEXT: callq use.i32 at PLT
; CHECK-NEXT: .LBB16_4: # %halfway
+; CHECK-NEXT: movl %ebx, %eax
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
; CHECK-NEXT: movl %r14d, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ebx
-; CHECK-NEXT: movl %edx, %edi
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: cvtsi2sd %rax, %xmm1
+; CHECK-NEXT: divsd %xmm0, %xmm1
+; CHECK-NEXT: cvttsd2si %xmm1, %rax
+; CHECK-NEXT: imull %ebx, %eax
+; CHECK-NEXT: movl %r14d, %edi
+; CHECK-NEXT: subl %eax, %edi
; CHECK-NEXT: callq use.i32 at PLT
; CHECK-NEXT: incl %r14d
; CHECK-NEXT: cmpl %ebp, %r14d
@@ -1029,17 +1110,25 @@ define void @simple_urem_fail_intermediate_inc(i32 %N, i32 %rem_amt) nounwind {
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: pushq %r14
; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $16, %rsp
; CHECK-NEXT: movl %esi, %ebx
; CHECK-NEXT: movl %edi, %r14d
; CHECK-NEXT: negl %r14d
; CHECK-NEXT: movl $1, %ebp
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB17_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl %ebp, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ebx
-; CHECK-NEXT: movl %edx, %edi
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: divsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Folded Reload
+; CHECK-NEXT: cvttsd2si %xmm0, %rax
+; CHECK-NEXT: imull %ebx, %eax
+; CHECK-NEXT: movl %ebp, %edi
+; CHECK-NEXT: subl %eax, %edi
; CHECK-NEXT: callq use.i32 at PLT
; CHECK-NEXT: movl %ebp, %eax
; CHECK-NEXT: incl %ebp
@@ -1047,6 +1136,7 @@ define void @simple_urem_fail_intermediate_inc(i32 %N, i32 %rem_amt) nounwind {
; CHECK-NEXT: cmpl $1, %eax
; CHECK-NEXT: jne .LBB17_2
; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: addq $16, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %r14
; CHECK-NEXT: popq %rbp
@@ -1098,21 +1188,30 @@ define void @simple_urem_to_sel_non_zero_start_fail(i32 %N, i32 %rem_amt) nounwi
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: pushq %r14
; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $16, %rsp
; CHECK-NEXT: movl %esi, %ebx
; CHECK-NEXT: movl %edi, %ebp
; CHECK-NEXT: movl $2, %r14d
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB19_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl %r14d, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ebx
-; CHECK-NEXT: movl %edx, %edi
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: divsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Folded Reload
+; CHECK-NEXT: cvttsd2si %xmm0, %rax
+; CHECK-NEXT: imull %ebx, %eax
+; CHECK-NEXT: movl %r14d, %edi
+; CHECK-NEXT: subl %eax, %edi
; CHECK-NEXT: callq use.i32 at PLT
; CHECK-NEXT: incl %r14d
; CHECK-NEXT: cmpl %r14d, %ebp
; CHECK-NEXT: jne .LBB19_2
; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: addq $16, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %r14
; CHECK-NEXT: popq %rbp
@@ -1196,18 +1295,26 @@ define void @simple_urem_to_sel_non_zero_start_through_add(i32 %N, i32 %rem_amt_
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: pushq %r14
; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $16, %rsp
; CHECK-NEXT: movl %esi, %ebx
; CHECK-NEXT: movl %edi, %r14d
; CHECK-NEXT: orl $16, %ebx
; CHECK-NEXT: negl %r14d
; CHECK-NEXT: movl $7, %ebp
+; CHECK-NEXT: movl %ebx, %eax
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB21_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl %ebp, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ebx
-; CHECK-NEXT: movl %edx, %edi
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: divsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Folded Reload
+; CHECK-NEXT: cvttsd2si %xmm0, %rax
+; CHECK-NEXT: imull %ebx, %eax
+; CHECK-NEXT: movl %ebp, %edi
+; CHECK-NEXT: subl %eax, %edi
; CHECK-NEXT: callq use.i32 at PLT
; CHECK-NEXT: movl %ebp, %eax
; CHECK-NEXT: incl %ebp
@@ -1215,6 +1322,7 @@ define void @simple_urem_to_sel_non_zero_start_through_add(i32 %N, i32 %rem_amt_
; CHECK-NEXT: cmpl $5, %eax
; CHECK-NEXT: jne .LBB21_2
; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: addq $16, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %r14
; CHECK-NEXT: popq %rbp
@@ -1247,18 +1355,26 @@ define void @simple_urem_to_sel_non_zero_start_through_add_fail_missing_nuw(i32
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: pushq %r14
; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $16, %rsp
; CHECK-NEXT: movl %esi, %ebx
; CHECK-NEXT: movl %edi, %r14d
; CHECK-NEXT: orl $16, %ebx
; CHECK-NEXT: negl %r14d
; CHECK-NEXT: movl $7, %ebp
+; CHECK-NEXT: movl %ebx, %eax
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB22_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl %ebp, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ebx
-; CHECK-NEXT: movl %edx, %edi
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: divsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Folded Reload
+; CHECK-NEXT: cvttsd2si %xmm0, %rax
+; CHECK-NEXT: imull %ebx, %eax
+; CHECK-NEXT: movl %ebp, %edi
+; CHECK-NEXT: subl %eax, %edi
; CHECK-NEXT: callq use.i32 at PLT
; CHECK-NEXT: movl %ebp, %eax
; CHECK-NEXT: incl %ebp
@@ -1266,6 +1382,7 @@ define void @simple_urem_to_sel_non_zero_start_through_add_fail_missing_nuw(i32
; CHECK-NEXT: cmpl $5, %eax
; CHECK-NEXT: jne .LBB22_2
; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: addq $16, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %r14
; CHECK-NEXT: popq %rbp
@@ -1298,17 +1415,25 @@ define void @simple_urem_to_sel_non_zero_start_through_add_fail_no_simplify_rem(
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: pushq %r14
; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $16, %rsp
; CHECK-NEXT: movl %esi, %ebx
; CHECK-NEXT: movl %edi, %r14d
; CHECK-NEXT: negl %r14d
; CHECK-NEXT: movl $7, %ebp
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB23_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl %ebp, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ebx
-; CHECK-NEXT: movl %edx, %edi
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: divsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Folded Reload
+; CHECK-NEXT: cvttsd2si %xmm0, %rax
+; CHECK-NEXT: imull %ebx, %eax
+; CHECK-NEXT: movl %ebp, %edi
+; CHECK-NEXT: subl %eax, %edi
; CHECK-NEXT: callq use.i32 at PLT
; CHECK-NEXT: movl %ebp, %eax
; CHECK-NEXT: incl %ebp
@@ -1316,6 +1441,7 @@ define void @simple_urem_to_sel_non_zero_start_through_add_fail_no_simplify_rem(
; CHECK-NEXT: cmpl $5, %eax
; CHECK-NEXT: jne .LBB23_2
; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: addq $16, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %r14
; CHECK-NEXT: popq %rbp
@@ -1398,18 +1524,26 @@ define void @simple_urem_to_sel_non_zero_start_through_sub_no_simplfy(i32 %N, i3
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: pushq %r14
; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $16, %rsp
; CHECK-NEXT: movl %edx, %ebx
; CHECK-NEXT: movl %esi, %ebp
; CHECK-NEXT: movl %edi, %r14d
; CHECK-NEXT: negl %r14d
; CHECK-NEXT: addl $-2, %ebx
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB25_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl %ebx, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ebp
-; CHECK-NEXT: movl %edx, %edi
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: divsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Folded Reload
+; CHECK-NEXT: cvttsd2si %xmm0, %rax
+; CHECK-NEXT: imull %ebp, %eax
+; CHECK-NEXT: movl %ebx, %edi
+; CHECK-NEXT: subl %eax, %edi
; CHECK-NEXT: callq use.i32 at PLT
; CHECK-NEXT: movl %ebx, %eax
; CHECK-NEXT: incl %ebx
@@ -1417,6 +1551,7 @@ define void @simple_urem_to_sel_non_zero_start_through_sub_no_simplfy(i32 %N, i3
; CHECK-NEXT: cmpl $-2, %eax
; CHECK-NEXT: jne .LBB25_2
; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: addq $16, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %r14
; CHECK-NEXT: popq %rbp
diff --git a/llvm/test/CodeGen/X86/hoist-invariant-load.ll b/llvm/test/CodeGen/X86/hoist-invariant-load.ll
index 68e10c0c98871..505051ae86ea8 100644
--- a/llvm/test/CodeGen/X86/hoist-invariant-load.ll
+++ b/llvm/test/CodeGen/X86/hoist-invariant-load.ll
@@ -263,23 +263,25 @@ exit:
define void @test_div_def(ptr dereferenceable(8) align(8) %x1,
; CHECK-LABEL: test_div_def:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: movq %rdx, %r8
-; CHECK-NEXT: xorl %r9d, %r9d
-; CHECK-NEXT: movl (%rdi), %edi
+; CHECK-NEXT: movl (%rdi), %eax
; CHECK-NEXT: movl (%rsi), %esi
+; CHECK-NEXT: vcvtsi2sd %rsi, %xmm15, %xmm0
+; CHECK-NEXT: vcvtsi2sd %rax, %xmm15, %xmm1
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vcvttsd2si %xmm0, %rsi
+; CHECK-NEXT: addl %esi, (%rdx,%rax,4)
; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: LBB5_2: ## %for.body
+; CHECK-NEXT: LBB5_1: ## %for.check
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: movl %edi, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %esi
-; CHECK-NEXT: addl %eax, (%r8,%r9,4)
-; CHECK-NEXT: ## %bb.1: ## %for.check
-; CHECK-NEXT: ## in Loop: Header=BB5_2 Depth=1
-; CHECK-NEXT: incq %r9
-; CHECK-NEXT: cmpl %ecx, %r9d
-; CHECK-NEXT: jl LBB5_2
-; CHECK-NEXT: ## %bb.3: ## %exit
+; CHECK-NEXT: incq %rax
+; CHECK-NEXT: cmpl %ecx, %eax
+; CHECK-NEXT: jge LBB5_3
+; CHECK-NEXT: ## %bb.2: ## %for.body
+; CHECK-NEXT: ## in Loop: Header=BB5_1 Depth=1
+; CHECK-NEXT: addl %esi, (%rdx,%rax,4)
+; CHECK-NEXT: jmp LBB5_1
+; CHECK-NEXT: LBB5_3: ## %exit
; CHECK-NEXT: retq
ptr dereferenceable(8) align(8) %x2,
ptr %y, i32 %count) nounwind nofree nosync {
diff --git a/llvm/test/CodeGen/X86/implicit-null-check.ll b/llvm/test/CodeGen/X86/implicit-null-check.ll
index de63c9ae209df..616286440af3e 100644
--- a/llvm/test/CodeGen/X86/implicit-null-check.ll
+++ b/llvm/test/CodeGen/X86/implicit-null-check.ll
@@ -261,8 +261,12 @@ define i32 @imp_null_check_udiv_result(ptr %x, i32 %p) {
; CHECK-NEXT: Ltmp8:
; CHECK-NEXT: movl (%rdi), %eax ## on-fault: LBB10_1
; CHECK-NEXT: ## %bb.2: ## %not_null
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %esi
+; CHECK-NEXT: movl %esi, %ecx
+; CHECK-NEXT: cvtsi2sd %rcx, %xmm0
+; CHECK-NEXT: cvtsi2sd %rax, %xmm1
+; CHECK-NEXT: divsd %xmm0, %xmm1
+; CHECK-NEXT: cvttsd2si %xmm1, %rax
+; CHECK-NEXT: ## kill: def $eax killed $eax killed $rax
; CHECK-NEXT: retq
; CHECK-NEXT: LBB10_1: ## %is_null
; CHECK-NEXT: movl $42, %eax
diff --git a/llvm/test/CodeGen/X86/insertelement-var-index.ll b/llvm/test/CodeGen/X86/insertelement-var-index.ll
index a4af339b5ebb2..02ec82dbdce1b 100644
--- a/llvm/test/CodeGen/X86/insertelement-var-index.ll
+++ b/llvm/test/CodeGen/X86/insertelement-var-index.ll
@@ -2264,7 +2264,7 @@ define <4 x double> @load_f64_v4f64(<4 x double> %v, ptr %p, i32 %y) nounwind {
define i32 @PR44139(ptr %p) {
; SSE-LABEL: PR44139:
; SSE: # %bb.0:
-; SSE-NEXT: movl (%rdi), %eax
+; SSE-NEXT: movq (%rdi), %rax
; SSE-NEXT: pshufd {{.*#+}} xmm0 = mem[0,1,0,1]
; SSE-NEXT: movdqa %xmm0, 96(%rdi)
; SSE-NEXT: movdqa %xmm0, 112(%rdi)
@@ -2279,9 +2279,13 @@ define i32 @PR44139(ptr %p) {
; SSE-NEXT: cmovnsl %eax, %ecx
; SSE-NEXT: andl $-2147483648, %ecx # imm = 0x80000000
; SSE-NEXT: addl %eax, %ecx
+; SSE-NEXT: xorps %xmm0, %xmm0
+; SSE-NEXT: cvtsi2sd %rcx, %xmm0
+; SSE-NEXT: movl %eax, %eax
+; SSE-NEXT: cvtsi2sd %rax, %xmm1
+; SSE-NEXT: divsd %xmm0, %xmm1
+; SSE-NEXT: cvttsd2si %xmm1, %rax
; SSE-NEXT: # kill: def $eax killed $eax killed $rax
-; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: divl %ecx
; SSE-NEXT: retq
;
; AVX1-LABEL: PR44139:
@@ -2299,9 +2303,12 @@ define i32 @PR44139(ptr %p) {
; AVX1-NEXT: cmovnsl %eax, %ecx
; AVX1-NEXT: andl $-2147483648, %ecx # imm = 0x80000000
; AVX1-NEXT: addl %eax, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm0
+; AVX1-NEXT: movl %eax, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm1
+; AVX1-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vcvttsd2si %xmm0, %rax
; AVX1-NEXT: # kill: def $eax killed $eax killed $rax
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
@@ -2320,9 +2327,12 @@ define i32 @PR44139(ptr %p) {
; AVX2-NEXT: cmovnsl %eax, %ecx
; AVX2-NEXT: andl $-2147483648, %ecx # imm = 0x80000000
; AVX2-NEXT: addl %eax, %ecx
+; AVX2-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm0
+; AVX2-NEXT: movl %eax, %eax
+; AVX2-NEXT: vcvtsi2sd %rax, %xmm15, %xmm1
+; AVX2-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vcvttsd2si %xmm0, %rax
; AVX2-NEXT: # kill: def $eax killed $eax killed $rax
-; AVX2-NEXT: xorl %edx, %edx
-; AVX2-NEXT: divl %ecx
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
@@ -2339,30 +2349,44 @@ define i32 @PR44139(ptr %p) {
; AVX512-NEXT: cmovnsl %eax, %ecx
; AVX512-NEXT: andl $-2147483648, %ecx # imm = 0x80000000
; AVX512-NEXT: addl %eax, %ecx
-; AVX512-NEXT: # kill: def $eax killed $eax killed $rax
-; AVX512-NEXT: xorl %edx, %edx
-; AVX512-NEXT: divl %ecx
+; AVX512-NEXT: vcvtusi2sd %ecx, %xmm15, %xmm0
+; AVX512-NEXT: vcvtusi2sd %eax, %xmm15, %xmm1
+; AVX512-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; AVX512-NEXT: vcvttsd2usi %xmm0, %eax
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
;
; X86AVX2-LABEL: PR44139:
; X86AVX2: # %bb.0:
-; X86AVX2-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86AVX2-NEXT: vbroadcastsd (%ecx), %ymm0
+; X86AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86AVX2-NEXT: vbroadcastsd (%eax), %ymm0
; X86AVX2-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm0[0],mem[0]
; X86AVX2-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7]
-; X86AVX2-NEXT: vmovaps %ymm0, 64(%ecx)
-; X86AVX2-NEXT: vmovaps %ymm0, 96(%ecx)
-; X86AVX2-NEXT: vmovaps %ymm0, 32(%ecx)
-; X86AVX2-NEXT: movl (%ecx), %eax
-; X86AVX2-NEXT: vmovaps %ymm1, (%ecx)
-; X86AVX2-NEXT: leal 2147483647(%eax), %ecx
-; X86AVX2-NEXT: testl %eax, %eax
-; X86AVX2-NEXT: cmovnsl %eax, %ecx
-; X86AVX2-NEXT: andl $-2147483648, %ecx # imm = 0x80000000
-; X86AVX2-NEXT: addl %eax, %ecx
-; X86AVX2-NEXT: xorl %edx, %edx
-; X86AVX2-NEXT: divl %ecx
+; X86AVX2-NEXT: vmovaps %ymm0, 64(%eax)
+; X86AVX2-NEXT: vmovaps %ymm0, 96(%eax)
+; X86AVX2-NEXT: vmovaps %ymm0, 32(%eax)
+; X86AVX2-NEXT: movl (%eax), %ecx
+; X86AVX2-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; X86AVX2-NEXT: vmovaps %ymm1, (%eax)
+; X86AVX2-NEXT: leal 2147483647(%ecx), %eax
+; X86AVX2-NEXT: testl %ecx, %ecx
+; X86AVX2-NEXT: cmovnsl %ecx, %eax
+; X86AVX2-NEXT: andl $-2147483648, %eax # imm = 0x80000000
+; X86AVX2-NEXT: addl %ecx, %eax
+; X86AVX2-NEXT: vmovd %eax, %xmm1
+; X86AVX2-NEXT: vmovq {{.*#+}} xmm2 = [4.503599627370496E+15,0.0E+0]
+; X86AVX2-NEXT: vpor %xmm2, %xmm1, %xmm1
+; X86AVX2-NEXT: vsubsd %xmm2, %xmm1, %xmm1
+; X86AVX2-NEXT: vorpd %xmm2, %xmm0, %xmm0
+; X86AVX2-NEXT: vsubsd %xmm2, %xmm0, %xmm0
+; X86AVX2-NEXT: vdivsd %xmm1, %xmm0, %xmm0
+; X86AVX2-NEXT: vcvttsd2si %xmm0, %ecx
+; X86AVX2-NEXT: movl %ecx, %edx
+; X86AVX2-NEXT: sarl $31, %edx
+; X86AVX2-NEXT: vsubsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86AVX2-NEXT: vcvttsd2si %xmm0, %eax
+; X86AVX2-NEXT: andl %edx, %eax
+; X86AVX2-NEXT: orl %ecx, %eax
; X86AVX2-NEXT: vzeroupper
; X86AVX2-NEXT: retl
%L = load <16 x i64>, ptr %p
diff --git a/llvm/test/CodeGen/X86/isel-sdiv.ll b/llvm/test/CodeGen/X86/isel-sdiv.ll
index 1aca8d1035664..c9518a62100b9 100644
--- a/llvm/test/CodeGen/X86/isel-sdiv.ll
+++ b/llvm/test/CodeGen/X86/isel-sdiv.ll
@@ -7,12 +7,6 @@
; RUN: llc < %s -global-isel -global-isel-abort=1 -mtriple=i686-linux-gnu | FileCheck %s --check-prefixes=X86,GISEL-X86
define i8 @test_sdiv_i8(i8 %arg1, i8 %arg2) nounwind {
-; X64-LABEL: test_sdiv_i8:
-; X64: # %bb.0:
-; X64-NEXT: movsbl %dil, %eax
-; X64-NEXT: idivb %sil
-; X64-NEXT: retq
-;
; DAG-X86-LABEL: test_sdiv_i8:
; DAG-X86: # %bb.0:
; DAG-X86-NEXT: movsbl {{[0-9]+}}(%esp), %eax
@@ -31,14 +25,6 @@ define i8 @test_sdiv_i8(i8 %arg1, i8 %arg2) nounwind {
}
define i16 @test_sdiv_i16(i16 %arg1, i16 %arg2) nounwind {
-; X64-LABEL: test_sdiv_i16:
-; X64: # %bb.0:
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: # kill: def $ax killed $ax killed $eax
-; X64-NEXT: cwtd
-; X64-NEXT: idivw %si
-; X64-NEXT: retq
-;
; DAG-X86-LABEL: test_sdiv_i16:
; DAG-X86: # %bb.0:
; DAG-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
@@ -59,13 +45,6 @@ define i16 @test_sdiv_i16(i16 %arg1, i16 %arg2) nounwind {
}
define i32 @test_sdiv_i32(i32 %arg1, i32 %arg2) nounwind {
-; X64-LABEL: test_sdiv_i32:
-; X64: # %bb.0:
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: cltd
-; X64-NEXT: idivl %esi
-; X64-NEXT: retq
-;
; X86-LABEL: test_sdiv_i32:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
diff --git a/llvm/test/CodeGen/X86/isel-srem.ll b/llvm/test/CodeGen/X86/isel-srem.ll
index 1dabf4175c852..d67087cfa8d0c 100644
--- a/llvm/test/CodeGen/X86/isel-srem.ll
+++ b/llvm/test/CodeGen/X86/isel-srem.ll
@@ -9,10 +9,16 @@
define i8 @test_srem_i8(i8 %arg1, i8 %arg2) nounwind {
; SDAG-X64-LABEL: test_srem_i8:
; SDAG-X64: # %bb.0:
-; SDAG-X64-NEXT: movsbl %dil, %eax
-; SDAG-X64-NEXT: idivb %sil
-; SDAG-X64-NEXT: movsbl %ah, %eax
+; SDAG-X64-NEXT: movsbl %sil, %edx
+; SDAG-X64-NEXT: cvtsi2ss %edx, %xmm0
+; SDAG-X64-NEXT: movsbl %dil, %ecx
+; SDAG-X64-NEXT: cvtsi2ss %ecx, %xmm1
+; SDAG-X64-NEXT: divss %xmm0, %xmm1
+; SDAG-X64-NEXT: cvttss2si %xmm1, %eax
; SDAG-X64-NEXT: # kill: def $al killed $al killed $eax
+; SDAG-X64-NEXT: mulb %dl
+; SDAG-X64-NEXT: subb %al, %cl
+; SDAG-X64-NEXT: movl %ecx, %eax
; SDAG-X64-NEXT: retq
;
; FAST-X64-LABEL: test_srem_i8:
@@ -59,14 +65,37 @@ define i8 @test_srem_i8(i8 %arg1, i8 %arg2) nounwind {
}
define i16 @test_srem_i16(i16 %arg1, i16 %arg2) nounwind {
-; X64-LABEL: test_srem_i16:
-; X64: # %bb.0:
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: # kill: def $ax killed $ax killed $eax
-; X64-NEXT: cwtd
-; X64-NEXT: idivw %si
-; X64-NEXT: movl %edx, %eax
-; X64-NEXT: retq
+; SDAG-X64-LABEL: test_srem_i16:
+; SDAG-X64: # %bb.0:
+; SDAG-X64-NEXT: movl %edi, %eax
+; SDAG-X64-NEXT: movswl %si, %ecx
+; SDAG-X64-NEXT: cvtsi2ss %ecx, %xmm0
+; SDAG-X64-NEXT: movswl %ax, %ecx
+; SDAG-X64-NEXT: cvtsi2ss %ecx, %xmm1
+; SDAG-X64-NEXT: divss %xmm0, %xmm1
+; SDAG-X64-NEXT: cvttss2si %xmm1, %ecx
+; SDAG-X64-NEXT: imull %esi, %ecx
+; SDAG-X64-NEXT: subl %ecx, %eax
+; SDAG-X64-NEXT: # kill: def $ax killed $ax killed $eax
+; SDAG-X64-NEXT: retq
+;
+; FAST-X64-LABEL: test_srem_i16:
+; FAST-X64: # %bb.0:
+; FAST-X64-NEXT: movl %edi, %eax
+; FAST-X64-NEXT: # kill: def $ax killed $ax killed $eax
+; FAST-X64-NEXT: cwtd
+; FAST-X64-NEXT: idivw %si
+; FAST-X64-NEXT: movl %edx, %eax
+; FAST-X64-NEXT: retq
+;
+; GISEL-X64-LABEL: test_srem_i16:
+; GISEL-X64: # %bb.0:
+; GISEL-X64-NEXT: movl %edi, %eax
+; GISEL-X64-NEXT: # kill: def $ax killed $ax killed $eax
+; GISEL-X64-NEXT: cwtd
+; GISEL-X64-NEXT: idivw %si
+; GISEL-X64-NEXT: movl %edx, %eax
+; GISEL-X64-NEXT: retq
;
; DAG-X86-LABEL: test_srem_i16:
; DAG-X86: # %bb.0:
@@ -90,13 +119,32 @@ define i16 @test_srem_i16(i16 %arg1, i16 %arg2) nounwind {
}
define i32 @test_srem_i32(i32 %arg1, i32 %arg2) nounwind {
-; X64-LABEL: test_srem_i32:
-; X64: # %bb.0:
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: cltd
-; X64-NEXT: idivl %esi
-; X64-NEXT: movl %edx, %eax
-; X64-NEXT: retq
+; SDAG-X64-LABEL: test_srem_i32:
+; SDAG-X64: # %bb.0:
+; SDAG-X64-NEXT: movl %edi, %eax
+; SDAG-X64-NEXT: cvtsi2sd %esi, %xmm0
+; SDAG-X64-NEXT: cvtsi2sd %edi, %xmm1
+; SDAG-X64-NEXT: divsd %xmm0, %xmm1
+; SDAG-X64-NEXT: cvttsd2si %xmm1, %ecx
+; SDAG-X64-NEXT: imull %esi, %ecx
+; SDAG-X64-NEXT: subl %ecx, %eax
+; SDAG-X64-NEXT: retq
+;
+; FAST-X64-LABEL: test_srem_i32:
+; FAST-X64: # %bb.0:
+; FAST-X64-NEXT: movl %edi, %eax
+; FAST-X64-NEXT: cltd
+; FAST-X64-NEXT: idivl %esi
+; FAST-X64-NEXT: movl %edx, %eax
+; FAST-X64-NEXT: retq
+;
+; GISEL-X64-LABEL: test_srem_i32:
+; GISEL-X64: # %bb.0:
+; GISEL-X64-NEXT: movl %edi, %eax
+; GISEL-X64-NEXT: cltd
+; GISEL-X64-NEXT: idivl %esi
+; GISEL-X64-NEXT: movl %edx, %eax
+; GISEL-X64-NEXT: retq
;
; X86-LABEL: test_srem_i32:
; X86: # %bb.0:
diff --git a/llvm/test/CodeGen/X86/isel-udiv.ll b/llvm/test/CodeGen/X86/isel-udiv.ll
index b123b3c7780fa..8470a10230969 100644
--- a/llvm/test/CodeGen/X86/isel-udiv.ll
+++ b/llvm/test/CodeGen/X86/isel-udiv.ll
@@ -7,12 +7,6 @@
; RUN: llc < %s -global-isel -global-isel-abort=1 -mtriple=i686-linux-gnu | FileCheck %s --check-prefixes=X86,GISEL-X86
define i8 @test_udiv_i8(i8 %arg1, i8 %arg2) nounwind {
-; X64-LABEL: test_udiv_i8:
-; X64: # %bb.0:
-; X64-NEXT: movzbl %dil, %eax
-; X64-NEXT: divb %sil
-; X64-NEXT: retq
-;
; DAG-X86-LABEL: test_udiv_i8:
; DAG-X86: # %bb.0:
; DAG-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
@@ -31,14 +25,6 @@ define i8 @test_udiv_i8(i8 %arg1, i8 %arg2) nounwind {
}
define i16 @test_udiv_i16(i16 %arg1, i16 %arg2) nounwind {
-; X64-LABEL: test_udiv_i16:
-; X64: # %bb.0:
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: # kill: def $ax killed $ax killed $eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divw %si
-; X64-NEXT: retq
-;
; DAG-X86-LABEL: test_udiv_i16:
; DAG-X86: # %bb.0:
; DAG-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
@@ -59,13 +45,6 @@ define i16 @test_udiv_i16(i16 %arg1, i16 %arg2) nounwind {
}
define i32 @test_udiv_i32(i32 %arg1, i32 %arg2) nounwind {
-; X64-LABEL: test_udiv_i32:
-; X64: # %bb.0:
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %esi
-; X64-NEXT: retq
-;
; X86-LABEL: test_udiv_i32:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
diff --git a/llvm/test/CodeGen/X86/isel-urem.ll b/llvm/test/CodeGen/X86/isel-urem.ll
index 386f08151ad9c..eb840b23c908c 100644
--- a/llvm/test/CodeGen/X86/isel-urem.ll
+++ b/llvm/test/CodeGen/X86/isel-urem.ll
@@ -9,10 +9,16 @@
define i8 @test_urem_i8(i8 %arg1, i8 %arg2) nounwind {
; SDAG-X64-LABEL: test_urem_i8:
; SDAG-X64: # %bb.0:
-; SDAG-X64-NEXT: movzbl %dil, %eax
-; SDAG-X64-NEXT: divb %sil
-; SDAG-X64-NEXT: movzbl %ah, %eax
+; SDAG-X64-NEXT: movzbl %sil, %edx
+; SDAG-X64-NEXT: cvtsi2ss %edx, %xmm0
+; SDAG-X64-NEXT: movzbl %dil, %ecx
+; SDAG-X64-NEXT: cvtsi2ss %ecx, %xmm1
+; SDAG-X64-NEXT: divss %xmm0, %xmm1
+; SDAG-X64-NEXT: cvttss2si %xmm1, %eax
; SDAG-X64-NEXT: # kill: def $al killed $al killed $eax
+; SDAG-X64-NEXT: mulb %dl
+; SDAG-X64-NEXT: subb %al, %cl
+; SDAG-X64-NEXT: movl %ecx, %eax
; SDAG-X64-NEXT: retq
;
; FAST-X64-LABEL: test_urem_i8:
@@ -59,14 +65,37 @@ define i8 @test_urem_i8(i8 %arg1, i8 %arg2) nounwind {
}
define i16 @test_urem_i16(i16 %arg1, i16 %arg2) nounwind {
-; X64-LABEL: test_urem_i16:
-; X64: # %bb.0:
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: # kill: def $ax killed $ax killed $eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divw %si
-; X64-NEXT: movl %edx, %eax
-; X64-NEXT: retq
+; SDAG-X64-LABEL: test_urem_i16:
+; SDAG-X64: # %bb.0:
+; SDAG-X64-NEXT: movl %edi, %eax
+; SDAG-X64-NEXT: movzwl %si, %ecx
+; SDAG-X64-NEXT: cvtsi2ss %ecx, %xmm0
+; SDAG-X64-NEXT: movzwl %ax, %ecx
+; SDAG-X64-NEXT: cvtsi2ss %ecx, %xmm1
+; SDAG-X64-NEXT: divss %xmm0, %xmm1
+; SDAG-X64-NEXT: cvttss2si %xmm1, %ecx
+; SDAG-X64-NEXT: imull %esi, %ecx
+; SDAG-X64-NEXT: subl %ecx, %eax
+; SDAG-X64-NEXT: # kill: def $ax killed $ax killed $eax
+; SDAG-X64-NEXT: retq
+;
+; FAST-X64-LABEL: test_urem_i16:
+; FAST-X64: # %bb.0:
+; FAST-X64-NEXT: movl %edi, %eax
+; FAST-X64-NEXT: # kill: def $ax killed $ax killed $eax
+; FAST-X64-NEXT: xorl %edx, %edx
+; FAST-X64-NEXT: divw %si
+; FAST-X64-NEXT: movl %edx, %eax
+; FAST-X64-NEXT: retq
+;
+; GISEL-X64-LABEL: test_urem_i16:
+; GISEL-X64: # %bb.0:
+; GISEL-X64-NEXT: movl %edi, %eax
+; GISEL-X64-NEXT: # kill: def $ax killed $ax killed $eax
+; GISEL-X64-NEXT: xorl %edx, %edx
+; GISEL-X64-NEXT: divw %si
+; GISEL-X64-NEXT: movl %edx, %eax
+; GISEL-X64-NEXT: retq
;
; DAG-X86-LABEL: test_urem_i16:
; DAG-X86: # %bb.0:
@@ -90,13 +119,34 @@ define i16 @test_urem_i16(i16 %arg1, i16 %arg2) nounwind {
}
define i32 @test_urem_i32(i32 %arg1, i32 %arg2) nounwind {
-; X64-LABEL: test_urem_i32:
-; X64: # %bb.0:
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %esi
-; X64-NEXT: movl %edx, %eax
-; X64-NEXT: retq
+; SDAG-X64-LABEL: test_urem_i32:
+; SDAG-X64: # %bb.0:
+; SDAG-X64-NEXT: movl %edi, %eax
+; SDAG-X64-NEXT: movl %esi, %ecx
+; SDAG-X64-NEXT: cvtsi2sd %rcx, %xmm0
+; SDAG-X64-NEXT: movl %edi, %ecx
+; SDAG-X64-NEXT: cvtsi2sd %rcx, %xmm1
+; SDAG-X64-NEXT: divsd %xmm0, %xmm1
+; SDAG-X64-NEXT: cvttsd2si %xmm1, %rcx
+; SDAG-X64-NEXT: imull %esi, %ecx
+; SDAG-X64-NEXT: subl %ecx, %eax
+; SDAG-X64-NEXT: retq
+;
+; FAST-X64-LABEL: test_urem_i32:
+; FAST-X64: # %bb.0:
+; FAST-X64-NEXT: movl %edi, %eax
+; FAST-X64-NEXT: xorl %edx, %edx
+; FAST-X64-NEXT: divl %esi
+; FAST-X64-NEXT: movl %edx, %eax
+; FAST-X64-NEXT: retq
+;
+; GISEL-X64-LABEL: test_urem_i32:
+; GISEL-X64: # %bb.0:
+; GISEL-X64-NEXT: movl %edi, %eax
+; GISEL-X64-NEXT: xorl %edx, %edx
+; GISEL-X64-NEXT: divl %esi
+; GISEL-X64-NEXT: movl %edx, %eax
+; GISEL-X64-NEXT: retq
;
; X86-LABEL: test_urem_i32:
; X86: # %bb.0:
diff --git a/llvm/test/CodeGen/X86/known-never-zero.ll b/llvm/test/CodeGen/X86/known-never-zero.ll
index 66f2eb7a31695..012dedaff8c4e 100644
--- a/llvm/test/CodeGen/X86/known-never-zero.ll
+++ b/llvm/test/CodeGen/X86/known-never-zero.ll
@@ -1557,17 +1557,33 @@ define i32 @udiv_known_nonzero(i32 %xx, i32 %y) {
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: orl $64, %eax
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl {{[0-9]+}}(%esp)
-; X86-NEXT: rep bsfl %eax, %eax
+; X86-NEXT: movsd {{.*#+}} xmm0 = [4.503599627370496E+15,0.0E+0]
+; X86-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X86-NEXT: orpd %xmm0, %xmm1
+; X86-NEXT: subsd %xmm0, %xmm1
+; X86-NEXT: movd %eax, %xmm2
+; X86-NEXT: por %xmm0, %xmm2
+; X86-NEXT: subsd %xmm0, %xmm2
+; X86-NEXT: divsd %xmm1, %xmm2
+; X86-NEXT: cvttsd2si %xmm2, %eax
+; X86-NEXT: movl %eax, %ecx
+; X86-NEXT: sarl $31, %ecx
+; X86-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
+; X86-NEXT: cvttsd2si %xmm2, %edx
+; X86-NEXT: andl %ecx, %edx
+; X86-NEXT: orl %eax, %edx
+; X86-NEXT: rep bsfl %edx, %eax
; X86-NEXT: retl
;
; X64-LABEL: udiv_known_nonzero:
; X64: # %bb.0:
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: orl $64, %eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %esi
+; X64-NEXT: # kill: def $edi killed $edi def $rdi
+; X64-NEXT: orl $64, %edi
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: vcvtsi2sd %rax, %xmm15, %xmm0
+; X64-NEXT: vcvtsi2sd %rdi, %xmm15, %xmm1
+; X64-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; X64-NEXT: vcvttsd2si %xmm0, %rax
; X64-NEXT: rep bsfl %eax, %eax
; X64-NEXT: retq
%x = or i32 %xx, 64
@@ -1579,68 +1595,112 @@ define i32 @udiv_known_nonzero(i32 %xx, i32 %y) {
define i32 @udiv_known_nonzero_vec(<4 x i32> %xx, <4 x i32> %y, ptr %p) nounwind {
; X86-LABEL: udiv_known_nonzero_vec:
; X86: # %bb.0:
-; X86-NEXT: pushl %edi
-; X86-NEXT: pushl %esi
-; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
-; X86-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
-; X86-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,1,1]
-; X86-NEXT: movd %xmm2, %ecx
-; X86-NEXT: movl $-1, %eax
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %ecx
-; X86-NEXT: movd %eax, %xmm3
-; X86-NEXT: movd %xmm1, %ecx
-; X86-NEXT: movd %xmm0, %eax
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %ecx
+; X86-NEXT: pxor %xmm5, %xmm5
+; X86-NEXT: movss {{.*#+}} xmm3 = [64,0,0,0]
+; X86-NEXT: orps %xmm0, %xmm3
+; X86-NEXT: xorps %xmm2, %xmm2
+; X86-NEXT: movss {{.*#+}} xmm2 = xmm3[0],xmm2[1,2,3]
+; X86-NEXT: movq {{.*#+}} xmm3 = [4.503599627370496E+15,0.0E+0]
+; X86-NEXT: movdqa %xmm1, %xmm4
+; X86-NEXT: psrldq {{.*#+}} xmm4 = xmm4[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; X86-NEXT: por %xmm3, %xmm4
+; X86-NEXT: subsd %xmm3, %xmm4
+; X86-NEXT: movaps %xmm0, %xmm6
+; X86-NEXT: psrldq {{.*#+}} xmm6 = xmm6[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; X86-NEXT: por %xmm3, %xmm6
+; X86-NEXT: subsd %xmm3, %xmm6
+; X86-NEXT: divsd %xmm4, %xmm6
+; X86-NEXT: cvttsd2si %xmm6, %ecx
+; X86-NEXT: movsd {{.*#+}} xmm4 = [2.147483648E+9,0.0E+0]
+; X86-NEXT: subsd %xmm4, %xmm6
+; X86-NEXT: cvttsd2si %xmm6, %eax
+; X86-NEXT: movdqa %xmm1, %xmm6
+; X86-NEXT: punpckhdq {{.*#+}} xmm6 = xmm6[2],xmm5[2],xmm6[3],xmm5[3]
+; X86-NEXT: unpckhps {{.*#+}} xmm0 = xmm0[2],xmm5[2],xmm0[3],xmm5[3]
+; X86-NEXT: movss {{.*#+}} xmm5 = xmm1[0],xmm5[1,2,3]
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: sarl $31, %edx
+; X86-NEXT: andl %edx, %eax
+; X86-NEXT: orl %ecx, %eax
+; X86-NEXT: por %xmm3, %xmm6
+; X86-NEXT: subsd %xmm3, %xmm6
+; X86-NEXT: orps %xmm3, %xmm0
+; X86-NEXT: subsd %xmm3, %xmm0
+; X86-NEXT: divsd %xmm6, %xmm0
+; X86-NEXT: movd %eax, %xmm6
+; X86-NEXT: cvttsd2si %xmm0, %eax
; X86-NEXT: movl %eax, %ecx
-; X86-NEXT: movd %eax, %xmm2
-; X86-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
-; X86-NEXT: pshufd {{.*#+}} xmm3 = xmm1[3,3,3,3]
-; X86-NEXT: movd %xmm3, %edi
-; X86-NEXT: pshufd {{.*#+}} xmm3 = xmm0[3,3,3,3]
-; X86-NEXT: movd %xmm3, %eax
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %edi
-; X86-NEXT: movd %eax, %xmm3
-; X86-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
-; X86-NEXT: movd %xmm1, %edi
-; X86-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
-; X86-NEXT: movd %xmm0, %eax
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %edi
-; X86-NEXT: movd %eax, %xmm0
-; X86-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
+; X86-NEXT: sarl $31, %ecx
+; X86-NEXT: subsd %xmm4, %xmm0
+; X86-NEXT: cvttsd2si %xmm0, %edx
+; X86-NEXT: andl %ecx, %edx
+; X86-NEXT: orl %eax, %edx
+; X86-NEXT: movd %edx, %xmm0
+; X86-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm6[0],xmm0[1],xmm6[1]
+; X86-NEXT: psrlq $32, %xmm1
+; X86-NEXT: por %xmm3, %xmm1
+; X86-NEXT: subsd %xmm3, %xmm1
+; X86-NEXT: movss {{.*#+}} xmm6 = [4294967295,0,0,0]
+; X86-NEXT: orpd %xmm3, %xmm6
+; X86-NEXT: subsd %xmm3, %xmm6
+; X86-NEXT: divsd %xmm1, %xmm6
+; X86-NEXT: cvttsd2si %xmm6, %ecx
+; X86-NEXT: subsd %xmm4, %xmm6
+; X86-NEXT: cvttsd2si %xmm6, %eax
+; X86-NEXT: orps %xmm3, %xmm5
+; X86-NEXT: subsd %xmm3, %xmm5
+; X86-NEXT: orps %xmm3, %xmm2
+; X86-NEXT: subsd %xmm3, %xmm2
+; X86-NEXT: divsd %xmm5, %xmm2
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: sarl $31, %edx
+; X86-NEXT: andl %edx, %eax
+; X86-NEXT: orl %ecx, %eax
+; X86-NEXT: cvttsd2si %xmm2, %ecx
+; X86-NEXT: subsd %xmm4, %xmm2
+; X86-NEXT: movd %eax, %xmm1
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: sarl $31, %eax
+; X86-NEXT: cvttsd2si %xmm2, %edx
+; X86-NEXT: andl %eax, %edx
+; X86-NEXT: orl %ecx, %edx
+; X86-NEXT: movd %edx, %xmm2
+; X86-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; X86-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
-; X86-NEXT: movdqa %xmm2, (%esi)
-; X86-NEXT: rep bsfl %ecx, %eax
-; X86-NEXT: popl %esi
-; X86-NEXT: popl %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movdqa %xmm2, (%eax)
+; X86-NEXT: rep bsfl %edx, %eax
; X86-NEXT: retl
;
; X64-LABEL: udiv_known_nonzero_vec:
; X64: # %bb.0:
-; X64-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; X64-NEXT: vpextrd $1, %xmm1, %ecx
-; X64-NEXT: movl $-1, %eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %ecx
-; X64-NEXT: movl %eax, %ecx
-; X64-NEXT: vmovd %xmm1, %esi
+; X64-NEXT: vorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vmovd %xmm1, %eax
+; X64-NEXT: vcvtsi2sd %rax, %xmm15, %xmm2
; X64-NEXT: vmovd %xmm0, %eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %esi
+; X64-NEXT: vcvtsi2sd %rax, %xmm15, %xmm3
+; X64-NEXT: vdivsd %xmm2, %xmm3, %xmm2
+; X64-NEXT: vcvttsd2si %xmm2, %rax
; X64-NEXT: vmovd %eax, %xmm2
-; X64-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2
-; X64-NEXT: vpextrd $2, %xmm1, %ecx
+; X64-NEXT: vpextrd $1, %xmm1, %eax
+; X64-NEXT: vcvtsi2sd %rax, %xmm15, %xmm3
+; X64-NEXT: vmovsd {{.*#+}} xmm4 = [4.294967295E+9,0.0E+0]
+; X64-NEXT: vdivsd %xmm3, %xmm4, %xmm3
+; X64-NEXT: vcvttsd2si %xmm3, %rax
+; X64-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2
+; X64-NEXT: vpextrd $2, %xmm1, %eax
+; X64-NEXT: vcvtsi2sd %rax, %xmm15, %xmm3
; X64-NEXT: vpextrd $2, %xmm0, %eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %ecx
+; X64-NEXT: vcvtsi2sd %rax, %xmm15, %xmm4
+; X64-NEXT: vdivsd %xmm3, %xmm4, %xmm3
+; X64-NEXT: vcvttsd2si %xmm3, %rax
; X64-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2
-; X64-NEXT: vpextrd $3, %xmm1, %ecx
+; X64-NEXT: vpextrd $3, %xmm1, %eax
+; X64-NEXT: vcvtsi2sd %rax, %xmm15, %xmm1
; X64-NEXT: vpextrd $3, %xmm0, %eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %ecx
+; X64-NEXT: vcvtsi2sd %rax, %xmm15, %xmm0
+; X64-NEXT: vdivsd %xmm1, %xmm0, %xmm0
+; X64-NEXT: vcvttsd2si %xmm0, %rax
; X64-NEXT: vpinsrd $3, %eax, %xmm2, %xmm0
; X64-NEXT: vmovdqa %xmm0, (%rdi)
; X64-NEXT: vmovd %xmm0, %eax
@@ -1657,22 +1717,36 @@ define i32 @udiv_known_nonzero_vec(<4 x i32> %xx, <4 x i32> %y, ptr %p) nounwind
define i32 @udiv_maybe_zero(i32 %x, i32 %y) {
; X86-LABEL: udiv_maybe_zero:
; X86: # %bb.0:
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl {{[0-9]+}}(%esp)
-; X86-NEXT: bsfl %eax, %ecx
+; X86-NEXT: movsd {{.*#+}} xmm0 = [4.503599627370496E+15,0.0E+0]
+; X86-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X86-NEXT: orpd %xmm0, %xmm1
+; X86-NEXT: subsd %xmm0, %xmm1
+; X86-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; X86-NEXT: orpd %xmm0, %xmm2
+; X86-NEXT: subsd %xmm0, %xmm2
+; X86-NEXT: divsd %xmm1, %xmm2
+; X86-NEXT: cvttsd2si %xmm2, %eax
+; X86-NEXT: movl %eax, %ecx
+; X86-NEXT: sarl $31, %ecx
+; X86-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
+; X86-NEXT: cvttsd2si %xmm2, %edx
+; X86-NEXT: andl %ecx, %edx
+; X86-NEXT: orl %eax, %edx
+; X86-NEXT: bsfl %edx, %ecx
; X86-NEXT: movl $32, %eax
; X86-NEXT: cmovnel %ecx, %eax
; X86-NEXT: retl
;
; X64-LABEL: udiv_maybe_zero:
; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: vcvtsi2sd %rax, %xmm15, %xmm0
; X64-NEXT: movl %edi, %eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %esi
-; X64-NEXT: movl $32, %ecx
-; X64-NEXT: rep bsfl %eax, %ecx
-; X64-NEXT: movl %ecx, %eax
+; X64-NEXT: vcvtsi2sd %rax, %xmm15, %xmm1
+; X64-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; X64-NEXT: vcvttsd2si %xmm0, %rcx
+; X64-NEXT: movl $32, %eax
+; X64-NEXT: rep bsfl %ecx, %eax
; X64-NEXT: retq
%z = udiv exact i32 %x, %y
%r = call i32 @llvm.cttz.i32(i32 %z, i1 false)
@@ -1684,17 +1758,20 @@ define i32 @sdiv_known_nonzero(i32 %xx, i32 %y) {
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: orl $64, %eax
-; X86-NEXT: cltd
-; X86-NEXT: idivl {{[0-9]+}}(%esp)
+; X86-NEXT: cvtsi2sd %eax, %xmm0
+; X86-NEXT: cvtsi2sdl {{[0-9]+}}(%esp), %xmm1
+; X86-NEXT: divsd %xmm1, %xmm0
+; X86-NEXT: cvttsd2si %xmm0, %eax
; X86-NEXT: rep bsfl %eax, %eax
; X86-NEXT: retl
;
; X64-LABEL: sdiv_known_nonzero:
; X64: # %bb.0:
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: orl $64, %eax
-; X64-NEXT: cltd
-; X64-NEXT: idivl %esi
+; X64-NEXT: orl $64, %edi
+; X64-NEXT: vcvtsi2sd %esi, %xmm15, %xmm0
+; X64-NEXT: vcvtsi2sd %edi, %xmm15, %xmm1
+; X64-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; X64-NEXT: vcvttsd2si %xmm0, %eax
; X64-NEXT: rep bsfl %eax, %eax
; X64-NEXT: retq
%x = or i32 %xx, 64
@@ -1747,9 +1824,10 @@ define i32 @sdiv_known_nonzero_vec(<4 x i32> %xx, <4 x i32> %y, ptr %p) nounwind
define i32 @sdiv_maybe_zero(i32 %x, i32 %y) {
; X86-LABEL: sdiv_maybe_zero:
; X86: # %bb.0:
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: cltd
-; X86-NEXT: idivl {{[0-9]+}}(%esp)
+; X86-NEXT: cvtsi2sdl {{[0-9]+}}(%esp), %xmm0
+; X86-NEXT: cvtsi2sdl {{[0-9]+}}(%esp), %xmm1
+; X86-NEXT: divsd %xmm0, %xmm1
+; X86-NEXT: cvttsd2si %xmm1, %eax
; X86-NEXT: bsfl %eax, %ecx
; X86-NEXT: movl $32, %eax
; X86-NEXT: cmovnel %ecx, %eax
@@ -1757,12 +1835,12 @@ define i32 @sdiv_maybe_zero(i32 %x, i32 %y) {
;
; X64-LABEL: sdiv_maybe_zero:
; X64: # %bb.0:
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: cltd
-; X64-NEXT: idivl %esi
-; X64-NEXT: movl $32, %ecx
-; X64-NEXT: rep bsfl %eax, %ecx
-; X64-NEXT: movl %ecx, %eax
+; X64-NEXT: vcvtsi2sd %esi, %xmm15, %xmm0
+; X64-NEXT: vcvtsi2sd %edi, %xmm15, %xmm1
+; X64-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; X64-NEXT: vcvttsd2si %xmm0, %ecx
+; X64-NEXT: movl $32, %eax
+; X64-NEXT: rep bsfl %ecx, %eax
; X64-NEXT: retq
%z = sdiv exact i32 %x, %y
%r = call i32 @llvm.cttz.i32(i32 %z, i1 false)
diff --git a/llvm/test/CodeGen/X86/known-pow2.ll b/llvm/test/CodeGen/X86/known-pow2.ll
index f85bc7d3eb699..3d3e0729c8345 100644
--- a/llvm/test/CodeGen/X86/known-pow2.ll
+++ b/llvm/test/CodeGen/X86/known-pow2.ll
@@ -71,7 +71,7 @@ define i32 @pow2_extractelt_vec(<4 x i32> %a0, ptr %p1, i32 %a2) {
define i32 @pow2_extractelt_vec_fail0(<4 x i32> %a0, ptr %p1, i32 %a2, i32 %a3) {
; CHECK-LABEL: pow2_extractelt_vec_fail0:
; CHECK: # %bb.0:
-; CHECK-NEXT: movl %edx, %ecx
+; CHECK-NEXT: # kill: def $edx killed $edx def $rdx
; CHECK-NEXT: movl %esi, %eax
; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: pcmpgtd %xmm0, %xmm1
@@ -80,10 +80,17 @@ define i32 @pow2_extractelt_vec_fail0(<4 x i32> %a0, ptr %p1, i32 %a2, i32 %a3)
; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: por %xmm0, %xmm1
; CHECK-NEXT: movdqa %xmm1, (%rdi)
-; CHECK-NEXT: andl $3, %ecx
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl (%rdi,%rcx,4)
-; CHECK-NEXT: movl %edx, %eax
+; CHECK-NEXT: andl $3, %edx
+; CHECK-NEXT: movl (%rdi,%rdx,4), %ecx
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2sd %rcx, %xmm0
+; CHECK-NEXT: movl %esi, %edx
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: cvtsi2sd %rdx, %xmm1
+; CHECK-NEXT: divsd %xmm0, %xmm1
+; CHECK-NEXT: cvttsd2si %xmm1, %rdx
+; CHECK-NEXT: imull %ecx, %edx
+; CHECK-NEXT: subl %edx, %eax
; CHECK-NEXT: retq
%cmp = icmp sgt <4 x i32> zeroinitializer, %a0
%sel = select <4 x i1> %cmp, <4 x i32> <i32 4, i32 2, i32 1, i32 0>, <4 x i32> <i32 8, i32 4, i32 2, i32 -1>
@@ -1348,11 +1355,18 @@ define i8 @pow2_trunc(i32 %x, i32 %a){
define i8 @pow2_trunc_fail(i32 %x, i32 %a){
; CHECK-LABEL: pow2_trunc_fail:
; CHECK: # %bb.0:
-; CHECK-NEXT: andb $78, %sil
-; CHECK-NEXT: movzbl %dil, %eax
-; CHECK-NEXT: divb %sil
-; CHECK-NEXT: movzbl %ah, %eax
+; CHECK-NEXT: movl %esi, %edx
+; CHECK-NEXT: andb $78, %dl
+; CHECK-NEXT: andl $78, %esi
+; CHECK-NEXT: cvtsi2ss %esi, %xmm0
+; CHECK-NEXT: movzbl %dil, %ecx
+; CHECK-NEXT: cvtsi2ss %ecx, %xmm1
+; CHECK-NEXT: divss %xmm0, %xmm1
+; CHECK-NEXT: cvttss2si %xmm1, %eax
; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: mulb %dl
+; CHECK-NEXT: subb %al, %cl
+; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: retq
%y = and i32 %a, 78
%x8 = trunc i32 %x to i8
@@ -1388,13 +1402,21 @@ define i8 @pow2_trunc_vec(i8 %x8, <4 x i32> %a, ptr %p) {
define i8 @pow2_truncc_vec_fail(<4 x i32> %x, <4 x i32> %a) {
; CHECK-LABEL: pow2_truncc_vec_fail:
; CHECK: # %bb.0:
-; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: movl $78, %eax
+; CHECK-NEXT: movd %eax, %xmm2
+; CHECK-NEXT: pand %xmm1, %xmm2
+; CHECK-NEXT: movd %xmm2, %edx
+; CHECK-NEXT: cvtdq2ps %xmm2, %xmm1
; CHECK-NEXT: movd %xmm0, %eax
-; CHECK-NEXT: movzbl %al, %eax
-; CHECK-NEXT: movd %xmm1, %ecx
-; CHECK-NEXT: divb %cl
-; CHECK-NEXT: movzbl %ah, %eax
+; CHECK-NEXT: movzbl %al, %ecx
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2ss %ecx, %xmm0
+; CHECK-NEXT: divss %xmm1, %xmm0
+; CHECK-NEXT: cvttss2si %xmm0, %eax
; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: mulb %dl
+; CHECK-NEXT: subb %al, %cl
+; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: retq
%a.splat = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> zeroinitializer
%y = and <4 x i32> %a.splat, <i32 78, i32 69, i32 67, i32 100>
diff --git a/llvm/test/CodeGen/X86/knownbits-div.ll b/llvm/test/CodeGen/X86/knownbits-div.ll
index 02e20a9010cc6..787bcdd8c1c60 100644
--- a/llvm/test/CodeGen/X86/knownbits-div.ll
+++ b/llvm/test/CodeGen/X86/knownbits-div.ll
@@ -30,9 +30,14 @@ define i8 @sdiv_exact_even_even_fail_unknown(i8 %x, i8 %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: andb $-2, %dil
; CHECK-NEXT: andb $-2, %sil
+; CHECK-NEXT: movsbl %sil, %eax
+; CHECK-NEXT: cvtsi2ss %eax, %xmm0
; CHECK-NEXT: movsbl %dil, %eax
-; CHECK-NEXT: idivb %sil
+; CHECK-NEXT: cvtsi2ss %eax, %xmm1
+; CHECK-NEXT: divss %xmm0, %xmm1
+; CHECK-NEXT: cvttss2si %xmm1, %eax
; CHECK-NEXT: andb $1, %al
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%num = and i8 %x, -2
%denum = and i8 %y, -2
@@ -56,11 +61,14 @@ define i8 @udiv_exact_even_odd(i8 %x, i8 %y) {
define i8 @udiv_exact_even_even_fail_unknown(i8 %x, i8 %y) {
; CHECK-LABEL: udiv_exact_even_even_fail_unknown:
; CHECK: # %bb.0:
-; CHECK-NEXT: andb $-2, %dil
-; CHECK-NEXT: andb $-2, %sil
-; CHECK-NEXT: movzbl %dil, %eax
-; CHECK-NEXT: divb %sil
+; CHECK-NEXT: andl $254, %esi
+; CHECK-NEXT: cvtsi2ss %esi, %xmm0
+; CHECK-NEXT: andl $254, %edi
+; CHECK-NEXT: cvtsi2ss %edi, %xmm1
+; CHECK-NEXT: divss %xmm0, %xmm1
+; CHECK-NEXT: cvttss2si %xmm1, %eax
; CHECK-NEXT: andb $1, %al
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%num = and i8 %x, -2
%denum = and i8 %y, -2
diff --git a/llvm/test/CodeGen/X86/load-scalar-as-vector.ll b/llvm/test/CodeGen/X86/load-scalar-as-vector.ll
index d2359ced3e19d..77647edc1cad6 100644
--- a/llvm/test/CodeGen/X86/load-scalar-as-vector.ll
+++ b/llvm/test/CodeGen/X86/load-scalar-as-vector.ll
@@ -334,17 +334,19 @@ define <8 x i16> @ashr_op1_constant(ptr %p) nounwind {
define <4 x i32> @sdiv_op0_constant(ptr %p) nounwind {
; SSE-LABEL: sdiv_op0_constant:
; SSE: # %bb.0:
-; SSE-NEXT: movl $42, %eax
-; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: idivl (%rdi)
+; SSE-NEXT: cvtsi2sdl (%rdi), %xmm0
+; SSE-NEXT: movsd {{.*#+}} xmm1 = [4.2E+1,0.0E+0]
+; SSE-NEXT: divsd %xmm0, %xmm1
+; SSE-NEXT: cvttsd2si %xmm1, %eax
; SSE-NEXT: movd %eax, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: sdiv_op0_constant:
; AVX: # %bb.0:
-; AVX-NEXT: movl $42, %eax
-; AVX-NEXT: xorl %edx, %edx
-; AVX-NEXT: idivl (%rdi)
+; AVX-NEXT: vcvtsi2sdl (%rdi), %xmm15, %xmm0
+; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [4.2E+1,0.0E+0]
+; AVX-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; AVX-NEXT: vcvttsd2si %xmm0, %eax
; AVX-NEXT: vmovd %eax, %xmm0
; AVX-NEXT: retq
%x = load i32, ptr %p
@@ -390,20 +392,28 @@ define <8 x i16> @sdiv_op1_constant(ptr %p) nounwind {
define <8 x i16> @srem_op0_constant(ptr %p) nounwind {
; SSE-LABEL: srem_op0_constant:
; SSE: # %bb.0:
-; SSE-NEXT: movw $42, %ax
-; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: idivw (%rdi)
-; SSE-NEXT: # kill: def $dx killed $dx def $edx
-; SSE-NEXT: movd %edx, %xmm0
+; SSE-NEXT: movswl (%rdi), %eax
+; SSE-NEXT: cvtsi2ss %eax, %xmm0
+; SSE-NEXT: movss {{.*#+}} xmm1 = [4.2E+1,0.0E+0,0.0E+0,0.0E+0]
+; SSE-NEXT: divss %xmm0, %xmm1
+; SSE-NEXT: cvttss2si %xmm1, %ecx
+; SSE-NEXT: imull %eax, %ecx
+; SSE-NEXT: movl $42, %eax
+; SSE-NEXT: subl %ecx, %eax
+; SSE-NEXT: movd %eax, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: srem_op0_constant:
; AVX: # %bb.0:
-; AVX-NEXT: movw $42, %ax
-; AVX-NEXT: xorl %edx, %edx
-; AVX-NEXT: idivw (%rdi)
-; AVX-NEXT: # kill: def $dx killed $dx def $edx
-; AVX-NEXT: vmovd %edx, %xmm0
+; AVX-NEXT: movswl (%rdi), %eax
+; AVX-NEXT: vcvtsi2ss %eax, %xmm15, %xmm0
+; AVX-NEXT: vmovss {{.*#+}} xmm1 = [4.2E+1,0.0E+0,0.0E+0,0.0E+0]
+; AVX-NEXT: vdivss %xmm0, %xmm1, %xmm0
+; AVX-NEXT: vcvttss2si %xmm0, %ecx
+; AVX-NEXT: imull %eax, %ecx
+; AVX-NEXT: movl $42, %eax
+; AVX-NEXT: subl %ecx, %eax
+; AVX-NEXT: vmovd %eax, %xmm0
; AVX-NEXT: retq
%x = load i16, ptr %p
%b = srem i16 42, %x
@@ -446,19 +456,13 @@ define <4 x i32> @srem_op1_constant(ptr %p) nounwind {
define <4 x i32> @udiv_op0_constant(ptr %p) nounwind {
; SSE-LABEL: udiv_op0_constant:
; SSE: # %bb.0:
-; SSE-NEXT: movl $42, %eax
-; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: divl (%rdi)
+; SSE-NEXT: movl (%rdi), %eax
+; SSE-NEXT: cvtsi2sd %rax, %xmm0
+; SSE-NEXT: movsd {{.*#+}} xmm1 = [4.2E+1,0.0E+0]
+; SSE-NEXT: divsd %xmm0, %xmm1
+; SSE-NEXT: cvttsd2si %xmm1, %rax
; SSE-NEXT: movd %eax, %xmm0
; SSE-NEXT: retq
-;
-; AVX-LABEL: udiv_op0_constant:
-; AVX: # %bb.0:
-; AVX-NEXT: movl $42, %eax
-; AVX-NEXT: xorl %edx, %edx
-; AVX-NEXT: divl (%rdi)
-; AVX-NEXT: vmovd %eax, %xmm0
-; AVX-NEXT: retq
%x = load i32, ptr %p
%b = udiv i32 42, %x
%r = insertelement <4 x i32> undef, i32 %b, i32 0
diff --git a/llvm/test/CodeGen/X86/machine-cp.ll b/llvm/test/CodeGen/X86/machine-cp.ll
index c84a1159ad56a..ffb6340271f26 100644
--- a/llvm/test/CodeGen/X86/machine-cp.ll
+++ b/llvm/test/CodeGen/X86/machine-cp.ll
@@ -6,23 +6,27 @@
define i32 @t1(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: t1:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: testl %esi, %esi
-; CHECK-NEXT: je LBB0_4
-; CHECK-NEXT: ## %bb.1: ## %while.body.preheader
-; CHECK-NEXT: movl %esi, %edx
+; CHECK-NEXT: je LBB0_1
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: LBB0_2: ## %while.body
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: movl %edx, %ecx
-; CHECK-NEXT: cltd
-; CHECK-NEXT: idivl %ecx
-; CHECK-NEXT: testl %edx, %edx
-; CHECK-NEXT: movl %ecx, %eax
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2sd %esi, %xmm0
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: cvtsi2sd %edi, %xmm1
+; CHECK-NEXT: divsd %xmm0, %xmm1
+; CHECK-NEXT: cvttsd2si %xmm1, %ecx
+; CHECK-NEXT: imull %esi, %ecx
+; CHECK-NEXT: movl %edi, %esi
+; CHECK-NEXT: subl %ecx, %esi
+; CHECK-NEXT: movl %eax, %edi
; CHECK-NEXT: jne LBB0_2
; CHECK-NEXT: ## %bb.3: ## %while.end
-; CHECK-NEXT: movl %ecx, %eax
-; CHECK-NEXT: LBB0_4:
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB0_1:
+; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
entry:
%cmp1 = icmp eq i32 %b, 0
diff --git a/llvm/test/CodeGen/X86/machine-trace-metrics-entryBB-critpath.ll b/llvm/test/CodeGen/X86/machine-trace-metrics-entryBB-critpath.ll
index 6e15d0294fda4..290c3ac121851 100644
--- a/llvm/test/CodeGen/X86/machine-trace-metrics-entryBB-critpath.ll
+++ b/llvm/test/CodeGen/X86/machine-trace-metrics-entryBB-critpath.ll
@@ -21,16 +21,17 @@
define i32 @_Z3fooiidd(i32 %a, i32 %b, double %d, double %e) #0 {
; CHECK-LABEL: _Z3fooiidd:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
-; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
-; CHECK-NEXT: leal (%rsi,%rdi), %ecx
+; CHECK-NEXT: addl %edi, %esi
; CHECK-NEXT: cvttsd2si %xmm0, %eax
-; CHECK-NEXT: addl %ecx, %eax
+; CHECK-NEXT: addl %esi, %eax
; CHECK-NEXT: cmpl $3, %edi
-; CHECK-NEXT: cmovll %ecx, %eax
-; CHECK-NEXT: cvttsd2si %xmm1, %ecx
-; CHECK-NEXT: cltd
-; CHECK-NEXT: idivl %ecx
+; CHECK-NEXT: cmovll %esi, %eax
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2sd %eax, %xmm0
+; CHECK-NEXT: cvttpd2dq %xmm1, %xmm1
+; CHECK-NEXT: cvtdq2pd %xmm1, %xmm1
+; CHECK-NEXT: divsd %xmm1, %xmm0
+; CHECK-NEXT: cvttsd2si %xmm0, %eax
; CHECK-NEXT: retq
entry:
%add = add nsw i32 %b, %a
diff --git a/llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll b/llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
index 1b0fd127a9ffa..0b0064a788002 100644
--- a/llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
+++ b/llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
@@ -363,16 +363,47 @@ define i1 @n0_urem_of_maybe_not_power_of_two(i32 %x, i32 %y) {
}
define i1 @n1_urem_by_maybe_power_of_two(i32 %x, i32 %y) {
-; CHECK-LABEL: n1_urem_by_maybe_power_of_two:
-; CHECK: # %bb.0:
-; CHECK-NEXT: movl %edi, %eax
-; CHECK-NEXT: andl $128, %eax
-; CHECK-NEXT: orl $1, %esi
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %esi
-; CHECK-NEXT: testl %edx, %edx
-; CHECK-NEXT: sete %al
-; CHECK-NEXT: retq
+; SSE2-LABEL: n1_urem_by_maybe_power_of_two:
+; SSE2: # %bb.0:
+; SSE2-NEXT: # kill: def $esi killed $esi def $rsi
+; SSE2-NEXT: andl $128, %edi
+; SSE2-NEXT: orl $1, %esi
+; SSE2-NEXT: cvtsi2sd %edi, %xmm0
+; SSE2-NEXT: cvtsi2sd %rsi, %xmm1
+; SSE2-NEXT: divsd %xmm1, %xmm0
+; SSE2-NEXT: cvttsd2si %xmm0, %rax
+; SSE2-NEXT: imull %esi, %eax
+; SSE2-NEXT: cmpl %eax, %edi
+; SSE2-NEXT: sete %al
+; SSE2-NEXT: retq
+;
+; SSE4-LABEL: n1_urem_by_maybe_power_of_two:
+; SSE4: # %bb.0:
+; SSE4-NEXT: # kill: def $esi killed $esi def $rsi
+; SSE4-NEXT: andl $128, %edi
+; SSE4-NEXT: orl $1, %esi
+; SSE4-NEXT: cvtsi2sd %edi, %xmm0
+; SSE4-NEXT: cvtsi2sd %rsi, %xmm1
+; SSE4-NEXT: divsd %xmm1, %xmm0
+; SSE4-NEXT: cvttsd2si %xmm0, %rax
+; SSE4-NEXT: imull %esi, %eax
+; SSE4-NEXT: cmpl %eax, %edi
+; SSE4-NEXT: sete %al
+; SSE4-NEXT: retq
+;
+; AVX2-LABEL: n1_urem_by_maybe_power_of_two:
+; AVX2: # %bb.0:
+; AVX2-NEXT: # kill: def $esi killed $esi def $rsi
+; AVX2-NEXT: andl $128, %edi
+; AVX2-NEXT: orl $1, %esi
+; AVX2-NEXT: vcvtsi2sd %edi, %xmm15, %xmm0
+; AVX2-NEXT: vcvtsi2sd %rsi, %xmm15, %xmm1
+; AVX2-NEXT: vdivsd %xmm1, %xmm0, %xmm0
+; AVX2-NEXT: vcvttsd2si %xmm0, %rax
+; AVX2-NEXT: imull %esi, %eax
+; AVX2-NEXT: cmpl %eax, %edi
+; AVX2-NEXT: sete %al
+; AVX2-NEXT: retq
%t0 = and i32 %x, 128 ; clearly a power-of-two or zero
%t1 = or i32 %y, 1 ; one low bit set, may be a power of two
%t2 = urem i32 %t0, %t1
diff --git a/llvm/test/CodeGen/X86/pr32282.ll b/llvm/test/CodeGen/X86/pr32282.ll
index a5bb7316a9673..f93d6a140c24a 100644
--- a/llvm/test/CodeGen/X86/pr32282.ll
+++ b/llvm/test/CodeGen/X86/pr32282.ll
@@ -35,26 +35,26 @@ define dso_local void @foo(i64 %x) nounwind {
;
; X64-LABEL: foo:
; X64: # %bb.0:
-; X64-NEXT: movq %rdi, %rax
-; X64-NEXT: movq d(%rip), %rcx
-; X64-NEXT: movabsq $3013716102212485120, %rdx # imm = 0x29D2DED3DE400000
-; X64-NEXT: andnq %rdx, %rcx, %rcx
+; X64-NEXT: movq d(%rip), %rax
+; X64-NEXT: movabsq $3013716102212485120, %rcx # imm = 0x29D2DED3DE400000
+; X64-NEXT: andnq %rcx, %rax, %rcx
; X64-NEXT: shrq $21, %rcx
; X64-NEXT: addq $7, %rcx
-; X64-NEXT: movq %rdi, %rdx
-; X64-NEXT: orq %rcx, %rdx
-; X64-NEXT: shrq $32, %rdx
+; X64-NEXT: movq %rdi, %rax
+; X64-NEXT: orq %rcx, %rax
+; X64-NEXT: shrq $32, %rax
; X64-NEXT: je .LBB0_1
; X64-NEXT: # %bb.2:
+; X64-NEXT: movq %rdi, %rax
; X64-NEXT: cqto
; X64-NEXT: idivq %rcx
; X64-NEXT: jmp .LBB0_3
; X64-NEXT: .LBB0_1:
-; X64-NEXT: # kill: def $eax killed $eax killed $rax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %ecx
-; X64-NEXT: # kill: def $eax killed $eax def $rax
-; X64-NEXT: .LBB0_3:
+; X64-NEXT: vcvtusi2sd %ecx, %xmm15, %xmm0
+; X64-NEXT: vcvtusi2sd %edi, %xmm15, %xmm1
+; X64-NEXT: vdivsd %xmm0, %xmm1, %xmm0
+; X64-NEXT: vcvttsd2usi %xmm0, %eax
+; X64-NEXT: .LBB0_3: # %.split
; X64-NEXT: testq %rax, %rax
; X64-NEXT: setne -{{[0-9]+}}(%rsp)
; X64-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/pr35316.ll b/llvm/test/CodeGen/X86/pr35316.ll
index 95e45a631aaaf..7fb85ce17b401 100644
--- a/llvm/test/CodeGen/X86/pr35316.ll
+++ b/llvm/test/CodeGen/X86/pr35316.ll
@@ -26,20 +26,21 @@ define void @foo() {
; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: movl $0, b(%rip)
-; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %esi
-; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %edi
-; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r8d
-; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
-; CHECK-NEXT: cltd
-; CHECK-NEXT: idivl a(%rip)
-; CHECK-NEXT: movl %eax, %ecx
-; CHECK-NEXT: movl c(%rip), %eax
-; CHECK-NEXT: cltd
-; CHECK-NEXT: idivl %r8d
-; CHECK-NEXT: andl %edi, %eax
-; CHECK-NEXT: addl %ecx, %eax
-; CHECK-NEXT: andl %esi, %eax
-; CHECK-NEXT: movl %eax, (%rax)
+; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
+; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %ecx
+; CHECK-NEXT: cvtsi2sdl -{{[0-9]+}}(%rsp), %xmm0
+; CHECK-NEXT: cvtsi2sdl a(%rip), %xmm1
+; CHECK-NEXT: cvtsi2sdl c(%rip), %xmm2
+; CHECK-NEXT: divsd %xmm0, %xmm2
+; CHECK-NEXT: cvttsd2si %xmm2, %edx
+; CHECK-NEXT: andl %ecx, %edx
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2sdl -{{[0-9]+}}(%rsp), %xmm0
+; CHECK-NEXT: divsd %xmm1, %xmm0
+; CHECK-NEXT: cvttsd2si %xmm0, %ecx
+; CHECK-NEXT: addl %edx, %ecx
+; CHECK-NEXT: andl %eax, %ecx
+; CHECK-NEXT: movl %ecx, (%rax)
; CHECK-NEXT: retq
entry:
%e = alloca i32, align 4
diff --git a/llvm/test/CodeGen/X86/shrink_vmul.ll b/llvm/test/CodeGen/X86/shrink_vmul.ll
index 9c6ecf400ead8..b28e537c6654b 100644
--- a/llvm/test/CodeGen/X86/shrink_vmul.ll
+++ b/llvm/test/CodeGen/X86/shrink_vmul.ll
@@ -1990,82 +1990,225 @@ define void @PR34947(ptr %p0, ptr %p1) nounwind {
; X86-SSE-NEXT: pushl %ebx
; X86-SSE-NEXT: pushl %edi
; X86-SSE-NEXT: pushl %esi
-; X86-SSE-NEXT: pushl %eax
-; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-SSE-NEXT: subl $52, %esp
+; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-SSE-NEXT: movzwl 16(%eax), %edx
-; X86-SSE-NEXT: movl %edx, (%esp) # 4-byte Spill
-; X86-SSE-NEXT: movdqa (%eax), %xmm2
-; X86-SSE-NEXT: pxor %xmm1, %xmm1
-; X86-SSE-NEXT: movdqa %xmm2, %xmm0
-; X86-SSE-NEXT: pextrw $7, %xmm2, %eax
-; X86-SSE-NEXT: pextrw $4, %xmm2, %esi
-; X86-SSE-NEXT: pextrw $1, %xmm2, %edi
-; X86-SSE-NEXT: pextrw $0, %xmm2, %ebx
-; X86-SSE-NEXT: pextrw $3, %xmm2, %ebp
-; X86-SSE-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]
-; X86-SSE-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
-; X86-SSE-NEXT: xorl %edx, %edx
-; X86-SSE-NEXT: divl 28(%ecx)
-; X86-SSE-NEXT: movd %edx, %xmm1
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,2,3]
-; X86-SSE-NEXT: movd %xmm3, %eax
-; X86-SSE-NEXT: xorl %edx, %edx
-; X86-SSE-NEXT: divl 24(%ecx)
-; X86-SSE-NEXT: movd %edx, %xmm3
-; X86-SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
+; X86-SSE-NEXT: movdqa (%eax), %xmm1
+; X86-SSE-NEXT: movdqa 16(%esi), %xmm4
+; X86-SSE-NEXT: pxor %xmm7, %xmm7
+; X86-SSE-NEXT: movdqa %xmm1, %xmm5
+; X86-SSE-NEXT: punpckhwd {{.*#+}} xmm5 = xmm5[4],xmm7[4],xmm5[5],xmm7[5],xmm5[6],xmm7[6],xmm5[7],xmm7[7]
+; X86-SSE-NEXT: movdqa %xmm4, %xmm0
+; X86-SSE-NEXT: punpckhdq {{.*#+}} xmm0 = xmm0[2],xmm7[2],xmm0[3],xmm7[3]
+; X86-SSE-NEXT: movq {{.*#+}} xmm3 = [4.503599627370496E+15,0.0E+0]
+; X86-SSE-NEXT: por %xmm3, %xmm0
+; X86-SSE-NEXT: subsd %xmm3, %xmm0
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[2,3,2,3]
+; X86-SSE-NEXT: movd %xmm2, %eax
+; X86-SSE-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-SSE-NEXT: xorps %xmm2, %xmm2
+; X86-SSE-NEXT: cvtsi2sd %eax, %xmm2
+; X86-SSE-NEXT: divsd %xmm0, %xmm2
+; X86-SSE-NEXT: movupd %xmm2, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; X86-SSE-NEXT: movdqa %xmm4, %xmm0
+; X86-SSE-NEXT: psrldq {{.*#+}} xmm0 = xmm0[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; X86-SSE-NEXT: por %xmm3, %xmm0
+; X86-SSE-NEXT: subsd %xmm3, %xmm0
+; X86-SSE-NEXT: pextrw $7, %xmm1, %eax
+; X86-SSE-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-SSE-NEXT: xorps %xmm2, %xmm2
+; X86-SSE-NEXT: cvtsi2sd %eax, %xmm2
+; X86-SSE-NEXT: divsd %xmm0, %xmm2
+; X86-SSE-NEXT: xorpd %xmm0, %xmm0
+; X86-SSE-NEXT: movss {{.*#+}} xmm0 = xmm4[0],xmm0[1,2,3]
+; X86-SSE-NEXT: psrlq $32, %xmm4
+; X86-SSE-NEXT: por %xmm3, %xmm4
+; X86-SSE-NEXT: subsd %xmm3, %xmm4
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,1,1]
+; X86-SSE-NEXT: movd %xmm5, %eax
+; X86-SSE-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-SSE-NEXT: xorps %xmm5, %xmm5
+; X86-SSE-NEXT: cvtsi2sd %eax, %xmm5
+; X86-SSE-NEXT: divsd %xmm4, %xmm5
+; X86-SSE-NEXT: orps %xmm3, %xmm0
+; X86-SSE-NEXT: subsd %xmm3, %xmm0
+; X86-SSE-NEXT: movdqu %xmm1, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; X86-SSE-NEXT: pextrw $4, %xmm1, %edi
+; X86-SSE-NEXT: cvtsi2sd %edi, %xmm6
+; X86-SSE-NEXT: divsd %xmm0, %xmm6
+; X86-SSE-NEXT: movdqa %xmm1, %xmm0
+; X86-SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm7[0],xmm0[1],xmm7[1],xmm0[2],xmm7[2],xmm0[3],xmm7[3]
+; X86-SSE-NEXT: movdqa (%esi), %xmm1
+; X86-SSE-NEXT: movdqa %xmm1, %xmm4
+; X86-SSE-NEXT: punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm7[2],xmm4[3],xmm7[3]
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
+; X86-SSE-NEXT: movd %xmm0, %eax
+; X86-SSE-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-SSE-NEXT: por %xmm3, %xmm4
+; X86-SSE-NEXT: subsd %xmm3, %xmm4
+; X86-SSE-NEXT: movdqa %xmm3, %xmm0
+; X86-SSE-NEXT: xorps %xmm7, %xmm7
+; X86-SSE-NEXT: cvtsi2sd %eax, %xmm7
+; X86-SSE-NEXT: divsd %xmm4, %xmm7
+; X86-SSE-NEXT: movdqu {{[-0-9]+}}(%e{{[sb]}}p), %xmm3 # 16-byte Reload
+; X86-SSE-NEXT: pextrw $3, %xmm3, %ecx
+; X86-SSE-NEXT: movl %ecx, (%esp) # 4-byte Spill
+; X86-SSE-NEXT: pextrw $1, %xmm3, %ebp
+; X86-SSE-NEXT: pextrw $0, %xmm3, %ebx
+; X86-SSE-NEXT: movsd {{.*#+}} xmm4 = [2.147483648E+9,0.0E+0]
+; X86-SSE-NEXT: movupd {{[-0-9]+}}(%e{{[sb]}}p), %xmm3 # 16-byte Reload
+; X86-SSE-NEXT: cvttsd2si %xmm3, %edx
+; X86-SSE-NEXT: subsd %xmm4, %xmm3
+; X86-SSE-NEXT: cvttsd2si %xmm3, %eax
+; X86-SSE-NEXT: movdqa %xmm1, %xmm3
+; X86-SSE-NEXT: psrldq {{.*#+}} xmm3 = xmm3[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; X86-SSE-NEXT: por %xmm0, %xmm3
+; X86-SSE-NEXT: subsd %xmm0, %xmm3
+; X86-SSE-NEXT: xorps %xmm0, %xmm0
+; X86-SSE-NEXT: cvtsi2sd %ecx, %xmm0
+; X86-SSE-NEXT: divsd %xmm3, %xmm0
+; X86-SSE-NEXT: movl %edx, %ecx
+; X86-SSE-NEXT: sarl $31, %ecx
+; X86-SSE-NEXT: andl %ecx, %eax
+; X86-SSE-NEXT: orl %edx, %eax
+; X86-SSE-NEXT: imull 24(%esi), %eax
+; X86-SSE-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-SSE-NEXT: subl %eax, %edx
+; X86-SSE-NEXT: cvttsd2si %xmm2, %eax
+; X86-SSE-NEXT: movapd %xmm4, %xmm3
+; X86-SSE-NEXT: subsd %xmm4, %xmm2
+; X86-SSE-NEXT: cvttsd2si %xmm2, %ecx
+; X86-SSE-NEXT: movd %edx, %xmm4
+; X86-SSE-NEXT: movl %eax, %edx
+; X86-SSE-NEXT: sarl $31, %edx
+; X86-SSE-NEXT: andl %edx, %ecx
+; X86-SSE-NEXT: orl %eax, %ecx
+; X86-SSE-NEXT: imull 28(%esi), %ecx
+; X86-SSE-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-SSE-NEXT: subl %ecx, %edx
+; X86-SSE-NEXT: cvttsd2si %xmm5, %eax
+; X86-SSE-NEXT: subsd %xmm3, %xmm5
+; X86-SSE-NEXT: cvttsd2si %xmm5, %ecx
+; X86-SSE-NEXT: movd %edx, %xmm5
+; X86-SSE-NEXT: movl %eax, %edx
+; X86-SSE-NEXT: sarl $31, %edx
+; X86-SSE-NEXT: andl %edx, %ecx
+; X86-SSE-NEXT: orl %eax, %ecx
+; X86-SSE-NEXT: imull 20(%esi), %ecx
+; X86-SSE-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-SSE-NEXT: subl %ecx, %edx
+; X86-SSE-NEXT: cvttsd2si %xmm6, %eax
+; X86-SSE-NEXT: subsd %xmm3, %xmm6
+; X86-SSE-NEXT: cvttsd2si %xmm6, %ecx
+; X86-SSE-NEXT: movd %edx, %xmm6
+; X86-SSE-NEXT: movl %eax, %edx
+; X86-SSE-NEXT: sarl $31, %edx
+; X86-SSE-NEXT: andl %edx, %ecx
+; X86-SSE-NEXT: orl %eax, %ecx
+; X86-SSE-NEXT: imull 16(%esi), %ecx
+; X86-SSE-NEXT: subl %ecx, %edi
+; X86-SSE-NEXT: cvttsd2si %xmm7, %eax
+; X86-SSE-NEXT: subsd %xmm3, %xmm7
+; X86-SSE-NEXT: cvttsd2si %xmm7, %ecx
+; X86-SSE-NEXT: movd %edi, %xmm2
+; X86-SSE-NEXT: movl %eax, %edx
+; X86-SSE-NEXT: sarl $31, %edx
+; X86-SSE-NEXT: andl %edx, %ecx
+; X86-SSE-NEXT: orl %eax, %ecx
+; X86-SSE-NEXT: movl %esi, %edx
+; X86-SSE-NEXT: imull 8(%esi), %ecx
+; X86-SSE-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-SSE-NEXT: subl %ecx, %eax
+; X86-SSE-NEXT: cvttsd2si %xmm0, %esi
+; X86-SSE-NEXT: subsd %xmm3, %xmm0
+; X86-SSE-NEXT: movapd %xmm3, %xmm7
+; X86-SSE-NEXT: cvttsd2si %xmm0, %edi
+; X86-SSE-NEXT: movd %eax, %xmm3
; X86-SSE-NEXT: movl %esi, %eax
-; X86-SSE-NEXT: xorl %edx, %edx
-; X86-SSE-NEXT: divl 16(%ecx)
+; X86-SSE-NEXT: sarl $31, %eax
+; X86-SSE-NEXT: andl %eax, %edi
+; X86-SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
+; X86-SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm6[0],xmm2[1],xmm6[1]
+; X86-SSE-NEXT: xorpd %xmm0, %xmm0
+; X86-SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; X86-SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
+; X86-SSE-NEXT: psrlq $32, %xmm1
+; X86-SSE-NEXT: movq {{.*#+}} xmm5 = [4.503599627370496E+15,0.0E+0]
+; X86-SSE-NEXT: por %xmm5, %xmm1
+; X86-SSE-NEXT: subsd %xmm5, %xmm1
+; X86-SSE-NEXT: xorps %xmm4, %xmm4
+; X86-SSE-NEXT: cvtsi2sd %ebp, %xmm4
+; X86-SSE-NEXT: divsd %xmm1, %xmm4
+; X86-SSE-NEXT: orl %esi, %edi
+; X86-SSE-NEXT: imull 12(%edx), %edi
+; X86-SSE-NEXT: movl %edx, %esi
+; X86-SSE-NEXT: movl (%esp), %edx # 4-byte Reload
+; X86-SSE-NEXT: subl %edi, %edx
+; X86-SSE-NEXT: cvttsd2si %xmm4, %eax
+; X86-SSE-NEXT: subsd %xmm7, %xmm4
+; X86-SSE-NEXT: cvttsd2si %xmm4, %ecx
; X86-SSE-NEXT: movd %edx, %xmm1
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; X86-SSE-NEXT: movd %xmm0, %eax
-; X86-SSE-NEXT: xorl %edx, %edx
-; X86-SSE-NEXT: divl 20(%ecx)
-; X86-SSE-NEXT: movd %edx, %xmm0
-; X86-SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; X86-SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
-; X86-SSE-NEXT: movl %edi, %eax
-; X86-SSE-NEXT: xorl %edx, %edx
-; X86-SSE-NEXT: divl 4(%ecx)
-; X86-SSE-NEXT: movd %edx, %xmm3
-; X86-SSE-NEXT: movl %ebx, %eax
-; X86-SSE-NEXT: xorl %edx, %edx
-; X86-SSE-NEXT: divl (%ecx)
-; X86-SSE-NEXT: movd %edx, %xmm0
-; X86-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
-; X86-SSE-NEXT: movl %ebp, %eax
-; X86-SSE-NEXT: xorl %edx, %edx
-; X86-SSE-NEXT: divl 12(%ecx)
-; X86-SSE-NEXT: movd %edx, %xmm3
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]
-; X86-SSE-NEXT: movd %xmm2, %eax
-; X86-SSE-NEXT: xorl %edx, %edx
-; X86-SSE-NEXT: divl 8(%ecx)
-; X86-SSE-NEXT: movd %edx, %xmm2
-; X86-SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
-; X86-SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; X86-SSE-NEXT: movl (%esp), %eax # 4-byte Reload
-; X86-SSE-NEXT: xorl %edx, %edx
-; X86-SSE-NEXT: divl 32(%ecx)
-; X86-SSE-NEXT: movdqa {{.*#+}} xmm2 = [8199,8199,8199,8199]
+; X86-SSE-NEXT: movl %eax, %edx
+; X86-SSE-NEXT: sarl $31, %edx
+; X86-SSE-NEXT: andl %edx, %ecx
+; X86-SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
+; X86-SSE-NEXT: orl %eax, %ecx
+; X86-SSE-NEXT: imull 4(%esi), %ecx
+; X86-SSE-NEXT: subl %ecx, %ebp
+; X86-SSE-NEXT: orps %xmm5, %xmm0
+; X86-SSE-NEXT: subsd %xmm5, %xmm0
+; X86-SSE-NEXT: xorps %xmm4, %xmm4
+; X86-SSE-NEXT: cvtsi2sd %ebx, %xmm4
+; X86-SSE-NEXT: divsd %xmm0, %xmm4
+; X86-SSE-NEXT: movd %ebp, %xmm1
+; X86-SSE-NEXT: cvttsd2si %xmm4, %eax
+; X86-SSE-NEXT: movl %eax, %ecx
+; X86-SSE-NEXT: sarl $31, %ecx
+; X86-SSE-NEXT: subsd %xmm7, %xmm4
+; X86-SSE-NEXT: cvttsd2si %xmm4, %edx
+; X86-SSE-NEXT: andl %ecx, %edx
+; X86-SSE-NEXT: orl %eax, %edx
+; X86-SSE-NEXT: movl %esi, %edi
+; X86-SSE-NEXT: imull (%esi), %edx
+; X86-SSE-NEXT: subl %edx, %ebx
+; X86-SSE-NEXT: movd %ebx, %xmm0
+; X86-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-SSE-NEXT: movzwl 16(%eax), %eax
+; X86-SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]
+; X86-SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X86-SSE-NEXT: orpd %xmm5, %xmm1
+; X86-SSE-NEXT: subsd %xmm5, %xmm1
+; X86-SSE-NEXT: xorps %xmm3, %xmm3
+; X86-SSE-NEXT: cvtsi2sd %eax, %xmm3
+; X86-SSE-NEXT: divsd %xmm1, %xmm3
+; X86-SSE-NEXT: cvttsd2si %xmm3, %edx
+; X86-SSE-NEXT: subsd %xmm7, %xmm3
+; X86-SSE-NEXT: cvttsd2si %xmm3, %ecx
+; X86-SSE-NEXT: movdqa {{.*#+}} xmm1 = [8199,8199,8199,8199]
; X86-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
-; X86-SSE-NEXT: pmuludq %xmm2, %xmm0
+; X86-SSE-NEXT: pmuludq %xmm1, %xmm0
; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; X86-SSE-NEXT: pmuludq %xmm2, %xmm3
+; X86-SSE-NEXT: pmuludq %xmm1, %xmm3
; X86-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
; X86-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
-; X86-SSE-NEXT: pmuludq %xmm2, %xmm1
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
-; X86-SSE-NEXT: pmuludq %xmm2, %xmm3
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
+; X86-SSE-NEXT: pmuludq %xmm1, %xmm2
+; X86-SSE-NEXT: pmuludq %xmm1, %xmm3
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; X86-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3]
; X86-SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
-; X86-SSE-NEXT: imull $8199, %edx, %eax # imm = 0x2007
-; X86-SSE-NEXT: movl %eax, (%eax)
+; X86-SSE-NEXT: movl %edx, %esi
+; X86-SSE-NEXT: sarl $31, %esi
+; X86-SSE-NEXT: andl %esi, %ecx
+; X86-SSE-NEXT: orl %edx, %ecx
+; X86-SSE-NEXT: imull 32(%edi), %ecx
; X86-SSE-NEXT: movdqa %xmm1, (%eax)
; X86-SSE-NEXT: movdqa %xmm0, (%eax)
-; X86-SSE-NEXT: addl $4, %esp
+; X86-SSE-NEXT: subl %ecx, %eax
+; X86-SSE-NEXT: imull $8199, %eax, %eax # imm = 0x2007
+; X86-SSE-NEXT: movl %eax, (%eax)
+; X86-SSE-NEXT: addl $52, %esp
; X86-SSE-NEXT: popl %esi
; X86-SSE-NEXT: popl %edi
; X86-SSE-NEXT: popl %ebx
@@ -2078,64 +2221,183 @@ define void @PR34947(ptr %p0, ptr %p1) nounwind {
; X86-AVX1-NEXT: pushl %ebx
; X86-AVX1-NEXT: pushl %edi
; X86-AVX1-NEXT: pushl %esi
-; X86-AVX1-NEXT: subl $16, %esp
-; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-AVX1-NEXT: subl $12, %esp
; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
+; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-AVX1-NEXT: vpmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
-; X86-AVX1-NEXT: vpmovzxwd {{.*#+}} xmm2 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
-; X86-AVX1-NEXT: vmovd %xmm2, %eax
-; X86-AVX1-NEXT: xorl %edx, %edx
-; X86-AVX1-NEXT: divl 32(%ecx)
-; X86-AVX1-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-AVX1-NEXT: vpextrd $3, %xmm1, %eax
-; X86-AVX1-NEXT: xorl %edx, %edx
-; X86-AVX1-NEXT: divl 28(%ecx)
-; X86-AVX1-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-AVX1-NEXT: vpextrd $2, %xmm1, %eax
-; X86-AVX1-NEXT: xorl %edx, %edx
-; X86-AVX1-NEXT: divl 24(%ecx)
+; X86-AVX1-NEXT: vpmovzxwd {{.*#+}} xmm5 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
+; X86-AVX1-NEXT: vmovq {{.*#+}} xmm0 = [4.503599627370496E+15,0.0E+0]
+; X86-AVX1-NEXT: vmovsd {{.*#+}} xmm2 = [2.147483648E+9,0.0E+0]
+; X86-AVX1-NEXT: vmovdqa 16(%eax), %xmm6
+; X86-AVX1-NEXT: vpsrldq {{.*#+}} xmm3 = xmm6[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; X86-AVX1-NEXT: vpor %xmm0, %xmm3, %xmm3
+; X86-AVX1-NEXT: vsubsd %xmm0, %xmm3, %xmm3
+; X86-AVX1-NEXT: vpshufd {{.*#+}} xmm4 = xmm5[3,3,3,3]
+; X86-AVX1-NEXT: vcvtdq2pd %xmm4, %xmm4
+; X86-AVX1-NEXT: vdivsd %xmm3, %xmm4, %xmm3
+; X86-AVX1-NEXT: vcvttsd2si %xmm3, %edx
+; X86-AVX1-NEXT: vsubsd %xmm2, %xmm3, %xmm3
+; X86-AVX1-NEXT: vcvttsd2si %xmm3, %esi
+; X86-AVX1-NEXT: vxorpd %xmm4, %xmm4, %xmm4
+; X86-AVX1-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm6[2],xmm4[2],xmm6[3],xmm4[3]
+; X86-AVX1-NEXT: vpor %xmm0, %xmm3, %xmm3
+; X86-AVX1-NEXT: vsubsd %xmm0, %xmm3, %xmm3
+; X86-AVX1-NEXT: vpshufd {{.*#+}} xmm7 = xmm5[2,3,2,3]
+; X86-AVX1-NEXT: vcvtdq2pd %xmm7, %xmm7
+; X86-AVX1-NEXT: vdivsd %xmm3, %xmm7, %xmm3
+; X86-AVX1-NEXT: vcvttsd2si %xmm3, %edi
+; X86-AVX1-NEXT: vsubsd %xmm2, %xmm3, %xmm3
+; X86-AVX1-NEXT: vcvttsd2si %xmm3, %ebx
+; X86-AVX1-NEXT: vpsrlq $32, %xmm6, %xmm3
+; X86-AVX1-NEXT: vpor %xmm0, %xmm3, %xmm3
+; X86-AVX1-NEXT: vsubsd %xmm0, %xmm3, %xmm3
+; X86-AVX1-NEXT: vpshufd {{.*#+}} xmm7 = xmm5[1,1,1,1]
+; X86-AVX1-NEXT: vcvtdq2pd %xmm7, %xmm7
+; X86-AVX1-NEXT: vdivsd %xmm3, %xmm7, %xmm7
+; X86-AVX1-NEXT: vpmovzxwd {{.*#+}} xmm3 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
+; X86-AVX1-NEXT: movl %edx, %eax
+; X86-AVX1-NEXT: sarl $31, %eax
+; X86-AVX1-NEXT: andl %eax, %esi
+; X86-AVX1-NEXT: vcvttsd2si %xmm7, %ebp
+; X86-AVX1-NEXT: vsubsd %xmm2, %xmm7, %xmm7
+; X86-AVX1-NEXT: vcvttsd2si %xmm7, %eax
+; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm6 = xmm6[0,1],xmm4[2,3,4,5,6,7]
+; X86-AVX1-NEXT: vpor %xmm0, %xmm6, %xmm6
+; X86-AVX1-NEXT: vsubsd %xmm0, %xmm6, %xmm6
+; X86-AVX1-NEXT: vcvtdq2pd %xmm5, %xmm7
+; X86-AVX1-NEXT: vdivsd %xmm6, %xmm7, %xmm7
+; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-AVX1-NEXT: vmovdqa (%ecx), %xmm6
+; X86-AVX1-NEXT: orl %edx, %esi
+; X86-AVX1-NEXT: imull 28(%ecx), %esi
+; X86-AVX1-NEXT: vpextrd $3, %xmm5, %ecx
+; X86-AVX1-NEXT: subl %esi, %ecx
+; X86-AVX1-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-AVX1-NEXT: movl %edi, %edx
+; X86-AVX1-NEXT: sarl $31, %edx
+; X86-AVX1-NEXT: andl %edx, %ebx
+; X86-AVX1-NEXT: orl %edi, %ebx
+; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-AVX1-NEXT: imull 24(%ecx), %ebx
+; X86-AVX1-NEXT: vpextrd $2, %xmm5, %edx
+; X86-AVX1-NEXT: subl %ebx, %edx
; X86-AVX1-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-AVX1-NEXT: vpextrd $1, %xmm1, %eax
-; X86-AVX1-NEXT: xorl %edx, %edx
-; X86-AVX1-NEXT: divl 20(%ecx)
-; X86-AVX1-NEXT: movl %edx, (%esp) # 4-byte Spill
-; X86-AVX1-NEXT: vmovd %xmm1, %eax
-; X86-AVX1-NEXT: xorl %edx, %edx
-; X86-AVX1-NEXT: divl 16(%ecx)
-; X86-AVX1-NEXT: movl %edx, %ebp
-; X86-AVX1-NEXT: vpextrd $3, %xmm0, %eax
-; X86-AVX1-NEXT: xorl %edx, %edx
-; X86-AVX1-NEXT: divl 12(%ecx)
-; X86-AVX1-NEXT: movl %edx, %ebx
-; X86-AVX1-NEXT: vpextrd $2, %xmm0, %eax
-; X86-AVX1-NEXT: xorl %edx, %edx
-; X86-AVX1-NEXT: divl 8(%ecx)
+; X86-AVX1-NEXT: movl %ebp, %esi
+; X86-AVX1-NEXT: sarl $31, %esi
+; X86-AVX1-NEXT: andl %esi, %eax
+; X86-AVX1-NEXT: orl %ebp, %eax
+; X86-AVX1-NEXT: imull 20(%ecx), %eax
+; X86-AVX1-NEXT: movl %ecx, %edx
+; X86-AVX1-NEXT: vpextrd $1, %xmm5, %ecx
+; X86-AVX1-NEXT: subl %eax, %ecx
+; X86-AVX1-NEXT: movl %ecx, (%esp) # 4-byte Spill
+; X86-AVX1-NEXT: vcvttsd2si %xmm7, %eax
+; X86-AVX1-NEXT: movl %eax, %edi
+; X86-AVX1-NEXT: sarl $31, %edi
+; X86-AVX1-NEXT: vsubsd %xmm2, %xmm7, %xmm7
+; X86-AVX1-NEXT: vcvttsd2si %xmm7, %ebx
+; X86-AVX1-NEXT: andl %edi, %ebx
+; X86-AVX1-NEXT: orl %eax, %ebx
+; X86-AVX1-NEXT: imull 16(%edx), %ebx
+; X86-AVX1-NEXT: vmovd %xmm5, %edi
+; X86-AVX1-NEXT: subl %ebx, %edi
+; X86-AVX1-NEXT: vpsrldq {{.*#+}} xmm5 = xmm6[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; X86-AVX1-NEXT: vpor %xmm0, %xmm5, %xmm5
+; X86-AVX1-NEXT: vsubsd %xmm0, %xmm5, %xmm5
+; X86-AVX1-NEXT: vpshufd {{.*#+}} xmm7 = xmm1[3,3,3,3]
+; X86-AVX1-NEXT: vcvtdq2pd %xmm7, %xmm7
+; X86-AVX1-NEXT: vdivsd %xmm5, %xmm7, %xmm5
+; X86-AVX1-NEXT: vcvttsd2si %xmm5, %eax
+; X86-AVX1-NEXT: movl %eax, %ebx
+; X86-AVX1-NEXT: sarl $31, %ebx
+; X86-AVX1-NEXT: vsubsd %xmm2, %xmm5, %xmm5
+; X86-AVX1-NEXT: vcvttsd2si %xmm5, %ebp
+; X86-AVX1-NEXT: andl %ebx, %ebp
+; X86-AVX1-NEXT: orl %eax, %ebp
+; X86-AVX1-NEXT: imull 12(%edx), %ebp
+; X86-AVX1-NEXT: vpextrd $3, %xmm1, %ebx
+; X86-AVX1-NEXT: subl %ebp, %ebx
+; X86-AVX1-NEXT: vpunpckhdq {{.*#+}} xmm5 = xmm6[2],xmm4[2],xmm6[3],xmm4[3]
+; X86-AVX1-NEXT: vpor %xmm0, %xmm5, %xmm5
+; X86-AVX1-NEXT: vsubsd %xmm0, %xmm5, %xmm5
+; X86-AVX1-NEXT: vpshufd {{.*#+}} xmm7 = xmm1[2,3,2,3]
+; X86-AVX1-NEXT: vcvtdq2pd %xmm7, %xmm7
+; X86-AVX1-NEXT: vdivsd %xmm5, %xmm7, %xmm5
+; X86-AVX1-NEXT: vcvttsd2si %xmm5, %ecx
+; X86-AVX1-NEXT: movl %ecx, %ebp
+; X86-AVX1-NEXT: sarl $31, %ebp
+; X86-AVX1-NEXT: vsubsd %xmm2, %xmm5, %xmm5
+; X86-AVX1-NEXT: vcvttsd2si %xmm5, %eax
+; X86-AVX1-NEXT: andl %ebp, %eax
+; X86-AVX1-NEXT: orl %ecx, %eax
+; X86-AVX1-NEXT: imull 8(%edx), %eax
; X86-AVX1-NEXT: movl %edx, %esi
-; X86-AVX1-NEXT: vpextrd $1, %xmm0, %eax
-; X86-AVX1-NEXT: xorl %edx, %edx
-; X86-AVX1-NEXT: divl 4(%ecx)
-; X86-AVX1-NEXT: movl %edx, %edi
-; X86-AVX1-NEXT: vmovd %xmm0, %eax
-; X86-AVX1-NEXT: xorl %edx, %edx
-; X86-AVX1-NEXT: divl (%ecx)
-; X86-AVX1-NEXT: vmovd %edx, %xmm0
-; X86-AVX1-NEXT: vpinsrd $1, %edi, %xmm0, %xmm0
-; X86-AVX1-NEXT: vpinsrd $2, %esi, %xmm0, %xmm0
-; X86-AVX1-NEXT: vpinsrd $3, %ebx, %xmm0, %xmm0
-; X86-AVX1-NEXT: vmovd %ebp, %xmm1
-; X86-AVX1-NEXT: vpinsrd $1, (%esp), %xmm1, %xmm1 # 4-byte Folded Reload
-; X86-AVX1-NEXT: vpinsrd $2, {{[-0-9]+}}(%e{{[sb]}}p), %xmm1, %xmm1 # 4-byte Folded Reload
-; X86-AVX1-NEXT: vpinsrd $3, {{[-0-9]+}}(%e{{[sb]}}p), %xmm1, %xmm1 # 4-byte Folded Reload
-; X86-AVX1-NEXT: imull $8199, {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
-; X86-AVX1-NEXT: # imm = 0x2007
-; X86-AVX1-NEXT: movl %eax, (%eax)
+; X86-AVX1-NEXT: vpextrd $2, %xmm1, %ebp
+; X86-AVX1-NEXT: subl %eax, %ebp
+; X86-AVX1-NEXT: vpsrlq $32, %xmm6, %xmm5
+; X86-AVX1-NEXT: vpor %xmm0, %xmm5, %xmm5
+; X86-AVX1-NEXT: vsubsd %xmm0, %xmm5, %xmm5
+; X86-AVX1-NEXT: vpshufd {{.*#+}} xmm7 = xmm1[1,1,1,1]
+; X86-AVX1-NEXT: vcvtdq2pd %xmm7, %xmm7
+; X86-AVX1-NEXT: vdivsd %xmm5, %xmm7, %xmm5
+; X86-AVX1-NEXT: vcvttsd2si %xmm5, %edx
+; X86-AVX1-NEXT: movl %edx, %ecx
+; X86-AVX1-NEXT: sarl $31, %ecx
+; X86-AVX1-NEXT: vsubsd %xmm2, %xmm5, %xmm5
+; X86-AVX1-NEXT: vcvttsd2si %xmm5, %eax
+; X86-AVX1-NEXT: andl %ecx, %eax
+; X86-AVX1-NEXT: orl %edx, %eax
+; X86-AVX1-NEXT: imull 4(%esi), %eax
+; X86-AVX1-NEXT: vpextrd $1, %xmm1, %esi
+; X86-AVX1-NEXT: subl %eax, %esi
+; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm6[0,1],xmm4[2,3,4,5,6,7]
+; X86-AVX1-NEXT: vpor %xmm0, %xmm4, %xmm4
+; X86-AVX1-NEXT: vsubsd %xmm0, %xmm4, %xmm4
+; X86-AVX1-NEXT: vcvtdq2pd %xmm1, %xmm5
+; X86-AVX1-NEXT: vdivsd %xmm4, %xmm5, %xmm4
+; X86-AVX1-NEXT: vcvttsd2si %xmm4, %ecx
+; X86-AVX1-NEXT: movl %ecx, %edx
+; X86-AVX1-NEXT: sarl $31, %edx
+; X86-AVX1-NEXT: vsubsd %xmm2, %xmm4, %xmm4
+; X86-AVX1-NEXT: vcvttsd2si %xmm4, %eax
+; X86-AVX1-NEXT: andl %edx, %eax
+; X86-AVX1-NEXT: orl %ecx, %eax
+; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-AVX1-NEXT: imull (%edx), %eax
+; X86-AVX1-NEXT: vmovd %xmm1, %ecx
+; X86-AVX1-NEXT: subl %eax, %ecx
+; X86-AVX1-NEXT: vmovd %ecx, %xmm1
+; X86-AVX1-NEXT: vpinsrd $1, %esi, %xmm1, %xmm1
+; X86-AVX1-NEXT: vmovss {{.*#+}} xmm4 = mem[0],zero,zero,zero
+; X86-AVX1-NEXT: movl %edx, %esi
+; X86-AVX1-NEXT: vorpd %xmm0, %xmm4, %xmm4
+; X86-AVX1-NEXT: vsubsd %xmm0, %xmm4, %xmm0
+; X86-AVX1-NEXT: vcvtdq2pd %xmm3, %xmm4
+; X86-AVX1-NEXT: vdivsd %xmm0, %xmm4, %xmm0
+; X86-AVX1-NEXT: vpinsrd $2, %ebp, %xmm1, %xmm1
+; X86-AVX1-NEXT: vcvttsd2si %xmm0, %ebp
+; X86-AVX1-NEXT: vsubsd %xmm2, %xmm0, %xmm0
+; X86-AVX1-NEXT: vpinsrd $3, %ebx, %xmm1, %xmm1
+; X86-AVX1-NEXT: vcvttsd2si %xmm0, %eax
+; X86-AVX1-NEXT: vmovd %edi, %xmm0
+; X86-AVX1-NEXT: vpinsrd $1, (%esp), %xmm0, %xmm0 # 4-byte Folded Reload
+; X86-AVX1-NEXT: vpinsrd $2, {{[-0-9]+}}(%e{{[sb]}}p), %xmm0, %xmm0 # 4-byte Folded Reload
+; X86-AVX1-NEXT: vmovd %xmm3, %edx
; X86-AVX1-NEXT: vbroadcastss {{.*#+}} xmm2 = [8199,8199,8199,8199]
-; X86-AVX1-NEXT: vpmulld %xmm2, %xmm0, %xmm0
; X86-AVX1-NEXT: vpmulld %xmm2, %xmm1, %xmm1
-; X86-AVX1-NEXT: vmovdqa %xmm1, (%eax)
+; X86-AVX1-NEXT: vpinsrd $3, {{[-0-9]+}}(%e{{[sb]}}p), %xmm0, %xmm0 # 4-byte Folded Reload
+; X86-AVX1-NEXT: vpmulld %xmm2, %xmm0, %xmm0
+; X86-AVX1-NEXT: movl %ebp, %ecx
+; X86-AVX1-NEXT: sarl $31, %ecx
+; X86-AVX1-NEXT: andl %ecx, %eax
+; X86-AVX1-NEXT: orl %ebp, %eax
+; X86-AVX1-NEXT: imull 32(%esi), %eax
; X86-AVX1-NEXT: vmovdqa %xmm0, (%eax)
-; X86-AVX1-NEXT: addl $16, %esp
+; X86-AVX1-NEXT: vmovdqa %xmm1, (%eax)
+; X86-AVX1-NEXT: subl %eax, %edx
+; X86-AVX1-NEXT: imull $8199, %edx, %eax # imm = 0x2007
+; X86-AVX1-NEXT: movl %eax, (%eax)
+; X86-AVX1-NEXT: addl $12, %esp
; X86-AVX1-NEXT: popl %esi
; X86-AVX1-NEXT: popl %edi
; X86-AVX1-NEXT: popl %ebx
@@ -2200,138 +2462,235 @@ define void @PR34947(ptr %p0, ptr %p1) nounwind {
;
; X64-SSE-LABEL: PR34947:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: movzwl 16(%rdi), %ecx
-; X64-SSE-NEXT: movdqa (%rdi), %xmm2
+; X64-SSE-NEXT: movdqa (%rdi), %xmm0
; X64-SSE-NEXT: pxor %xmm1, %xmm1
-; X64-SSE-NEXT: movdqa %xmm2, %xmm0
-; X64-SSE-NEXT: pextrw $7, %xmm2, %eax
-; X64-SSE-NEXT: pextrw $4, %xmm2, %edi
-; X64-SSE-NEXT: pextrw $1, %xmm2, %r8d
-; X64-SSE-NEXT: pextrw $0, %xmm2, %r9d
-; X64-SSE-NEXT: pextrw $3, %xmm2, %r10d
-; X64-SSE-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]
-; X64-SSE-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
-; X64-SSE-NEXT: xorl %edx, %edx
-; X64-SSE-NEXT: divl 28(%rsi)
-; X64-SSE-NEXT: movd %edx, %xmm1
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,2,3]
-; X64-SSE-NEXT: movd %xmm3, %eax
-; X64-SSE-NEXT: xorl %edx, %edx
-; X64-SSE-NEXT: divl 24(%rsi)
-; X64-SSE-NEXT: movd %edx, %xmm3
-; X64-SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
-; X64-SSE-NEXT: movl %edi, %eax
-; X64-SSE-NEXT: xorl %edx, %edx
-; X64-SSE-NEXT: divl 16(%rsi)
-; X64-SSE-NEXT: movd %edx, %xmm1
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; X64-SSE-NEXT: movd %xmm0, %eax
-; X64-SSE-NEXT: xorl %edx, %edx
-; X64-SSE-NEXT: divl 20(%rsi)
-; X64-SSE-NEXT: movd %edx, %xmm0
-; X64-SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; X64-SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
-; X64-SSE-NEXT: movl %r8d, %eax
-; X64-SSE-NEXT: xorl %edx, %edx
-; X64-SSE-NEXT: divl 4(%rsi)
-; X64-SSE-NEXT: movd %edx, %xmm0
-; X64-SSE-NEXT: movl %r9d, %eax
-; X64-SSE-NEXT: xorl %edx, %edx
-; X64-SSE-NEXT: divl (%rsi)
-; X64-SSE-NEXT: movd %edx, %xmm3
-; X64-SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1]
-; X64-SSE-NEXT: movl %r10d, %eax
-; X64-SSE-NEXT: xorl %edx, %edx
-; X64-SSE-NEXT: divl 12(%rsi)
-; X64-SSE-NEXT: movd %edx, %xmm0
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]
+; X64-SSE-NEXT: movdqa %xmm0, %xmm3
+; X64-SSE-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7]
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm3[2,3,2,3]
; X64-SSE-NEXT: movd %xmm2, %eax
-; X64-SSE-NEXT: xorl %edx, %edx
-; X64-SSE-NEXT: divl 8(%rsi)
-; X64-SSE-NEXT: movd %edx, %xmm2
-; X64-SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
+; X64-SSE-NEXT: xorps %xmm2, %xmm2
+; X64-SSE-NEXT: cvtsi2sd %eax, %xmm2
+; X64-SSE-NEXT: movl 24(%rsi), %ecx
+; X64-SSE-NEXT: cvtsi2sd %rcx, %xmm4
+; X64-SSE-NEXT: divsd %xmm4, %xmm2
+; X64-SSE-NEXT: cvttsd2si %xmm2, %rdx
+; X64-SSE-NEXT: imull %edx, %ecx
+; X64-SSE-NEXT: subl %ecx, %eax
+; X64-SSE-NEXT: movd %eax, %xmm2
+; X64-SSE-NEXT: movl 28(%rsi), %eax
+; X64-SSE-NEXT: xorps %xmm4, %xmm4
+; X64-SSE-NEXT: cvtsi2sd %rax, %xmm4
+; X64-SSE-NEXT: pextrw $7, %xmm0, %ecx
+; X64-SSE-NEXT: cvtsi2sd %ecx, %xmm5
+; X64-SSE-NEXT: divsd %xmm4, %xmm5
+; X64-SSE-NEXT: cvttsd2si %xmm5, %rdx
+; X64-SSE-NEXT: imull %edx, %eax
+; X64-SSE-NEXT: subl %eax, %ecx
+; X64-SSE-NEXT: movd %ecx, %xmm4
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,1,1]
+; X64-SSE-NEXT: movd %xmm3, %eax
+; X64-SSE-NEXT: xorps %xmm3, %xmm3
+; X64-SSE-NEXT: cvtsi2sd %eax, %xmm3
+; X64-SSE-NEXT: movl 20(%rsi), %ecx
+; X64-SSE-NEXT: xorps %xmm5, %xmm5
+; X64-SSE-NEXT: cvtsi2sd %rcx, %xmm5
+; X64-SSE-NEXT: divsd %xmm5, %xmm3
+; X64-SSE-NEXT: cvttsd2si %xmm3, %rdx
+; X64-SSE-NEXT: imull %edx, %ecx
+; X64-SSE-NEXT: subl %ecx, %eax
+; X64-SSE-NEXT: movl 16(%rsi), %r9d
+; X64-SSE-NEXT: xorps %xmm3, %xmm3
+; X64-SSE-NEXT: cvtsi2sd %r9, %xmm3
+; X64-SSE-NEXT: pextrw $4, %xmm0, %r10d
+; X64-SSE-NEXT: xorps %xmm5, %xmm5
+; X64-SSE-NEXT: cvtsi2sd %r10d, %xmm5
+; X64-SSE-NEXT: divsd %xmm3, %xmm5
+; X64-SSE-NEXT: cvttsd2si %xmm5, %rcx
+; X64-SSE-NEXT: movl 4(%rsi), %edx
+; X64-SSE-NEXT: xorps %xmm3, %xmm3
+; X64-SSE-NEXT: cvtsi2sd %rdx, %xmm3
+; X64-SSE-NEXT: pextrw $1, %xmm0, %r8d
+; X64-SSE-NEXT: cvtsi2sd %r8d, %xmm6
+; X64-SSE-NEXT: divsd %xmm3, %xmm6
+; X64-SSE-NEXT: movd %eax, %xmm5
+; X64-SSE-NEXT: movzwl 16(%rdi), %eax
+; X64-SSE-NEXT: imull %ecx, %r9d
+; X64-SSE-NEXT: movl 32(%rsi), %ecx
+; X64-SSE-NEXT: subl %r9d, %r10d
+; X64-SSE-NEXT: cvttsd2si %xmm6, %rdi
+; X64-SSE-NEXT: movd %r10d, %xmm3
+; X64-SSE-NEXT: imull %edi, %edx
+; X64-SSE-NEXT: pextrw $0, %xmm0, %edi
+; X64-SSE-NEXT: pextrw $3, %xmm0, %r9d
+; X64-SSE-NEXT: movdqa %xmm0, %xmm6
+; X64-SSE-NEXT: punpcklwd {{.*#+}} xmm6 = xmm6[0],xmm1[0],xmm6[1],xmm1[1],xmm6[2],xmm1[2],xmm6[3],xmm1[3]
+; X64-SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
+; X64-SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm5[0],xmm3[1],xmm5[1]
; X64-SSE-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm2[0]
-; X64-SSE-NEXT: movl %ecx, %eax
-; X64-SSE-NEXT: xorl %edx, %edx
-; X64-SSE-NEXT: divl 32(%rsi)
-; X64-SSE-NEXT: movdqa {{.*#+}} xmm0 = [8199,8199,8199,8199]
+; X64-SSE-NEXT: subl %edx, %r8d
+; X64-SSE-NEXT: movl (%rsi), %edx
+; X64-SSE-NEXT: movd %r8d, %xmm1
+; X64-SSE-NEXT: xorps %xmm0, %xmm0
+; X64-SSE-NEXT: cvtsi2sd %rdx, %xmm0
+; X64-SSE-NEXT: xorps %xmm2, %xmm2
+; X64-SSE-NEXT: cvtsi2sd %edi, %xmm2
+; X64-SSE-NEXT: divsd %xmm0, %xmm2
+; X64-SSE-NEXT: cvttsd2si %xmm2, %r8
+; X64-SSE-NEXT: imull %r8d, %edx
+; X64-SSE-NEXT: subl %edx, %edi
+; X64-SSE-NEXT: movd %edi, %xmm0
+; X64-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm6[2,3,2,3]
+; X64-SSE-NEXT: movd %xmm1, %edx
+; X64-SSE-NEXT: xorps %xmm1, %xmm1
+; X64-SSE-NEXT: cvtsi2sd %edx, %xmm1
+; X64-SSE-NEXT: movl 8(%rsi), %edi
+; X64-SSE-NEXT: xorps %xmm2, %xmm2
+; X64-SSE-NEXT: cvtsi2sd %rdi, %xmm2
+; X64-SSE-NEXT: divsd %xmm2, %xmm1
+; X64-SSE-NEXT: cvttsd2si %xmm1, %r8
+; X64-SSE-NEXT: imull %r8d, %edi
+; X64-SSE-NEXT: subl %edi, %edx
+; X64-SSE-NEXT: movd %edx, %xmm1
+; X64-SSE-NEXT: movl 12(%rsi), %edx
+; X64-SSE-NEXT: xorps %xmm2, %xmm2
+; X64-SSE-NEXT: cvtsi2sd %rdx, %xmm2
+; X64-SSE-NEXT: xorps %xmm4, %xmm4
+; X64-SSE-NEXT: cvtsi2sd %r9d, %xmm4
+; X64-SSE-NEXT: divsd %xmm2, %xmm4
+; X64-SSE-NEXT: cvttsd2si %xmm4, %rsi
+; X64-SSE-NEXT: imull %esi, %edx
+; X64-SSE-NEXT: subl %edx, %r9d
+; X64-SSE-NEXT: movd %r9d, %xmm2
+; X64-SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
+; X64-SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; X64-SSE-NEXT: xorps %xmm1, %xmm1
+; X64-SSE-NEXT: cvtsi2sd %eax, %xmm1
+; X64-SSE-NEXT: xorps %xmm2, %xmm2
+; X64-SSE-NEXT: cvtsi2sd %rcx, %xmm2
+; X64-SSE-NEXT: divsd %xmm2, %xmm1
+; X64-SSE-NEXT: cvttsd2si %xmm1, %rdx
+; X64-SSE-NEXT: imull %ecx, %edx
+; X64-SSE-NEXT: subl %edx, %eax
+; X64-SSE-NEXT: movdqa {{.*#+}} xmm1 = [8199,8199,8199,8199]
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; X64-SSE-NEXT: pmuludq %xmm1, %xmm0
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; X64-SSE-NEXT: pmuludq %xmm1, %xmm2
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
+; X64-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; X64-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,1,3,3]
-; X64-SSE-NEXT: pmuludq %xmm0, %xmm3
+; X64-SSE-NEXT: pmuludq %xmm1, %xmm3
; X64-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
-; X64-SSE-NEXT: pmuludq %xmm0, %xmm2
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
-; X64-SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; X64-SSE-NEXT: pmuludq %xmm0, %xmm1
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
-; X64-SSE-NEXT: pmuludq %xmm0, %xmm2
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
-; X64-SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; X64-SSE-NEXT: imull $8199, %edx, %eax # imm = 0x2007
+; X64-SSE-NEXT: pmuludq %xmm1, %xmm2
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
+; X64-SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
+; X64-SSE-NEXT: imull $8199, %eax, %eax # imm = 0x2007
; X64-SSE-NEXT: movl %eax, (%rax)
-; X64-SSE-NEXT: movdqa %xmm1, (%rax)
; X64-SSE-NEXT: movdqa %xmm3, (%rax)
+; X64-SSE-NEXT: movdqa %xmm0, (%rax)
; X64-SSE-NEXT: retq
;
; X64-AVX1-LABEL: PR34947:
; X64-AVX1: # %bb.0:
-; X64-AVX1-NEXT: pushq %rbp
; X64-AVX1-NEXT: pushq %rbx
+; X64-AVX1-NEXT: movl 32(%rsi), %eax
; X64-AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
; X64-AVX1-NEXT: vpmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
; X64-AVX1-NEXT: vpmovzxwd {{.*#+}} xmm2 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
+; X64-AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm3
+; X64-AVX1-NEXT: vcvtdq2pd %xmm2, %xmm4
+; X64-AVX1-NEXT: vdivsd %xmm3, %xmm4, %xmm3
+; X64-AVX1-NEXT: vcvttsd2si %xmm3, %rcx
+; X64-AVX1-NEXT: imull %eax, %ecx
; X64-AVX1-NEXT: vmovd %xmm2, %eax
-; X64-AVX1-NEXT: xorl %edx, %edx
-; X64-AVX1-NEXT: divl 32(%rsi)
-; X64-AVX1-NEXT: movl %edx, %ecx
-; X64-AVX1-NEXT: vpextrd $3, %xmm1, %eax
-; X64-AVX1-NEXT: xorl %edx, %edx
-; X64-AVX1-NEXT: divl 28(%rsi)
-; X64-AVX1-NEXT: movl %edx, %edi
-; X64-AVX1-NEXT: vpextrd $2, %xmm1, %eax
-; X64-AVX1-NEXT: xorl %edx, %edx
-; X64-AVX1-NEXT: divl 24(%rsi)
-; X64-AVX1-NEXT: movl %edx, %r8d
-; X64-AVX1-NEXT: vpextrd $1, %xmm1, %eax
-; X64-AVX1-NEXT: xorl %edx, %edx
-; X64-AVX1-NEXT: divl 20(%rsi)
-; X64-AVX1-NEXT: movl %edx, %r9d
-; X64-AVX1-NEXT: vmovd %xmm1, %eax
-; X64-AVX1-NEXT: xorl %edx, %edx
-; X64-AVX1-NEXT: divl 16(%rsi)
-; X64-AVX1-NEXT: movl %edx, %r10d
-; X64-AVX1-NEXT: vpextrd $3, %xmm0, %eax
-; X64-AVX1-NEXT: xorl %edx, %edx
-; X64-AVX1-NEXT: divl 12(%rsi)
-; X64-AVX1-NEXT: movl %edx, %r11d
-; X64-AVX1-NEXT: vpextrd $2, %xmm0, %eax
-; X64-AVX1-NEXT: xorl %edx, %edx
-; X64-AVX1-NEXT: divl 8(%rsi)
-; X64-AVX1-NEXT: movl %edx, %ebx
-; X64-AVX1-NEXT: vpextrd $1, %xmm0, %eax
-; X64-AVX1-NEXT: xorl %edx, %edx
-; X64-AVX1-NEXT: divl 4(%rsi)
-; X64-AVX1-NEXT: movl %edx, %ebp
-; X64-AVX1-NEXT: vmovd %xmm0, %eax
-; X64-AVX1-NEXT: xorl %edx, %edx
-; X64-AVX1-NEXT: divl (%rsi)
-; X64-AVX1-NEXT: vmovd %edx, %xmm0
-; X64-AVX1-NEXT: vpinsrd $1, %ebp, %xmm0, %xmm0
-; X64-AVX1-NEXT: vpinsrd $2, %ebx, %xmm0, %xmm0
-; X64-AVX1-NEXT: vpinsrd $3, %r11d, %xmm0, %xmm0
+; X64-AVX1-NEXT: subl %ecx, %eax
+; X64-AVX1-NEXT: movl 28(%rsi), %edx
+; X64-AVX1-NEXT: vcvtsi2sd %rdx, %xmm15, %xmm2
+; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm1[3,3,3,3]
+; X64-AVX1-NEXT: vcvtdq2pd %xmm3, %xmm3
+; X64-AVX1-NEXT: vdivsd %xmm2, %xmm3, %xmm2
+; X64-AVX1-NEXT: vcvttsd2si %xmm2, %rcx
+; X64-AVX1-NEXT: imull %ecx, %edx
+; X64-AVX1-NEXT: vpextrd $3, %xmm1, %ecx
+; X64-AVX1-NEXT: subl %edx, %ecx
+; X64-AVX1-NEXT: movl 24(%rsi), %edi
+; X64-AVX1-NEXT: vcvtsi2sd %rdi, %xmm15, %xmm2
+; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
+; X64-AVX1-NEXT: vcvtdq2pd %xmm3, %xmm3
+; X64-AVX1-NEXT: vdivsd %xmm2, %xmm3, %xmm2
+; X64-AVX1-NEXT: vcvttsd2si %xmm2, %rdx
+; X64-AVX1-NEXT: imull %edx, %edi
+; X64-AVX1-NEXT: vpextrd $2, %xmm1, %edx
+; X64-AVX1-NEXT: subl %edi, %edx
+; X64-AVX1-NEXT: movl 20(%rsi), %r8d
+; X64-AVX1-NEXT: vcvtsi2sd %r8, %xmm15, %xmm2
+; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm1[1,1,1,1]
+; X64-AVX1-NEXT: vcvtdq2pd %xmm3, %xmm3
+; X64-AVX1-NEXT: vdivsd %xmm2, %xmm3, %xmm2
+; X64-AVX1-NEXT: vcvttsd2si %xmm2, %rdi
+; X64-AVX1-NEXT: imull %edi, %r8d
+; X64-AVX1-NEXT: vpextrd $1, %xmm1, %edi
+; X64-AVX1-NEXT: subl %r8d, %edi
+; X64-AVX1-NEXT: movl 16(%rsi), %r9d
+; X64-AVX1-NEXT: vcvtsi2sd %r9, %xmm15, %xmm2
+; X64-AVX1-NEXT: vcvtdq2pd %xmm1, %xmm3
+; X64-AVX1-NEXT: vdivsd %xmm2, %xmm3, %xmm2
+; X64-AVX1-NEXT: vcvttsd2si %xmm2, %r8
+; X64-AVX1-NEXT: imull %r8d, %r9d
+; X64-AVX1-NEXT: vmovd %xmm1, %r8d
+; X64-AVX1-NEXT: subl %r9d, %r8d
+; X64-AVX1-NEXT: movl 12(%rsi), %r10d
+; X64-AVX1-NEXT: vcvtsi2sd %r10, %xmm15, %xmm1
+; X64-AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm0[3,3,3,3]
+; X64-AVX1-NEXT: vcvtdq2pd %xmm2, %xmm2
+; X64-AVX1-NEXT: vdivsd %xmm1, %xmm2, %xmm1
+; X64-AVX1-NEXT: vcvttsd2si %xmm1, %r9
+; X64-AVX1-NEXT: imull %r9d, %r10d
+; X64-AVX1-NEXT: vpextrd $3, %xmm0, %r9d
+; X64-AVX1-NEXT: subl %r10d, %r9d
+; X64-AVX1-NEXT: movl 8(%rsi), %r11d
+; X64-AVX1-NEXT: vcvtsi2sd %r11, %xmm15, %xmm1
+; X64-AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm0[2,3,2,3]
+; X64-AVX1-NEXT: vcvtdq2pd %xmm2, %xmm2
+; X64-AVX1-NEXT: vdivsd %xmm1, %xmm2, %xmm1
+; X64-AVX1-NEXT: vcvttsd2si %xmm1, %r10
+; X64-AVX1-NEXT: imull %r10d, %r11d
+; X64-AVX1-NEXT: vpextrd $2, %xmm0, %r10d
+; X64-AVX1-NEXT: subl %r11d, %r10d
+; X64-AVX1-NEXT: movl (%rsi), %r11d
+; X64-AVX1-NEXT: movl 4(%rsi), %esi
+; X64-AVX1-NEXT: vcvtsi2sd %rsi, %xmm15, %xmm1
+; X64-AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm0[1,1,1,1]
+; X64-AVX1-NEXT: vcvtdq2pd %xmm2, %xmm2
+; X64-AVX1-NEXT: vdivsd %xmm1, %xmm2, %xmm1
+; X64-AVX1-NEXT: vcvttsd2si %xmm1, %rbx
+; X64-AVX1-NEXT: imull %ebx, %esi
+; X64-AVX1-NEXT: vpextrd $1, %xmm0, %ebx
+; X64-AVX1-NEXT: subl %esi, %ebx
+; X64-AVX1-NEXT: vcvtsi2sd %r11, %xmm15, %xmm1
+; X64-AVX1-NEXT: vcvtdq2pd %xmm0, %xmm2
+; X64-AVX1-NEXT: vdivsd %xmm1, %xmm2, %xmm1
+; X64-AVX1-NEXT: vcvttsd2si %xmm1, %rsi
+; X64-AVX1-NEXT: imull %esi, %r11d
+; X64-AVX1-NEXT: vmovd %xmm0, %esi
+; X64-AVX1-NEXT: subl %r11d, %esi
+; X64-AVX1-NEXT: vmovd %esi, %xmm0
+; X64-AVX1-NEXT: vpinsrd $1, %ebx, %xmm0, %xmm0
+; X64-AVX1-NEXT: vpinsrd $2, %r10d, %xmm0, %xmm0
+; X64-AVX1-NEXT: vpinsrd $3, %r9d, %xmm0, %xmm0
; X64-AVX1-NEXT: vbroadcastss {{.*#+}} xmm1 = [8199,8199,8199,8199]
; X64-AVX1-NEXT: vpmulld %xmm1, %xmm0, %xmm0
-; X64-AVX1-NEXT: vmovd %r10d, %xmm2
-; X64-AVX1-NEXT: vpinsrd $1, %r9d, %xmm2, %xmm2
-; X64-AVX1-NEXT: vpinsrd $2, %r8d, %xmm2, %xmm2
-; X64-AVX1-NEXT: vpinsrd $3, %edi, %xmm2, %xmm2
+; X64-AVX1-NEXT: vmovd %r8d, %xmm2
+; X64-AVX1-NEXT: vpinsrd $1, %edi, %xmm2, %xmm2
+; X64-AVX1-NEXT: vpinsrd $2, %edx, %xmm2, %xmm2
+; X64-AVX1-NEXT: vpinsrd $3, %ecx, %xmm2, %xmm2
; X64-AVX1-NEXT: vpmulld %xmm1, %xmm2, %xmm1
-; X64-AVX1-NEXT: imull $8199, %ecx, %eax # imm = 0x2007
+; X64-AVX1-NEXT: imull $8199, %eax, %eax # imm = 0x2007
; X64-AVX1-NEXT: movl %eax, (%rax)
; X64-AVX1-NEXT: vmovdqa %xmm1, (%rax)
; X64-AVX1-NEXT: vmovdqa %xmm0, (%rax)
; X64-AVX1-NEXT: popq %rbx
-; X64-AVX1-NEXT: popq %rbp
; X64-AVX1-NEXT: retq
;
; X64-AVX2-LABEL: PR34947:
diff --git a/llvm/test/CodeGen/X86/speculation-hardening-sls.ll b/llvm/test/CodeGen/X86/speculation-hardening-sls.ll
index a68d6f039939e..a946d666fad4b 100644
--- a/llvm/test/CodeGen/X86/speculation-hardening-sls.ll
+++ b/llvm/test/CodeGen/X86/speculation-hardening-sls.ll
@@ -1,16 +1,40 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mattr=harden-sls-ret -mtriple=x86_64-unknown-unknown < %s | FileCheck %s -check-prefixes=CHECK,RET
; RUN: llc -mattr=harden-sls-ijmp -mtriple=x86_64-unknown-unknown < %s | FileCheck %s -check-prefixes=CHECK,IJMP
define dso_local i32 @double_return(i32 %a, i32 %b) local_unnamed_addr {
-; CHECK-LABEL: double_return:
-; CHECK: jle
-; CHECK-NOT: int3
-; CHECK: retq
-; RET-NEXT: int3
-; IJMP-NOT: int3
-; CHECK: retq
-; RET-NEXT: int3
-; IJMP-NOT: int3
+; RET-LABEL: double_return:
+; RET: # %bb.0: # %entry
+; RET-NEXT: testl %edi, %edi
+; RET-NEXT: jle .LBB0_3
+; RET-NEXT: # %bb.1: # %if.then
+; RET-NEXT: cvtsi2sd %esi, %xmm0
+; RET-NEXT: cvtsi2sd %edi, %xmm1
+; RET-NEXT: jmp .LBB0_2
+; RET-NEXT: .LBB0_3: # %if.else
+; RET-NEXT: cvtsi2sd %edi, %xmm0
+; RET-NEXT: cvtsi2sd %esi, %xmm1
+; RET-NEXT: .LBB0_2: # %if.then
+; RET-NEXT: divsd %xmm0, %xmm1
+; RET-NEXT: cvttsd2si %xmm1, %eax
+; RET-NEXT: retq
+; RET-NEXT: int3
+;
+; IJMP-LABEL: double_return:
+; IJMP: # %bb.0: # %entry
+; IJMP-NEXT: testl %edi, %edi
+; IJMP-NEXT: jle .LBB0_3
+; IJMP-NEXT: # %bb.1: # %if.then
+; IJMP-NEXT: cvtsi2sd %esi, %xmm0
+; IJMP-NEXT: cvtsi2sd %edi, %xmm1
+; IJMP-NEXT: jmp .LBB0_2
+; IJMP-NEXT: .LBB0_3: # %if.else
+; IJMP-NEXT: cvtsi2sd %edi, %xmm0
+; IJMP-NEXT: cvtsi2sd %esi, %xmm1
+; IJMP-NEXT: .LBB0_2: # %if.then
+; IJMP-NEXT: divsd %xmm0, %xmm1
+; IJMP-NEXT: cvttsd2si %xmm1, %eax
+; IJMP-NEXT: retq
entry:
%cmp = icmp sgt i32 %a, 0
br i1 %cmp, label %if.then, label %if.else
@@ -28,16 +52,34 @@ if.else: ; preds = %entry
; Function Attrs: norecurse nounwind readnone
define dso_local i32 @indirect_branch(i32 %a, i32 %b, i32 %i) {
-; CHECK-LABEL: indirect_branch:
-; CHECK: jmpq *
-; RET-NOT: int3
-; IJMP-NEXT: int3
-; CHECK: retq
-; RET-NEXT: int3
-; IJMP-NOT: int3
-; CHECK: retq
-; RET-NEXT: int3
-; IJMP-NOT: int3
+; RET-LABEL: indirect_branch:
+; RET: # %bb.0: # %entry
+; RET-NEXT: movslq %edx, %rax
+; RET-NEXT: jmpq *.L__const.indirect_branch.ptr(,%rax,8)
+; RET-NEXT: .Ltmp0: # Block address taken
+; RET-NEXT: .LBB1_2: # %return
+; RET-NEXT: xorl %eax, %eax
+; RET-NEXT: retq
+; RET-NEXT: int3
+; RET-NEXT: .Ltmp1: # Block address taken
+; RET-NEXT: .LBB1_1: # %l2
+; RET-NEXT: movl $1, %eax
+; RET-NEXT: retq
+; RET-NEXT: int3
+;
+; IJMP-LABEL: indirect_branch:
+; IJMP: # %bb.0: # %entry
+; IJMP-NEXT: movslq %edx, %rax
+; IJMP-NEXT: jmpq *.L__const.indirect_branch.ptr(,%rax,8)
+; IJMP-NEXT: int3
+; IJMP-NEXT: .Ltmp0: # Block address taken
+; IJMP-NEXT: .LBB1_2: # %return
+; IJMP-NEXT: xorl %eax, %eax
+; IJMP-NEXT: retq
+; IJMP-NEXT: .Ltmp1: # Block address taken
+; IJMP-NEXT: .LBB1_1: # %l2
+; IJMP-NEXT: movl $1, %eax
+; IJMP-NEXT: retq
entry:
%idxprom = sext i32 %i to i64
%arrayidx = getelementptr inbounds [2 x ptr], ptr @__const.indirect_branch.ptr, i64 0, i64 %idxprom
@@ -53,16 +95,35 @@ return: ; preds = %entry, %l2
}
define i32 @asmgoto() {
-; CHECK-LABEL: asmgoto:
-; CHECK: # %bb.0: # %entry
-; CHECK: jmp .L
-; CHECK-NOT: int3
-; CHECK: retq
-; RET-NEXT: int3
-; IJMP-NOT: int3
-; CHECK: retq
-; RET-NEXT: int3
-; IJMP-NOT: int3
+; RET-LABEL: asmgoto:
+; RET: # %bb.0: # %entry
+; RET-NEXT: #APP
+; RET-NEXT: jmp .LBB2_2
+; RET-NEXT: #NO_APP
+; RET-NEXT: # %bb.1: # %asm.fallthrough
+; RET-NEXT: xorl %eax, %eax
+; RET-NEXT: retq
+; RET-NEXT: int3
+; RET-NEXT: .LBB2_2: # Inline asm indirect target
+; RET-NEXT: # %d
+; RET-NEXT: # Label of block must be emitted
+; RET-NEXT: movl $1, %eax
+; RET-NEXT: retq
+; RET-NEXT: int3
+;
+; IJMP-LABEL: asmgoto:
+; IJMP: # %bb.0: # %entry
+; IJMP-NEXT: #APP
+; IJMP-NEXT: jmp .LBB2_2
+; IJMP-NEXT: #NO_APP
+; IJMP-NEXT: # %bb.1: # %asm.fallthrough
+; IJMP-NEXT: xorl %eax, %eax
+; IJMP-NEXT: retq
+; IJMP-NEXT: .LBB2_2: # Inline asm indirect target
+; IJMP-NEXT: # %d
+; IJMP-NEXT: # Label of block must be emitted
+; IJMP-NEXT: movl $1, %eax
+; IJMP-NEXT: retq
entry:
callbr void asm sideeffect "jmp $0", "!i"()
to label %asm.fallthrough [label %d]
@@ -76,11 +137,14 @@ d: ; preds = %asm.fallthrough, %entry
}
define void @bar(ptr %0) {
-; CHECK-LABEL: bar:
-; CHECK: jmpq *
-; RET-NOT: int3
-; IJMP-NEXT: int3
-; CHECK-NOT: ret
+; RET-LABEL: bar:
+; RET: # %bb.0:
+; RET-NEXT: jmpq *%rdi # TAILCALL
+;
+; IJMP-LABEL: bar:
+; IJMP: # %bb.0:
+; IJMP-NEXT: jmpq *%rdi # TAILCALL
+; IJMP-NEXT: int3
tail call void %0()
ret void
}
@@ -89,9 +153,8 @@ declare dso_local void @foo()
define dso_local void @bar2() {
; CHECK-LABEL: bar2:
-; CHECK: jmp foo
-; CHECK-NOT: int3
-; CHECK-NOT: ret
+; CHECK: # %bb.0:
+; CHECK-NEXT: jmp foo # TAILCALL
tail call void @foo()
ret void
}
diff --git a/llvm/test/CodeGen/X86/split-vector-rem.ll b/llvm/test/CodeGen/X86/split-vector-rem.ll
index c9dbc9201068f..8430e9e222149 100644
--- a/llvm/test/CodeGen/X86/split-vector-rem.ll
+++ b/llvm/test/CodeGen/X86/split-vector-rem.ll
@@ -50,62 +50,110 @@ define <8 x i32> @bar(<8 x i32> %t, <8 x i32> %u) {
; CHECK-LABEL: bar:
; CHECK: # %bb.0:
; CHECK-NEXT: movdqa %xmm0, %xmm4
-; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
-; CHECK-NEXT: movd %xmm0, %eax
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm2[3,3,3,3]
-; CHECK-NEXT: movd %xmm0, %ecx
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ecx
-; CHECK-NEXT: movd %edx, %xmm0
-; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm4[2,3,2,3]
-; CHECK-NEXT: movd %xmm5, %eax
-; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm2[2,3,2,3]
+; CHECK-NEXT: movd %xmm0, %eax
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm4[3,3,3,3]
; CHECK-NEXT: movd %xmm5, %ecx
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ecx
-; CHECK-NEXT: movd %edx, %xmm5
+; CHECK-NEXT: xorps %xmm5, %xmm5
+; CHECK-NEXT: cvtsi2sd %rcx, %xmm5
+; CHECK-NEXT: divsd %xmm0, %xmm5
+; CHECK-NEXT: cvttsd2si %xmm5, %rdx
+; CHECK-NEXT: imull %eax, %edx
+; CHECK-NEXT: subl %edx, %ecx
+; CHECK-NEXT: movd %ecx, %xmm0
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm2[2,3,2,3]
+; CHECK-NEXT: movd %xmm5, %eax
+; CHECK-NEXT: xorps %xmm5, %xmm5
+; CHECK-NEXT: cvtsi2sd %rax, %xmm5
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm4[2,3,2,3]
+; CHECK-NEXT: movd %xmm6, %ecx
+; CHECK-NEXT: xorps %xmm6, %xmm6
+; CHECK-NEXT: cvtsi2sd %rcx, %xmm6
+; CHECK-NEXT: divsd %xmm5, %xmm6
+; CHECK-NEXT: cvttsd2si %xmm6, %rdx
+; CHECK-NEXT: imull %eax, %edx
+; CHECK-NEXT: subl %edx, %ecx
+; CHECK-NEXT: movd %ecx, %xmm5
; CHECK-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm0[0],xmm5[1],xmm0[1]
-; CHECK-NEXT: movd %xmm4, %eax
-; CHECK-NEXT: movd %xmm2, %ecx
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ecx
-; CHECK-NEXT: movd %edx, %xmm0
-; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,1,1]
-; CHECK-NEXT: movd %xmm4, %eax
+; CHECK-NEXT: movd %xmm2, %eax
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2sd %rax, %xmm0
+; CHECK-NEXT: movd %xmm4, %ecx
+; CHECK-NEXT: xorps %xmm6, %xmm6
+; CHECK-NEXT: cvtsi2sd %rcx, %xmm6
+; CHECK-NEXT: divsd %xmm0, %xmm6
+; CHECK-NEXT: cvttsd2si %xmm6, %rdx
+; CHECK-NEXT: imull %eax, %edx
+; CHECK-NEXT: subl %edx, %ecx
+; CHECK-NEXT: movd %ecx, %xmm0
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,1,1]
-; CHECK-NEXT: movd %xmm2, %ecx
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ecx
-; CHECK-NEXT: movd %edx, %xmm2
+; CHECK-NEXT: movd %xmm2, %eax
+; CHECK-NEXT: xorps %xmm2, %xmm2
+; CHECK-NEXT: cvtsi2sd %rax, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,1,1]
+; CHECK-NEXT: movd %xmm4, %ecx
+; CHECK-NEXT: xorps %xmm4, %xmm4
+; CHECK-NEXT: cvtsi2sd %rcx, %xmm4
+; CHECK-NEXT: divsd %xmm2, %xmm4
+; CHECK-NEXT: cvttsd2si %xmm4, %rdx
+; CHECK-NEXT: imull %eax, %edx
+; CHECK-NEXT: subl %edx, %ecx
+; CHECK-NEXT: movd %ecx, %xmm2
; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm5[0]
-; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,3,3,3]
-; CHECK-NEXT: movd %xmm2, %eax
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm3[3,3,3,3]
-; CHECK-NEXT: movd %xmm2, %ecx
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ecx
-; CHECK-NEXT: movd %edx, %xmm2
-; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm1[2,3,2,3]
-; CHECK-NEXT: movd %xmm4, %eax
-; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm3[2,3,2,3]
+; CHECK-NEXT: movd %xmm2, %eax
+; CHECK-NEXT: xorps %xmm2, %xmm2
+; CHECK-NEXT: cvtsi2sd %rax, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm1[3,3,3,3]
; CHECK-NEXT: movd %xmm4, %ecx
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ecx
-; CHECK-NEXT: movd %edx, %xmm4
+; CHECK-NEXT: xorps %xmm4, %xmm4
+; CHECK-NEXT: cvtsi2sd %rcx, %xmm4
+; CHECK-NEXT: divsd %xmm2, %xmm4
+; CHECK-NEXT: cvttsd2si %xmm4, %rdx
+; CHECK-NEXT: imull %eax, %edx
+; CHECK-NEXT: subl %edx, %ecx
+; CHECK-NEXT: movd %ecx, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm3[2,3,2,3]
+; CHECK-NEXT: movd %xmm4, %eax
+; CHECK-NEXT: xorps %xmm4, %xmm4
+; CHECK-NEXT: cvtsi2sd %rax, %xmm4
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm1[2,3,2,3]
+; CHECK-NEXT: movd %xmm5, %ecx
+; CHECK-NEXT: xorps %xmm5, %xmm5
+; CHECK-NEXT: cvtsi2sd %rcx, %xmm5
+; CHECK-NEXT: divsd %xmm4, %xmm5
+; CHECK-NEXT: cvttsd2si %xmm5, %rdx
+; CHECK-NEXT: imull %eax, %edx
+; CHECK-NEXT: subl %edx, %ecx
+; CHECK-NEXT: movd %ecx, %xmm4
; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
-; CHECK-NEXT: movd %xmm1, %eax
-; CHECK-NEXT: movd %xmm3, %ecx
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ecx
-; CHECK-NEXT: movd %edx, %xmm2
+; CHECK-NEXT: movd %xmm3, %eax
+; CHECK-NEXT: xorps %xmm2, %xmm2
+; CHECK-NEXT: cvtsi2sd %rax, %xmm2
+; CHECK-NEXT: movd %xmm1, %ecx
+; CHECK-NEXT: xorps %xmm5, %xmm5
+; CHECK-NEXT: cvtsi2sd %rcx, %xmm5
+; CHECK-NEXT: divsd %xmm2, %xmm5
+; CHECK-NEXT: cvttsd2si %xmm5, %rdx
+; CHECK-NEXT: imull %eax, %edx
+; CHECK-NEXT: subl %edx, %ecx
+; CHECK-NEXT: movd %ecx, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,1,1]
+; CHECK-NEXT: movd %xmm3, %eax
+; CHECK-NEXT: xorps %xmm3, %xmm3
+; CHECK-NEXT: cvtsi2sd %rax, %xmm3
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
-; CHECK-NEXT: movd %xmm1, %eax
-; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,1,1,1]
; CHECK-NEXT: movd %xmm1, %ecx
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ecx
-; CHECK-NEXT: movd %edx, %xmm1
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: cvtsi2sd %rcx, %xmm1
+; CHECK-NEXT: divsd %xmm3, %xmm1
+; CHECK-NEXT: cvttsd2si %xmm1, %rdx
+; CHECK-NEXT: imull %eax, %edx
+; CHECK-NEXT: subl %edx, %ecx
+; CHECK-NEXT: movd %ecx, %xmm1
; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; CHECK-NEXT: movdqa %xmm2, %xmm1
diff --git a/llvm/test/CodeGen/X86/udiv_fix.ll b/llvm/test/CodeGen/X86/udiv_fix.ll
index b2ad846b1be7e..a09821ba037fa 100644
--- a/llvm/test/CodeGen/X86/udiv_fix.ll
+++ b/llvm/test/CodeGen/X86/udiv_fix.ll
@@ -12,12 +12,14 @@ declare <4 x i32> @llvm.udiv.fix.v4i32(<4 x i32>, <4 x i32>, i32)
define i16 @func(i16 %x, i16 %y) nounwind {
; X64-LABEL: func:
; X64: # %bb.0:
-; X64-NEXT: movzwl %si, %ecx
+; X64-NEXT: movzwl %si, %eax
+; X64-NEXT: cvtsi2ss %eax, %xmm0
; X64-NEXT: movzwl %di, %eax
; X64-NEXT: shll $7, %eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %ecx
-; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: cvtsi2ss %eax, %xmm1
+; X64-NEXT: divss %xmm0, %xmm1
+; X64-NEXT: cvttss2si %xmm1, %rax
+; X64-NEXT: # kill: def $ax killed $ax killed $rax
; X64-NEXT: retq
;
; X86-LABEL: func:
@@ -40,9 +42,11 @@ define i16 @func2(i8 %x, i8 %y) nounwind {
; X64-NEXT: andl $32767, %eax # imm = 0x7FFF
; X64-NEXT: movsbl %sil, %ecx
; X64-NEXT: andl $32767, %ecx # imm = 0x7FFF
+; X64-NEXT: cvtsi2sd %ecx, %xmm0
; X64-NEXT: shll $14, %eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %ecx
+; X64-NEXT: cvtsi2sd %eax, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %rax
; X64-NEXT: addl %eax, %eax
; X64-NEXT: cwtl
; X64-NEXT: shrl %eax
@@ -73,13 +77,15 @@ define i16 @func2(i8 %x, i8 %y) nounwind {
define i16 @func3(i15 %x, i8 %y) nounwind {
; X64-LABEL: func3:
; X64: # %bb.0:
-; X64-NEXT: # kill: def $edi killed $edi def $rdi
-; X64-NEXT: leal (%rdi,%rdi), %eax
-; X64-NEXT: movzbl %sil, %ecx
-; X64-NEXT: shll $4, %ecx
+; X64-NEXT: movzbl %sil, %eax
+; X64-NEXT: shll $4, %eax
+; X64-NEXT: cvtsi2ss %eax, %xmm0
+; X64-NEXT: addl %edi, %edi
+; X64-NEXT: movzwl %di, %eax
+; X64-NEXT: cvtsi2ss %eax, %xmm1
+; X64-NEXT: divss %xmm0, %xmm1
+; X64-NEXT: cvttss2si %xmm1, %eax
; X64-NEXT: # kill: def $ax killed $ax killed $eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divw %cx
; X64-NEXT: retq
;
; X86-LABEL: func3:
@@ -103,11 +109,15 @@ define i16 @func3(i15 %x, i8 %y) nounwind {
define i4 @func4(i4 %x, i4 %y) nounwind {
; X64-LABEL: func4:
; X64: # %bb.0:
-; X64-NEXT: andb $15, %sil
; X64-NEXT: andb $15, %dil
+; X64-NEXT: andl $15, %esi
+; X64-NEXT: cvtsi2ss %esi, %xmm0
; X64-NEXT: shlb $2, %dil
; X64-NEXT: movzbl %dil, %eax
-; X64-NEXT: divb %sil
+; X64-NEXT: cvtsi2ss %eax, %xmm1
+; X64-NEXT: divss %xmm0, %xmm1
+; X64-NEXT: cvttss2si %xmm1, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
;
; X86-LABEL: func4:
@@ -181,9 +191,12 @@ define i18 @func6(i16 %x, i16 %y) nounwind {
; X64-NEXT: andl $262143, %eax # imm = 0x3FFFF
; X64-NEXT: movswl %si, %ecx
; X64-NEXT: andl $262143, %ecx # imm = 0x3FFFF
+; X64-NEXT: cvtsi2sd %ecx, %xmm0
; X64-NEXT: shll $7, %eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %ecx
+; X64-NEXT: cvtsi2sd %eax, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %rax
+; X64-NEXT: # kill: def $eax killed $eax killed $rax
; X64-NEXT: retq
;
; X86-LABEL: func6:
@@ -205,12 +218,14 @@ define i18 @func6(i16 %x, i16 %y) nounwind {
define i16 @func7(i16 %x, i16 %y) nounwind {
; X64-LABEL: func7:
; X64: # %bb.0:
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: shll $16, %eax
-; X64-NEXT: movzwl %si, %ecx
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %ecx
-; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: # kill: def $edi killed $edi def $rdi
+; X64-NEXT: movzwl %si, %eax
+; X64-NEXT: cvtsi2sd %eax, %xmm0
+; X64-NEXT: shll $16, %edi
+; X64-NEXT: cvtsi2sd %rdi, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %rax
+; X64-NEXT: # kill: def $ax killed $ax killed $rax
; X64-NEXT: retq
;
; X86-LABEL: func7:
diff --git a/llvm/test/CodeGen/X86/udiv_fix_sat.ll b/llvm/test/CodeGen/X86/udiv_fix_sat.ll
index 565918e5b159b..76380ee104c6e 100644
--- a/llvm/test/CodeGen/X86/udiv_fix_sat.ll
+++ b/llvm/test/CodeGen/X86/udiv_fix_sat.ll
@@ -12,14 +12,16 @@ declare <4 x i32> @llvm.udiv.fix.sat.v4i32(<4 x i32>, <4 x i32>, i32)
define i16 @func(i16 %x, i16 %y) nounwind {
; X64-LABEL: func:
; X64: # %bb.0:
-; X64-NEXT: movzwl %si, %ecx
+; X64-NEXT: movzwl %si, %eax
+; X64-NEXT: cvtsi2ss %eax, %xmm0
; X64-NEXT: movzwl %di, %eax
; X64-NEXT: shll $8, %eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %ecx
-; X64-NEXT: cmpl $131071, %eax # imm = 0x1FFFF
-; X64-NEXT: movl $131071, %ecx # imm = 0x1FFFF
-; X64-NEXT: cmovael %ecx, %eax
+; X64-NEXT: cvtsi2ss %eax, %xmm1
+; X64-NEXT: divss %xmm0, %xmm1
+; X64-NEXT: cvttss2si %xmm1, %rcx
+; X64-NEXT: cmpl $131071, %ecx # imm = 0x1FFFF
+; X64-NEXT: movl $131071, %eax # imm = 0x1FFFF
+; X64-NEXT: cmovbl %ecx, %eax
; X64-NEXT: shrl %eax
; X64-NEXT: # kill: def $ax killed $ax killed $eax
; X64-NEXT: retq
@@ -49,9 +51,11 @@ define i16 @func2(i8 %x, i8 %y) nounwind {
; X64-NEXT: andl $32767, %eax # imm = 0x7FFF
; X64-NEXT: movsbl %sil, %ecx
; X64-NEXT: andl $32767, %ecx # imm = 0x7FFF
+; X64-NEXT: cvtsi2sd %ecx, %xmm0
; X64-NEXT: shll $14, %eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %ecx
+; X64-NEXT: cvtsi2sd %eax, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %rax
; X64-NEXT: cmpl $32767, %eax # imm = 0x7FFF
; X64-NEXT: movl $32767, %ecx # imm = 0x7FFF
; X64-NEXT: cmovbl %eax, %ecx
@@ -88,13 +92,15 @@ define i16 @func2(i8 %x, i8 %y) nounwind {
define i16 @func3(i15 %x, i8 %y) nounwind {
; X64-LABEL: func3:
; X64: # %bb.0:
-; X64-NEXT: # kill: def $edi killed $edi def $rdi
-; X64-NEXT: leal (%rdi,%rdi), %eax
-; X64-NEXT: movzbl %sil, %ecx
-; X64-NEXT: shll $4, %ecx
+; X64-NEXT: movzbl %sil, %eax
+; X64-NEXT: shll $4, %eax
+; X64-NEXT: cvtsi2ss %eax, %xmm0
+; X64-NEXT: addl %edi, %edi
+; X64-NEXT: movzwl %di, %eax
+; X64-NEXT: cvtsi2ss %eax, %xmm1
+; X64-NEXT: divss %xmm0, %xmm1
+; X64-NEXT: cvttss2si %xmm1, %eax
; X64-NEXT: # kill: def $ax killed $ax killed $eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divw %cx
; X64-NEXT: retq
;
; X86-LABEL: func3:
@@ -118,12 +124,14 @@ define i16 @func3(i15 %x, i8 %y) nounwind {
define i4 @func4(i4 %x, i4 %y) nounwind {
; X64-LABEL: func4:
; X64: # %bb.0:
-; X64-NEXT: andb $15, %sil
; X64-NEXT: andb $15, %dil
+; X64-NEXT: andl $15, %esi
+; X64-NEXT: cvtsi2ss %esi, %xmm0
; X64-NEXT: shlb $2, %dil
; X64-NEXT: movzbl %dil, %eax
-; X64-NEXT: divb %sil
-; X64-NEXT: movzbl %al, %ecx
+; X64-NEXT: cvtsi2ss %eax, %xmm1
+; X64-NEXT: divss %xmm0, %xmm1
+; X64-NEXT: cvttss2si %xmm1, %ecx
; X64-NEXT: cmpb $15, %cl
; X64-NEXT: movl $15, %eax
; X64-NEXT: cmovbl %ecx, %eax
@@ -221,12 +229,14 @@ define i18 @func6(i16 %x, i16 %y) nounwind {
; X64-NEXT: andl $262143, %eax # imm = 0x3FFFF
; X64-NEXT: movswl %si, %ecx
; X64-NEXT: andl $262143, %ecx # imm = 0x3FFFF
+; X64-NEXT: cvtsi2sd %ecx, %xmm0
; X64-NEXT: shll $7, %eax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %ecx
-; X64-NEXT: cmpl $262143, %eax # imm = 0x3FFFF
-; X64-NEXT: movl $262143, %ecx # imm = 0x3FFFF
-; X64-NEXT: cmovael %ecx, %eax
+; X64-NEXT: cvtsi2sd %eax, %xmm1
+; X64-NEXT: divsd %xmm0, %xmm1
+; X64-NEXT: cvttsd2si %xmm1, %rcx
+; X64-NEXT: cmpl $262143, %ecx # imm = 0x3FFFF
+; X64-NEXT: movl $262143, %eax # imm = 0x3FFFF
+; X64-NEXT: cmovbl %ecx, %eax
; X64-NEXT: retq
;
; X86-LABEL: func6:
diff --git a/llvm/test/CodeGen/X86/unknown-location.ll b/llvm/test/CodeGen/X86/unknown-location.ll
index 3b90cf04b6971..6775278d16ae2 100644
--- a/llvm/test/CodeGen/X86/unknown-location.ll
+++ b/llvm/test/CodeGen/X86/unknown-location.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -asm-verbose=false -mtriple=x86_64-apple-darwin10 -use-unknown-locations=Enable | FileCheck %s
; The divide instruction does not have a debug location. CodeGen should
@@ -32,3 +33,5 @@ entry:
!10 = !DIFile(filename: "test.c", directory: "/dir")
!11 = !{}
!12 = !{i32 1, !"Debug Info Version", i32 3}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/X86/urem-power-of-two.ll b/llvm/test/CodeGen/X86/urem-power-of-two.ll
index 16dddfa7e819d..1819bd0740480 100644
--- a/llvm/test/CodeGen/X86/urem-power-of-two.ll
+++ b/llvm/test/CodeGen/X86/urem-power-of-two.ll
@@ -81,20 +81,33 @@ define i8 @and_pow_2(i8 %x, i8 %y) {
; X86-LABEL: and_pow_2:
; X86: # %bb.0:
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: andb $4, %cl
-; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: divb %cl
-; X86-NEXT: movzbl %ah, %eax
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: andb $4, %dl
+; X86-NEXT: cvtsi2ss %ecx, %xmm0
+; X86-NEXT: movzbl %dl, %eax
+; X86-NEXT: cvtsi2ss %eax, %xmm1
+; X86-NEXT: divss %xmm1, %xmm0
+; X86-NEXT: cvttss2si %xmm0, %eax
; X86-NEXT: # kill: def $al killed $al killed $eax
+; X86-NEXT: mulb %dl
+; X86-NEXT: subb %al, %cl
+; X86-NEXT: movl %ecx, %eax
; X86-NEXT: retl
;
; X64-LABEL: and_pow_2:
; X64: # %bb.0:
-; X64-NEXT: andb $4, %sil
-; X64-NEXT: movzbl %dil, %eax
-; X64-NEXT: divb %sil
-; X64-NEXT: movzbl %ah, %eax
+; X64-NEXT: movl %esi, %edx
+; X64-NEXT: andb $4, %dl
+; X64-NEXT: andl $4, %esi
+; X64-NEXT: cvtsi2ss %esi, %xmm0
+; X64-NEXT: movzbl %dil, %ecx
+; X64-NEXT: cvtsi2ss %ecx, %xmm1
+; X64-NEXT: divss %xmm0, %xmm1
+; X64-NEXT: cvttss2si %xmm1, %eax
; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: mulb %dl
+; X64-NEXT: subb %al, %cl
+; X64-NEXT: movl %ecx, %eax
; X64-NEXT: retq
%and = and i8 %y, 4
%urem = urem i8 %x, %and
diff --git a/llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll b/llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
index 54e158d87e792..6244cd320ecf4 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
@@ -430,32 +430,48 @@ define <16 x i8> @test_divconstant_16i8(<16 x i8> %a) nounwind {
define <4 x i32> @test_divv_4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
; SSE2-LABEL: test_divv_4i32:
; SSE2: # %bb.0:
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,3,3,3]
-; SSE2-NEXT: movd %xmm2, %eax
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,3,3,3]
-; SSE2-NEXT: movd %xmm2, %ecx
-; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divl %ecx
-; SSE2-NEXT: movd %eax, %xmm2
-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,2,3]
+; SSE2-NEXT: movd %xmm2, %eax
+; SSE2-NEXT: xorps %xmm2, %xmm2
+; SSE2-NEXT: cvtsi2sd %rax, %xmm2
+; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[3,3,3,3]
; SSE2-NEXT: movd %xmm3, %eax
+; SSE2-NEXT: xorps %xmm3, %xmm3
+; SSE2-NEXT: cvtsi2sd %rax, %xmm3
+; SSE2-NEXT: divsd %xmm2, %xmm3
+; SSE2-NEXT: cvttsd2si %xmm3, %rax
+; SSE2-NEXT: movd %eax, %xmm2
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
-; SSE2-NEXT: movd %xmm3, %ecx
-; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divl %ecx
+; SSE2-NEXT: movd %xmm3, %eax
+; SSE2-NEXT: xorps %xmm3, %xmm3
+; SSE2-NEXT: cvtsi2sd %rax, %xmm3
+; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,2,3]
+; SSE2-NEXT: movd %xmm4, %eax
+; SSE2-NEXT: xorps %xmm4, %xmm4
+; SSE2-NEXT: cvtsi2sd %rax, %xmm4
+; SSE2-NEXT: divsd %xmm3, %xmm4
+; SSE2-NEXT: cvttsd2si %xmm4, %rax
; SSE2-NEXT: movd %eax, %xmm3
; SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
+; SSE2-NEXT: movd %xmm1, %eax
+; SSE2-NEXT: xorps %xmm2, %xmm2
+; SSE2-NEXT: cvtsi2sd %rax, %xmm2
; SSE2-NEXT: movd %xmm0, %eax
-; SSE2-NEXT: movd %xmm1, %ecx
-; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divl %ecx
+; SSE2-NEXT: xorps %xmm4, %xmm4
+; SSE2-NEXT: cvtsi2sd %rax, %xmm4
+; SSE2-NEXT: divsd %xmm2, %xmm4
+; SSE2-NEXT: cvttsd2si %xmm4, %rax
; SSE2-NEXT: movd %eax, %xmm2
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
+; SSE2-NEXT: movd %xmm1, %eax
+; SSE2-NEXT: xorps %xmm1, %xmm1
+; SSE2-NEXT: cvtsi2sd %rax, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE2-NEXT: movd %xmm0, %eax
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
-; SSE2-NEXT: movd %xmm0, %ecx
-; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divl %ecx
+; SSE2-NEXT: xorps %xmm0, %xmm0
+; SSE2-NEXT: cvtsi2sd %rax, %xmm0
+; SSE2-NEXT: divsd %xmm1, %xmm0
+; SSE2-NEXT: cvttsd2si %xmm0, %rax
; SSE2-NEXT: movd %eax, %xmm0
; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
@@ -464,52 +480,71 @@ define <4 x i32> @test_divv_4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
;
; SSE41-LABEL: test_divv_4i32:
; SSE41: # %bb.0:
+; SSE41-NEXT: pextrd $1, %xmm1, %eax
+; SSE41-NEXT: cvtsi2sd %rax, %xmm2
; SSE41-NEXT: pextrd $1, %xmm0, %eax
-; SSE41-NEXT: pextrd $1, %xmm1, %ecx
-; SSE41-NEXT: xorl %edx, %edx
-; SSE41-NEXT: divl %ecx
-; SSE41-NEXT: movl %eax, %ecx
-; SSE41-NEXT: movd %xmm0, %eax
-; SSE41-NEXT: movd %xmm1, %esi
-; SSE41-NEXT: xorl %edx, %edx
-; SSE41-NEXT: divl %esi
-; SSE41-NEXT: movd %eax, %xmm2
-; SSE41-NEXT: pinsrd $1, %ecx, %xmm2
+; SSE41-NEXT: cvtsi2sd %rax, %xmm3
+; SSE41-NEXT: divsd %xmm2, %xmm3
+; SSE41-NEXT: cvttsd2si %xmm3, %rax
+; SSE41-NEXT: movd %xmm1, %ecx
+; SSE41-NEXT: xorps %xmm2, %xmm2
+; SSE41-NEXT: cvtsi2sd %rcx, %xmm2
+; SSE41-NEXT: movd %xmm0, %ecx
+; SSE41-NEXT: xorps %xmm3, %xmm3
+; SSE41-NEXT: cvtsi2sd %rcx, %xmm3
+; SSE41-NEXT: divsd %xmm2, %xmm3
+; SSE41-NEXT: cvttsd2si %xmm3, %rcx
+; SSE41-NEXT: movd %ecx, %xmm2
+; SSE41-NEXT: pinsrd $1, %eax, %xmm2
+; SSE41-NEXT: pextrd $2, %xmm1, %eax
+; SSE41-NEXT: xorps %xmm3, %xmm3
+; SSE41-NEXT: cvtsi2sd %rax, %xmm3
; SSE41-NEXT: pextrd $2, %xmm0, %eax
-; SSE41-NEXT: pextrd $2, %xmm1, %ecx
-; SSE41-NEXT: xorl %edx, %edx
-; SSE41-NEXT: divl %ecx
+; SSE41-NEXT: cvtsi2sd %rax, %xmm4
+; SSE41-NEXT: divsd %xmm3, %xmm4
+; SSE41-NEXT: cvttsd2si %xmm4, %rax
; SSE41-NEXT: pinsrd $2, %eax, %xmm2
+; SSE41-NEXT: pextrd $3, %xmm1, %eax
+; SSE41-NEXT: xorps %xmm1, %xmm1
+; SSE41-NEXT: cvtsi2sd %rax, %xmm1
; SSE41-NEXT: pextrd $3, %xmm0, %eax
-; SSE41-NEXT: pextrd $3, %xmm1, %ecx
-; SSE41-NEXT: xorl %edx, %edx
-; SSE41-NEXT: divl %ecx
+; SSE41-NEXT: xorps %xmm0, %xmm0
+; SSE41-NEXT: cvtsi2sd %rax, %xmm0
+; SSE41-NEXT: divsd %xmm1, %xmm0
+; SSE41-NEXT: cvttsd2si %xmm0, %rax
; SSE41-NEXT: pinsrd $3, %eax, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: test_divv_4i32:
; AVX1: # %bb.0:
-; AVX1-NEXT: vpextrd $1, %xmm0, %eax
-; AVX1-NEXT: vpextrd $1, %xmm1, %ecx
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
-; AVX1-NEXT: movl %eax, %ecx
-; AVX1-NEXT: vmovd %xmm0, %eax
-; AVX1-NEXT: vmovd %xmm1, %esi
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %esi
-; AVX1-NEXT: vmovd %eax, %xmm2
-; AVX1-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2
+; AVX1-NEXT: vpextrd $1, %xmm1, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm2
+; AVX1-NEXT: vextractps $1, %xmm0, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm3
+; AVX1-NEXT: vdivsd %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vcvttsd2si %xmm2, %rax
+; AVX1-NEXT: vmovd %xmm1, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm2
+; AVX1-NEXT: vmovd %xmm0, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm3
+; AVX1-NEXT: vdivsd %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vcvttsd2si %xmm2, %rcx
+; AVX1-NEXT: vmovd %ecx, %xmm2
+; AVX1-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2
+; AVX1-NEXT: vpextrd $2, %xmm1, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm3
; AVX1-NEXT: vpextrd $2, %xmm0, %eax
-; AVX1-NEXT: vpextrd $2, %xmm1, %ecx
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm4
+; AVX1-NEXT: vdivsd %xmm3, %xmm4, %xmm3
+; AVX1-NEXT: vcvttsd2si %xmm3, %rax
; AVX1-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2
+; AVX1-NEXT: vpextrd $3, %xmm1, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm1
; AVX1-NEXT: vpextrd $3, %xmm0, %eax
-; AVX1-NEXT: vpextrd $3, %xmm1, %ecx
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm0
+; AVX1-NEXT: vdivsd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vcvttsd2si %xmm0, %rax
; AVX1-NEXT: vpinsrd $3, %eax, %xmm2, %xmm0
; AVX1-NEXT: retq
;
@@ -2083,33 +2118,57 @@ define <8 x i16> @test_remv_8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
define <4 x i32> @test_remv_4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
; SSE2-LABEL: test_remv_4i32:
; SSE2: # %bb.0:
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,3,3,3]
-; SSE2-NEXT: movd %xmm2, %eax
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,3,3,3]
-; SSE2-NEXT: movd %xmm2, %ecx
-; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divl %ecx
-; SSE2-NEXT: movd %edx, %xmm2
-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,2,3]
-; SSE2-NEXT: movd %xmm3, %eax
-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
+; SSE2-NEXT: movd %xmm2, %eax
+; SSE2-NEXT: xorps %xmm2, %xmm2
+; SSE2-NEXT: cvtsi2sd %rax, %xmm2
+; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[3,3,3,3]
; SSE2-NEXT: movd %xmm3, %ecx
-; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divl %ecx
-; SSE2-NEXT: movd %edx, %xmm3
+; SSE2-NEXT: xorps %xmm3, %xmm3
+; SSE2-NEXT: cvtsi2sd %rcx, %xmm3
+; SSE2-NEXT: divsd %xmm2, %xmm3
+; SSE2-NEXT: cvttsd2si %xmm3, %rdx
+; SSE2-NEXT: imull %eax, %edx
+; SSE2-NEXT: subl %edx, %ecx
+; SSE2-NEXT: movd %ecx, %xmm2
+; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
+; SSE2-NEXT: movd %xmm3, %eax
+; SSE2-NEXT: xorps %xmm3, %xmm3
+; SSE2-NEXT: cvtsi2sd %rax, %xmm3
+; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,2,3]
+; SSE2-NEXT: movd %xmm4, %ecx
+; SSE2-NEXT: xorps %xmm4, %xmm4
+; SSE2-NEXT: cvtsi2sd %rcx, %xmm4
+; SSE2-NEXT: divsd %xmm3, %xmm4
+; SSE2-NEXT: cvttsd2si %xmm4, %rdx
+; SSE2-NEXT: imull %eax, %edx
+; SSE2-NEXT: subl %edx, %ecx
+; SSE2-NEXT: movd %ecx, %xmm3
; SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
-; SSE2-NEXT: movd %xmm0, %eax
-; SSE2-NEXT: movd %xmm1, %ecx
-; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divl %ecx
-; SSE2-NEXT: movd %edx, %xmm2
+; SSE2-NEXT: movd %xmm1, %eax
+; SSE2-NEXT: xorps %xmm2, %xmm2
+; SSE2-NEXT: cvtsi2sd %rax, %xmm2
+; SSE2-NEXT: movd %xmm0, %ecx
+; SSE2-NEXT: xorps %xmm4, %xmm4
+; SSE2-NEXT: cvtsi2sd %rcx, %xmm4
+; SSE2-NEXT: divsd %xmm2, %xmm4
+; SSE2-NEXT: cvttsd2si %xmm4, %rdx
+; SSE2-NEXT: imull %eax, %edx
+; SSE2-NEXT: subl %edx, %ecx
+; SSE2-NEXT: movd %ecx, %xmm2
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
+; SSE2-NEXT: movd %xmm1, %eax
+; SSE2-NEXT: xorps %xmm1, %xmm1
+; SSE2-NEXT: cvtsi2sd %rax, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; SSE2-NEXT: movd %xmm0, %eax
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
; SSE2-NEXT: movd %xmm0, %ecx
-; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divl %ecx
-; SSE2-NEXT: movd %edx, %xmm0
+; SSE2-NEXT: xorps %xmm0, %xmm0
+; SSE2-NEXT: cvtsi2sd %rcx, %xmm0
+; SSE2-NEXT: divsd %xmm1, %xmm0
+; SSE2-NEXT: cvttsd2si %xmm0, %rdx
+; SSE2-NEXT: imull %eax, %edx
+; SSE2-NEXT: subl %edx, %ecx
+; SSE2-NEXT: movd %ecx, %xmm0
; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; SSE2-NEXT: movdqa %xmm2, %xmm0
@@ -2117,53 +2176,88 @@ define <4 x i32> @test_remv_4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
;
; SSE41-LABEL: test_remv_4i32:
; SSE41: # %bb.0:
-; SSE41-NEXT: pextrd $1, %xmm0, %eax
-; SSE41-NEXT: pextrd $1, %xmm1, %ecx
-; SSE41-NEXT: xorl %edx, %edx
-; SSE41-NEXT: divl %ecx
-; SSE41-NEXT: movl %edx, %ecx
-; SSE41-NEXT: movd %xmm0, %eax
-; SSE41-NEXT: movd %xmm1, %esi
-; SSE41-NEXT: xorl %edx, %edx
-; SSE41-NEXT: divl %esi
+; SSE41-NEXT: pextrd $1, %xmm1, %eax
+; SSE41-NEXT: cvtsi2sd %rax, %xmm2
+; SSE41-NEXT: pextrd $1, %xmm0, %ecx
+; SSE41-NEXT: cvtsi2sd %rcx, %xmm3
+; SSE41-NEXT: divsd %xmm2, %xmm3
+; SSE41-NEXT: cvttsd2si %xmm3, %rdx
+; SSE41-NEXT: imull %eax, %edx
+; SSE41-NEXT: subl %edx, %ecx
+; SSE41-NEXT: movd %xmm1, %eax
+; SSE41-NEXT: xorps %xmm2, %xmm2
+; SSE41-NEXT: cvtsi2sd %rax, %xmm2
+; SSE41-NEXT: movd %xmm0, %edx
+; SSE41-NEXT: xorps %xmm3, %xmm3
+; SSE41-NEXT: cvtsi2sd %rdx, %xmm3
+; SSE41-NEXT: divsd %xmm2, %xmm3
+; SSE41-NEXT: cvttsd2si %xmm3, %rsi
+; SSE41-NEXT: imull %eax, %esi
+; SSE41-NEXT: subl %esi, %edx
; SSE41-NEXT: movd %edx, %xmm2
; SSE41-NEXT: pinsrd $1, %ecx, %xmm2
-; SSE41-NEXT: pextrd $2, %xmm0, %eax
-; SSE41-NEXT: pextrd $2, %xmm1, %ecx
-; SSE41-NEXT: xorl %edx, %edx
-; SSE41-NEXT: divl %ecx
-; SSE41-NEXT: pinsrd $2, %edx, %xmm2
-; SSE41-NEXT: pextrd $3, %xmm0, %eax
-; SSE41-NEXT: pextrd $3, %xmm1, %ecx
-; SSE41-NEXT: xorl %edx, %edx
-; SSE41-NEXT: divl %ecx
-; SSE41-NEXT: pinsrd $3, %edx, %xmm2
+; SSE41-NEXT: pextrd $2, %xmm1, %eax
+; SSE41-NEXT: xorps %xmm3, %xmm3
+; SSE41-NEXT: cvtsi2sd %rax, %xmm3
+; SSE41-NEXT: pextrd $2, %xmm0, %ecx
+; SSE41-NEXT: cvtsi2sd %rcx, %xmm4
+; SSE41-NEXT: divsd %xmm3, %xmm4
+; SSE41-NEXT: cvttsd2si %xmm4, %rdx
+; SSE41-NEXT: imull %eax, %edx
+; SSE41-NEXT: subl %edx, %ecx
+; SSE41-NEXT: pinsrd $2, %ecx, %xmm2
+; SSE41-NEXT: pextrd $3, %xmm1, %eax
+; SSE41-NEXT: xorps %xmm1, %xmm1
+; SSE41-NEXT: cvtsi2sd %rax, %xmm1
+; SSE41-NEXT: pextrd $3, %xmm0, %ecx
+; SSE41-NEXT: xorps %xmm0, %xmm0
+; SSE41-NEXT: cvtsi2sd %rcx, %xmm0
+; SSE41-NEXT: divsd %xmm1, %xmm0
+; SSE41-NEXT: cvttsd2si %xmm0, %rdx
+; SSE41-NEXT: imull %eax, %edx
+; SSE41-NEXT: subl %edx, %ecx
+; SSE41-NEXT: pinsrd $3, %ecx, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: test_remv_4i32:
; AVX1: # %bb.0:
-; AVX1-NEXT: vpextrd $1, %xmm0, %eax
-; AVX1-NEXT: vpextrd $1, %xmm1, %ecx
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
-; AVX1-NEXT: movl %edx, %ecx
-; AVX1-NEXT: vmovd %xmm0, %eax
-; AVX1-NEXT: vmovd %xmm1, %esi
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %esi
+; AVX1-NEXT: vpextrd $1, %xmm1, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm2
+; AVX1-NEXT: vextractps $1, %xmm0, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm3
+; AVX1-NEXT: vdivsd %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vcvttsd2si %xmm2, %rdx
+; AVX1-NEXT: imull %eax, %edx
+; AVX1-NEXT: subl %edx, %ecx
+; AVX1-NEXT: vmovd %xmm1, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm2
+; AVX1-NEXT: vmovd %xmm0, %edx
+; AVX1-NEXT: vcvtsi2sd %rdx, %xmm15, %xmm3
+; AVX1-NEXT: vdivsd %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vcvttsd2si %xmm2, %rsi
+; AVX1-NEXT: imull %eax, %esi
+; AVX1-NEXT: subl %esi, %edx
; AVX1-NEXT: vmovd %edx, %xmm2
; AVX1-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2
-; AVX1-NEXT: vpextrd $2, %xmm0, %eax
-; AVX1-NEXT: vpextrd $2, %xmm1, %ecx
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
-; AVX1-NEXT: vpinsrd $2, %edx, %xmm2, %xmm2
-; AVX1-NEXT: vpextrd $3, %xmm0, %eax
-; AVX1-NEXT: vpextrd $3, %xmm1, %ecx
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
-; AVX1-NEXT: vpinsrd $3, %edx, %xmm2, %xmm0
+; AVX1-NEXT: vpextrd $2, %xmm1, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm3
+; AVX1-NEXT: vpextrd $2, %xmm0, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm4
+; AVX1-NEXT: vdivsd %xmm3, %xmm4, %xmm3
+; AVX1-NEXT: vcvttsd2si %xmm3, %rdx
+; AVX1-NEXT: imull %eax, %edx
+; AVX1-NEXT: subl %edx, %ecx
+; AVX1-NEXT: vpinsrd $2, %ecx, %xmm2, %xmm2
+; AVX1-NEXT: vpextrd $3, %xmm1, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm1
+; AVX1-NEXT: vpextrd $3, %xmm0, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm0
+; AVX1-NEXT: vdivsd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vcvttsd2si %xmm0, %rdx
+; AVX1-NEXT: imull %eax, %edx
+; AVX1-NEXT: subl %edx, %ecx
+; AVX1-NEXT: vpinsrd $3, %ecx, %xmm2, %xmm0
; AVX1-NEXT: retq
;
; AVX2NOBW-LABEL: test_remv_4i32:
diff --git a/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll b/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
index 1353c09e4e3f1..0ed4155e74bec 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
@@ -352,49 +352,63 @@ define <32 x i8> @test_divconstant_32i8(<32 x i8> %a) nounwind {
define <8 x i32> @test_divv_8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
; AVX1-LABEL: test_divv_8i32:
; AVX1: # %bb.0:
-; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
; AVX1-NEXT: vpextrd $1, %xmm2, %eax
-; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
-; AVX1-NEXT: vpextrd $1, %xmm3, %ecx
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
-; AVX1-NEXT: movl %eax, %ecx
-; AVX1-NEXT: vmovd %xmm2, %eax
-; AVX1-NEXT: vmovd %xmm3, %esi
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %esi
-; AVX1-NEXT: vmovd %eax, %xmm4
-; AVX1-NEXT: vpinsrd $1, %ecx, %xmm4, %xmm4
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm3
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4
+; AVX1-NEXT: vpextrd $1, %xmm4, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm5
+; AVX1-NEXT: vdivsd %xmm3, %xmm5, %xmm3
+; AVX1-NEXT: vcvttsd2si %xmm3, %rax
+; AVX1-NEXT: vmovd %xmm2, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm3
+; AVX1-NEXT: vmovd %xmm4, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm5
+; AVX1-NEXT: vdivsd %xmm3, %xmm5, %xmm3
+; AVX1-NEXT: vcvttsd2si %xmm3, %rcx
+; AVX1-NEXT: vmovd %ecx, %xmm3
+; AVX1-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3
; AVX1-NEXT: vpextrd $2, %xmm2, %eax
-; AVX1-NEXT: vpextrd $2, %xmm3, %ecx
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
-; AVX1-NEXT: vpinsrd $2, %eax, %xmm4, %xmm4
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm5
+; AVX1-NEXT: vpextrd $2, %xmm4, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm6
+; AVX1-NEXT: vdivsd %xmm5, %xmm6, %xmm5
+; AVX1-NEXT: vcvttsd2si %xmm5, %rax
+; AVX1-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3
; AVX1-NEXT: vpextrd $3, %xmm2, %eax
-; AVX1-NEXT: vpextrd $3, %xmm3, %ecx
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
-; AVX1-NEXT: vpinsrd $3, %eax, %xmm4, %xmm2
-; AVX1-NEXT: vpextrd $1, %xmm0, %eax
-; AVX1-NEXT: vpextrd $1, %xmm1, %ecx
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
-; AVX1-NEXT: movl %eax, %ecx
-; AVX1-NEXT: vmovd %xmm0, %eax
-; AVX1-NEXT: vmovd %xmm1, %esi
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %esi
-; AVX1-NEXT: vmovd %eax, %xmm3
-; AVX1-NEXT: vpinsrd $1, %ecx, %xmm3, %xmm3
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm2
+; AVX1-NEXT: vpextrd $3, %xmm4, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm4
+; AVX1-NEXT: vdivsd %xmm2, %xmm4, %xmm2
+; AVX1-NEXT: vcvttsd2si %xmm2, %rax
+; AVX1-NEXT: vpinsrd $3, %eax, %xmm3, %xmm2
+; AVX1-NEXT: vpextrd $1, %xmm1, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm3
+; AVX1-NEXT: vextractps $1, %xmm0, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm4
+; AVX1-NEXT: vdivsd %xmm3, %xmm4, %xmm3
+; AVX1-NEXT: vcvttsd2si %xmm3, %rax
+; AVX1-NEXT: vmovd %xmm1, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm3
+; AVX1-NEXT: vmovd %xmm0, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm4
+; AVX1-NEXT: vdivsd %xmm3, %xmm4, %xmm3
+; AVX1-NEXT: vcvttsd2si %xmm3, %rcx
+; AVX1-NEXT: vmovd %ecx, %xmm3
+; AVX1-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3
+; AVX1-NEXT: vpextrd $2, %xmm1, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm4
; AVX1-NEXT: vpextrd $2, %xmm0, %eax
-; AVX1-NEXT: vpextrd $2, %xmm1, %ecx
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm5
+; AVX1-NEXT: vdivsd %xmm4, %xmm5, %xmm4
+; AVX1-NEXT: vcvttsd2si %xmm4, %rax
; AVX1-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3
+; AVX1-NEXT: vpextrd $3, %xmm1, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm1
; AVX1-NEXT: vpextrd $3, %xmm0, %eax
-; AVX1-NEXT: vpextrd $3, %xmm1, %ecx
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm0
+; AVX1-NEXT: vdivsd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vcvttsd2si %xmm0, %rax
; AVX1-NEXT: vpinsrd $3, %eax, %xmm3, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq
@@ -981,50 +995,80 @@ define <32 x i8> @test_remconstant_32i8(<32 x i8> %a) nounwind {
define <8 x i32> @test_remv_8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
; AVX1-LABEL: test_remv_8i32:
; AVX1: # %bb.0:
-; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
; AVX1-NEXT: vpextrd $1, %xmm2, %eax
-; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm4
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
; AVX1-NEXT: vpextrd $1, %xmm3, %ecx
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
-; AVX1-NEXT: movl %edx, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm5
+; AVX1-NEXT: vdivsd %xmm4, %xmm5, %xmm4
+; AVX1-NEXT: vcvttsd2si %xmm4, %rdx
+; AVX1-NEXT: imull %eax, %edx
+; AVX1-NEXT: subl %edx, %ecx
; AVX1-NEXT: vmovd %xmm2, %eax
-; AVX1-NEXT: vmovd %xmm3, %esi
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %esi
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm4
+; AVX1-NEXT: vmovd %xmm3, %edx
+; AVX1-NEXT: vcvtsi2sd %rdx, %xmm15, %xmm5
+; AVX1-NEXT: vdivsd %xmm4, %xmm5, %xmm4
+; AVX1-NEXT: vcvttsd2si %xmm4, %rsi
+; AVX1-NEXT: imull %eax, %esi
+; AVX1-NEXT: subl %esi, %edx
; AVX1-NEXT: vmovd %edx, %xmm4
; AVX1-NEXT: vpinsrd $1, %ecx, %xmm4, %xmm4
; AVX1-NEXT: vpextrd $2, %xmm2, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm5
; AVX1-NEXT: vpextrd $2, %xmm3, %ecx
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
-; AVX1-NEXT: vpinsrd $2, %edx, %xmm4, %xmm4
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm6
+; AVX1-NEXT: vdivsd %xmm5, %xmm6, %xmm5
+; AVX1-NEXT: vcvttsd2si %xmm5, %rdx
+; AVX1-NEXT: imull %eax, %edx
+; AVX1-NEXT: subl %edx, %ecx
+; AVX1-NEXT: vpinsrd $2, %ecx, %xmm4, %xmm4
; AVX1-NEXT: vpextrd $3, %xmm2, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm2
; AVX1-NEXT: vpextrd $3, %xmm3, %ecx
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
-; AVX1-NEXT: vpinsrd $3, %edx, %xmm4, %xmm2
-; AVX1-NEXT: vpextrd $1, %xmm0, %eax
-; AVX1-NEXT: vpextrd $1, %xmm1, %ecx
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
-; AVX1-NEXT: movl %edx, %ecx
-; AVX1-NEXT: vmovd %xmm0, %eax
-; AVX1-NEXT: vmovd %xmm1, %esi
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %esi
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm3
+; AVX1-NEXT: vdivsd %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vcvttsd2si %xmm2, %rdx
+; AVX1-NEXT: imull %eax, %edx
+; AVX1-NEXT: subl %edx, %ecx
+; AVX1-NEXT: vpinsrd $3, %ecx, %xmm4, %xmm2
+; AVX1-NEXT: vpextrd $1, %xmm1, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm3
+; AVX1-NEXT: vextractps $1, %xmm0, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm4
+; AVX1-NEXT: vdivsd %xmm3, %xmm4, %xmm3
+; AVX1-NEXT: vcvttsd2si %xmm3, %rdx
+; AVX1-NEXT: imull %eax, %edx
+; AVX1-NEXT: subl %edx, %ecx
+; AVX1-NEXT: vmovd %xmm1, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm3
+; AVX1-NEXT: vmovd %xmm0, %edx
+; AVX1-NEXT: vcvtsi2sd %rdx, %xmm15, %xmm4
+; AVX1-NEXT: vdivsd %xmm3, %xmm4, %xmm3
+; AVX1-NEXT: vcvttsd2si %xmm3, %rsi
+; AVX1-NEXT: imull %eax, %esi
+; AVX1-NEXT: subl %esi, %edx
; AVX1-NEXT: vmovd %edx, %xmm3
; AVX1-NEXT: vpinsrd $1, %ecx, %xmm3, %xmm3
-; AVX1-NEXT: vpextrd $2, %xmm0, %eax
-; AVX1-NEXT: vpextrd $2, %xmm1, %ecx
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
-; AVX1-NEXT: vpinsrd $2, %edx, %xmm3, %xmm3
-; AVX1-NEXT: vpextrd $3, %xmm0, %eax
-; AVX1-NEXT: vpextrd $3, %xmm1, %ecx
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
-; AVX1-NEXT: vpinsrd $3, %edx, %xmm3, %xmm0
+; AVX1-NEXT: vpextrd $2, %xmm1, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm4
+; AVX1-NEXT: vpextrd $2, %xmm0, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm5
+; AVX1-NEXT: vdivsd %xmm4, %xmm5, %xmm4
+; AVX1-NEXT: vcvttsd2si %xmm4, %rdx
+; AVX1-NEXT: imull %eax, %edx
+; AVX1-NEXT: subl %edx, %ecx
+; AVX1-NEXT: vpinsrd $2, %ecx, %xmm3, %xmm3
+; AVX1-NEXT: vpextrd $3, %xmm1, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm1
+; AVX1-NEXT: vpextrd $3, %xmm0, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm0
+; AVX1-NEXT: vdivsd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vcvttsd2si %xmm0, %rdx
+; AVX1-NEXT: imull %eax, %edx
+; AVX1-NEXT: subl %edx, %ecx
+; AVX1-NEXT: vpinsrd $3, %ecx, %xmm3, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/vector-idiv-v2i32.ll b/llvm/test/CodeGen/X86/vector-idiv-v2i32.ll
index 36b9631e276e9..5cca5ab0375aa 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-v2i32.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-v2i32.ll
@@ -323,48 +323,80 @@ define void @test_srem_pow2_v2i32(ptr %x, ptr %y) nounwind {
define void @test_udiv_v2i32(ptr %x, ptr %y, ptr %z) nounwind {
; X64-LABEL: test_udiv_v2i32:
; X64: # %bb.0:
-; X64-NEXT: movq %rdx, %rcx
; X64-NEXT: movq (%rdi), %rax
; X64-NEXT: movq %rax, %xmm0
-; X64-NEXT: movq (%rsi), %rsi
-; X64-NEXT: movq %rsi, %xmm1
-; X64-NEXT: # kill: def $eax killed $eax killed $rax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %esi
+; X64-NEXT: movq (%rsi), %rcx
+; X64-NEXT: movq %rcx, %xmm1
+; X64-NEXT: movl %ecx, %ecx
+; X64-NEXT: cvtsi2sd %rcx, %xmm2
+; X64-NEXT: movl %eax, %eax
+; X64-NEXT: cvtsi2sd %rax, %xmm3
+; X64-NEXT: divsd %xmm2, %xmm3
+; X64-NEXT: cvttsd2si %xmm3, %rax
; X64-NEXT: movd %eax, %xmm2
+; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
+; X64-NEXT: movd %xmm1, %eax
+; X64-NEXT: xorps %xmm1, %xmm1
+; X64-NEXT: cvtsi2sd %rax, %xmm1
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
-; X64-NEXT: movd %xmm0, %esi
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %esi
+; X64-NEXT: xorps %xmm0, %xmm0
+; X64-NEXT: cvtsi2sd %rax, %xmm0
+; X64-NEXT: divsd %xmm1, %xmm0
+; X64-NEXT: cvttsd2si %xmm0, %rax
; X64-NEXT: movd %eax, %xmm0
; X64-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
-; X64-NEXT: movq %xmm2, (%rcx)
+; X64-NEXT: movq %xmm2, (%rdx)
; X64-NEXT: retq
;
; X86-LABEL: test_udiv_v2i32:
; X86: # %bb.0:
; X86-NEXT: pushl %esi
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
-; X86-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
-; X86-NEXT: movd %xmm0, %eax
-; X86-NEXT: movd %xmm1, %esi
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %esi
-; X86-NEXT: movd %eax, %xmm2
-; X86-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; X86-NEXT: movd %xmm0, %eax
+; X86-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
+; X86-NEXT: xorps %xmm0, %xmm0
+; X86-NEXT: xorps %xmm3, %xmm3
+; X86-NEXT: movss {{.*#+}} xmm3 = xmm1[0],xmm3[1,2,3]
+; X86-NEXT: movsd {{.*#+}} xmm5 = mem[0],zero
+; X86-NEXT: xorps %xmm4, %xmm4
+; X86-NEXT: movss {{.*#+}} xmm4 = xmm5[0],xmm4[1,2,3]
+; X86-NEXT: movsd {{.*#+}} xmm2 = [4.503599627370496E+15,0.0E+0]
+; X86-NEXT: orps %xmm2, %xmm4
+; X86-NEXT: subsd %xmm2, %xmm4
+; X86-NEXT: orps %xmm2, %xmm3
+; X86-NEXT: subsd %xmm2, %xmm3
+; X86-NEXT: divsd %xmm4, %xmm3
+; X86-NEXT: cvttsd2si %xmm3, %ecx
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: sarl $31, %edx
+; X86-NEXT: movsd {{.*#+}} xmm4 = [2.147483648E+9,0.0E+0]
+; X86-NEXT: subsd %xmm4, %xmm3
+; X86-NEXT: cvttsd2si %xmm3, %esi
+; X86-NEXT: andl %edx, %esi
+; X86-NEXT: orl %ecx, %esi
+; X86-NEXT: movd %esi, %xmm3
+; X86-NEXT: shufps {{.*#+}} xmm5 = xmm5[1,1,1,1]
+; X86-NEXT: xorps %xmm6, %xmm6
+; X86-NEXT: movss {{.*#+}} xmm6 = xmm5[0],xmm6[1,2,3]
+; X86-NEXT: orps %xmm2, %xmm6
+; X86-NEXT: subsd %xmm2, %xmm6
; X86-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1]
-; X86-NEXT: movd %xmm1, %esi
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %esi
-; X86-NEXT: movd %eax, %xmm0
-; X86-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
-; X86-NEXT: movq %xmm2, (%ecx)
+; X86-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; X86-NEXT: orps %xmm2, %xmm0
+; X86-NEXT: subsd %xmm2, %xmm0
+; X86-NEXT: divsd %xmm6, %xmm0
+; X86-NEXT: cvttsd2si %xmm0, %ecx
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: sarl $31, %edx
+; X86-NEXT: subsd %xmm4, %xmm0
+; X86-NEXT: cvttsd2si %xmm0, %esi
+; X86-NEXT: andl %edx, %esi
+; X86-NEXT: orl %ecx, %esi
+; X86-NEXT: movd %esi, %xmm0
+; X86-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1]
+; X86-NEXT: movq %xmm3, (%eax)
; X86-NEXT: popl %esi
; X86-NEXT: retl
%a = load <2 x i32>, ptr %x
@@ -377,48 +409,92 @@ define void @test_udiv_v2i32(ptr %x, ptr %y, ptr %z) nounwind {
define void @test_urem_v2i32(ptr %x, ptr %y, ptr %z) nounwind {
; X64-LABEL: test_urem_v2i32:
; X64: # %bb.0:
-; X64-NEXT: movq %rdx, %rcx
; X64-NEXT: movq (%rdi), %rax
; X64-NEXT: movq %rax, %xmm0
-; X64-NEXT: movq (%rsi), %rsi
-; X64-NEXT: movq %rsi, %xmm1
-; X64-NEXT: # kill: def $eax killed $eax killed $rax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %esi
-; X64-NEXT: movd %edx, %xmm2
+; X64-NEXT: movq (%rsi), %rcx
+; X64-NEXT: movq %rcx, %xmm1
+; X64-NEXT: movl %ecx, %esi
+; X64-NEXT: cvtsi2sd %rsi, %xmm2
+; X64-NEXT: movl %eax, %esi
+; X64-NEXT: cvtsi2sd %rsi, %xmm3
+; X64-NEXT: divsd %xmm2, %xmm3
+; X64-NEXT: cvttsd2si %xmm3, %rsi
+; X64-NEXT: imull %ecx, %esi
+; X64-NEXT: subl %esi, %eax
+; X64-NEXT: movd %eax, %xmm2
+; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
+; X64-NEXT: movd %xmm1, %eax
+; X64-NEXT: xorps %xmm1, %xmm1
+; X64-NEXT: cvtsi2sd %rax, %xmm1
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
-; X64-NEXT: movd %xmm0, %esi
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divl %esi
-; X64-NEXT: movd %edx, %xmm0
+; X64-NEXT: movd %xmm0, %ecx
+; X64-NEXT: xorps %xmm0, %xmm0
+; X64-NEXT: cvtsi2sd %rcx, %xmm0
+; X64-NEXT: divsd %xmm1, %xmm0
+; X64-NEXT: cvttsd2si %xmm0, %rsi
+; X64-NEXT: imull %eax, %esi
+; X64-NEXT: subl %esi, %ecx
+; X64-NEXT: movd %ecx, %xmm0
; X64-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
-; X64-NEXT: movq %xmm2, (%rcx)
+; X64-NEXT: movq %xmm2, (%rdx)
; X64-NEXT: retq
;
; X86-LABEL: test_urem_v2i32:
; X86: # %bb.0:
; X86-NEXT: pushl %esi
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
-; X86-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
-; X86-NEXT: movd %xmm0, %eax
-; X86-NEXT: movd %xmm1, %esi
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %esi
-; X86-NEXT: movd %edx, %xmm2
-; X86-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; X86-NEXT: movd %xmm0, %eax
+; X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
+; X86-NEXT: xorps %xmm2, %xmm2
+; X86-NEXT: xorps %xmm4, %xmm4
+; X86-NEXT: movss {{.*#+}} xmm4 = xmm0[0],xmm4[1,2,3]
+; X86-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
+; X86-NEXT: xorps %xmm5, %xmm5
+; X86-NEXT: movss {{.*#+}} xmm5 = xmm1[0],xmm5[1,2,3]
+; X86-NEXT: movsd {{.*#+}} xmm3 = [4.503599627370496E+15,0.0E+0]
+; X86-NEXT: orps %xmm3, %xmm5
+; X86-NEXT: subsd %xmm3, %xmm5
+; X86-NEXT: orps %xmm3, %xmm4
+; X86-NEXT: subsd %xmm3, %xmm4
+; X86-NEXT: divsd %xmm5, %xmm4
+; X86-NEXT: cvttsd2si %xmm4, %ecx
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: sarl $31, %edx
+; X86-NEXT: movsd {{.*#+}} xmm5 = [2.147483648E+9,0.0E+0]
+; X86-NEXT: subsd %xmm5, %xmm4
+; X86-NEXT: cvttsd2si %xmm4, %esi
+; X86-NEXT: andl %edx, %esi
+; X86-NEXT: orl %ecx, %esi
+; X86-NEXT: movd %xmm1, %ecx
+; X86-NEXT: imull %esi, %ecx
+; X86-NEXT: movd %xmm0, %edx
+; X86-NEXT: subl %ecx, %edx
+; X86-NEXT: movd %edx, %xmm4
; X86-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1]
-; X86-NEXT: movd %xmm1, %esi
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: divl %esi
+; X86-NEXT: xorps %xmm6, %xmm6
+; X86-NEXT: movss {{.*#+}} xmm6 = xmm1[0],xmm6[1,2,3]
+; X86-NEXT: orps %xmm3, %xmm6
+; X86-NEXT: subsd %xmm3, %xmm6
+; X86-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
+; X86-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
+; X86-NEXT: orps %xmm3, %xmm2
+; X86-NEXT: subsd %xmm3, %xmm2
+; X86-NEXT: divsd %xmm6, %xmm2
+; X86-NEXT: cvttsd2si %xmm2, %ecx
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: sarl $31, %edx
+; X86-NEXT: subsd %xmm5, %xmm2
+; X86-NEXT: cvttsd2si %xmm2, %esi
+; X86-NEXT: andl %edx, %esi
+; X86-NEXT: orl %ecx, %esi
+; X86-NEXT: movd %xmm1, %ecx
+; X86-NEXT: imull %esi, %ecx
+; X86-NEXT: movd %xmm0, %edx
+; X86-NEXT: subl %ecx, %edx
; X86-NEXT: movd %edx, %xmm0
-; X86-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
-; X86-NEXT: movq %xmm2, (%ecx)
+; X86-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm0[0],xmm4[1],xmm0[1]
+; X86-NEXT: movq %xmm4, (%eax)
; X86-NEXT: popl %esi
; X86-NEXT: retl
%a = load <2 x i32>, ptr %x
diff --git a/llvm/test/CodeGen/X86/vector-rem.ll b/llvm/test/CodeGen/X86/vector-rem.ll
index f9124ae05b392..c7bb7c43b4742 100644
--- a/llvm/test/CodeGen/X86/vector-rem.ll
+++ b/llvm/test/CodeGen/X86/vector-rem.ll
@@ -31,33 +31,57 @@ define <4 x i32> @foo(<4 x i32> %t, <4 x i32> %u) nounwind {
define <4 x i32> @bar(<4 x i32> %t, <4 x i32> %u) nounwind {
; CHECK-LABEL: bar:
; CHECK: # %bb.0:
-; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,3,3,3]
-; CHECK-NEXT: movd %xmm2, %eax
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,3,3,3]
-; CHECK-NEXT: movd %xmm2, %ecx
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ecx
-; CHECK-NEXT: movd %edx, %xmm2
-; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,2,3]
-; CHECK-NEXT: movd %xmm3, %eax
-; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
+; CHECK-NEXT: movd %xmm2, %eax
+; CHECK-NEXT: xorps %xmm2, %xmm2
+; CHECK-NEXT: cvtsi2sd %rax, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm0[3,3,3,3]
; CHECK-NEXT: movd %xmm3, %ecx
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ecx
-; CHECK-NEXT: movd %edx, %xmm3
+; CHECK-NEXT: xorps %xmm3, %xmm3
+; CHECK-NEXT: cvtsi2sd %rcx, %xmm3
+; CHECK-NEXT: divsd %xmm2, %xmm3
+; CHECK-NEXT: cvttsd2si %xmm3, %rdx
+; CHECK-NEXT: imull %eax, %edx
+; CHECK-NEXT: subl %edx, %ecx
+; CHECK-NEXT: movd %ecx, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
+; CHECK-NEXT: movd %xmm3, %eax
+; CHECK-NEXT: xorps %xmm3, %xmm3
+; CHECK-NEXT: cvtsi2sd %rax, %xmm3
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,2,3]
+; CHECK-NEXT: movd %xmm4, %ecx
+; CHECK-NEXT: xorps %xmm4, %xmm4
+; CHECK-NEXT: cvtsi2sd %rcx, %xmm4
+; CHECK-NEXT: divsd %xmm3, %xmm4
+; CHECK-NEXT: cvttsd2si %xmm4, %rdx
+; CHECK-NEXT: imull %eax, %edx
+; CHECK-NEXT: subl %edx, %ecx
+; CHECK-NEXT: movd %ecx, %xmm3
; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
-; CHECK-NEXT: movd %xmm0, %eax
-; CHECK-NEXT: movd %xmm1, %ecx
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ecx
-; CHECK-NEXT: movd %edx, %xmm2
+; CHECK-NEXT: movd %xmm1, %eax
+; CHECK-NEXT: xorps %xmm2, %xmm2
+; CHECK-NEXT: cvtsi2sd %rax, %xmm2
+; CHECK-NEXT: movd %xmm0, %ecx
+; CHECK-NEXT: xorps %xmm4, %xmm4
+; CHECK-NEXT: cvtsi2sd %rcx, %xmm4
+; CHECK-NEXT: divsd %xmm2, %xmm4
+; CHECK-NEXT: cvttsd2si %xmm4, %rdx
+; CHECK-NEXT: imull %eax, %edx
+; CHECK-NEXT: subl %edx, %ecx
+; CHECK-NEXT: movd %ecx, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
+; CHECK-NEXT: movd %xmm1, %eax
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: cvtsi2sd %rax, %xmm1
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; CHECK-NEXT: movd %xmm0, %eax
-; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
; CHECK-NEXT: movd %xmm0, %ecx
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ecx
-; CHECK-NEXT: movd %edx, %xmm0
+; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: cvtsi2sd %rcx, %xmm0
+; CHECK-NEXT: divsd %xmm1, %xmm0
+; CHECK-NEXT: cvttsd2si %xmm0, %rdx
+; CHECK-NEXT: imull %eax, %edx
+; CHECK-NEXT: subl %edx, %ecx
+; CHECK-NEXT: movd %ecx, %xmm0
; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; CHECK-NEXT: movdqa %xmm2, %xmm0
diff --git a/llvm/test/CodeGen/X86/x86-cmov-converter.ll b/llvm/test/CodeGen/X86/x86-cmov-converter.ll
index b02da217e76b2..539736b2dbb13 100644
--- a/llvm/test/CodeGen/X86/x86-cmov-converter.ll
+++ b/llvm/test/CodeGen/X86/x86-cmov-converter.ll
@@ -191,24 +191,25 @@ define void @CmovNotInHotPath(i32 %n, i32 %a, i32 %b, ptr nocapture %c, ptr noca
; CHECK-NEXT: testl %edi, %edi
; CHECK-NEXT: jle .LBB1_3
; CHECK-NEXT: # %bb.1: # %for.body.preheader
-; CHECK-NEXT: movl %edx, %r9d
-; CHECK-NEXT: movl %edi, %edi
-; CHECK-NEXT: xorl %r10d, %r10d
-; CHECK-NEXT: movl $10, %r11d
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: xorl %edi, %edi
+; CHECK-NEXT: movl $10, %r9d
+; CHECK-NEXT: cvtsi2sd %edx, %xmm0
; CHECK-NEXT: .LBB1_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: movl (%rcx,%r10,4), %eax
-; CHECK-NEXT: movl %eax, %edx
-; CHECK-NEXT: imull %esi, %edx
-; CHECK-NEXT: cmpl %r9d, %edx
-; CHECK-NEXT: cmovgl %r11d, %eax
-; CHECK-NEXT: movl %eax, (%rcx,%r10,4)
-; CHECK-NEXT: movl (%r8,%r10,4), %eax
-; CHECK-NEXT: cltd
-; CHECK-NEXT: idivl %r9d
-; CHECK-NEXT: movl %eax, (%r8,%r10,4)
-; CHECK-NEXT: addq $1, %r10
-; CHECK-NEXT: cmpq %r10, %rdi
+; CHECK-NEXT: movl (%rcx,%rdi,4), %r10d
+; CHECK-NEXT: movl %r10d, %r11d
+; CHECK-NEXT: imull %esi, %r11d
+; CHECK-NEXT: cmpl %edx, %r11d
+; CHECK-NEXT: cmovgl %r9d, %r10d
+; CHECK-NEXT: movl %r10d, (%rcx,%rdi,4)
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: cvtsi2sdl (%r8,%rdi,4), %xmm1
+; CHECK-NEXT: divsd %xmm0, %xmm1
+; CHECK-NEXT: cvttsd2si %xmm1, %r10d
+; CHECK-NEXT: movl %r10d, (%r8,%rdi,4)
+; CHECK-NEXT: addq $1, %rdi
+; CHECK-NEXT: cmpq %rdi, %rax
; CHECK-NEXT: jne .LBB1_2
; CHECK-NEXT: .LBB1_3: # %for.cond.cleanup
; CHECK-NEXT: retq
@@ -218,29 +219,30 @@ define void @CmovNotInHotPath(i32 %n, i32 %a, i32 %b, ptr nocapture %c, ptr noca
; CHECK-FORCEALL-NEXT: testl %edi, %edi
; CHECK-FORCEALL-NEXT: jle .LBB1_5
; CHECK-FORCEALL-NEXT: # %bb.1: # %for.body.preheader
-; CHECK-FORCEALL-NEXT: movl %edx, %r9d
-; CHECK-FORCEALL-NEXT: movl %edi, %edi
-; CHECK-FORCEALL-NEXT: xorl %r10d, %r10d
+; CHECK-FORCEALL-NEXT: movl %edi, %eax
+; CHECK-FORCEALL-NEXT: xorl %edi, %edi
+; CHECK-FORCEALL-NEXT: cvtsi2sd %edx, %xmm0
; CHECK-FORCEALL-NEXT: .LBB1_2: # %for.body
; CHECK-FORCEALL-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-FORCEALL-NEXT: movl (%rcx,%r10,4), %eax
-; CHECK-FORCEALL-NEXT: movl %eax, %r11d
+; CHECK-FORCEALL-NEXT: movl (%rcx,%rdi,4), %r9d
+; CHECK-FORCEALL-NEXT: movl %r9d, %r11d
; CHECK-FORCEALL-NEXT: imull %esi, %r11d
-; CHECK-FORCEALL-NEXT: movl $10, %edx
-; CHECK-FORCEALL-NEXT: cmpl %r9d, %r11d
+; CHECK-FORCEALL-NEXT: movl $10, %r10d
+; CHECK-FORCEALL-NEXT: cmpl %edx, %r11d
; CHECK-FORCEALL-NEXT: jg .LBB1_4
; CHECK-FORCEALL-NEXT: # %bb.3: # %for.body
; CHECK-FORCEALL-NEXT: # in Loop: Header=BB1_2 Depth=1
-; CHECK-FORCEALL-NEXT: movl %eax, %edx
+; CHECK-FORCEALL-NEXT: movl %r9d, %r10d
; CHECK-FORCEALL-NEXT: .LBB1_4: # %for.body
; CHECK-FORCEALL-NEXT: # in Loop: Header=BB1_2 Depth=1
-; CHECK-FORCEALL-NEXT: movl %edx, (%rcx,%r10,4)
-; CHECK-FORCEALL-NEXT: movl (%r8,%r10,4), %eax
-; CHECK-FORCEALL-NEXT: cltd
-; CHECK-FORCEALL-NEXT: idivl %r9d
-; CHECK-FORCEALL-NEXT: movl %eax, (%r8,%r10,4)
-; CHECK-FORCEALL-NEXT: addq $1, %r10
-; CHECK-FORCEALL-NEXT: cmpq %r10, %rdi
+; CHECK-FORCEALL-NEXT: movl %r10d, (%rcx,%rdi,4)
+; CHECK-FORCEALL-NEXT: xorps %xmm1, %xmm1
+; CHECK-FORCEALL-NEXT: cvtsi2sdl (%r8,%rdi,4), %xmm1
+; CHECK-FORCEALL-NEXT: divsd %xmm0, %xmm1
+; CHECK-FORCEALL-NEXT: cvttsd2si %xmm1, %r9d
+; CHECK-FORCEALL-NEXT: movl %r9d, (%r8,%rdi,4)
+; CHECK-FORCEALL-NEXT: addq $1, %rdi
+; CHECK-FORCEALL-NEXT: cmpq %rdi, %rax
; CHECK-FORCEALL-NEXT: jne .LBB1_2
; CHECK-FORCEALL-NEXT: .LBB1_5: # %for.cond.cleanup
; CHECK-FORCEALL-NEXT: retq
@@ -597,68 +599,76 @@ define void @Transform(ptr%arr, ptr%arr2, i32 %a, i32 %b, i32 %c, i32 %n) #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: testb %al, %al
-; CHECK-NEXT: jne .LBB6_5
+; CHECK-NEXT: jne .LBB6_3
; CHECK-NEXT: # %bb.1: # %while.body.preheader
+; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: movl %edx, %ecx
-; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cvtsi2sd %rcx, %xmm0
+; CHECK-NEXT: movl $11, %ecx
; CHECK-NEXT: .LBB6_2: # %while.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: movslq %esi, %rsi
-; CHECK-NEXT: movl (%rdi,%rsi,4), %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %ecx
-; CHECK-NEXT: movl %eax, %edx
-; CHECK-NEXT: movl $11, %eax
-; CHECK-NEXT: movl %ecx, %r8d
-; CHECK-NEXT: cmpl %ecx, %edx
-; CHECK-NEXT: ja .LBB6_4
-; CHECK-NEXT: # %bb.3: # %while.body
-; CHECK-NEXT: # in Loop: Header=BB6_2 Depth=1
-; CHECK-NEXT: movl $22, %eax
-; CHECK-NEXT: movl $22, %r8d
-; CHECK-NEXT: .LBB6_4: # %while.body
-; CHECK-NEXT: # in Loop: Header=BB6_2 Depth=1
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %r8d
-; CHECK-NEXT: movl %edx, (%rdi,%rsi,4)
-; CHECK-NEXT: addl $1, %esi
-; CHECK-NEXT: cmpl %r9d, %esi
+; CHECK-NEXT: cltq
+; CHECK-NEXT: movl (%rdi,%rax,4), %esi
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: cvtsi2sd %rsi, %xmm1
+; CHECK-NEXT: divsd %xmm0, %xmm1
+; CHECK-NEXT: cvttsd2si %xmm1, %rsi
+; CHECK-NEXT: cmpl %edx, %esi
+; CHECK-NEXT: movl $22, %esi
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: movl %edx, %r8d
+; CHECK-NEXT: cmovbel %esi, %r8d
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: cvtsi2sd %r8, %xmm1
+; CHECK-NEXT: xorps %xmm2, %xmm2
+; CHECK-NEXT: cvtsi2sd %esi, %xmm2
+; CHECK-NEXT: divsd %xmm1, %xmm2
+; CHECK-NEXT: cvttsd2si %xmm2, %r10
+; CHECK-NEXT: imull %r8d, %r10d
+; CHECK-NEXT: subl %r10d, %esi
+; CHECK-NEXT: movl %esi, (%rdi,%rax,4)
+; CHECK-NEXT: addl $1, %eax
+; CHECK-NEXT: cmpl %r9d, %eax
; CHECK-NEXT: ja .LBB6_2
-; CHECK-NEXT: .LBB6_5: # %while.end
+; CHECK-NEXT: .LBB6_3: # %while.end
; CHECK-NEXT: retq
;
; CHECK-FORCEALL-LABEL: Transform:
; CHECK-FORCEALL: # %bb.0: # %entry
; CHECK-FORCEALL-NEXT: movb $1, %al
; CHECK-FORCEALL-NEXT: testb %al, %al
-; CHECK-FORCEALL-NEXT: jne .LBB6_5
+; CHECK-FORCEALL-NEXT: jne .LBB6_3
; CHECK-FORCEALL-NEXT: # %bb.1: # %while.body.preheader
+; CHECK-FORCEALL-NEXT: xorl %eax, %eax
; CHECK-FORCEALL-NEXT: movl %edx, %ecx
-; CHECK-FORCEALL-NEXT: xorl %esi, %esi
+; CHECK-FORCEALL-NEXT: cvtsi2sd %rcx, %xmm0
+; CHECK-FORCEALL-NEXT: movl $11, %ecx
; CHECK-FORCEALL-NEXT: .LBB6_2: # %while.body
; CHECK-FORCEALL-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-FORCEALL-NEXT: movslq %esi, %rsi
-; CHECK-FORCEALL-NEXT: movl (%rdi,%rsi,4), %eax
-; CHECK-FORCEALL-NEXT: xorl %edx, %edx
-; CHECK-FORCEALL-NEXT: divl %ecx
-; CHECK-FORCEALL-NEXT: movl %eax, %edx
-; CHECK-FORCEALL-NEXT: movl $11, %eax
-; CHECK-FORCEALL-NEXT: movl %ecx, %r8d
-; CHECK-FORCEALL-NEXT: cmpl %ecx, %edx
-; CHECK-FORCEALL-NEXT: ja .LBB6_4
-; CHECK-FORCEALL-NEXT: # %bb.3: # %while.body
-; CHECK-FORCEALL-NEXT: # in Loop: Header=BB6_2 Depth=1
-; CHECK-FORCEALL-NEXT: movl $22, %eax
-; CHECK-FORCEALL-NEXT: movl $22, %r8d
-; CHECK-FORCEALL-NEXT: .LBB6_4: # %while.body
-; CHECK-FORCEALL-NEXT: # in Loop: Header=BB6_2 Depth=1
-; CHECK-FORCEALL-NEXT: xorl %edx, %edx
-; CHECK-FORCEALL-NEXT: divl %r8d
-; CHECK-FORCEALL-NEXT: movl %edx, (%rdi,%rsi,4)
-; CHECK-FORCEALL-NEXT: addl $1, %esi
-; CHECK-FORCEALL-NEXT: cmpl %r9d, %esi
+; CHECK-FORCEALL-NEXT: cltq
+; CHECK-FORCEALL-NEXT: movl (%rdi,%rax,4), %esi
+; CHECK-FORCEALL-NEXT: xorps %xmm1, %xmm1
+; CHECK-FORCEALL-NEXT: cvtsi2sd %rsi, %xmm1
+; CHECK-FORCEALL-NEXT: divsd %xmm0, %xmm1
+; CHECK-FORCEALL-NEXT: cvttsd2si %xmm1, %rsi
+; CHECK-FORCEALL-NEXT: cmpl %edx, %esi
+; CHECK-FORCEALL-NEXT: movl $22, %esi
+; CHECK-FORCEALL-NEXT: cmoval %ecx, %esi
+; CHECK-FORCEALL-NEXT: movl %edx, %r8d
+; CHECK-FORCEALL-NEXT: cmovbel %esi, %r8d
+; CHECK-FORCEALL-NEXT: xorps %xmm1, %xmm1
+; CHECK-FORCEALL-NEXT: cvtsi2sd %r8, %xmm1
+; CHECK-FORCEALL-NEXT: xorps %xmm2, %xmm2
+; CHECK-FORCEALL-NEXT: cvtsi2sd %esi, %xmm2
+; CHECK-FORCEALL-NEXT: divsd %xmm1, %xmm2
+; CHECK-FORCEALL-NEXT: cvttsd2si %xmm2, %r10
+; CHECK-FORCEALL-NEXT: imull %r8d, %r10d
+; CHECK-FORCEALL-NEXT: subl %r10d, %esi
+; CHECK-FORCEALL-NEXT: movl %esi, (%rdi,%rax,4)
+; CHECK-FORCEALL-NEXT: addl $1, %eax
+; CHECK-FORCEALL-NEXT: cmpl %r9d, %eax
; CHECK-FORCEALL-NEXT: ja .LBB6_2
-; CHECK-FORCEALL-NEXT: .LBB6_5: # %while.end
+; CHECK-FORCEALL-NEXT: .LBB6_3: # %while.end
; CHECK-FORCEALL-NEXT: retq
entry:
%cmp10 = icmp ugt i32 0, %n
>From 2bca718538d5d76ab91e5cfc1be746b8996d4c1a Mon Sep 17 00:00:00 2001
From: Ankit Kumar Tiwari <ankit.cybertron at gmail.com>
Date: Thu, 20 Aug 2026 22:03:25 +0530
Subject: [PATCH 6/7] Rebase and cleanup
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 46 +++----
.../CodeGen/X86/bypass-slow-division-tune.ll | 88 +++----------
llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll | 118 +++++++++++-------
3 files changed, 113 insertions(+), 139 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 4bd36d762c7b6..f86402de1295d 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -50720,10 +50720,15 @@ static SDValue combineIntDivRem(SDNode *N, SelectionDAG &DAG,
EVT VT = N->getValueType(0);
SDLoc DL(N);
-
if (!Subtarget.hasSSE2())
return SDValue();
+ if (!VT.isVector() && (Subtarget.useSoftFloat() ||
+ DAG.getMachineFunction().getFunction().hasFnAttribute(
+ Attribute::NoImplicitFloat) ||
+ DAG.getMachineFunction().getFunction().hasOptSize()))
+ return SDValue();
+
SDValue Dividend = N->getOperand(0);
SDValue Divisor = N->getOperand(1);
unsigned Opc = N->getOpcode();
@@ -50735,33 +50740,28 @@ static SDValue combineIntDivRem(SDNode *N, SelectionDAG &DAG,
bool IsRem = Opc == ISD::UREM || Opc == ISD::SREM;
bool IsSigned = Opc == ISD::SDIV || Opc == ISD::SREM;
- // Scalar functions that do not use XMM registers must not get this combine.
- if (!VT.isVector() &&
- (Subtarget.useSoftFloat() ||
- DAG.getMachineFunction().getFunction().hasFnAttribute(
- Attribute::NoImplicitFloat)))
- return SDValue();
-
// If the result is only read back as scalar extracts, scalarization computes
// just the demanded lanes. Keep the vector operation when every lane is
// extracted, which occurs when non-power-of-two vectors are returned.
- APInt ExtractedElts = APInt::getZero(VT.getVectorNumElements());
- bool OnlyExtracts = true;
- for (const SDNode *U : N->users()) {
- if (U->getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
- OnlyExtracts = false;
- break;
+ if (VT.isVector()) {
+ APInt ExtractedElts = APInt::getZero(VT.getVectorNumElements());
+ bool OnlyExtracts = true;
+ for (const SDNode *U : N->users()) {
+ if (U->getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
+ OnlyExtracts = false;
+ break;
+ }
+ auto *Idx = dyn_cast<ConstantSDNode>(U->getOperand(1));
+ if (!Idx)
+ continue;
+ const APInt &IdxVal = Idx->getAPIntValue();
+ if (IdxVal.uge(VT.getVectorNumElements()))
+ continue;
+ ExtractedElts.setBit(IdxVal.getZExtValue());
}
- auto *Idx = dyn_cast<ConstantSDNode>(U->getOperand(1));
- if (!Idx)
- continue;
- const APInt &IdxVal = Idx->getAPIntValue();
- if (IdxVal.uge(VT.getVectorNumElements()))
- continue;
- ExtractedElts.setBit(IdxVal.getZExtValue());
+ if (OnlyExtracts && !ExtractedElts.isAllOnes())
+ return SDValue();
}
- if (OnlyExtracts && !ExtractedElts.isAllOnes())
- return SDValue();
// Magic multiply lowers constant divisors cheaper than a divide.
if (DAG.isConstantIntBuildVectorOrConstantInt(Divisor))
diff --git a/llvm/test/CodeGen/X86/bypass-slow-division-tune.ll b/llvm/test/CodeGen/X86/bypass-slow-division-tune.ll
index 4b4674dc177fd..13625f1691a43 100644
--- a/llvm/test/CodeGen/X86/bypass-slow-division-tune.ll
+++ b/llvm/test/CodeGen/X86/bypass-slow-division-tune.ll
@@ -314,44 +314,18 @@ define i64 @div64_hugews(i64 %a, i64 %b) {
}
define i32 @div32_optsize(i32 %a, i32 %b) optsize {
-; ATOM-LABEL: div32_optsize:
-; ATOM: # %bb.0:
-; ATOM-NEXT: cvtsi2sd %esi, %xmm0
-; ATOM-NEXT: cvtsi2sd %edi, %xmm1
-; ATOM-NEXT: divsd %xmm0, %xmm1
-; ATOM-NEXT: cvttsd2si %xmm1, %eax
-; ATOM-NEXT: retq
-;
-; X64-LABEL: div32_optsize:
-; X64: # %bb.0:
-; X64-NEXT: cvtsi2sd %esi, %xmm0
-; X64-NEXT: cvtsi2sd %edi, %xmm1
-; X64-NEXT: divsd %xmm0, %xmm1
-; X64-NEXT: cvttsd2si %xmm1, %eax
-; X64-NEXT: retq
-;
-; SLM-LABEL: div32_optsize:
-; SLM: # %bb.0:
-; SLM-NEXT: cvtsi2sd %esi, %xmm0
-; SLM-NEXT: cvtsi2sd %edi, %xmm1
-; SLM-NEXT: divsd %xmm0, %xmm1
-; SLM-NEXT: cvttsd2si %xmm1, %eax
-; SLM-NEXT: retq
-;
-; SKL-LABEL: div32_optsize:
-; SKL: # %bb.0:
-; SKL-NEXT: vcvtsi2sd %esi, %xmm15, %xmm0
-; SKL-NEXT: vcvtsi2sd %edi, %xmm15, %xmm1
-; SKL-NEXT: vdivsd %xmm0, %xmm1, %xmm0
-; SKL-NEXT: vcvttsd2si %xmm0, %eax
-; SKL-NEXT: retq
+; CHECK-LABEL: div32_optsize:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: cltd
+; CHECK-NEXT: idivl %esi
+; CHECK-NEXT: retq
;
; HUGEWS-LABEL: div32_optsize:
; HUGEWS: # %bb.0:
-; HUGEWS-NEXT: vcvtsi2sd %esi, %xmm15, %xmm0
-; HUGEWS-NEXT: vcvtsi2sd %edi, %xmm15, %xmm1
-; HUGEWS-NEXT: vdivsd %xmm0, %xmm1, %xmm0
-; HUGEWS-NEXT: vcvttsd2si %xmm0, %eax
+; HUGEWS-NEXT: movl %edi, %eax
+; HUGEWS-NEXT: cltd
+; HUGEWS-NEXT: idivl %esi
; HUGEWS-NEXT: retq
%div = sdiv i32 %a, %b
ret i32 %div
@@ -402,44 +376,18 @@ define i32 @div32_pgso(i32 %a, i32 %b) !prof !15 {
}
define i32 @div32_minsize(i32 %a, i32 %b) minsize {
-; ATOM-LABEL: div32_minsize:
-; ATOM: # %bb.0:
-; ATOM-NEXT: cvtsi2sd %esi, %xmm0
-; ATOM-NEXT: cvtsi2sd %edi, %xmm1
-; ATOM-NEXT: divsd %xmm0, %xmm1
-; ATOM-NEXT: cvttsd2si %xmm1, %eax
-; ATOM-NEXT: retq
-;
-; X64-LABEL: div32_minsize:
-; X64: # %bb.0:
-; X64-NEXT: cvtsi2sd %esi, %xmm0
-; X64-NEXT: cvtsi2sd %edi, %xmm1
-; X64-NEXT: divsd %xmm0, %xmm1
-; X64-NEXT: cvttsd2si %xmm1, %eax
-; X64-NEXT: retq
-;
-; SLM-LABEL: div32_minsize:
-; SLM: # %bb.0:
-; SLM-NEXT: cvtsi2sd %esi, %xmm0
-; SLM-NEXT: cvtsi2sd %edi, %xmm1
-; SLM-NEXT: divsd %xmm0, %xmm1
-; SLM-NEXT: cvttsd2si %xmm1, %eax
-; SLM-NEXT: retq
-;
-; SKL-LABEL: div32_minsize:
-; SKL: # %bb.0:
-; SKL-NEXT: vcvtsi2sd %esi, %xmm15, %xmm0
-; SKL-NEXT: vcvtsi2sd %edi, %xmm15, %xmm1
-; SKL-NEXT: vdivsd %xmm0, %xmm1, %xmm0
-; SKL-NEXT: vcvttsd2si %xmm0, %eax
-; SKL-NEXT: retq
+; CHECK-LABEL: div32_minsize:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: cltd
+; CHECK-NEXT: idivl %esi
+; CHECK-NEXT: retq
;
; HUGEWS-LABEL: div32_minsize:
; HUGEWS: # %bb.0:
-; HUGEWS-NEXT: vcvtsi2sd %esi, %xmm15, %xmm0
-; HUGEWS-NEXT: vcvtsi2sd %edi, %xmm15, %xmm1
-; HUGEWS-NEXT: vdivsd %xmm0, %xmm1, %xmm0
-; HUGEWS-NEXT: vcvttsd2si %xmm0, %eax
+; HUGEWS-NEXT: movl %edi, %eax
+; HUGEWS-NEXT: cltd
+; HUGEWS-NEXT: idivl %esi
; HUGEWS-NEXT: retq
%div = sdiv i32 %a, %b
ret i32 %div
diff --git a/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll b/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
index 0ed4155e74bec..9d2fff601dcbd 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
@@ -461,46 +461,57 @@ define <8 x i32> @test_divv_8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
define <7 x i32> @test_divv_7i32(<7 x i32> %a, <7 x i32> %b) nounwind {
; AVX1-LABEL: test_divv_7i32:
; AVX1: # %bb.0:
-; AVX1-NEXT: vpextrd $1, %xmm0, %eax
-; AVX1-NEXT: vpextrd $1, %xmm1, %ecx
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
-; AVX1-NEXT: movl %eax, %ecx
-; AVX1-NEXT: vmovd %xmm0, %eax
-; AVX1-NEXT: vmovd %xmm1, %esi
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %esi
-; AVX1-NEXT: vmovd %eax, %xmm2
-; AVX1-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2
+; AVX1-NEXT: vpextrd $1, %xmm1, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm2
+; AVX1-NEXT: vextractps $1, %xmm0, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm3
+; AVX1-NEXT: vdivsd %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vcvttsd2si %xmm2, %rax
+; AVX1-NEXT: vmovd %xmm1, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm2
+; AVX1-NEXT: vmovd %xmm0, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm3
+; AVX1-NEXT: vdivsd %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vcvttsd2si %xmm2, %rcx
+; AVX1-NEXT: vmovd %ecx, %xmm2
+; AVX1-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2
+; AVX1-NEXT: vpextrd $2, %xmm1, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm3
; AVX1-NEXT: vpextrd $2, %xmm0, %eax
-; AVX1-NEXT: vpextrd $2, %xmm1, %ecx
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm4
+; AVX1-NEXT: vdivsd %xmm3, %xmm4, %xmm3
+; AVX1-NEXT: vcvttsd2si %xmm3, %rax
; AVX1-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2
+; AVX1-NEXT: vpextrd $3, %xmm1, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm3
; AVX1-NEXT: vpextrd $3, %xmm0, %eax
-; AVX1-NEXT: vpextrd $3, %xmm1, %ecx
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm4
+; AVX1-NEXT: vdivsd %xmm3, %xmm4, %xmm3
+; AVX1-NEXT: vcvttsd2si %xmm3, %rax
; AVX1-NEXT: vpinsrd $3, %eax, %xmm2, %xmm2
-; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
-; AVX1-NEXT: vpextrd $2, %xmm0, %eax
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
-; AVX1-NEXT: vpextrd $2, %xmm1, %ecx
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
-; AVX1-NEXT: movl %eax, %ecx
-; AVX1-NEXT: vpextrd $1, %xmm0, %eax
-; AVX1-NEXT: vpextrd $1, %xmm1, %esi
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %esi
-; AVX1-NEXT: movl %eax, %esi
-; AVX1-NEXT: vmovd %xmm0, %eax
-; AVX1-NEXT: vmovd %xmm1, %edi
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %edi
-; AVX1-NEXT: vmovd %eax, %xmm0
-; AVX1-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0
-; AVX1-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0
+; AVX1-NEXT: vpextrd $2, %xmm1, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm3
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT: vextractps $2, %xmm0, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm4
+; AVX1-NEXT: vdivsd %xmm3, %xmm4, %xmm3
+; AVX1-NEXT: vcvttsd2si %xmm3, %rax
+; AVX1-NEXT: vpextrd $1, %xmm1, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm3
+; AVX1-NEXT: vextractps $1, %xmm0, %ecx
+; AVX1-NEXT: vcvtsi2sd %rcx, %xmm15, %xmm4
+; AVX1-NEXT: vdivsd %xmm3, %xmm4, %xmm3
+; AVX1-NEXT: vcvttsd2si %xmm3, %rcx
+; AVX1-NEXT: vmovd %xmm1, %edx
+; AVX1-NEXT: vcvtsi2sd %rdx, %xmm15, %xmm1
+; AVX1-NEXT: vmovd %xmm0, %edx
+; AVX1-NEXT: vcvtsi2sd %rdx, %xmm15, %xmm0
+; AVX1-NEXT: vdivsd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vcvttsd2si %xmm0, %rdx
+; AVX1-NEXT: vmovd %edx, %xmm0
+; AVX1-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
+; AVX1-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
; AVX1-NEXT: retq
;
@@ -551,21 +562,36 @@ define <7 x i32> @test_divv_7i32(<7 x i32> %a, <7 x i32> %b) nounwind {
define i32 @test_divv_7i32_extract0(<7 x i32> %a, <7 x i32> %b) nounwind {
; AVX1-LABEL: test_divv_7i32_extract0:
; AVX1: # %bb.0:
+; AVX1-NEXT: vmovd %xmm1, %eax
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm1
; AVX1-NEXT: vmovd %xmm0, %eax
-; AVX1-NEXT: vmovd %xmm1, %ecx
-; AVX1-NEXT: xorl %edx, %edx
-; AVX1-NEXT: divl %ecx
+; AVX1-NEXT: vcvtsi2sd %rax, %xmm15, %xmm0
+; AVX1-NEXT: vdivsd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vcvttsd2si %xmm0, %rax
+; AVX1-NEXT: # kill: def $eax killed $eax killed $rax
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
-; AVX2-LABEL: test_divv_7i32_extract0:
-; AVX2: # %bb.0:
-; AVX2-NEXT: vmovd %xmm0, %eax
-; AVX2-NEXT: vmovd %xmm1, %ecx
-; AVX2-NEXT: xorl %edx, %edx
-; AVX2-NEXT: divl %ecx
-; AVX2-NEXT: vzeroupper
-; AVX2-NEXT: retq
+; AVX2NOBW-LABEL: test_divv_7i32_extract0:
+; AVX2NOBW: # %bb.0:
+; AVX2NOBW-NEXT: vmovd %xmm1, %eax
+; AVX2NOBW-NEXT: vcvtsi2sd %rax, %xmm15, %xmm1
+; AVX2NOBW-NEXT: vmovd %xmm0, %eax
+; AVX2NOBW-NEXT: vcvtsi2sd %rax, %xmm15, %xmm0
+; AVX2NOBW-NEXT: vdivsd %xmm1, %xmm0, %xmm0
+; AVX2NOBW-NEXT: vcvttsd2si %xmm0, %rax
+; AVX2NOBW-NEXT: # kill: def $eax killed $eax killed $rax
+; AVX2NOBW-NEXT: vzeroupper
+; AVX2NOBW-NEXT: retq
+;
+; AVX512BW-LABEL: test_divv_7i32_extract0:
+; AVX512BW: # %bb.0:
+; AVX512BW-NEXT: vcvtudq2pd %ymm1, %zmm1
+; AVX512BW-NEXT: vcvtudq2pd %ymm0, %zmm0
+; AVX512BW-NEXT: vdivsd %xmm1, %xmm0, %xmm0
+; AVX512BW-NEXT: vcvttsd2usi %xmm0, %eax
+; AVX512BW-NEXT: vzeroupper
+; AVX512BW-NEXT: retq
%res = udiv <7 x i32> %a, %b
%elt = extractelement <7 x i32> %res, i32 0
ret i32 %elt
>From e6d8cdc35422f31c313c02decf1b0e7ee6a30231 Mon Sep 17 00:00:00 2001
From: Ankit Kumar Tiwari <ankit.cybertron at gmail.com>
Date: Thu, 20 Aug 2026 22:31:58 +0530
Subject: [PATCH 7/7] Add optsize/minsize tests
---
llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll | 23 ++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll b/llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll
index 7a7b6f3c1f1c4..8b250d2387d0f 100644
--- a/llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll
+++ b/llvm/test/CodeGen/X86/scalar-intdiv-to-fp.ll
@@ -288,3 +288,26 @@ define i32 @sdiv_i32_strictfp(i32 %a, i32 %b) nounwind strictfp {
%r = sdiv i32 %a, %b
ret i32 %r
}
+
+define i32 @sdiv_i32_optsize(i32 %a, i32 %b) nounwind optsize {
+; CHECK-LABEL: sdiv_i32_optsize:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: cltd
+; CHECK-NEXT: idivl %esi
+; CHECK-NEXT: retq
+ %r = sdiv i32 %a, %b
+ ret i32 %r
+}
+
+define i32 @sdiv_i32_minsize(i32 %a, i32 %b) nounwind minsize {
+; CHECK-LABEL: sdiv_i32_minsize:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: cltd
+; CHECK-NEXT: idivl %esi
+; CHECK-NEXT: retq
+ %r = sdiv i32 %a, %b
+ ret i32 %r
+}
+
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