[llvm] a706b2d - [AMDGPU][GISel] Rename amdgpu-reg-bank-legalize
via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 20 06:12:55 PDT 2026
Author: Aiden Grossman
Date: 2026-08-20T06:12:50-07:00
New Revision: a706b2df2ad48cb8d37e010ea821cd86f1be3721
URL: https://github.com/llvm/llvm-project/commit/a706b2df2ad48cb8d37e010ea821cd86f1be3721
DIFF: https://github.com/llvm/llvm-project/commit/a706b2df2ad48cb8d37e010ea821cd86f1be3721.diff
LOG: [AMDGPU][GISel] Rename amdgpu-reg-bank-legalize
Hyphenate to be consistent with other pass names like
amdgpu-reg-bank-select.
Reviewers: arsenm, vangthao95, aeubanks
Pull Request: https://github.com/llvm/llvm-project/pull/217488
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-sext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add-sub.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.v2f16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-minmax-uminmax.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-uinc-udec-wrap.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
index d28d5c8c556a7..19ba2f5ca6fb5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
@@ -32,7 +32,7 @@
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/InitializePasses.h"
-#define DEBUG_TYPE "amdgpu-regbanklegalize"
+#define DEBUG_TYPE "amdgpu-reg-bank-legalize"
using namespace llvm;
using namespace AMDGPU;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index d7815341805bb..a9252cbd82722 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -28,7 +28,7 @@
#include "llvm/CodeGen/MachineUniformityAnalysis.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
-#define DEBUG_TYPE "amdgpu-regbanklegalize"
+#define DEBUG_TYPE "amdgpu-reg-bank-legalize"
using namespace llvm;
using namespace AMDGPU;
@@ -49,7 +49,7 @@ RegBankLegalizeHelper::RegBankLegalizeHelper(
bool RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
const SetOfRulesForOpcode *RuleSet = RBLRules.getRulesForOpc(MI);
if (!RuleSet) {
- reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ reportGISelFailure(MF, MORE, DEBUG_TYPE,
"No AMDGPU RegBankLegalize rules defined for opcode",
MI);
return false;
@@ -57,7 +57,7 @@ bool RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
const RegBankLLTMapping *Mapping = RuleSet->findMappingForMI(MI, MRI, MUI);
if (!Mapping) {
- reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ reportGISelFailure(MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: none of the rules defined with "
"'Any' for MI's opcode matched MI",
MI);
@@ -502,7 +502,7 @@ bool RegBankLegalizeHelper::lowerVccExtToSel(MachineInstr &MI) {
break;
default:
reportGISelFailure(
- MF, MORE, "amdgpu-regbanklegalize",
+ MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: lowerVccExtToSel, Opcode not supported", MI);
return false;
}
@@ -510,7 +510,7 @@ bool RegBankLegalizeHelper::lowerVccExtToSel(MachineInstr &MI) {
B.buildMergeValues(Dst, {Lo.getReg(0), Hi.getReg(0)});
} else {
reportGISelFailure(
- MF, MORE, "amdgpu-regbanklegalize",
+ MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: lowerVccExtToSel, Type not supported", MI);
return false;
}
@@ -575,7 +575,7 @@ bool RegBankLegalizeHelper::lowerUnpackBitShift(MachineInstr &MI) {
}
default:
reportGISelFailure(
- MF, MORE, "amdgpu-regbanklegalize",
+ MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: lowerUnpackBitShift, case not implemented",
MI);
return false;
@@ -612,7 +612,7 @@ bool RegBankLegalizeHelper::lowerUnpackMinMax(MachineInstr &MI) {
}
default:
reportGISelFailure(
- MF, MORE, "amdgpu-regbanklegalize",
+ MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: lowerUnpackMinMax, case not implemented", MI);
return false;
}
@@ -1084,7 +1084,7 @@ bool RegBankLegalizeHelper::lowerExtrVecEltToSel(MachineInstr &MI) {
B.buildMergeLikeInstr(Dst, {PrevLo, PrevHi});
} else {
reportGISelFailure(
- MF, MORE, "amdgpu-regbanklegalize",
+ MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: ExtrVecEltToSel unsupported element type", MI);
return false;
}
@@ -1181,7 +1181,7 @@ bool RegBankLegalizeHelper::lowerInsVecEltToSel(MachineInstr &MI) {
B.buildMergeLikeInstr(Dst, Selects);
} else {
reportGISelFailure(
- MF, MORE, "amdgpu-regbanklegalize",
+ MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: InsVecEltToSel unsupported element type", MI);
return false;
}
@@ -1463,7 +1463,7 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI,
break;
}
default:
- reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ reportGISelFailure(MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: Ext32To64, unsuported opcode",
MI);
return false;
@@ -1568,7 +1568,7 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI,
else if (Size / 128 == 4)
splitLoad(MI, {B128, B128, B128, B128});
else {
- reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ reportGISelFailure(MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: SplitLoad, unsuported type",
MI);
return false;
@@ -1582,7 +1582,7 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI,
else if (DstTy == V6S16)
splitLoad(MI, {V4S16, V2S16}, V2S16);
else {
- reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ reportGISelFailure(MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: SplitLoad, unsuported type",
MI);
return false;
@@ -1653,7 +1653,7 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI,
else if (DstTy == V6S16)
widenLoad(MI, V8S16, V2S16);
else {
- reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ reportGISelFailure(MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: WidenLoad, unsuported type",
MI);
return false;
@@ -1691,7 +1691,7 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI,
GUnmerge *Unmerge = dyn_cast<GUnmerge>(&MI);
LLT Ty = MRI.getType(Unmerge->getSourceReg());
if (Ty.getSizeInBits() % 32 != 0) {
- reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ reportGISelFailure(MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: unmerge not multiple of 32",
MI);
return false;
@@ -2283,13 +2283,13 @@ bool RegBankLegalizeHelper::applyMappingDst(
}
case InvalidMapping: {
reportGISelFailure(
- MF, MORE, "amdgpu-regbanklegalize",
+ MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: missing fast rule ('Div' or 'Uni') for", MI);
return false;
}
default:
reportGISelFailure(
- MF, MORE, "amdgpu-regbanklegalize",
+ MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: applyMappingDst, ID not supported", MI);
return false;
}
@@ -2549,7 +2549,7 @@ bool RegBankLegalizeHelper::applyMappingSrc(
}
default:
reportGISelFailure(
- MF, MORE, "amdgpu-regbanklegalize",
+ MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: applyMappingSrc, ID not supported", MI);
return false;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 437be2b429356..bd21d5ca650dc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -21,7 +21,7 @@
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/Support/AMDGPUAddrSpace.h"
-#define DEBUG_TYPE "amdgpu-regbanklegalize"
+#define DEBUG_TYPE "amdgpu-reg-bank-legalize"
using namespace llvm;
using namespace AMDGPU;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir
index 69789b3bef9be..2f1f0ae285c92 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgpu10.10 -run-pass=amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass=amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
---
name: readanylane_to_virtual_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
index bb6b197c94f50..79c107bfaad05 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu10.10 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: abs_sgpr_s16
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
index c3c86a8e5bfa9..77a614d89e849 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
---
name: add_s16_ss
legalized: true
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
index 3cdc6cbb6a23c..c6f0124ac9bbc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
---
name: add_s16_ss
legalized: true
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
index 16f5786192f01..f4232ed440e0e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck %s
---
name: add_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
index 8f62befe6a09b..f153f02e2f05e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -run-pass=amdgpu-reg-bank-select,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
---
name: add_v2s16_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
index d6aa1e2205b64..8dd947e4a459e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: exp_compr_v2f16_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
index ed6ec5dc4626f..ad29404b6d1a1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu11.00 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu11.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
--- |
define amdgpu_ps void @exp_s(float inreg %v0, float inreg %v1, float inreg %v2, float inreg %v3) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
index 1277811ef438b..1efd7462f3230 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -verify-machineinstrs -o - %s | FileCheck %s
---
name: buffer_load_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
index 907c0c08172c7..4a2d3ee405d41 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: ballot_sgpr_src
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
index 8be8dba65debb..b06a6db73bf37 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: class_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
index 1721a32fac8ba..51b73df884e55 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: cvt_pkrtz_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
index 326266d1dfb41..ff6ce7d2e2934 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: div_fmas_sss_scc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
index 75b863c36d8e7..2539c72044d29 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: div_scale_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
index 29e10560a863b..1be36a60a93a5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: ds_append_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
index 966c2c5734267..6f635d8e09002 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: ds_bpermute_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
index 9db727d09e507..45e8d0debb86d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: ds_consume_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
index 1e89b23a5d3a9..5ba4faefa8092 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: ds_gws_init_s_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
index 803d1a68a2218..01736eb7c46cd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: ds_gws_init_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
index 624c3f118a43b..bbcecb186c4ed 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: ds_ordered_add_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
index b76ee46734d41..a87fc081537ae 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: ds_ordered_swap_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
index 7bcadab1b5404..52cff72aa3bf1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: ds_permute_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
index 7ce41a1519faf..4ee1688ad0da9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: ds_swizzle_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
index f01e2a279d431..376bca07c82d5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -verify-machineinstrs -o - %s | FileCheck %s
---
name: fcmp_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
index f16b620373e2e..0756e6d6bbeee 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: fmul_legacy_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
index 52ab632a7364c..80683ba20cf6b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: groupstaticsize
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
index 1a1b2494932b4..8f7f014e09e5a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -verify-machineinstrs -o - %s | FileCheck %s
---
name: icmp_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
index d1006c18bd1a8..4e5abfdca0050 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s
-; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s
+; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s
+; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s
; Natural mapping
define amdgpu_ps void @load_1d_vgpr_vaddr__sgpr_srsrc(<8 x i32> inreg %rsrc, i32 %s) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
index 4ad8eb432c676..548824b05c507 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s
-; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s
; Natural mapping
define amdgpu_ps void @sample_1d_vgpr_vaddr__sgpr_rsrc__sgpr_samp(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
index edbf30e8b9c7e..d60f122545431 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: interp_mov_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
index 7d7d26caffb4e..2c920f75e289e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: interp_p1_f16_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
index 37748f1a81ff7..08ea7aba39698 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: interp_p1_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
index 453ed19b1b1aa..3f22072d64827 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: interp_p2_f16_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
index 5a6bbe0aa4337..8a2f5920c485a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: interp_p2_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
index fd1ba1648defa..94ecc203e7931 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s| FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s| FileCheck %s
---
name: kill_scc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
index a81034ac67a2d..f5e1ea5886989 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu11.00 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu11.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: lds_direct_load_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
index abe6ee6b5da72..7ad25941c6952 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu11.00 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu11.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: lds_param_load_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
index cfbd56cce0e22..efd9b02760d11 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: live_mask
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
index 29d70bb21ba35..45b17afa852ae 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.0a -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -amdgpu-mfma-vgpr-form=0 %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.0a -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -amdgpu-mfma-vgpr-form=0 %s -o - | FileCheck %s
---
name: mfma_f32_32x32x4bf16_1k_vva
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir
index 16060422b3761..3ba277f8671ba 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.42 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -amdgpu-mfma-vgpr-form=0 %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.42 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -amdgpu-mfma-vgpr-form=0 %s -o - | FileCheck %s
---
name: mfma_i32_16x16x32_i8_vva
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
index 30745f3c83e8d..1ac907dd220c0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -verify-machineinstrs %s -o - | FileCheck %s
---
name: mfma_f32_32x32x1f32_vva
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
index 29d587728feb2..4051cda04c92d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: ps_live
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll
index 9a7f82c02c52b..37060571106b3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu7.00-mesa-mesa3d -simplify-mir -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s -check-prefix=GFX7
-; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -simplify-mir -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s -check-prefixes=GFX1200_1250,GFX1200
-; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu12.50-mesa-mesa3d -simplify-mir -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s -check-prefixes=GFX1200_1250,GFX1250
+; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu7.00-mesa-mesa3d -simplify-mir -stop-after=amdgpu-reg-bank-legalize -o - %s | FileCheck %s -check-prefix=GFX7
+; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -simplify-mir -stop-after=amdgpu-reg-bank-legalize -o - %s | FileCheck %s -check-prefixes=GFX1200_1250,GFX1200
+; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu12.50-mesa-mesa3d -simplify-mir -stop-after=amdgpu-reg-bank-legalize -o - %s | FileCheck %s -check-prefixes=GFX1200_1250,GFX1250
; Natural mapping
define amdgpu_ps i32 @ptr_s_buffer_load_i32(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
index 5468f2462876b..2480b1b1ff167 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-fast -o - %s | FileCheck %s
-; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-greedy -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -regbankselect-fast -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -regbankselect-greedy -o - %s | FileCheck %s
; Natural mapping
define amdgpu_ps float @raw_buffer_load__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
index 77f6b1e90c590..4ae5d545e9bfd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -o - %s | FileCheck %s
; Natural mapping
define amdgpu_ps float @raw_ptr_buffer_load__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset(ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
index 7f37f124afa1a..623311c0fb3ed 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -o - %s | FileCheck %s
---
name: readfirstlane_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
index f649799f3491f..02c8f4564e13b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: readlane_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
index 8e985b16d322f..ace9eb5bee30b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu7.01-mesa-mesa3d -simplify-mir -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s -check-prefix=GFX7
-; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -simplify-mir -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s -check-prefixes=GFX1200_1250,GFX1200
-; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu12.50-mesa-mesa3d -simplify-mir -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s -check-prefixes=GFX1200_1250,GFX1250
+; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu7.01-mesa-mesa3d -simplify-mir -stop-after=amdgpu-reg-bank-legalize -o - %s | FileCheck %s -check-prefix=GFX7
+; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -simplify-mir -stop-after=amdgpu-reg-bank-legalize -o - %s | FileCheck %s -check-prefixes=GFX1200_1250,GFX1200
+; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu12.50-mesa-mesa3d -simplify-mir -stop-after=amdgpu-reg-bank-legalize -o - %s | FileCheck %s -check-prefixes=GFX1200_1250,GFX1250
; Natural mapping
define amdgpu_ps i32 @s_buffer_load_i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
index c415a99c0568c..995486d6deb42 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu10.10 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: s_get_waveid_in_workgroup
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
index 2552cccbeda81..257a7297659b1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -o - %s | FileCheck %s
---
name: getpc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
index 949f51b67badf..d9335084ba9f9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: getreg
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
index adc5cc79126cf..fa5950bd276de 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: memrealtime
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
index 2f6349031024a..f4b16267b05e9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: memtime
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
index 0e584824d56ff..d445d4012d9bb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: sendmsg_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
index c7f2371848530..c02e09fa3057f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: sendmsghalt_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
index d327372fc7c86..6f2c21fcfd4b7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-fast -o - %s | FileCheck %s
-; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-greedy -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -regbankselect-fast -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -regbankselect-greedy -o - %s | FileCheck %s
; Natural mapping
define amdgpu_ps float @struct_buffer_load__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
index 8ca6f705fac04..fcdf5421f666d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -o - %s | FileCheck %s
; Natural mapping
define amdgpu_ps void @struct_buffer_store__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, float %val, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
index 195fd39eebf19..01f8b628125bf 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-fast -o - %s | FileCheck %s
-; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-greedy -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -regbankselect-fast -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -regbankselect-greedy -o - %s | FileCheck %s
; Natural mapping
define amdgpu_ps float @struct_ptr_buffer_load__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
index 39ae330f17582..7b1270c9517aa 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -o - %s | FileCheck %s
; Natural mapping
define amdgpu_ps void @struct_ptr_buffer_store__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(ptr addrspace(8) inreg %rsrc, float %val, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
index db165a7188e74..b3de77b8b43ed 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: update_dpp_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
index 16c05762d9aed..067c27c082144 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: wqm_demote_scc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
index f0dd10acef870..5e0e43e7a087e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: wqm_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
index 825c61931a629..e7ad79a42e595 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: writelane_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
index 73d2d54fc4a62..cd3e2acf887bd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: strict_wwm_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
index 3f657f59d3c33..e511bd46a90d2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: ffbh_u32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
index e24ede1dac735..6738775796f97 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: ffbl_b32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
index 6caa158a5a055..ee8c929731229 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
# TODO: We could use scalar
---
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
index f418ce0d1a26e..dc0876f9aca41 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: and_s1_sgpr_sgpr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
index e82e7f765987f..6e2b54e84422b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: and_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
index 01617e6eb6af4..72e9d29bed4bb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: anyext_s32_to_s64_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
index 25d46dff89381..10be7671cdbe1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -o - %s | FileCheck %s
---
name: ashr_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
index 41a0979c7fc5a..8e4cc927c3154 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.0a -run-pass=amdgpu-reg-bank-select,amdgpu-regbanklegalize %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.0a -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -o - | FileCheck %s
---
name: assert_align_vgpr_s32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-sext.mir
index db28183ed851a..7e4064c1ee164 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-sext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-sext.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.0a -run-pass=amdgpu-reg-bank-select,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.0a -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
---
name: assert_sext_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
index 18e2261fcdf58..b9e74e3477d32 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.0a -run-pass=amdgpu-reg-bank-select,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.0a -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
---
name: assert_zext_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
index 634c9bb18a8e6..09c05ec1c5dab 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: amdgpu_atomic_cmpxchg_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add-sub.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add-sub.mir
index 65a0f5a648d4e..24ca47fef2fe0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add-sub.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add-sub.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
# Test G_ATOMICRMW_ADD and G_ATOMICRMW_SUB register bank selection and legalization
# for
diff erent address spaces (flat P0, global P1, local P3) and data sizes (S32, S64)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
index 09a8dd8bf88a3..c3b8f0b2192d2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
---
name: atomicrmw_add_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
index d78f017262e5f..2047834023ff1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu12.01 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.01 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: atomicrmw_and_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
index 2fcc4369ab83a..144157b8ea406 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: atomicrmw_fadd_global_f32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.v2f16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.v2f16.mir
index c8bb34d01c1e2..0fd72e1b041d3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.v2f16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.v2f16.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.42 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.42 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
# Test G_ATOMICRMW_FADD with V2F16 (V2S16) type - register bank selection and
# legalization for flat, global, and local address spaces.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
index f998769d3c320..ecd079e8f9655 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: atomicrmw_max_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
index a913fe8514420..1f315a9d6c050 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: atomicrmw_min_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-minmax-uminmax.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-minmax-uminmax.mir
index 920f1feceea0a..ba7423e471444 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-minmax-uminmax.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-minmax-uminmax.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -run-pass=amdgpu-reg-bank-select,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
# Test G_ATOMICRMW_MIN, G_ATOMICRMW_MAX, G_ATOMICRMW_UMIN, G_ATOMICRMW_UMAX
# register bank selection and legalization for flat, global, and local address spaces.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
index 11c0ecda00dff..c63966961ceda 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu12.01 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.01 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: atomicrmw_or_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
index cbd3148ee4a0d..f7db0780bd1c0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu12.01 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.01 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: atomicrmw_sub_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-uinc-udec-wrap.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-uinc-udec-wrap.mir
index cd427224e6fea..b21819dd24e9c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-uinc-udec-wrap.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-uinc-udec-wrap.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -run-pass=amdgpu-reg-bank-select,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
# Test G_ATOMICRMW_UINC_WRAP and G_ATOMICRMW_UDEC_WRAP
# register bank selection and legalization for flat, global, and local address spaces.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
index 74628d107da51..3a2f5a7239379 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: atomicrmw_umax_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
index 53be8eb3b97af..4f9459b0bfc1b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: atomicrmw_umin_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
index a525705f727ce..9aa17d395970b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: atomicrmw_xchg_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
index eb08004283a30..3528cb1cbacda 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu12.01 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.01 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: atomicrmw_xor_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
index 29271e4aa83d3..0e0c027b84870 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck %s
---
name: bitcast_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
index 153bc165d9552..4fa8b386febf1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: bitreverse_i32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
index 16dcffe4bf447..db3e68d8be193 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
index d07bc4fcf91c2..68e24f8e0185c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck %s
---
name: brcond_vcc_cond
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
index 0311ecfba6567..4bf9d6e13f053 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: bswap_i32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
index 3df7530c87dc2..4767301be5590 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.08 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.08 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -o - %s | FileCheck %s
---
name: build_vector_v2s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
index b9afd0dbdb7d7..1c4bab48d2bbd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu9.0a-amd-amdhsa -stop-after=amdgpu-regbanklegalize -regbankselect-fast -o - %s | FileCheck %s
-; RUN: llc -global-isel -mtriple=amdgpu9.0a-amd-amdhsa -stop-after=amdgpu-regbanklegalize -regbankselect-greedy -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu9.0a-amd-amdhsa -stop-after=amdgpu-reg-bank-legalize -regbankselect-fast -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu9.0a-amd-amdhsa -stop-after=amdgpu-reg-bank-legalize -regbankselect-greedy -o - %s | FileCheck %s
define amdgpu_ps void @test_uniform_indirect_call_p0(ptr inreg %fptr) {
; CHECK-LABEL: name: test_uniform_indirect_call_p0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
index ab5ac76730aca..cf2b7558a0af7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -verify-machineinstrs -o - %s | FileCheck %s
---
name: concat_vectors_v4s16_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
index 7c0ec8fa03237..f4e1464a6409e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu7.01 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu7.01 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: test_constant_s32_vgpr_use
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir
index a504da0316c12..29fb7b7491a4b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: ctlz_zero_poison_s32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
index 215f1369737b3..7d1cc74b7edbc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: ctpop_s32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir
index 4c085a2572950..ec3f5e0148cc1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: cttz_zero_poison_s32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
index eca4c7b5c1b63..deeb4469409bf 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck %s
# Check the default mappings for various instructions.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
index 10ddfb2e98142..40b969b7adf3a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=WAVE64 %s
-# RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=WAVE32 %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=WAVE64 %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=WAVE32 %s
---
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
index c01b3d5cd7946..621a1fe635755 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck -check-prefix=WAVE64 %s
-# RUN: llc -mtriple=amdgpu10.10 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck -check-prefix=WAVE32 %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck -check-prefix=WAVE64 %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck -check-prefix=WAVE32 %s
---
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
index 41f7544e954c6..128a52568c859 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu6.00 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: fabs_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
index 75a633f735a6c..f87e14855ff2c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck %s
---
name: fadd_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
index 73cf570ae9f2d..432e93057846e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu12.00 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: fcanonicalize_s16_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
index 4e92423f96e8f..ce0b8bdcabe02 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: fceil_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
index b8e4bfbb9e540..92c4a655b453e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck --check-prefixes=GCN,GFX803 %s
-# RUN: llc -mtriple=amdgpu11.50 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck --check-prefixes=GCN,GFX1150 %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck --check-prefixes=GCN,GFX803 %s
+# RUN: llc -mtriple=amdgpu11.50 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck --check-prefixes=GCN,GFX1150 %s
---
name: fcmp_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
index 3de5058151449..e6f1c253c66e2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=CHECK,GFX8 %s
-# RUN: llc -mtriple=amdgpu11.00 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=CHECK,GFX11 %s
-# RUN: llc -mtriple=amdgpu12.00 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=CHECK,GFX12 %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=CHECK,GFX8 %s
+# RUN: llc -mtriple=amdgpu11.00 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=CHECK,GFX11 %s
+# RUN: llc -mtriple=amdgpu12.00 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=CHECK,GFX12 %s
---
name: fexp2_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
index a5742708058c8..1495c447f1305 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: ffloor_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
index e473e6358dfdc..a1d1355cf54cf 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: flog2_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
index 9f3e5b877dfc8..8cb44a7f5ff54 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu12.00 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: fma_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
index 16ee93d061fa8..c7aaf8241cc93 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: fmul_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
index 1fc8b42b6e01c..fd4cdc5a59fdd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu6.00 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: fneg_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
index d29f233ac07e6..ebe97ae369cd2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: fpext_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir
index 81b21178611cc..7f4abf3135c1f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-regbanklegalize -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize -o - %s | FileCheck %s
---
name: fptosi_sat_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
index 409786ee7dc8d..b4b290b22cd58 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: fptosi_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir
index 9d20723afcb42..4fa8c71fc3547 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-regbanklegalize -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize -o - %s | FileCheck %s
---
name: fptoui_sat_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
index bce43471af2ba..f9d5d8107aa4d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: fptoui_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
index 15ff8b04d182a..8f35440ccd774 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: fptrunc_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
index 793f6638ac970..a337166f9aca0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck %s
---
name: test_frame_index_p5
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
index ec886c37fe224..7569b9d93ab71 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck %s
-# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck %s
-# RUN: llc -mtriple=amdgpu10.10 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: test_freeze_s1_vgpr_to_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
index bed2a348d1e22..0d7a557b8963d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -verify-machineinstrs -o - %s | FileCheck %s
---
name: fshr_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
index d8cedea99da3e..b2fb47c86de98 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck -check-prefixes=GCN,GFX9 %s
-# RUN: llc -mtriple=amdgpu12.00 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck -check-prefixes=GCN,GFX12 %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck -check-prefixes=GCN,GFX9 %s
+# RUN: llc -mtriple=amdgpu12.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck -check-prefixes=GCN,GFX12 %s
---
name: fsqrt_s16_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
index 91946d8443fb4..f6baa9911d983 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: fsub_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
index 69c99a3371897..7e196b78aef69 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-regbanklegalize -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
---
name: icmp_eq_s16_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir
index 71d34bc7b8dff..cc32020b8324d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: intrinsic_roundeven_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
index a47b16e641d4e..d5b26f1ebb847 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: intrinsic_trunc_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
index 12e3f4708d6d4..cea46cfc9e496 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgpu6.00 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -mtriple=amdgpu6.00 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: inttoptr_s_p0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
index 35f71ffdeed3b..e5b81a7d12ba4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu7.01-amd-amdhsa -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=GCN,GFX7
-# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu12.00-amd-amdhsa -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=GCN,GFX12
-# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu12.50-amd-amdhsa -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -o - | FileCheck %s -check-prefixes=GCN,GFX12
+# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu7.01-amd-amdhsa -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=GCN,GFX7
+# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu12.00-amd-amdhsa -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=GCN,GFX12
+# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu12.50-amd-amdhsa -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck %s -check-prefixes=GCN,GFX12
--- |
define amdgpu_kernel void @load_global_v8i32_non_uniform(ptr addrspace(1) %in) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
index 8a0dbb98ac7f3..73d35645974f9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -o - %s | FileCheck %s
---
name: lshr_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
index 08ed4720f0754..e0ed06d3cfa54 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: merge_s64_s32_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir
index b62b53ea13aa2..3ef155ff6ff46 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgpu10.10 -run-pass=amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass=amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
---
name: uniform_in_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
index 6765019255d6d..a53a428278f95 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgpu10.10 -run-pass=reg-bank-select %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS_GFX10
# RUN: llc -mtriple=amdgpu12.00 -run-pass=reg-bank-select %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS_GFX12
-# RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS_GFX10
-# RUN: llc -mtriple=amdgpu12.00 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS_GFX12
+# RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS_GFX10
+# RUN: llc -mtriple=amdgpu12.00 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS_GFX12
---
name: salu_float
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
index 12bfe46c326c6..42427e9e38a83 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgpu10.10 -run-pass=reg-bank-select %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS
-# RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS
+# RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS
---
name: uniform_in_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
index b40714da619ec..29c70223d70dc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu12.00 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: mul_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
index 9b8c3c8ba9fc6..bec296743a084 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: or_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
index 0e17e4daff419..795639267a30b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu6.00 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck %s
---
name: gep_p0_s_k
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
index 7c66e5f8895fe..41f7a939f09ae 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu12.00-amd-amdpal -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00-amd-amdpal -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: ptrmask_p1_s_k
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
index 25919dc4e5ada..edddc69f4023b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgpu6.00 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -mtriple=amdgpu6.00 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: ptrtoint_s_p0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
index df0e876b6ec3d..81d7223c7c8c4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: sadde_s32_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
index 9936b894cf3ae..a43e5d69205f9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu11.50 -run-pass=amdgpu-reg-bank-select,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck --check-prefixes=GFX1150 %s
+# RUN: llc -mtriple=amdgpu11.50 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck --check-prefixes=GFX1150 %s
---
name: fadd_f32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
index ef22092f847d3..61d1d746f9c85 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -verify-machineinstrs -o - %s | FileCheck %s
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
index 2787b811a37c6..e03e3440847c3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: select_s32_scc_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
index 8416306b84170..cd8f9d9c9f9b7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: sext_inreg_s_s32_1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
index 94524a2edf03f..3db0910882ef1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: sext_s32_to_s64_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
index baa3a57d8af62..0e81717e4a027 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -o - %s | FileCheck %s
---
name: sextload_constant_i8_to_i32_uniform
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
index 716104d05ea79..15b550aaabc79 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -o - %s | FileCheck %s
---
name: shl_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
index a6c11483ac104..4f7f66ddf66e4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: sitofp_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
index 6ef026281a419..86e507a80e203 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: smax_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
index 16fcafc78bfb6..aa466c699f9f9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: smin_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
index 05ecb10187d68..cf537e8fb1075 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu6.00-amd-amdpal -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck -check-prefix=GFX6 %s
-# RUN: llc -mtriple=amdgpu9.00-amd-amdpal -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgpu6.00-amd-amdpal -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck -check-prefix=GFX6 %s
+# RUN: llc -mtriple=amdgpu9.00-amd-amdpal -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck -check-prefix=GFX9 %s
---
name: smulh_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
index 036856a1a4c92..0bbafccef1fd8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu7.01-mesa-mesa3d -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -o - | FileCheck -check-prefix=GFX7 %s
-# RUN: llc -mtriple=amdgpu12.00-mesa-mesa3d -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -o - | FileCheck -check-prefix=GFX12 %s
-# RUN: llc -mtriple=amdgpu12.50-mesa-mesa3d -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -o - | FileCheck -check-prefix=GFX12 %s
+# RUN: llc -mtriple=amdgpu7.01-mesa-mesa3d -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck -check-prefix=GFX7 %s
+# RUN: llc -mtriple=amdgpu12.00-mesa-mesa3d -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck -check-prefix=GFX12 %s
+# RUN: llc -mtriple=amdgpu12.50-mesa-mesa3d -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck -check-prefix=GFX12 %s
--- |
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
index ff645e2f6c569..e809d5fb8449a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: ssube_s32_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
index 038d3cd9fdebe..8f48bdccfb7ca 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -run-pass=amdgpu-reg-bank-select,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
---
name: sub_s16_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
index f5817c626fed6..d9748f938e9a1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu6.00 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX,GFX6 %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX,GFX8 %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX,GFX6 %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX,GFX8 %s
---
name: trunc_i64_to_i32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
index 82316bf1033bd..c1631a9831d4c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
---
name: uadde_s32_sss
legalized: true
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
index be0b5ebe5c596..fc48a4989190a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: uaddo_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
index 021a7469a32dd..73b59bb86c1f0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -verify-machineinstrs -o - %s | FileCheck %s
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
index d238fa55d29eb..9603a79a3ae63 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: uitofp_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
index ff6bf391bdac9..aeb808f433f9b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: umax_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
index f0575f2672461..df02a8fd88b83 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: umin_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
index cc7b52d01e41f..2fa6163d53497 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu6.00-amd-amdpal -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck -check-prefix=GFX6 %s
-# RUN: llc -mtriple=amdgpu9.00-amd-amdpal -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgpu6.00-amd-amdpal -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck -check-prefix=GFX6 %s
+# RUN: llc -mtriple=amdgpu9.00-amd-amdpal -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck -check-prefix=GFX9 %s
---
name: umulh_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
index cac58be31bfda..40ee28a8178bd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu7.00-amd-amdpal -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" -mattr=+unaligned-access-mode %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX7 %s
-# RUN: llc -mtriple=amdgpu10.10-amd-amdpal -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" -mattr=+unaligned-access-mode %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX1010 %s
+# RUN: llc -mtriple=amdgpu7.00-amd-amdpal -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -mattr=+unaligned-access-mode %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX7 %s
+# RUN: llc -mtriple=amdgpu10.10-amd-amdpal -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -mattr=+unaligned-access-mode %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX1010 %s
# FixMe: need merge/unmerge artifact combine
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
index 28b965b156420..8b6a948569ce0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: test_unmerge_s64_s32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
index ce8ae69c55f8b..331731d5d15ea 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
---
name: usube_s32_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
index 1bbe23a306e0e..3e5bb73529480 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: usubo_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
index 340e7d0bece2c..1227176114e8f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa -run-pass=amdgpu-reg-bank-select,amdgpu-regbanklegalize -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize -o - %s | FileCheck %s
---
name: waterfall_divergent_call_p0_no_args
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
index 8219235d360d8..4ea502dd94c7e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
-# RUN: llc -mtriple=amdgpu9.00 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
-# RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
---
name: constant_load_i8_align8
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
index ae5f0296f4ec1..311ff66bc3563 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: xor_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
index a4dddf6020ce2..3dd82d58284b2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: zext_s32_to_s64_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
index f1434f3353e14..7ec038b3ecdc9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -verify-machineinstrs -o - %s | FileCheck %s
---
name: zextload_constant_i8_to_i32_uniform
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
index 64e00135ec273..8623911456922 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu7.01 -mattr=+flat-for-global -run-pass="amdgpu-reg-bank-select,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu7.01 -mattr=+flat-for-global -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck %s
--- |
define amdgpu_kernel void @load_constant(ptr addrspace(4) %ptr0) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
index ed9ee19acbe29..149ebee8c6c2c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=amdgpu11.00 -run-pass=amdgpu-regbanklegalize -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu11.00 -run-pass=amdgpu-reg-bank-legalize -verify-machineinstrs %s -o - | FileCheck %s
---
name: unmerge_sgprS16_from_V2S16
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