[llvm] [AArch64][Vectorizer] Enable scalable factor-3 interleaving (PR #217370)

[David Sherwood via llvm-commits]

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@@ -5738,12 +5738,16 @@ InstructionCost AArch64TTIImpl::getInterleavedMemoryOpCost(
   if (VecTy->isScalableTy() && !ST->hasSVE())
     return InstructionCost::getInvalid();
 
-  // Scalable VFs will emit vector.[de]interleave intrinsics, and currently we
-  // only have lowering for power-of-2 factors.
-  // TODO: Add lowering for vector.[de]interleave3 intrinsics and support in
-  // InterleavedAccessPass for ld3/st3
-  if (VecTy->isScalableTy() && !isPowerOf2_32(Factor))
-    return InstructionCost::getInvalid();
+  // Scalable VFs emit vector.[de]interleave intrinsics, for which the target
+  // supports factors up to the maximum supported interleave factor.
+  if (VecTy->isScalableTy()) {
+    if (Factor > TLI->getMaxSupportedInterleaveFactor())
+      return InstructionCost::getInvalid();
+
+    if (Factor == 3 &&
+        DL.getTypeSizeInBits(VecTy).getKnownMinValue() != (3 * 128))
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david-arm wrote:

Given the factor-3 variant is a bit more complicated, I think it would be worth adding some cost model tests similar to Transforms/LoopVectorize/AArch64/interleaved_cost.ll and Transforms/LoopVectorize/AArch64/sve-interleave-low-vf-cost.ll, to show costs for i16 element types, etc. I'd expect some VFs to report an invalid cost due to not being == <vscale x 3 x 128> bits in size.

https://github.com/llvm/llvm-project/pull/217370