[llvm] [AMDGPU] Do not propagate ninf/nsz from sqrt when forming rsq (PR #217599)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 20 05:02:43 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Arseniy Obolenskiy (aobolensk)
<details>
<summary>Changes</summary>
These flags only apply to the sqrt, not the quotient
1.0/sqrt(+0.0) is a valid +inf if the fdiv has no ninf, so copying them makes it poison
---
Full diff: https://github.com/llvm/llvm-project/pull/217599.diff
3 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp (+6-2)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll (+66-27)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll (+21-21)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
index fd0eb6d7a12e7..d253aaf3b82f3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
@@ -742,9 +742,13 @@ Value *AMDGPUCodeGenPrepareImpl::optimizeWithRsq(
// TODO: Handle other numerator values with arcp.
if (CLHS->isOne() || (IsNegative = CLHS->isMinusOne())) {
- // Add in the sqrt flags.
+ // Add sqrt flags, but keep ninf/nsz from the div: they don't say
+ // anything about the quotient.
IRBuilder<>::FastMathFlagGuard Guard(Builder);
- Builder.setFastMathFlags(DivFMF | SqrtFMF);
+ FastMathFlags NewFMF = DivFMF | SqrtFMF;
+ NewFMF.setNoInfs(DivFMF.noInfs());
+ NewFMF.setNoSignedZeros(DivFMF.noSignedZeros());
+ Builder.setFastMathFlags(NewFMF);
if (Den->getType()->isFloatTy()) {
if ((DivFMF.approxFunc() && SqrtFMF.approxFunc()) ||
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll
index de38916c22852..2f0f7ba345736 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll
@@ -148,15 +148,15 @@ define double @neg_rsq_f64_nnan_ninf(double %x) {
define double @rsq_f64_sqrt_nnan_ninf(double %x) {
; CHECK-LABEL: define double @rsq_f64_sqrt_nnan_ninf(
; CHECK-SAME: double [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf contract double @llvm.amdgcn.rsq.f64(double [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = fcmp nnan ninf contract oeq double [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP3:%.*]] = select nnan ninf contract i1 [[TMP2]], double [[TMP1]], double [[X]]
-; CHECK-NEXT: [[TMP4:%.*]] = fneg nnan ninf contract double [[TMP1]]
-; CHECK-NEXT: [[TMP5:%.*]] = fmul nnan ninf contract double [[TMP3]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = call nnan ninf contract double @llvm.fma.f64(double [[TMP5]], double [[TMP1]], double 1.000000e+00)
-; CHECK-NEXT: [[TMP7:%.*]] = fmul nnan ninf contract double [[TMP6]], [[TMP1]]
-; CHECK-NEXT: [[TMP8:%.*]] = call nnan ninf contract double @llvm.fma.f64(double [[TMP6]], double 3.750000e-01, double 5.000000e-01)
-; CHECK-NEXT: [[FDIV:%.*]] = call nnan ninf contract double @llvm.fma.f64(double [[TMP7]], double [[TMP8]], double [[TMP1]])
+; CHECK-NEXT: [[TMP1:%.*]] = call nnan contract double @llvm.amdgcn.rsq.f64(double [[X]])
+; CHECK-NEXT: [[TMP2:%.*]] = fcmp nnan contract oeq double [[X]], 0.000000e+00
+; CHECK-NEXT: [[TMP3:%.*]] = select nnan contract i1 [[TMP2]], double [[TMP1]], double [[X]]
+; CHECK-NEXT: [[TMP4:%.*]] = fneg nnan contract double [[TMP1]]
+; CHECK-NEXT: [[TMP5:%.*]] = fmul nnan contract double [[TMP3]], [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = call nnan contract double @llvm.fma.f64(double [[TMP5]], double [[TMP1]], double 1.000000e+00)
+; CHECK-NEXT: [[TMP7:%.*]] = fmul nnan contract double [[TMP6]], [[TMP1]]
+; CHECK-NEXT: [[TMP8:%.*]] = call nnan contract double @llvm.fma.f64(double [[TMP6]], double 3.750000e-01, double 5.000000e-01)
+; CHECK-NEXT: [[FDIV:%.*]] = call nnan contract double @llvm.fma.f64(double [[TMP7]], double [[TMP8]], double [[TMP1]])
; CHECK-NEXT: ret double [[FDIV]]
;
%sqrt.x = call contract nnan ninf double @llvm.sqrt.f64(double %x)
@@ -675,15 +675,15 @@ define double @rsq_f64_nnan_fdiv(double %x) {
define double @rsq_f64_ninf_sqrt(double %x) {
; CHECK-LABEL: define double @rsq_f64_ninf_sqrt(
; CHECK-SAME: double [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call ninf contract double @llvm.amdgcn.rsq.f64(double [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = fcmp ninf contract oeq double [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP3:%.*]] = select ninf contract i1 [[TMP2]], double [[TMP1]], double [[X]]
-; CHECK-NEXT: [[TMP4:%.*]] = fneg ninf contract double [[TMP1]]
-; CHECK-NEXT: [[TMP5:%.*]] = fmul ninf contract double [[TMP3]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = call ninf contract double @llvm.fma.f64(double [[TMP5]], double [[TMP1]], double 1.000000e+00)
-; CHECK-NEXT: [[TMP7:%.*]] = fmul ninf contract double [[TMP6]], [[TMP1]]
-; CHECK-NEXT: [[TMP8:%.*]] = call ninf contract double @llvm.fma.f64(double [[TMP6]], double 3.750000e-01, double 5.000000e-01)
-; CHECK-NEXT: [[FDIV:%.*]] = call ninf contract double @llvm.fma.f64(double [[TMP7]], double [[TMP8]], double [[TMP1]])
+; CHECK-NEXT: [[TMP1:%.*]] = call contract double @llvm.amdgcn.rsq.f64(double [[X]])
+; CHECK-NEXT: [[TMP2:%.*]] = fcmp contract oeq double [[X]], 0.000000e+00
+; CHECK-NEXT: [[TMP3:%.*]] = select contract i1 [[TMP2]], double [[TMP1]], double [[X]]
+; CHECK-NEXT: [[TMP4:%.*]] = fneg contract double [[TMP1]]
+; CHECK-NEXT: [[TMP5:%.*]] = fmul contract double [[TMP3]], [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = call contract double @llvm.fma.f64(double [[TMP5]], double [[TMP1]], double 1.000000e+00)
+; CHECK-NEXT: [[TMP7:%.*]] = fmul contract double [[TMP6]], [[TMP1]]
+; CHECK-NEXT: [[TMP8:%.*]] = call contract double @llvm.fma.f64(double [[TMP6]], double 3.750000e-01, double 5.000000e-01)
+; CHECK-NEXT: [[FDIV:%.*]] = call contract double @llvm.fma.f64(double [[TMP7]], double [[TMP8]], double [[TMP1]])
; CHECK-NEXT: ret double [[FDIV]]
;
%sqrt.x = call contract ninf double @llvm.sqrt.f64(double %x)
@@ -711,15 +711,15 @@ define double @rsq_f64_ninf_fdiv(double %x) {
define double @rsq_f64_ninf_sqrt_nnan_fdiv(double %x) {
; CHECK-LABEL: define double @rsq_f64_ninf_sqrt_nnan_fdiv(
; CHECK-SAME: double [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf contract double @llvm.amdgcn.rsq.f64(double [[X]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp nnan ninf contract oeq double [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP8:%.*]] = select nnan ninf contract i1 [[TMP7]], double [[TMP1]], double [[X]]
-; CHECK-NEXT: [[TMP2:%.*]] = fneg nnan ninf contract double [[TMP1]]
-; CHECK-NEXT: [[TMP3:%.*]] = fmul nnan ninf contract double [[TMP8]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = call nnan ninf contract double @llvm.fma.f64(double [[TMP3]], double [[TMP1]], double 1.000000e+00)
-; CHECK-NEXT: [[TMP5:%.*]] = fmul nnan ninf contract double [[TMP4]], [[TMP1]]
-; CHECK-NEXT: [[TMP6:%.*]] = call nnan ninf contract double @llvm.fma.f64(double [[TMP4]], double 3.750000e-01, double 5.000000e-01)
-; CHECK-NEXT: [[FDIV:%.*]] = call nnan ninf contract double @llvm.fma.f64(double [[TMP5]], double [[TMP6]], double [[TMP1]])
+; CHECK-NEXT: [[TMP1:%.*]] = call nnan contract double @llvm.amdgcn.rsq.f64(double [[X]])
+; CHECK-NEXT: [[TMP2:%.*]] = fcmp nnan contract oeq double [[X]], 0.000000e+00
+; CHECK-NEXT: [[TMP3:%.*]] = select nnan contract i1 [[TMP2]], double [[TMP1]], double [[X]]
+; CHECK-NEXT: [[TMP4:%.*]] = fneg nnan contract double [[TMP1]]
+; CHECK-NEXT: [[TMP5:%.*]] = fmul nnan contract double [[TMP3]], [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = call nnan contract double @llvm.fma.f64(double [[TMP5]], double [[TMP1]], double 1.000000e+00)
+; CHECK-NEXT: [[TMP7:%.*]] = fmul nnan contract double [[TMP6]], [[TMP1]]
+; CHECK-NEXT: [[TMP8:%.*]] = call nnan contract double @llvm.fma.f64(double [[TMP6]], double 3.750000e-01, double 5.000000e-01)
+; CHECK-NEXT: [[FDIV:%.*]] = call nnan contract double @llvm.fma.f64(double [[TMP7]], double [[TMP8]], double [[TMP1]])
; CHECK-NEXT: ret double [[FDIV]]
;
%sqrt.x = call contract ninf double @llvm.sqrt.f64(double %x)
@@ -744,6 +744,45 @@ define double @rsq_f64_nann_sqrt_ninf_fdiv(double %x) {
ret double %fdiv
}
+; nsz on the sqrt doesn't constrain the zero quotient sign at x = +inf.
+define double @rsq_f64_nsz_sqrt(double %x) {
+; CHECK-LABEL: define double @rsq_f64_nsz_sqrt(
+; CHECK-SAME: double [[X:%.*]]) {
+; CHECK-NEXT: [[TMP1:%.*]] = call contract double @llvm.amdgcn.rsq.f64(double [[X]])
+; CHECK-NEXT: [[TMP2:%.*]] = call i1 @llvm.is.fpclass.f64(double [[X]], /* (pinf zero) */ i32 608)
+; CHECK-NEXT: [[TMP3:%.*]] = select contract i1 [[TMP2]], double [[TMP1]], double [[X]]
+; CHECK-NEXT: [[TMP4:%.*]] = fneg contract double [[TMP1]]
+; CHECK-NEXT: [[TMP5:%.*]] = fmul contract double [[TMP3]], [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = call contract double @llvm.fma.f64(double [[TMP5]], double [[TMP1]], double 1.000000e+00)
+; CHECK-NEXT: [[TMP7:%.*]] = fmul contract double [[TMP6]], [[TMP1]]
+; CHECK-NEXT: [[TMP8:%.*]] = call contract double @llvm.fma.f64(double [[TMP6]], double 3.750000e-01, double 5.000000e-01)
+; CHECK-NEXT: [[FDIV:%.*]] = call contract double @llvm.fma.f64(double [[TMP7]], double [[TMP8]], double [[TMP1]])
+; CHECK-NEXT: ret double [[FDIV]]
+;
+ %sqrt.x = call contract nsz double @llvm.sqrt.f64(double %x)
+ %fdiv = fdiv contract double 1.0, %sqrt.x
+ ret double %fdiv
+}
+
+define double @rsq_f64_nsz_fdiv(double %x) {
+; CHECK-LABEL: define double @rsq_f64_nsz_fdiv(
+; CHECK-SAME: double [[X:%.*]]) {
+; CHECK-NEXT: [[TMP1:%.*]] = call nsz contract double @llvm.amdgcn.rsq.f64(double [[X]])
+; CHECK-NEXT: [[TMP2:%.*]] = call i1 @llvm.is.fpclass.f64(double [[X]], /* (pinf zero) */ i32 608)
+; CHECK-NEXT: [[TMP3:%.*]] = select nsz contract i1 [[TMP2]], double [[TMP1]], double [[X]]
+; CHECK-NEXT: [[TMP4:%.*]] = fneg nsz contract double [[TMP1]]
+; CHECK-NEXT: [[TMP5:%.*]] = fmul nsz contract double [[TMP3]], [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = call nsz contract double @llvm.fma.f64(double [[TMP5]], double [[TMP1]], double 1.000000e+00)
+; CHECK-NEXT: [[TMP7:%.*]] = fmul nsz contract double [[TMP6]], [[TMP1]]
+; CHECK-NEXT: [[TMP8:%.*]] = call nsz contract double @llvm.fma.f64(double [[TMP6]], double 3.750000e-01, double 5.000000e-01)
+; CHECK-NEXT: [[FDIV:%.*]] = call nsz contract double @llvm.fma.f64(double [[TMP7]], double [[TMP8]], double [[TMP1]])
+; CHECK-NEXT: ret double [[FDIV]]
+;
+ %sqrt.x = call contract double @llvm.sqrt.f64(double %x)
+ %fdiv = fdiv contract nsz double 1.0, %sqrt.x
+ ret double %fdiv
+}
+
define double @rsq_f64_assume_nonzero(double %x) {
; CHECK-LABEL: define double @rsq_f64_assume_nonzero(
; CHECK-SAME: double [[X:%.*]]) {
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll
index affad6b4796e0..f3a9e235f1a4a 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll
@@ -1808,20 +1808,20 @@ define amdgpu_kernel void @rsq_f32_fpmath_flags(ptr addrspace(1) %out, float %x)
; IEEE-NEXT: [[TMP20:%.*]] = select nsz contract i1 [[TMP16]], float 4.096000e+03, float 1.000000e+00
; IEEE-NEXT: [[FDIV_OPENCL_NSZ:%.*]] = fmul nsz contract float [[TMP19]], [[TMP20]]
; IEEE-NEXT: store volatile float [[FDIV_OPENCL_NSZ]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP21:%.*]] = fcmp nnan ninf contract olt float [[X]], f0x00800000
-; IEEE-NEXT: [[TMP22:%.*]] = select nnan ninf contract i1 [[TMP21]], float f0x4B800000, float 1.000000e+00
-; IEEE-NEXT: [[TMP23:%.*]] = fmul nnan ninf contract float [[X]], [[TMP22]]
-; IEEE-NEXT: [[TMP24:%.*]] = call nnan ninf contract float @llvm.amdgcn.rsq.f32(float [[TMP23]])
-; IEEE-NEXT: [[TMP25:%.*]] = select nnan ninf contract i1 [[TMP21]], float 4.096000e+03, float 1.000000e+00
-; IEEE-NEXT: [[FDIV_OPENCL_NNAN_MIX0:%.*]] = fmul nnan ninf contract float [[TMP24]], [[TMP25]]
+; IEEE-NEXT: [[TMP21:%.*]] = fcmp nnan contract olt float [[X]], f0x00800000
+; IEEE-NEXT: [[TMP22:%.*]] = select nnan contract i1 [[TMP21]], float f0x4B800000, float 1.000000e+00
+; IEEE-NEXT: [[TMP23:%.*]] = fmul nnan contract float [[X]], [[TMP22]]
+; IEEE-NEXT: [[TMP24:%.*]] = call nnan contract float @llvm.amdgcn.rsq.f32(float [[TMP23]])
+; IEEE-NEXT: [[TMP25:%.*]] = select nnan contract i1 [[TMP21]], float 4.096000e+03, float 1.000000e+00
+; IEEE-NEXT: [[FDIV_OPENCL_NNAN_MIX0:%.*]] = fmul nnan contract float [[TMP24]], [[TMP25]]
; IEEE-NEXT: store volatile float [[FDIV_OPENCL_NNAN_MIX0]], ptr addrspace(1) [[OUT]], align 4
; IEEE-NEXT: [[TMP26:%.*]] = fcmp nnan ninf contract olt float [[X]], f0x00800000
; IEEE-NEXT: [[TMP27:%.*]] = select nnan ninf contract i1 [[TMP26]], float f0x4B800000, float 1.000000e+00
; IEEE-NEXT: [[TMP28:%.*]] = fmul nnan ninf contract float [[X]], [[TMP27]]
; IEEE-NEXT: [[TMP29:%.*]] = call nnan ninf contract float @llvm.amdgcn.rsq.f32(float [[TMP28]])
; IEEE-NEXT: [[TMP30:%.*]] = select nnan ninf contract i1 [[TMP26]], float 4.096000e+03, float 1.000000e+00
-; IEEE-NEXT: [[FDIV_OPENCL_NNAN_MIX1:%.*]] = fmul nnan ninf contract float [[TMP29]], [[TMP30]]
-; IEEE-NEXT: store volatile float [[FDIV_OPENCL_NNAN_MIX1]], ptr addrspace(1) [[OUT]], align 4
+; IEEE-NEXT: [[FDIV_OPENCL_NINF_MIX1:%.*]] = fmul nnan ninf contract float [[TMP29]], [[TMP30]]
+; IEEE-NEXT: store volatile float [[FDIV_OPENCL_NINF_MIX1]], ptr addrspace(1) [[OUT]], align 4
; IEEE-NEXT: ret void
;
; DAZ-LABEL: define amdgpu_kernel void @rsq_f32_fpmath_flags(
@@ -1834,10 +1834,10 @@ define amdgpu_kernel void @rsq_f32_fpmath_flags(ptr addrspace(1) %out, float %x)
; DAZ-NEXT: store volatile float [[FDIV_OPENCL_NNAN]], ptr addrspace(1) [[OUT]], align 4
; DAZ-NEXT: [[FDIV_OPENCL_NSZ:%.*]] = call nsz contract float @llvm.amdgcn.rsq.f32(float [[X]])
; DAZ-NEXT: store volatile float [[FDIV_OPENCL_NSZ]], ptr addrspace(1) [[OUT]], align 4
-; DAZ-NEXT: [[FDIV_OPENCL_NNAN_MIX0:%.*]] = call nnan ninf contract float @llvm.amdgcn.rsq.f32(float [[X]])
+; DAZ-NEXT: [[FDIV_OPENCL_NNAN_MIX0:%.*]] = call nnan contract float @llvm.amdgcn.rsq.f32(float [[X]])
; DAZ-NEXT: store volatile float [[FDIV_OPENCL_NNAN_MIX0]], ptr addrspace(1) [[OUT]], align 4
-; DAZ-NEXT: [[FDIV_OPENCL_NNAN_MIX1:%.*]] = call nnan ninf contract float @llvm.amdgcn.rsq.f32(float [[X]])
-; DAZ-NEXT: store volatile float [[FDIV_OPENCL_NNAN_MIX1]], ptr addrspace(1) [[OUT]], align 4
+; DAZ-NEXT: [[FDIV_OPENCL_NINF_MIX1:%.*]] = call nnan ninf contract float @llvm.amdgcn.rsq.f32(float [[X]])
+; DAZ-NEXT: store volatile float [[FDIV_OPENCL_NINF_MIX1]], ptr addrspace(1) [[OUT]], align 4
; DAZ-NEXT: ret void
;
%sqrt.x.3ulp.ninf.nnan = call contract ninf nnan float @llvm.sqrt.f32(float %x), !fpmath !3 ; OpenCL default requires 3 for sqrt and 2.5 for fdiv
@@ -1860,9 +1860,9 @@ define amdgpu_kernel void @rsq_f32_fpmath_flags(ptr addrspace(1) %out, float %x)
%fdiv.opencl.nnan.mix0 = fdiv contract nnan float 1.0, %sqrt.x.3ulp.ninf.mix0, !fpmath !0
store volatile float %fdiv.opencl.nnan.mix0, ptr addrspace(1) %out, align 4
- %sqrt.x.3ulp.ninf.mix1 = call contract ninf float @llvm.sqrt.f32(float %x), !fpmath !3
- %fdiv.opencl.nnan.mix1 = fdiv contract nnan float 1.0, %sqrt.x.3ulp.ninf.mix1, !fpmath !0
- store volatile float %fdiv.opencl.nnan.mix1, ptr addrspace(1) %out, align 4
+ %sqrt.x.3ulp.nnan.mix1 = call contract nnan float @llvm.sqrt.f32(float %x), !fpmath !3
+ %fdiv.opencl.ninf.mix1 = fdiv contract ninf float 1.0, %sqrt.x.3ulp.nnan.mix1, !fpmath !0
+ store volatile float %fdiv.opencl.ninf.mix1, ptr addrspace(1) %out, align 4
ret void
}
@@ -1938,17 +1938,17 @@ define float @rsq_f32_missing_contract1(float %x) {
define float @rsq_f32_flag_merge(float %x) {
; IEEE-LABEL: define float @rsq_f32_flag_merge(
; IEEE-SAME: float [[X:%.*]]) #[[ATTR1]] {
-; IEEE-NEXT: [[TMP1:%.*]] = fcmp ninf nsz contract olt float [[X]], f0x00800000
-; IEEE-NEXT: [[TMP2:%.*]] = select ninf nsz contract i1 [[TMP1]], float f0x4B800000, float 1.000000e+00
-; IEEE-NEXT: [[TMP3:%.*]] = fmul ninf nsz contract float [[X]], [[TMP2]]
-; IEEE-NEXT: [[TMP4:%.*]] = call ninf nsz contract float @llvm.amdgcn.rsq.f32(float [[TMP3]])
-; IEEE-NEXT: [[TMP5:%.*]] = select ninf nsz contract i1 [[TMP1]], float 4.096000e+03, float 1.000000e+00
-; IEEE-NEXT: [[FDIV_OPENCL:%.*]] = fmul ninf nsz contract float [[TMP4]], [[TMP5]]
+; IEEE-NEXT: [[TMP1:%.*]] = fcmp nsz contract olt float [[X]], f0x00800000
+; IEEE-NEXT: [[TMP2:%.*]] = select nsz contract i1 [[TMP1]], float f0x4B800000, float 1.000000e+00
+; IEEE-NEXT: [[TMP3:%.*]] = fmul nsz contract float [[X]], [[TMP2]]
+; IEEE-NEXT: [[TMP4:%.*]] = call nsz contract float @llvm.amdgcn.rsq.f32(float [[TMP3]])
+; IEEE-NEXT: [[TMP5:%.*]] = select nsz contract i1 [[TMP1]], float 4.096000e+03, float 1.000000e+00
+; IEEE-NEXT: [[FDIV_OPENCL:%.*]] = fmul nsz contract float [[TMP4]], [[TMP5]]
; IEEE-NEXT: ret float [[FDIV_OPENCL]]
;
; DAZ-LABEL: define float @rsq_f32_flag_merge(
; DAZ-SAME: float [[X:%.*]]) #[[ATTR1]] {
-; DAZ-NEXT: [[FDIV_OPENCL:%.*]] = call ninf nsz contract float @llvm.amdgcn.rsq.f32(float [[X]])
+; DAZ-NEXT: [[FDIV_OPENCL:%.*]] = call nsz contract float @llvm.amdgcn.rsq.f32(float [[X]])
; DAZ-NEXT: ret float [[FDIV_OPENCL]]
;
%sqrt.x.3ulp = call contract ninf float @llvm.sqrt.f32(float %x), !fpmath !2
``````````
</details>
https://github.com/llvm/llvm-project/pull/217599
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