[llvm] [AMDGPU][GlobalISel] Eliminate READANYLANE round trips in mixed build_vector/merge (PR #210449)

[Matt Arsenault via llvm-commits]

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@@ -575,6 +589,73 @@ bool AMDGPURegBankCombinerImpl::matchMinMaxToMinMax3(
   return true;
 }
 
+// Sgpr0 = G_AMDGPU_READANYLANE Vgpr0
+// Src = G_MERGE_LIKE Sgpr0, Sgpr1, ...
+// Dst = COPY Src
+// ->
+// Vgpr1 = COPY Sgpr1
+// Dst = G_MERGE_LIKE Vgpr0, Vgpr1, ...
+//
+// Merge sources that are not readanylanes have to be uniform, copying them to a
+// vgpr is a broadcast. Requires at least one readanylane source, otherwise this
+// would only move the copy from the merge result to its sources.
+bool AMDGPURegBankCombinerImpl::matchMergeReadAnyLaneToVgpr(
+    MachineInstr &Copy, SmallVector<Register> &Srcs) const {
+  Register Dst = Copy.getOperand(0).getReg();
+  Register Src = Copy.getOperand(1).getReg();
+
+  if (!isVgprRegBank(Dst))
+    return false;
+
+  // Skip physical source registers and source registers with register class.
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arsenm wrote:

```suggestion
```
This comment isn't providing a reason

https://github.com/llvm/llvm-project/pull/210449