[llvm] [AMDGPU] Fix eliminateFrameIndex clobbering a scavenged register (PR #217470)

[Matt Arsenault via llvm-commits]

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@@ -3372,6 +3372,20 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
                  : RS->scavengeRegisterBackwards(*RC, MI, false, 0);
 
       int64_t Offset = FrameInfo.getObjectOffset(Index);
+
+      // The carry-out lane of Add is unused, so it is safe to write with
+      // S_MOV_B32 even into a VGPR.
+      auto MaterializeCarryOutOffset = [&](MachineInstrBuilder &Add) {
+        Register ConstOffsetReg;
+        if (!isWave32)
+          ConstOffsetReg = getSubReg(Add.getReg(1), AMDGPU::sub0);
+        else
+          ConstOffsetReg = Add.getReg(1);
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arsenm wrote:

Assign from ternary operator 

https://github.com/llvm/llvm-project/pull/217470