[llvm] PPC: Fix EXTSW elimination promoting a subregister operand (PR #208051)

[Matt Arsenault via llvm-commits]

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@@ -5499,6 +5499,13 @@ void PPCInstrInfo::promoteInstr32To64ForElimEXTSW(const Register &Reg,
     if (!OperandReg.isVirtual())
       continue;
 
+    // An operand that reads the sub_32 subregister of a 64-bit register already
+    // holds the value in a full 64-bit register.
+    if (Operand.getSubReg() == PPC::sub_32) {
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arsenm wrote:

  The 64-bit register is used directly, but that's the point, this isn't promoting anything new. sub_32 only exists on g8rc, so a gprc operand like the SRD shift amount can't reach this path; it still falls through to the existing class check. The only operands here are already g8rc reads via .sub_32, which the old code copied verbatim and carried an illegal subreg into the full-register instruction.
This just sources those low 32 bits from the register directly instead.

https://github.com/llvm/llvm-project/pull/208051