[llvm] 394de25 - AArch64: Use m_GPtrAdd in selectAddrModeRegisterOffset (#217446)

[via llvm-commits]

Author: Matt Arsenault
Date: 2026-08-20T10:25:24+02:00
New Revision: 394de25db7d7e9c5d00bb7ab93e6666bad9a3bc6

URL: https://github.com/llvm/llvm-project/commit/394de25db7d7e9c5d00bb7ab93e6666bad9a3bc6
DIFF: https://github.com/llvm/llvm-project/commit/394de25db7d7e9c5d00bb7ab93e6666bad9a3bc6.diff

LOG: AArch64: Use m_GPtrAdd in selectAddrModeRegisterOffset (#217446)

Replace the getVRegDef + G_PTR_ADD opcode check and operand 
accesses with an m_GPtrAdd matcher.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 601829c3f7546..f349ae38e8fd8 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -7367,23 +7367,19 @@ AArch64InstructionSelector::selectAddrModeRegisterOffset(
   MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
 
   // We need a GEP.
-  MachineInstr *Gep = MRI.getVRegDef(Root.getReg());
-  if (Gep->getOpcode() != TargetOpcode::G_PTR_ADD)
+  Register Base, Offset;
+  if (!mi_match(Root.getReg(), MRI, m_GPtrAdd(m_Reg(Base), m_Reg(Offset))))
     return std::nullopt;
 
   // If this is used more than once, let's not bother folding.
   // TODO: Check if they are memory ops. If they are, then we can still fold
   // without having to recompute anything.
-  if (!MRI.hasOneNonDBGUse(Gep->getOperand(0).getReg()))
+  if (!MRI.hasOneNonDBGUse(Root.getReg()))
     return std::nullopt;
 
   // Base is the GEP's LHS, offset is its RHS.
-  return {{[=](MachineInstrBuilder &MIB) {
-             MIB.addUse(Gep->getOperand(1).getReg());
-           },
-           [=](MachineInstrBuilder &MIB) {
-             MIB.addUse(Gep->getOperand(2).getReg());
-           },
+  return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(Base); },
+           [=](MachineInstrBuilder &MIB) { MIB.addUse(Offset); },
            [=](MachineInstrBuilder &MIB) {
              // Need to add both immediates here to make sure that they are both
              // added to the instruction.