[llvm] [AArch64] Reject non-scalable types in named Z-register constraints (PR #217551)
Kieran B via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 20 01:16:00 PDT 2026
https://github.com/kieroxide created https://github.com/llvm/llvm-project/pull/217551
LLVM currently handles typed named Z-register constraints inconsistently. Depending on the operand type and whether SVE is available, compilation may succeed, crash, or trigger an assertion.
Reject typed Z-register operands when SVE or streaming SVE is unavailable, and reject non-scalable operand types. Preserve the existing behavior for untyped Z-register clobbers.
Original Crash Report: [Here](https://github.com/llvm/llvm-project/issues/169027)
>From b729e2fe0beb52da3e4efffa7fb549ad19d38280 Mon Sep 17 00:00:00 2001
From: Kieran Bailey <kieran.bailey at arm.com>
Date: Wed, 19 Aug 2026 14:55:52 +0000
Subject: [PATCH] [AArch64] Reject non-scalable types in named Z-register
constraints
LLVM currently handles typed named Z-register constraints inconsistently.
Depending on the operand type and whether SVE is available, compilation may
succeed, crash, or trigger an assertion.
Reject typed Z-register operands when SVE or streaming SVE is unavailable, and
reject non-scalable operand types. Preserve the existing behavior for untyped
Z-register clobbers.
---
.../Target/AArch64/AArch64ISelLowering.cpp | 24 ++-
.../inline-asm-named-z-reg-constraints.ll | 145 ++++++++++++++++++
2 files changed, 163 insertions(+), 6 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/inline-asm-named-z-reg-constraints.ll
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 89a9249d11412..a1cf4ab700256 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -14357,13 +14357,25 @@ AArch64TargetLowering::getRegForInlineAsmConstraint(
}
} else {
if (const auto P = parseSVERegAsConstraint(Constraint)) {
- // SME functions that are not in streaming mode, should
- // still observe clobbers of Z-registers by clobbering
- // the lower 128bits of those registers.
- if (AArch64::ZPRRegClass.hasSubClassEq(P->second) &&
+ if (!AArch64::ZPRRegClass.hasSubClassEq(P->second))
+ return *P;
+
+ // A named Z-register constraint with MVT::Other represents an untyped
+ // clobber.
+ if (VT == MVT::Other) {
+ // SME functions that are not in streaming mode, should
+ // still observe clobbers of Z-registers by clobbering
+ // the lower 128bits of those registers.
+ if (!Subtarget->isSVEorStreamingSVEAvailable())
+ return std::make_pair(TRI->getSubReg(P->first, AArch64::zsub),
+ &AArch64::FPR128RegClass);
+ return *P;
+ }
+
+ if (!VT.isScalableVector() ||
!Subtarget->isSVEorStreamingSVEAvailable())
- return std::make_pair(TRI->getSubReg(P->first, AArch64::zsub),
- &AArch64::FPR128RegClass);
+ return std::make_pair(0U, nullptr);
+
return *P;
}
if (const auto PC = parsePredicateConstraint(Constraint))
diff --git a/llvm/test/CodeGen/AArch64/inline-asm-named-z-reg-constraints.ll b/llvm/test/CodeGen/AArch64/inline-asm-named-z-reg-constraints.ll
new file mode 100644
index 0000000000000..63e7c960f0fbc
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/inline-asm-named-z-reg-constraints.ll
@@ -0,0 +1,145 @@
+; RUN: split-file %s %t
+; RUN: not llc -mtriple=aarch64-linux-gnu %t/negative.ll -o - 2>&1 | FileCheck %s
+; RUN: not llc -mtriple=aarch64-linux-gnu -mattr=+sve %t/negative.ll -o - 2>&1 | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve %t/positive.ll -o - | FileCheck %s --check-prefix=POSITIVE
+
+; CHECK-COUNT-7: error: could not allocate input reg for constraint '{z0}'
+; CHECK-COUNT-14: error: could not allocate output register for constraint '{z0}'
+
+; Test representative non-scalable types for each selected bit size.
+
+;--- negative.ll
+
+define void @input_8bit(<1 x i8> %value) {
+ call void asm sideeffect "", "{z0}"(<1 x i8> %value)
+ ret void
+}
+
+define void @input_16bit(<2 x i8> %value) {
+ call void asm sideeffect "", "{z0}"(<2 x i8> %value)
+ ret void
+}
+
+define void @input_32bit(<4 x i8> %value) {
+ call void asm sideeffect "", "{z0}"(<4 x i8> %value)
+ ret void
+}
+
+define void @input_64bit(<8 x i8> %value) {
+ call void asm sideeffect "", "{z0}"(<8 x i8> %value)
+ ret void
+}
+
+define void @input_128bit(<16 x i8> %value) {
+ call void asm sideeffect "", "{z0}"(<16 x i8> %value)
+ ret void
+}
+
+define void @input_256bit(<32 x i8> %value) {
+ call void asm sideeffect "", "{z0}"(<32 x i8> %value)
+ ret void
+}
+
+define void @input_scalar_i32(i32 %value) {
+ call void asm sideeffect "", "{z0}"(i32 %value)
+ ret void
+}
+
+define <1 x i8> @output_8bit() {
+ %value = call <1 x i8> asm sideeffect "", "={z0}"()
+ ret <1 x i8> %value
+}
+
+define <2 x i8> @output_16bit() {
+ %value = call <2 x i8> asm sideeffect "", "={z0}"()
+ ret <2 x i8> %value
+}
+
+define <4 x i8> @output_32bit() {
+ %value = call <4 x i8> asm sideeffect "", "={z0}"()
+ ret <4 x i8> %value
+}
+
+define <8 x i8> @output_64bit() {
+ %value = call <8 x i8> asm sideeffect "", "={z0}"()
+ ret <8 x i8> %value
+}
+
+define <16 x i8> @output_128bit() {
+ %value = call <16 x i8> asm sideeffect "", "={z0}"()
+ ret <16 x i8> %value
+}
+
+define <32 x i8> @output_256bit() {
+ %value = call <32 x i8> asm sideeffect "", "={z0}"()
+ ret <32 x i8> %value
+}
+
+define i32 @output_scalar_i32() {
+ %value = call i32 asm sideeffect "", "={z0}"()
+ ret i32 %value
+}
+
+define <1 x i8> @inout_8bit(<1 x i8> %value) {
+ %result = call <1 x i8> asm sideeffect "", "={z0},0"(<1 x i8> %value)
+ ret <1 x i8> %result
+}
+
+define <2 x i8> @inout_16bit(<2 x i8> %value) {
+ %result = call <2 x i8> asm sideeffect "", "={z0},0"(<2 x i8> %value)
+ ret <2 x i8> %result
+}
+
+define <4 x i8> @inout_32bit(<4 x i8> %value) {
+ %result = call <4 x i8> asm sideeffect "", "={z0},0"(<4 x i8> %value)
+ ret <4 x i8> %result
+}
+
+define <8 x i8> @inout_64bit(<8 x i8> %value) {
+ %result = call <8 x i8> asm sideeffect "", "={z0},0"(<8 x i8> %value)
+ ret <8 x i8> %result
+}
+
+define <16 x i8> @inout_128bit(<16 x i8> %value) {
+ %result = call <16 x i8> asm sideeffect "", "={z0},0"(<16 x i8> %value)
+ ret <16 x i8> %result
+}
+
+define <32 x i8> @inout_256bit(<32 x i8> %value) {
+ %result = call <32 x i8> asm sideeffect "", "={z0},0"(<32 x i8> %value)
+ ret <32 x i8> %result
+}
+
+define i32 @inout_scalar_i32(i32 %value) {
+ %result = call i32 asm sideeffect "", "={z0},0"(i32 %value)
+ ret i32 %result
+}
+
+;--- positive.ll
+
+define void @input_scalable(<vscale x 2 x i64> %value) {
+; POSITIVE-LABEL: input_scalable:
+; POSITIVE: //APP
+; POSITIVE-NEXT: mov z0.d, z0.d
+; POSITIVE-NEXT: //NO_APP
+ call void asm sideeffect "mov $0.d, $0.d", "{z0}"(<vscale x 2 x i64> %value)
+ ret void
+}
+
+define <vscale x 2 x i64> @output_scalable() {
+; POSITIVE-LABEL: output_scalable:
+; POSITIVE: //APP
+; POSITIVE-NEXT: mov z0.d, #0
+; POSITIVE-NEXT: //NO_APP
+ %value = call <vscale x 2 x i64> asm sideeffect "dup $0.d, #0", "={z0}"()
+ ret <vscale x 2 x i64> %value
+}
+
+define <vscale x 2 x i64> @inout_scalable(<vscale x 2 x i64> %value) {
+; POSITIVE-LABEL: inout_scalable:
+; POSITIVE: //APP
+; POSITIVE-NEXT: mov z0.d, z0.d
+; POSITIVE-NEXT: //NO_APP
+ %result = call <vscale x 2 x i64> asm sideeffect "mov $0.d, $0.d", "={z0},0"(<vscale x 2 x i64> %value)
+ ret <vscale x 2 x i64> %result
+}
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