[llvm] [RISCV][Disassembler] Symbolize UImm20 and SImm12Lo operands (PR #217550)

[via llvm-commits]

https://github.com/Thrrreeee created https://github.com/llvm/llvm-project/pull/217550

Enable `MCSymbolizer` handling for RISC-V `UImm20` and `SImm12Lo` operands. Fall back to the original immediate when symbolization is not available. `SImm12Lo` values are sign-extended, while `UImm20` values remain unchanged.

This enables clients such as BOLT to reconstruct symbolic operands for HI20/LO12, PC-relative, and GOT relocations during instruction decoding. 

This change only adds symbolizer hooks for these operands; the actual symbolization is delegated to the installed `MCSymbolizer`. When no symbolizer is installed, the existing immediate-based disassembly behavior is preserved. Test coverage may need to be added after RISCVMCSymbolizer is implemented in BOLT. 

>From dcc390f261799f6ac50758248fbc6762c311d3aa Mon Sep 17 00:00:00 2001
From: shijinrui <shijinrui at bytedance.com>
Date: Thu, 20 Aug 2026 15:52:23 +0800
Subject: [PATCH] [RISCV][Disassembler] Symbolize UImm20 and SImm12Lo operands

---
 .../RISCV/Disassembler/RISCVDisassembler.cpp  | 25 +++++++++++++++++++
 llvm/lib/Target/RISCV/RISCVInstrInfo.td       |  2 ++
 2 files changed, 27 insertions(+)

diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 3b3eb5195a9b4..18fdfe69a11e3 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -403,6 +403,31 @@ static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm,
   return MCDisassembler::Success;
 }
 
+static DecodeStatus decodeSImm12LoOperand(MCInst &Inst, uint32_t Imm,
+                                          int64_t Address,
+                                          const MCDisassembler *Decoder) {
+  assert(isUInt<12>(Imm) && "Invalid immediate");
+  const int64_t Value = SignExtend64<12>(Imm);
+  if (!Decoder->tryAddingSymbolicOperand(Inst, Value, Address,
+                                         /*IsBranch=*/false,
+                                         /*Offset=*/0, /*OpSize=*/4,
+                                         /*InstSize=*/4))
+    Inst.addOperand(MCOperand::createImm(Value));
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeUImm20Operand(MCInst &Inst, uint32_t Imm,
+                                        int64_t Address,
+                                        const MCDisassembler *Decoder) {
+  assert(isUInt<20>(Imm) && "Invalid immediate");
+  if (!Decoder->tryAddingSymbolicOperand(Inst, Imm, Address,
+                                         /*IsBranch=*/false,
+                                         /*Offset=*/0, /*OpSize=*/4,
+                                         /*InstSize=*/4))
+    Inst.addOperand(MCOperand::createImm(Imm));
+  return MCDisassembler::Success;
+}
+
 template <unsigned N>
 static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
                                              int64_t Address,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 5be74d729c5b0..5a37b229664c4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -400,6 +400,7 @@ def uimm64 : RISCVUImmOp<64>;
 def simm12 : RISCVSImmLeafOp<12>;
 
 class Simm12LoOp : RISCVSImmLeafOp<12> {
+  let DecoderMethod = "decodeSImm12LoOperand";
   let MCOperandPredicate = [{
     int64_t Imm;
     if (MCOp.evaluateAsConstantImm(Imm))
@@ -455,6 +456,7 @@ def bare_simm13_lsb0 : BareSImm13Lsb0MaybeSym,
 def bare_simm13_lsb0_bb : BareSImm13Lsb0MaybeSym;
 
 class UImm20OperandMaybeSym : RISCVUImmOp<20> {
+  let DecoderMethod = "decodeUImm20Operand";
   let MCOperandPredicate = [{
     int64_t Imm;
     if (MCOp.evaluateAsConstantImm(Imm))