[llvm] a97f512 - [Mips] Fix getInstSizeInBytes for instructions with delay slots (#216665)

[via llvm-commits]

Author: yingopq
Date: 2026-08-20T10:55:25+08:00
New Revision: a97f512d71574c0b9adc9bc6216909387499e0e8

URL: https://github.com/llvm/llvm-project/commit/a97f512d71574c0b9adc9bc6216909387499e0e8
DIFF: https://github.com/llvm/llvm-project/commit/a97f512d71574c0b9adc9bc6216909387499e0e8.diff

LOG: [Mips] Fix getInstSizeInBytes for instructions with delay slots (#216665)

MIPS branch/jump instructions (B, BEQ, JALR64Pseudo, PseudoReturn64,
etc.) have a delay slot. The actual encoded size is 8 bytes (instr +
NOP). This fixes "out of range PC16 fixup" errors on large functions.

This issue was exposed in llvm 23 by commit pr #191460 which changed
MipsBranchExpansion to use MBB::iterator instead of instr_iterator,
making the MBB size calculation more accurate and revealing the
pre-existing bug.

Thanks for the pr #187703 `AllowOverEstimate` to help find instr which
actual size mismatch expected size .

Fix #112010.

Added: 
    

Modified: 
    llvm/lib/Target/Mips/MipsInstrInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
index 8648aa0836693..3df62754e2140 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
@@ -708,6 +708,10 @@ bool MipsInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
 unsigned MipsInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
   switch (MI.getOpcode()) {
   default:
+    if (MI.hasDelaySlot()) {
+      // instr + 1 nop
+      return MI.getDesc().getSize() + 4;
+    }
     return MI.getDesc().getSize();
   case  TargetOpcode::INLINEASM:
   case  TargetOpcode::INLINEASM_BR: {       // Inline Asm: Variable size.