[llvm] [AMDGPU][GlobalISel] Fix BITOP3 selecting B16 opcode for 32-bit vector types (PR #217048)

[Shilei Tian via llvm-commits]

================
@@ -4462,7 +4462,11 @@ bool AMDGPUInstructionSelector::selectBITOP3(MachineInstr &MI) const {
   if (NumOpcodes < 2 || Src.empty())
     return false;
 
-  const bool IsB32 = MRI->getType(DstReg) == LLT::scalar(32);
+  // RegBankSelect splits wider VALU logic ops and widens 1-bit ones, so only
+  // 16 and 32 bit types reach here. Note that <2 x i16> is 32 bits wide.
+  unsigned Size = MRI->getType(DstReg).getSizeInBits();
+  assert((Size == 16 || Size == 32) && "Unexpected VALU logic op size");
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shiltian wrote:

```suggestion
  assert((Size == 16 || Size == 32) && "unexpected VALU logic op size");
```

https://github.com/llvm/llvm-project/pull/217048