[llvm] [AMDGPU] Fix SIPeepholeSDWA crash on OR with VOPC SDWA operand (PR #217084)

[Arseniy Obolenskiy via llvm-commits]

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@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgpu10.30 < %s | FileCheck -check-prefix=GFX1030 %s
+
+; E2e companion to or_of_vopc_sdwa in sdwa-peephole-instr-gfx10.mir (missing dst_sel on VOPC SDWA).
+
+define i32 @or_of_vopc_sdwa(i32 %a, i32 %b) {
+; GFX1030-LABEL: or_of_vopc_sdwa:
+; GFX1030:       ; %bb.0:
+; GFX1030-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT:    v_add_nc_u32_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX1030-NEXT:    v_cmp_eq_u32_sdwa s4, v0, v1 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX1030-NEXT:    v_or_b32_e32 v0, s4, v2
+; GFX1030-NEXT:    s_setpc_b64 s[30:31]
+  %ah = lshr i32 %a, 16
+  %bh = lshr i32 %b, 16
+  %sum = add i32 %ah, %bh
+  %mask = call i32 @llvm.amdgcn.icmp.i32.i32(i32 %ah, i32 %bh, i32 32)
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aobolensk wrote:

Needs to be the intrinsic here. Plain icmp+zext adds `v_cndmask_b32` instruction before `or` and there is no bug reproduction 

https://github.com/llvm/llvm-project/pull/217084