[llvm] [AMDGPU] Remove more redundant ANDs (PR #216900)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 19 06:19:36 PDT 2026
https://github.com/LU-JOHN updated https://github.com/llvm/llvm-project/pull/216900
>From 6e59303dc51bc6c60d1c1c16dfd1707fb8ec1085 Mon Sep 17 00:00:00 2001
From: John Lu <John.Lu at amd.com>
Date: Mon, 17 Aug 2026 20:42:23 -0500
Subject: [PATCH 1/3] Remove more redundant ANDs
Signed-off-by: John Lu <John.Lu at amd.com>
---
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 80 ++-
.../AMDGPU/GlobalISel/cvt_f32_ubyte.ll | 5 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll | 454 ++++++++----------
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll | 444 ++++++++---------
llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll | 12 +-
.../AMDGPU/GlobalISel/vni8-across-blocks.ll | 4 +-
llvm/test/CodeGen/AMDGPU/anyext.ll | 2 -
llvm/test/CodeGen/AMDGPU/bf16.ll | 7 -
...ffer-fat-pointers-contents-legalization.ll | 1 -
llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll | 29 +-
llvm/test/CodeGen/AMDGPU/fabs.bf16.ll | 2 -
.../fold-zero-high-bits-clear-kill-flags.mir | 102 ++++
llvm/test/CodeGen/AMDGPU/freeze.ll | 212 +++-----
llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll | 5 -
.../CodeGen/AMDGPU/llvm.is.fpclass.f16.ll | 177 +++----
llvm/test/CodeGen/AMDGPU/load-constant-i1.ll | 71 ++-
llvm/test/CodeGen/AMDGPU/load-constant-i8.ll | 4 +-
llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll | 32 +-
llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll | 21 +-
.../AMDGPU/sdwa-peephole-cndmask-fail.ll | 12 +-
llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll | 6 +-
.../AMDGPU/strictfp_f16_abi_promote.ll | 13 +-
llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll | 23 +-
23 files changed, 747 insertions(+), 971 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index efbe5cf281f0f..02812c9170490 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -250,7 +250,7 @@ class SIFoldOperandsImpl {
bool tryConstantFoldOp(MachineInstr *MI) const;
bool tryFoldCndMask(MachineInstr &MI) const;
- bool tryFoldZeroHighBits(MachineInstr &MI) const;
+ bool tryFoldRedundantAnd(MachineInstr &ChildMI) const;
bool foldInstOperand(MachineInstr &MI, const FoldableDef &OpToFold) const;
bool foldCopyToAGPRRegSequence(MachineInstr *CopyMI) const;
@@ -1855,26 +1855,74 @@ bool SIFoldOperandsImpl::tryFoldCndMask(MachineInstr &MI) const {
return true;
}
-bool SIFoldOperandsImpl::tryFoldZeroHighBits(MachineInstr &MI) const {
- if (MI.getOpcode() != AMDGPU::V_AND_B32_e64 &&
- MI.getOpcode() != AMDGPU::V_AND_B32_e32)
+// Eliminate redundant AND operations by detecting when ChildMI's mask contains
+// ParentMI's mask.
+//
+// For example:
+// ParentMI: %1 = AND %0, 0x7fff
+// ChildMI: %2 = AND %1, 0xffff
+//
+// This also handles cases where ParentMI implicitly zeros high bits (e.g., f16
+// operations that write 16-bit results into 32-bit registers), making a
+// subsequent AND with 0xffff redundant.
+bool SIFoldOperandsImpl::tryFoldRedundantAnd(MachineInstr &ChildMI) const {
+ // Ensure implicit defs (e.g., $scc) are not live.
+ if (!ChildMI.allImplicitDefsAreDead())
return false;
- std::optional<int64_t> Src0Imm =
- TII->getImmOrMaterializedImm(MI.getOperand(1));
- if (!Src0Imm || *Src0Imm != 0xffff || !MI.getOperand(2).isReg())
+ // Helper to extract mask, register, and register operand index from an AND
+ // instruction. Mask can be detected in either operand 1 or 2. Returns {mask,
+ // register, operand_index}.
+ auto getMaskAndReg = [this](MachineInstr &AndMI)
+ -> std::optional<std::tuple<int64_t, Register, unsigned>> {
+ unsigned Opc = AndMI.getOpcode();
+ if (Opc != AMDGPU::V_AND_B32_e64 && Opc != AMDGPU::V_AND_B32_e32 &&
+ Opc != AMDGPU::S_AND_B32)
+ return std::nullopt;
+
+ std::optional<int64_t> MaskImm =
+ TII->getImmOrMaterializedImm(AndMI.getOperand(1));
+ if (MaskImm && AndMI.getOperand(2).isReg())
+ return std::make_tuple(*MaskImm, AndMI.getOperand(2).getReg(), 2);
+
+ MaskImm = TII->getImmOrMaterializedImm(AndMI.getOperand(2));
+ if (MaskImm && AndMI.getOperand(1).isReg())
+ return std::make_tuple(*MaskImm, AndMI.getOperand(1).getReg(), 1);
+
+ return std::nullopt;
+ };
+
+ auto ChildMaskAndReg = getMaskAndReg(ChildMI);
+ if (!ChildMaskAndReg)
return false;
- Register Src1 = MI.getOperand(2).getReg();
- MachineInstr *SrcDef = MRI->getVRegDef(Src1);
- if (!ST->zeroesHigh16BitsOfDest(SrcDef->getOpcode()))
+ auto [ChildMask, ChildReg, ChildRegIdx] = *ChildMaskAndReg;
+ MachineInstr *ParentMI = MRI->getVRegDef(ChildReg);
+
+ int64_t ParentMask;
+ auto ParentMaskAndReg = getMaskAndReg(*ParentMI);
+ if (ParentMaskAndReg) {
+ // Parent is an AND - extract its mask.
+ ParentMask = std::get<0>(*ParentMaskAndReg);
+ } else if (ST->zeroesHigh16BitsOfDest(ParentMI->getOpcode())) {
+ // Parent instruction implicitly zeros high 16 bits.
+ ParentMask = 0xffff;
+ } else {
return false;
+ }
- Register Dst = MI.getOperand(0).getReg();
- MRI->replaceRegWith(Dst, Src1);
- if (!MI.getOperand(2).isKill())
- MRI->clearKillFlags(Src1);
- MI.eraseFromParent();
+ // Check if ChildMI is not redundant.
+ if ((ParentMask & ChildMask) != ParentMask)
+ return false;
+
+ Register Dst = ChildMI.getOperand(0).getReg();
+ MRI->replaceRegWith(Dst, ChildReg);
+
+ // Clear kill flags if the register operand is not marked as kill.
+ if (!ChildMI.getOperand(ChildRegIdx).isKill())
+ MRI->clearKillFlags(ChildReg);
+
+ ChildMI.eraseFromParent();
return true;
}
@@ -2906,7 +2954,7 @@ bool SIFoldOperandsImpl::run(MachineFunction &MF, const MachineLoopInfo *MLI) {
continue;
}
- if (tryFoldZeroHighBits(MI)) {
+ if (tryFoldRedundantAnd(MI)) {
Changed = true;
continue;
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
index cb727f183556b..cc4a0c7fc0c9c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
@@ -1531,16 +1531,13 @@ define float @v_test_uitofp_i16_byte_to_f32(i16 %arg0) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_test_uitofp_i16_byte_to_f32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v1, 0xffff
-; VI-NEXT: v_and_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
; VI-NEXT: s_setpc_b64 s[30:31]
%masked = and i16 %arg0, 255
%itofp = uitofp i16 %masked to float
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
index 6844b698473c7..c84d9738152b9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
@@ -71,9 +71,8 @@ define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX8-NEXT: s_and_b32 s1, s1, 0x7f
; GFX8-NEXT: s_sub_i32 s3, 6, s2
; GFX8-NEXT: s_and_b32 s2, s2, 0x7f
-; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX8-NEXT: s_lshl_b32 s0, s0, s2
; GFX8-NEXT: s_lshr_b32 s1, s1, 1
+; GFX8-NEXT: s_lshl_b32 s0, s0, s2
; GFX8-NEXT: s_and_b32 s2, s3, 0x7f
; GFX8-NEXT: s_lshr_b32 s1, s1, s2
; GFX8-NEXT: s_or_b32 s0, s0, s1
@@ -103,10 +102,9 @@ define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX9-NEXT: s_add_i32 s4, s2, -7
; GFX9-NEXT: s_cmp_lg_u32 s3, 0
; GFX9-NEXT: s_cselect_b32 s2, s4, s2
-; GFX9-NEXT: s_and_b32 s1, s1, 0x7f
; GFX9-NEXT: s_sub_i32 s3, 6, s2
; GFX9-NEXT: s_and_b32 s2, s2, 0x7f
-; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX9-NEXT: s_and_b32 s1, s1, 0x7f
; GFX9-NEXT: s_lshl_b32 s0, s0, s2
; GFX9-NEXT: s_lshr_b32 s1, s1, 1
; GFX9-NEXT: s_and_b32 s2, s3, 0x7f
@@ -140,7 +138,6 @@ define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX10-NEXT: s_cselect_b32 s2, s4, s2
; GFX10-NEXT: s_and_b32 s1, s1, 0x7f
; GFX10-NEXT: s_sub_i32 s3, 6, s2
-; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
; GFX10-NEXT: s_and_b32 s2, s2, 0x7f
; GFX10-NEXT: s_lshr_b32 s1, s1, 1
; GFX10-NEXT: s_and_b32 s3, s3, 0x7f
@@ -181,7 +178,6 @@ define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX11-NEXT: s_cselect_b32 s2, s4, s2
; GFX11-NEXT: s_and_b32 s1, s1, 0x7f
; GFX11-NEXT: s_sub_i32 s3, 6, s2
-; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
; GFX11-NEXT: s_and_b32 s2, s2, 0x7f
; GFX11-NEXT: s_lshr_b32 s1, s1, 1
; GFX11-NEXT: s_and_b32 s3, s3, 0x7f
@@ -415,7 +411,6 @@ define amdgpu_ps i8 @s_fshl_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
; GFX8-LABEL: s_fshl_i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_and_b32 s1, s1, 0xff
-; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
; GFX8-NEXT: s_and_b32 s3, s2, 7
; GFX8-NEXT: s_lshr_b32 s1, s1, 1
; GFX8-NEXT: s_andn2_b32 s2, 7, s2
@@ -427,7 +422,6 @@ define amdgpu_ps i8 @s_fshl_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
; GFX9-LABEL: s_fshl_i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s1, s1, 0xff
-; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_and_b32 s3, s2, 7
; GFX9-NEXT: s_lshr_b32 s1, s1, 1
; GFX9-NEXT: s_andn2_b32 s2, 7, s2
@@ -440,9 +434,8 @@ define amdgpu_ps i8 @s_fshl_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s1, s1, 0xff
; GFX10-NEXT: s_and_b32 s3, s2, 7
-; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX10-NEXT: s_andn2_b32 s2, 7, s2
; GFX10-NEXT: s_lshr_b32 s1, s1, 1
+; GFX10-NEXT: s_andn2_b32 s2, 7, s2
; GFX10-NEXT: s_lshl_b32 s0, s0, s3
; GFX10-NEXT: s_lshr_b32 s1, s1, s2
; GFX10-NEXT: s_or_b32 s0, s0, s1
@@ -452,9 +445,8 @@ define amdgpu_ps i8 @s_fshl_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_and_b32 s3, s2, 7
-; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX11-NEXT: s_and_not1_b32 s2, 7, s2
; GFX11-NEXT: s_lshr_b32 s1, s1, 1
+; GFX11-NEXT: s_and_not1_b32 s2, 7, s2
; GFX11-NEXT: s_lshl_b32 s0, s0, s3
; GFX11-NEXT: s_lshr_b32 s1, s1, s2
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -561,7 +553,6 @@ define amdgpu_ps i8 @s_fshl_i8_4(i8 inreg %lhs, i8 inreg %rhs) {
; GFX8-LABEL: s_fshl_i8_4:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_and_b32 s1, s1, 0xff
-; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
; GFX8-NEXT: s_lshl_b32 s0, s0, 4
; GFX8-NEXT: s_lshr_b32 s1, s1, 4
; GFX8-NEXT: s_or_b32 s0, s0, s1
@@ -570,7 +561,6 @@ define amdgpu_ps i8 @s_fshl_i8_4(i8 inreg %lhs, i8 inreg %rhs) {
; GFX9-LABEL: s_fshl_i8_4:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s1, s1, 0xff
-; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_lshl_b32 s0, s0, 4
; GFX9-NEXT: s_lshr_b32 s1, s1, 4
; GFX9-NEXT: s_or_b32 s0, s0, s1
@@ -580,7 +570,6 @@ define amdgpu_ps i8 @s_fshl_i8_4(i8 inreg %lhs, i8 inreg %rhs) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s1, s1, 0xff
; GFX10-NEXT: s_lshl_b32 s0, s0, 4
-; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
; GFX10-NEXT: s_lshr_b32 s1, s1, 4
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
@@ -589,9 +578,8 @@ define amdgpu_ps i8 @s_fshl_i8_4(i8 inreg %lhs, i8 inreg %rhs) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_lshl_b32 s0, s0, 4
-; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_lshr_b32 s1, s1, 4
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_or_b32 s0, s0, s1
; GFX11-NEXT: ; return to shader part epilog
%result = call i8 @llvm.fshl.i8(i8 %lhs, i8 %rhs, i8 4)
@@ -668,7 +656,6 @@ define amdgpu_ps i8 @s_fshl_i8_5(i8 inreg %lhs, i8 inreg %rhs) {
; GFX8-LABEL: s_fshl_i8_5:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_and_b32 s1, s1, 0xff
-; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
; GFX8-NEXT: s_lshl_b32 s0, s0, 5
; GFX8-NEXT: s_lshr_b32 s1, s1, 3
; GFX8-NEXT: s_or_b32 s0, s0, s1
@@ -677,7 +664,6 @@ define amdgpu_ps i8 @s_fshl_i8_5(i8 inreg %lhs, i8 inreg %rhs) {
; GFX9-LABEL: s_fshl_i8_5:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s1, s1, 0xff
-; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_lshl_b32 s0, s0, 5
; GFX9-NEXT: s_lshr_b32 s1, s1, 3
; GFX9-NEXT: s_or_b32 s0, s0, s1
@@ -687,7 +673,6 @@ define amdgpu_ps i8 @s_fshl_i8_5(i8 inreg %lhs, i8 inreg %rhs) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s1, s1, 0xff
; GFX10-NEXT: s_lshl_b32 s0, s0, 5
-; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
; GFX10-NEXT: s_lshr_b32 s1, s1, 3
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
@@ -696,9 +681,8 @@ define amdgpu_ps i8 @s_fshl_i8_5(i8 inreg %lhs, i8 inreg %rhs) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_lshl_b32 s0, s0, 5
-; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_lshr_b32 s1, s1, 3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_or_b32 s0, s0, s1
; GFX11-NEXT: ; return to shader part epilog
%result = call i8 @llvm.fshl.i8(i8 %lhs, i8 %rhs, i8 5)
@@ -792,7 +776,6 @@ define amdgpu_ps i16 @s_fshl_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s4, s1, 8
; GFX8-NEXT: s_and_b32 s1, s1, 0xff
-; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
; GFX8-NEXT: s_lshr_b32 s5, s2, 8
; GFX8-NEXT: s_and_b32 s6, s2, 7
; GFX8-NEXT: s_lshr_b32 s1, s1, 1
@@ -800,10 +783,9 @@ define amdgpu_ps i16 @s_fshl_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
; GFX8-NEXT: s_lshr_b32 s3, s0, 8
; GFX8-NEXT: s_lshl_b32 s0, s0, s6
; GFX8-NEXT: s_lshr_b32 s1, s1, s2
-; GFX8-NEXT: s_and_b32 s2, s4, 0xff
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: s_and_b32 s1, s5, 7
-; GFX8-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX8-NEXT: s_and_b32 s2, s4, 0xff
; GFX8-NEXT: s_lshl_b32 s1, s3, s1
; GFX8-NEXT: s_lshr_b32 s2, s2, 1
; GFX8-NEXT: s_andn2_b32 s3, 7, s5
@@ -819,7 +801,6 @@ define amdgpu_ps i16 @s_fshl_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshr_b32 s4, s1, 8
; GFX9-NEXT: s_and_b32 s1, s1, 0xff
-; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_lshr_b32 s5, s2, 8
; GFX9-NEXT: s_and_b32 s6, s2, 7
; GFX9-NEXT: s_lshr_b32 s1, s1, 1
@@ -827,10 +808,9 @@ define amdgpu_ps i16 @s_fshl_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
; GFX9-NEXT: s_lshr_b32 s3, s0, 8
; GFX9-NEXT: s_lshl_b32 s0, s0, s6
; GFX9-NEXT: s_lshr_b32 s1, s1, s2
-; GFX9-NEXT: s_and_b32 s2, s4, 0xff
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: s_and_b32 s1, s5, 7
-; GFX9-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX9-NEXT: s_and_b32 s2, s4, 0xff
; GFX9-NEXT: s_lshl_b32 s1, s3, s1
; GFX9-NEXT: s_lshr_b32 s2, s2, 1
; GFX9-NEXT: s_andn2_b32 s3, 7, s5
@@ -846,12 +826,10 @@ define amdgpu_ps i16 @s_fshl_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s4, s1, 8
; GFX10-NEXT: s_lshr_b32 s5, s2, 8
-; GFX10-NEXT: s_and_b32 s4, s4, 0xff
-; GFX10-NEXT: s_and_b32 s1, s1, 0xff
; GFX10-NEXT: s_and_b32 s6, s2, 7
-; GFX10-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX10-NEXT: s_and_b32 s4, s4, 0xff
; GFX10-NEXT: s_lshr_b32 s3, s0, 8
-; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX10-NEXT: s_and_b32 s1, s1, 0xff
; GFX10-NEXT: s_lshl_b32 s0, s0, s6
; GFX10-NEXT: s_and_b32 s6, s5, 7
; GFX10-NEXT: s_lshr_b32 s4, s4, 1
@@ -873,12 +851,10 @@ define amdgpu_ps i16 @s_fshl_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
; GFX11: ; %bb.0:
; GFX11-NEXT: s_lshr_b32 s4, s1, 8
; GFX11-NEXT: s_lshr_b32 s5, s2, 8
-; GFX11-NEXT: s_and_b32 s4, s4, 0xff
-; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_and_b32 s6, s2, 7
-; GFX11-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX11-NEXT: s_and_b32 s4, s4, 0xff
; GFX11-NEXT: s_lshr_b32 s3, s0, 8
-; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_lshl_b32 s0, s0, s6
; GFX11-NEXT: s_and_b32 s6, s5, 7
; GFX11-NEXT: s_lshr_b32 s4, s4, 1
@@ -1134,7 +1110,6 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX8-NEXT: s_lshr_b32 s5, s0, 24
; GFX8-NEXT: s_lshl_b32 s0, s0, s11
; GFX8-NEXT: s_and_b32 s11, s1, 0xff
-; GFX8-NEXT: s_and_b32 s11, 0xffff, s11
; GFX8-NEXT: s_lshr_b32 s8, s2, 8
; GFX8-NEXT: s_lshr_b32 s9, s2, 16
; GFX8-NEXT: s_lshr_b32 s10, s2, 24
@@ -1146,7 +1121,6 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX8-NEXT: s_and_b32 s2, s8, 7
; GFX8-NEXT: s_lshl_b32 s2, s3, s2
; GFX8-NEXT: s_and_b32 s3, s6, 0xff
-; GFX8-NEXT: s_and_b32 s3, 0xffff, s3
; GFX8-NEXT: s_lshr_b32 s3, s3, 1
; GFX8-NEXT: s_andn2_b32 s6, 7, s8
; GFX8-NEXT: s_lshr_b32 s3, s3, s6
@@ -1155,7 +1129,6 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX8-NEXT: s_and_b32 s3, s9, 7
; GFX8-NEXT: s_lshl_b32 s3, s4, s3
; GFX8-NEXT: s_and_b32 s4, s7, 0xff
-; GFX8-NEXT: s_and_b32 s4, 0xffff, s4
; GFX8-NEXT: s_lshr_b32 s4, s4, 1
; GFX8-NEXT: s_andn2_b32 s6, 7, s9
; GFX8-NEXT: s_lshr_b32 s4, s4, s6
@@ -1186,7 +1159,6 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX9-NEXT: s_lshr_b32 s5, s0, 24
; GFX9-NEXT: s_lshl_b32 s0, s0, s11
; GFX9-NEXT: s_and_b32 s11, s1, 0xff
-; GFX9-NEXT: s_and_b32 s11, 0xffff, s11
; GFX9-NEXT: s_lshr_b32 s8, s2, 8
; GFX9-NEXT: s_lshr_b32 s9, s2, 16
; GFX9-NEXT: s_lshr_b32 s10, s2, 24
@@ -1198,7 +1170,6 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX9-NEXT: s_and_b32 s2, s8, 7
; GFX9-NEXT: s_lshl_b32 s2, s3, s2
; GFX9-NEXT: s_and_b32 s3, s6, 0xff
-; GFX9-NEXT: s_and_b32 s3, 0xffff, s3
; GFX9-NEXT: s_lshr_b32 s3, s3, 1
; GFX9-NEXT: s_andn2_b32 s6, 7, s8
; GFX9-NEXT: s_lshr_b32 s3, s3, s6
@@ -1207,7 +1178,6 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX9-NEXT: s_and_b32 s3, s9, 7
; GFX9-NEXT: s_lshl_b32 s3, s4, s3
; GFX9-NEXT: s_and_b32 s4, s7, 0xff
-; GFX9-NEXT: s_and_b32 s4, 0xffff, s4
; GFX9-NEXT: s_lshr_b32 s4, s4, 1
; GFX9-NEXT: s_andn2_b32 s6, 7, s9
; GFX9-NEXT: s_lshr_b32 s4, s4, s6
@@ -1232,40 +1202,37 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
;
; GFX10-LABEL: s_fshl_v4i8:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_and_b32 s10, s1, 0xff
; GFX10-NEXT: s_lshr_b32 s6, s1, 8
-; GFX10-NEXT: s_and_b32 s10, 0xffff, s10
+; GFX10-NEXT: s_and_b32 s11, s1, 0xff
; GFX10-NEXT: s_lshr_b32 s8, s2, 8
; GFX10-NEXT: s_lshr_b32 s9, s2, 16
-; GFX10-NEXT: s_lshr_b32 s11, s2, 24
+; GFX10-NEXT: s_lshr_b32 s10, s2, 24
; GFX10-NEXT: s_and_b32 s12, s2, 7
-; GFX10-NEXT: s_lshr_b32 s10, s10, 1
+; GFX10-NEXT: s_lshr_b32 s11, s11, 1
; GFX10-NEXT: s_andn2_b32 s2, 7, s2
+; GFX10-NEXT: s_and_b32 s6, s6, 0xff
; GFX10-NEXT: s_lshr_b32 s3, s0, 8
+; GFX10-NEXT: s_lshr_b32 s2, s11, s2
+; GFX10-NEXT: s_and_b32 s11, s8, 7
+; GFX10-NEXT: s_lshr_b32 s6, s6, 1
+; GFX10-NEXT: s_andn2_b32 s8, 7, s8
; GFX10-NEXT: s_lshr_b32 s4, s0, 16
; GFX10-NEXT: s_lshr_b32 s5, s0, 24
+; GFX10-NEXT: s_lshr_b32 s7, s1, 16
; GFX10-NEXT: s_lshl_b32 s0, s0, s12
-; GFX10-NEXT: s_lshr_b32 s2, s10, s2
-; GFX10-NEXT: s_and_b32 s6, s6, 0xff
+; GFX10-NEXT: s_lshl_b32 s3, s3, s11
+; GFX10-NEXT: s_lshr_b32 s6, s6, s8
; GFX10-NEXT: s_or_b32 s0, s0, s2
-; GFX10-NEXT: s_and_b32 s2, 0xffff, s6
-; GFX10-NEXT: s_lshr_b32 s7, s1, 16
-; GFX10-NEXT: s_and_b32 s6, s8, 7
-; GFX10-NEXT: s_lshr_b32 s2, s2, 1
-; GFX10-NEXT: s_andn2_b32 s8, 7, s8
-; GFX10-NEXT: s_lshl_b32 s3, s3, s6
-; GFX10-NEXT: s_lshr_b32 s2, s2, s8
-; GFX10-NEXT: s_and_b32 s6, s7, 0xff
-; GFX10-NEXT: s_or_b32 s2, s3, s2
-; GFX10-NEXT: s_and_b32 s3, 0xffff, s6
+; GFX10-NEXT: s_or_b32 s2, s3, s6
+; GFX10-NEXT: s_and_b32 s3, s7, 0xff
; GFX10-NEXT: s_and_b32 s6, s9, 7
; GFX10-NEXT: s_lshr_b32 s3, s3, 1
; GFX10-NEXT: s_andn2_b32 s7, 7, s9
; GFX10-NEXT: s_lshl_b32 s4, s4, s6
; GFX10-NEXT: s_lshr_b32 s3, s3, s7
-; GFX10-NEXT: s_and_b32 s6, s11, 7
+; GFX10-NEXT: s_and_b32 s6, s10, 7
; GFX10-NEXT: s_lshr_b32 s1, s1, 25
-; GFX10-NEXT: s_andn2_b32 s7, 7, s11
+; GFX10-NEXT: s_andn2_b32 s7, 7, s10
; GFX10-NEXT: s_lshl_b32 s5, s5, s6
; GFX10-NEXT: s_lshr_b32 s1, s1, s7
; GFX10-NEXT: s_or_b32 s3, s4, s3
@@ -1284,40 +1251,37 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
;
; GFX11-LABEL: s_fshl_v4i8:
; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s10, s1, 0xff
; GFX11-NEXT: s_lshr_b32 s6, s1, 8
-; GFX11-NEXT: s_and_b32 s10, 0xffff, s10
+; GFX11-NEXT: s_and_b32 s11, s1, 0xff
; GFX11-NEXT: s_lshr_b32 s8, s2, 8
; GFX11-NEXT: s_lshr_b32 s9, s2, 16
-; GFX11-NEXT: s_lshr_b32 s11, s2, 24
+; GFX11-NEXT: s_lshr_b32 s10, s2, 24
; GFX11-NEXT: s_and_b32 s12, s2, 7
-; GFX11-NEXT: s_lshr_b32 s10, s10, 1
+; GFX11-NEXT: s_lshr_b32 s11, s11, 1
; GFX11-NEXT: s_and_not1_b32 s2, 7, s2
+; GFX11-NEXT: s_and_b32 s6, s6, 0xff
; GFX11-NEXT: s_lshr_b32 s3, s0, 8
+; GFX11-NEXT: s_lshr_b32 s2, s11, s2
+; GFX11-NEXT: s_and_b32 s11, s8, 7
+; GFX11-NEXT: s_lshr_b32 s6, s6, 1
+; GFX11-NEXT: s_and_not1_b32 s8, 7, s8
; GFX11-NEXT: s_lshr_b32 s4, s0, 16
; GFX11-NEXT: s_lshr_b32 s5, s0, 24
+; GFX11-NEXT: s_lshr_b32 s7, s1, 16
; GFX11-NEXT: s_lshl_b32 s0, s0, s12
-; GFX11-NEXT: s_lshr_b32 s2, s10, s2
-; GFX11-NEXT: s_and_b32 s6, s6, 0xff
+; GFX11-NEXT: s_lshl_b32 s3, s3, s11
+; GFX11-NEXT: s_lshr_b32 s6, s6, s8
; GFX11-NEXT: s_or_b32 s0, s0, s2
-; GFX11-NEXT: s_and_b32 s2, 0xffff, s6
-; GFX11-NEXT: s_lshr_b32 s7, s1, 16
-; GFX11-NEXT: s_and_b32 s6, s8, 7
-; GFX11-NEXT: s_lshr_b32 s2, s2, 1
-; GFX11-NEXT: s_and_not1_b32 s8, 7, s8
-; GFX11-NEXT: s_lshl_b32 s3, s3, s6
-; GFX11-NEXT: s_lshr_b32 s2, s2, s8
-; GFX11-NEXT: s_and_b32 s6, s7, 0xff
-; GFX11-NEXT: s_or_b32 s2, s3, s2
-; GFX11-NEXT: s_and_b32 s3, 0xffff, s6
+; GFX11-NEXT: s_or_b32 s2, s3, s6
+; GFX11-NEXT: s_and_b32 s3, s7, 0xff
; GFX11-NEXT: s_and_b32 s6, s9, 7
; GFX11-NEXT: s_lshr_b32 s3, s3, 1
; GFX11-NEXT: s_and_not1_b32 s7, 7, s9
; GFX11-NEXT: s_lshl_b32 s4, s4, s6
; GFX11-NEXT: s_lshr_b32 s3, s3, s7
-; GFX11-NEXT: s_and_b32 s6, s11, 7
+; GFX11-NEXT: s_and_b32 s6, s10, 7
; GFX11-NEXT: s_lshr_b32 s1, s1, 25
-; GFX11-NEXT: s_and_not1_b32 s7, 7, s11
+; GFX11-NEXT: s_and_not1_b32 s7, 7, s10
; GFX11-NEXT: s_lshl_b32 s5, s5, s6
; GFX11-NEXT: s_lshr_b32 s1, s1, s7
; GFX11-NEXT: s_or_b32 s3, s4, s3
@@ -1997,20 +1961,18 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 inreg %amt.arg) {
; GFX6-LABEL: s_fshl_v2i24:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_lshr_b32 s6, s0, 16
; GFX6-NEXT: s_lshr_b32 s7, s1, 8
; GFX6-NEXT: s_bfe_u32 s9, s0, 0x80008
; GFX6-NEXT: s_and_b32 s1, s1, 0xff
; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: s_lshr_b32 s6, s0, 16
; GFX6-NEXT: s_and_b32 s8, s0, 0xff
; GFX6-NEXT: s_lshl_b32 s9, s9, 8
-; GFX6-NEXT: s_and_b32 s6, s6, 0xff
; GFX6-NEXT: v_alignbit_b32 v0, s1, v0, 24
-; GFX6-NEXT: s_and_b32 s1, s7, 0xff
; GFX6-NEXT: s_or_b32 s8, s8, s9
-; GFX6-NEXT: s_and_b32 s6, 0xffff, s6
+; GFX6-NEXT: s_and_b32 s6, s6, 0xff
; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX6-NEXT: s_and_b32 s1, s7, 0xff
; GFX6-NEXT: s_lshr_b32 s7, s3, 8
; GFX6-NEXT: s_and_b32 s3, s3, 0xff
; GFX6-NEXT: v_mov_b32_e32 v0, s2
@@ -2026,45 +1988,41 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: v_readfirstlane_b32 s2, v0
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT: s_and_b32 s3, s7, 0xff
; GFX6-NEXT: s_lshl_b32 s9, s9, 8
+; GFX6-NEXT: s_or_b32 s8, s8, s9
; GFX6-NEXT: s_and_b32 s1, s1, 0xff
-; GFX6-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX6-NEXT: s_and_b32 s3, s7, 0xff
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX6-NEXT: s_or_b32 s8, s8, s9
-; GFX6-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX6-NEXT: s_lshl_b32 s3, s3, 16
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: s_and_b32 s8, 0xffff, s8
; GFX6-NEXT: s_lshl_b32 s1, s1, 16
-; GFX6-NEXT: s_or_b32 s2, s2, s3
-; GFX6-NEXT: s_lshr_b32 s3, s4, 16
+; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_bfe_u32 s9, s4, 0x80008
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: s_or_b32 s1, s8, s1
+; GFX6-NEXT: s_or_b32 s2, s2, s3
+; GFX6-NEXT: s_lshr_b32 s3, s4, 16
; GFX6-NEXT: s_and_b32 s8, s4, 0xff
; GFX6-NEXT: s_lshl_b32 s9, s9, 8
-; GFX6-NEXT: s_and_b32 s3, s3, 0xff
; GFX6-NEXT: s_or_b32 s8, s8, s9
-; GFX6-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX6-NEXT: s_and_b32 s3, s3, 0xff
; GFX6-NEXT: s_and_b32 s8, 0xffff, s8
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
-; GFX6-NEXT: v_mov_b32_e32 v1, s4
-; GFX6-NEXT: v_readfirstlane_b32 s4, v0
; GFX6-NEXT: s_or_b32 s3, s8, s3
-; GFX6-NEXT: s_mul_i32 s8, s4, 0xffffffe8
-; GFX6-NEXT: v_mul_hi_u32 v0, v0, s8
+; GFX6-NEXT: v_readfirstlane_b32 s8, v0
+; GFX6-NEXT: s_mul_i32 s9, s8, 0xffffffe8
+; GFX6-NEXT: v_mul_hi_u32 v0, v0, s9
; GFX6-NEXT: s_lshr_b32 s7, s5, 8
; GFX6-NEXT: s_and_b32 s5, s5, 0xff
-; GFX6-NEXT: s_and_b32 s7, s7, 0xff
-; GFX6-NEXT: v_readfirstlane_b32 s8, v0
-; GFX6-NEXT: s_add_i32 s4, s4, s8
-; GFX6-NEXT: v_mov_b32_e32 v0, s4
-; GFX6-NEXT: v_mul_hi_u32 v0, s3, v0
+; GFX6-NEXT: v_mov_b32_e32 v1, s4
; GFX6-NEXT: v_alignbit_b32 v1, s5, v1, 24
-; GFX6-NEXT: s_and_b32 s7, 0xffff, s7
-; GFX6-NEXT: v_readfirstlane_b32 s5, v1
+; GFX6-NEXT: v_readfirstlane_b32 s5, v0
+; GFX6-NEXT: s_add_i32 s5, s8, s5
+; GFX6-NEXT: v_mov_b32_e32 v0, s5
+; GFX6-NEXT: v_mul_hi_u32 v0, s3, v0
+; GFX6-NEXT: s_and_b32 s7, s7, 0xff
+; GFX6-NEXT: v_readfirstlane_b32 s4, v1
; GFX6-NEXT: s_lshl_b32 s7, s7, 16
-; GFX6-NEXT: s_or_b32 s5, s5, s7
+; GFX6-NEXT: s_or_b32 s4, s4, s7
; GFX6-NEXT: v_readfirstlane_b32 s7, v0
; GFX6-NEXT: s_mulk_i32 s7, 0xffe8
; GFX6-NEXT: s_add_i32 s3, s3, s7
@@ -2076,9 +2034,9 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_cmp_ge_u32 s3, 24
; GFX6-NEXT: s_cselect_b32 s7, 1, 0
; GFX6-NEXT: s_sub_i32 s8, s3, 24
-; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mov_b32_e32 v0, s5
; GFX6-NEXT: s_cmp_lg_u32 s7, 0
-; GFX6-NEXT: v_mul_hi_u32 v0, s5, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX6-NEXT: s_cselect_b32 s3, s8, s3
; GFX6-NEXT: s_sub_i32 s7, 23, s3
; GFX6-NEXT: s_lshr_b32 s1, s1, 1
@@ -2087,12 +2045,12 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_or_b32 s3, s3, s1
; GFX6-NEXT: v_readfirstlane_b32 s1, v0
; GFX6-NEXT: s_mulk_i32 s1, 0xffe8
-; GFX6-NEXT: s_add_i32 s5, s5, s1
-; GFX6-NEXT: s_cmp_ge_u32 s5, 24
+; GFX6-NEXT: s_add_i32 s4, s4, s1
+; GFX6-NEXT: s_cmp_ge_u32 s4, 24
; GFX6-NEXT: s_cselect_b32 s1, 1, 0
-; GFX6-NEXT: s_sub_i32 s4, s5, 24
+; GFX6-NEXT: s_sub_i32 s5, s4, 24
; GFX6-NEXT: s_cmp_lg_u32 s1, 0
-; GFX6-NEXT: s_cselect_b32 s1, s4, s5
+; GFX6-NEXT: s_cselect_b32 s1, s5, s4
; GFX6-NEXT: s_cmp_ge_u32 s1, 24
; GFX6-NEXT: s_cselect_b32 s4, 1, 0
; GFX6-NEXT: s_sub_i32 s5, s1, 24
@@ -2127,18 +2085,16 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX8-NEXT: s_lshr_b32 s8, s0, 24
; GFX8-NEXT: s_and_b32 s0, s0, 0xff
; GFX8-NEXT: s_lshl_b32 s6, s6, 8
+; GFX8-NEXT: s_lshr_b32 s9, s1, 8
; GFX8-NEXT: s_or_b32 s0, s0, s6
; GFX8-NEXT: s_and_b32 s6, s7, 0xff
-; GFX8-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX8-NEXT: s_lshr_b32 s9, s1, 8
+; GFX8-NEXT: s_and_b32 s1, s1, 0xff
; GFX8-NEXT: s_and_b32 s0, 0xffff, s0
; GFX8-NEXT: s_lshl_b32 s6, s6, 16
-; GFX8-NEXT: s_and_b32 s1, s1, 0xff
-; GFX8-NEXT: s_or_b32 s0, s0, s6
; GFX8-NEXT: s_lshl_b32 s1, s1, 8
-; GFX8-NEXT: s_and_b32 s6, s9, 0xff
+; GFX8-NEXT: s_or_b32 s0, s0, s6
; GFX8-NEXT: s_or_b32 s1, s8, s1
-; GFX8-NEXT: s_and_b32 s6, 0xffff, s6
+; GFX8-NEXT: s_and_b32 s6, s9, 0xff
; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
; GFX8-NEXT: s_lshl_b32 s6, s6, 16
; GFX8-NEXT: s_or_b32 s1, s1, s6
@@ -2148,34 +2104,31 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX8-NEXT: s_lshr_b32 s8, s2, 24
; GFX8-NEXT: s_and_b32 s2, s2, 0xff
; GFX8-NEXT: s_lshl_b32 s6, s6, 8
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX8-NEXT: s_lshr_b32 s9, s3, 8
; GFX8-NEXT: s_or_b32 s2, s2, s6
; GFX8-NEXT: s_and_b32 s6, s7, 0xff
-; GFX8-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX8-NEXT: s_lshr_b32 s9, s3, 8
+; GFX8-NEXT: s_and_b32 s3, s3, 0xff
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_and_b32 s2, 0xffff, s2
; GFX8-NEXT: s_lshl_b32 s6, s6, 16
-; GFX8-NEXT: s_and_b32 s3, s3, 0xff
-; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
-; GFX8-NEXT: s_or_b32 s2, s2, s6
; GFX8-NEXT: s_lshl_b32 s3, s3, 8
-; GFX8-NEXT: s_and_b32 s6, s9, 0xff
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX8-NEXT: s_or_b32 s2, s2, s6
; GFX8-NEXT: s_or_b32 s3, s8, s3
-; GFX8-NEXT: s_and_b32 s6, 0xffff, s6
+; GFX8-NEXT: s_and_b32 s6, s9, 0xff
; GFX8-NEXT: s_and_b32 s3, 0xffff, s3
; GFX8-NEXT: s_lshl_b32 s6, s6, 16
; GFX8-NEXT: s_or_b32 s3, s3, s6
; GFX8-NEXT: s_lshr_b32 s6, s4, 8
-; GFX8-NEXT: s_and_b32 s6, s6, 0xff
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX8-NEXT: s_and_b32 s6, s6, 0xff
+; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: s_lshr_b32 s7, s4, 16
; GFX8-NEXT: s_lshr_b32 s8, s4, 24
; GFX8-NEXT: s_and_b32 s4, s4, 0xff
; GFX8-NEXT: s_lshl_b32 s6, s6, 8
-; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: s_or_b32 s4, s4, s6
; GFX8-NEXT: s_and_b32 s6, s7, 0xff
-; GFX8-NEXT: s_and_b32 s6, 0xffff, s6
; GFX8-NEXT: s_and_b32 s4, 0xffff, s4
; GFX8-NEXT: s_lshl_b32 s6, s6, 16
; GFX8-NEXT: s_or_b32 s4, s4, s6
@@ -2191,7 +2144,6 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX8-NEXT: s_and_b32 s7, s9, 0xff
-; GFX8-NEXT: s_and_b32 s7, 0xffff, s7
; GFX8-NEXT: s_and_b32 s5, 0xffff, s5
; GFX8-NEXT: s_lshl_b32 s7, s7, 16
; GFX8-NEXT: s_or_b32 s5, s5, s7
@@ -2257,18 +2209,16 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_lshr_b32 s8, s0, 24
; GFX9-NEXT: s_and_b32 s0, s0, 0xff
; GFX9-NEXT: s_lshl_b32 s6, s6, 8
+; GFX9-NEXT: s_lshr_b32 s9, s1, 8
; GFX9-NEXT: s_or_b32 s0, s0, s6
; GFX9-NEXT: s_and_b32 s6, s7, 0xff
-; GFX9-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX9-NEXT: s_lshr_b32 s9, s1, 8
+; GFX9-NEXT: s_and_b32 s1, s1, 0xff
; GFX9-NEXT: s_and_b32 s0, 0xffff, s0
; GFX9-NEXT: s_lshl_b32 s6, s6, 16
-; GFX9-NEXT: s_and_b32 s1, s1, 0xff
-; GFX9-NEXT: s_or_b32 s0, s0, s6
; GFX9-NEXT: s_lshl_b32 s1, s1, 8
-; GFX9-NEXT: s_and_b32 s6, s9, 0xff
+; GFX9-NEXT: s_or_b32 s0, s0, s6
; GFX9-NEXT: s_or_b32 s1, s8, s1
-; GFX9-NEXT: s_and_b32 s6, 0xffff, s6
+; GFX9-NEXT: s_and_b32 s6, s9, 0xff
; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_lshl_b32 s6, s6, 16
; GFX9-NEXT: s_or_b32 s1, s1, s6
@@ -2278,43 +2228,39 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_lshr_b32 s8, s2, 24
; GFX9-NEXT: s_and_b32 s2, s2, 0xff
; GFX9-NEXT: s_lshl_b32 s6, s6, 8
+; GFX9-NEXT: s_lshr_b32 s9, s3, 8
; GFX9-NEXT: s_or_b32 s2, s2, s6
; GFX9-NEXT: s_and_b32 s6, s7, 0xff
-; GFX9-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX9-NEXT: s_lshr_b32 s9, s3, 8
+; GFX9-NEXT: s_and_b32 s3, s3, 0xff
; GFX9-NEXT: s_and_b32 s2, 0xffff, s2
; GFX9-NEXT: s_lshl_b32 s6, s6, 16
-; GFX9-NEXT: s_and_b32 s3, s3, 0xff
-; GFX9-NEXT: s_or_b32 s2, s2, s6
; GFX9-NEXT: s_lshl_b32 s3, s3, 8
-; GFX9-NEXT: s_and_b32 s6, s9, 0xff
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX9-NEXT: s_or_b32 s2, s2, s6
; GFX9-NEXT: s_or_b32 s3, s8, s3
-; GFX9-NEXT: s_and_b32 s6, 0xffff, s6
+; GFX9-NEXT: s_and_b32 s6, s9, 0xff
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_and_b32 s3, 0xffff, s3
; GFX9-NEXT: s_lshl_b32 s6, s6, 16
-; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX9-NEXT: s_or_b32 s3, s3, s6
; GFX9-NEXT: s_lshr_b32 s6, s4, 8
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_and_b32 s6, s6, 0xff
; GFX9-NEXT: s_lshr_b32 s7, s4, 16
; GFX9-NEXT: s_lshr_b32 s8, s4, 24
; GFX9-NEXT: s_and_b32 s4, s4, 0xff
; GFX9-NEXT: s_lshl_b32 s6, s6, 8
-; GFX9-NEXT: s_or_b32 s4, s4, s6
-; GFX9-NEXT: s_and_b32 s6, s7, 0xff
-; GFX9-NEXT: s_and_b32 s6, 0xffff, s6
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: s_lshr_b32 s9, s5, 8
-; GFX9-NEXT: s_and_b32 s4, 0xffff, s4
-; GFX9-NEXT: s_lshl_b32 s6, s6, 16
+; GFX9-NEXT: s_or_b32 s4, s4, s6
+; GFX9-NEXT: s_and_b32 s6, s7, 0xff
; GFX9-NEXT: s_and_b32 s5, s5, 0xff
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: s_or_b32 s4, s4, s6
+; GFX9-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX9-NEXT: s_lshl_b32 s6, s6, 16
; GFX9-NEXT: s_lshl_b32 s5, s5, 8
-; GFX9-NEXT: s_and_b32 s6, s9, 0xff
+; GFX9-NEXT: s_or_b32 s4, s4, s6
; GFX9-NEXT: s_or_b32 s5, s8, s5
-; GFX9-NEXT: s_and_b32 s6, 0xffff, s6
+; GFX9-NEXT: s_and_b32 s6, s9, 0xff
; GFX9-NEXT: s_and_b32 s5, 0xffff, s5
; GFX9-NEXT: s_lshl_b32 s6, s6, 16
; GFX9-NEXT: s_or_b32 s5, s5, s6
@@ -2377,24 +2323,22 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX10-LABEL: s_fshl_v2i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s6, s0, 8
-; GFX10-NEXT: s_lshr_b32 s7, s0, 16
+; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX10-NEXT: s_and_b32 s6, s6, 0xff
+; GFX10-NEXT: s_lshr_b32 s7, s0, 16
; GFX10-NEXT: s_lshr_b32 s8, s0, 24
; GFX10-NEXT: s_and_b32 s0, s0, 0xff
; GFX10-NEXT: s_lshl_b32 s6, s6, 8
-; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX10-NEXT: s_lshr_b32 s9, s1, 8
; GFX10-NEXT: s_or_b32 s0, s0, s6
; GFX10-NEXT: s_and_b32 s6, s7, 0xff
-; GFX10-NEXT: s_lshr_b32 s9, s1, 8
-; GFX10-NEXT: s_and_b32 s6, 0xffff, s6
; GFX10-NEXT: s_and_b32 s1, s1, 0xff
+; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: s_and_b32 s0, 0xffff, s0
-; GFX10-NEXT: s_lshl_b32 s6, s6, 16
; GFX10-NEXT: s_lshl_b32 s1, s1, 8
-; GFX10-NEXT: s_and_b32 s7, s9, 0xff
-; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX10-NEXT: s_lshl_b32 s6, s6, 16
; GFX10-NEXT: s_or_b32 s1, s8, s1
-; GFX10-NEXT: s_and_b32 s7, 0xffff, s7
+; GFX10-NEXT: s_and_b32 s7, s9, 0xff
; GFX10-NEXT: s_or_b32 s0, s0, s6
; GFX10-NEXT: s_lshr_b32 s6, s2, 8
; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
@@ -2405,74 +2349,70 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX10-NEXT: s_lshr_b32 s8, s2, 24
; GFX10-NEXT: s_and_b32 s2, s2, 0xff
; GFX10-NEXT: s_lshl_b32 s6, s6, 8
-; GFX10-NEXT: s_lshr_b32 s9, s3, 8
+; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: s_or_b32 s2, s2, s6
; GFX10-NEXT: s_and_b32 s6, s7, 0xff
+; GFX10-NEXT: s_lshr_b32 s9, s3, 8
; GFX10-NEXT: s_and_b32 s3, s3, 0xff
-; GFX10-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: s_and_b32 s2, 0xffff, s2
; GFX10-NEXT: s_lshl_b32 s6, s6, 16
; GFX10-NEXT: s_lshl_b32 s3, s3, 8
-; GFX10-NEXT: s_and_b32 s7, s9, 0xff
-; GFX10-NEXT: s_or_b32 s3, s8, s3
-; GFX10-NEXT: s_and_b32 s7, 0xffff, s7
; GFX10-NEXT: s_or_b32 s2, s2, s6
; GFX10-NEXT: s_lshr_b32 s6, s4, 8
+; GFX10-NEXT: s_or_b32 s3, s8, s3
+; GFX10-NEXT: s_and_b32 s7, s9, 0xff
+; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX10-NEXT: s_and_b32 s6, s6, 0xff
; GFX10-NEXT: s_and_b32 s3, 0xffff, s3
; GFX10-NEXT: s_lshl_b32 s7, s7, 16
-; GFX10-NEXT: s_and_b32 s6, s6, 0xff
-; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX10-NEXT: s_and_b32 s8, s4, 0xff
+; GFX10-NEXT: s_lshl_b32 s6, s6, 8
; GFX10-NEXT: s_or_b32 s3, s3, s7
; GFX10-NEXT: s_lshr_b32 s7, s4, 16
-; GFX10-NEXT: s_lshr_b32 s8, s4, 24
-; GFX10-NEXT: s_and_b32 s4, s4, 0xff
-; GFX10-NEXT: s_lshl_b32 s6, s6, 8
-; GFX10-NEXT: s_lshr_b32 s9, s5, 8
-; GFX10-NEXT: s_or_b32 s4, s4, s6
-; GFX10-NEXT: s_and_b32 s6, s7, 0xff
-; GFX10-NEXT: v_readfirstlane_b32 s7, v0
+; GFX10-NEXT: s_or_b32 s6, s8, s6
+; GFX10-NEXT: v_readfirstlane_b32 s8, v0
+; GFX10-NEXT: s_and_b32 s7, s7, 0xff
; GFX10-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX10-NEXT: s_and_b32 s4, 0xffff, s4
-; GFX10-NEXT: s_lshl_b32 s6, s6, 16
+; GFX10-NEXT: s_lshl_b32 s7, s7, 16
+; GFX10-NEXT: s_lshr_b32 s9, s5, 8
+; GFX10-NEXT: s_or_b32 s6, s6, s7
+; GFX10-NEXT: s_mul_i32 s7, s8, 0xffffffe8
; GFX10-NEXT: s_and_b32 s5, s5, 0xff
-; GFX10-NEXT: s_or_b32 s4, s4, s6
-; GFX10-NEXT: s_mul_i32 s6, s7, 0xffffffe8
+; GFX10-NEXT: s_mul_hi_u32 s7, s8, s7
+; GFX10-NEXT: s_lshr_b32 s4, s4, 24
+; GFX10-NEXT: s_add_i32 s8, s8, s7
; GFX10-NEXT: s_lshl_b32 s5, s5, 8
-; GFX10-NEXT: s_mul_hi_u32 s6, s7, s6
-; GFX10-NEXT: s_or_b32 s5, s8, s5
-; GFX10-NEXT: s_add_i32 s7, s7, s6
-; GFX10-NEXT: s_and_b32 s8, s9, 0xff
-; GFX10-NEXT: s_mul_hi_u32 s6, s4, s7
-; GFX10-NEXT: s_and_b32 s8, 0xffff, s8
-; GFX10-NEXT: s_mulk_i32 s6, 0xffe8
-; GFX10-NEXT: s_and_b32 s5, 0xffff, s5
-; GFX10-NEXT: s_lshl_b32 s8, s8, 16
-; GFX10-NEXT: s_add_i32 s4, s4, s6
-; GFX10-NEXT: s_or_b32 s5, s5, s8
-; GFX10-NEXT: s_cmp_ge_u32 s4, 24
-; GFX10-NEXT: s_cselect_b32 s6, 1, 0
-; GFX10-NEXT: s_sub_i32 s8, s4, 24
-; GFX10-NEXT: s_cmp_lg_u32 s6, 0
-; GFX10-NEXT: s_cselect_b32 s4, s8, s4
-; GFX10-NEXT: s_cmp_ge_u32 s4, 24
+; GFX10-NEXT: s_mul_hi_u32 s7, s6, s8
+; GFX10-NEXT: s_or_b32 s4, s4, s5
+; GFX10-NEXT: s_and_b32 s5, s9, 0xff
+; GFX10-NEXT: s_mulk_i32 s7, 0xffe8
+; GFX10-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX10-NEXT: s_lshl_b32 s5, s5, 16
+; GFX10-NEXT: s_add_i32 s6, s6, s7
+; GFX10-NEXT: s_or_b32 s4, s4, s5
+; GFX10-NEXT: s_cmp_ge_u32 s6, 24
+; GFX10-NEXT: s_cselect_b32 s5, 1, 0
+; GFX10-NEXT: s_sub_i32 s7, s6, 24
+; GFX10-NEXT: s_cmp_lg_u32 s5, 0
+; GFX10-NEXT: s_cselect_b32 s5, s7, s6
+; GFX10-NEXT: s_cmp_ge_u32 s5, 24
; GFX10-NEXT: s_cselect_b32 s6, 1, 0
-; GFX10-NEXT: s_sub_i32 s8, s4, 24
+; GFX10-NEXT: s_sub_i32 s7, s5, 24
; GFX10-NEXT: s_cmp_lg_u32 s6, 0
-; GFX10-NEXT: s_cselect_b32 s4, s8, s4
+; GFX10-NEXT: s_cselect_b32 s5, s7, s5
; GFX10-NEXT: s_lshr_b32 s2, s2, 1
-; GFX10-NEXT: s_sub_i32 s6, 23, s4
-; GFX10-NEXT: s_lshl_b32 s0, s0, s4
-; GFX10-NEXT: s_mul_hi_u32 s4, s5, s7
+; GFX10-NEXT: s_sub_i32 s6, 23, s5
+; GFX10-NEXT: s_lshl_b32 s0, s0, s5
+; GFX10-NEXT: s_mul_hi_u32 s5, s4, s8
; GFX10-NEXT: s_lshr_b32 s2, s2, s6
-; GFX10-NEXT: s_mulk_i32 s4, 0xffe8
+; GFX10-NEXT: s_mulk_i32 s5, 0xffe8
; GFX10-NEXT: s_or_b32 s0, s0, s2
-; GFX10-NEXT: s_add_i32 s5, s5, s4
-; GFX10-NEXT: s_cmp_ge_u32 s5, 24
+; GFX10-NEXT: s_add_i32 s4, s4, s5
+; GFX10-NEXT: s_cmp_ge_u32 s4, 24
; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_sub_i32 s4, s5, 24
+; GFX10-NEXT: s_sub_i32 s5, s4, 24
; GFX10-NEXT: s_cmp_lg_u32 s2, 0
-; GFX10-NEXT: s_cselect_b32 s2, s4, s5
+; GFX10-NEXT: s_cselect_b32 s2, s5, s4
; GFX10-NEXT: s_cmp_ge_u32 s2, 24
; GFX10-NEXT: s_cselect_b32 s4, 1, 0
; GFX10-NEXT: s_sub_i32 s5, s2, 24
@@ -2611,24 +2551,22 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX11-FAKE16-LABEL: s_fshl_v2i24:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_lshr_b32 s6, s0, 8
-; GFX11-FAKE16-NEXT: s_lshr_b32 s7, s0, 16
+; GFX11-FAKE16-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX11-FAKE16-NEXT: s_and_b32 s6, s6, 0xff
+; GFX11-FAKE16-NEXT: s_lshr_b32 s7, s0, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s8, s0, 24
; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s6, 8
-; GFX11-FAKE16-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX11-FAKE16-NEXT: s_lshr_b32 s9, s1, 8
; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s6
; GFX11-FAKE16-NEXT: s_and_b32 s6, s7, 0xff
-; GFX11-FAKE16-NEXT: s_lshr_b32 s9, s1, 8
-; GFX11-FAKE16-NEXT: s_and_b32 s6, 0xffff, s6
; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, 0xff
+; GFX11-FAKE16-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: s_and_b32 s0, 0xffff, s0
-; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s6, 16
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 8
-; GFX11-FAKE16-NEXT: s_and_b32 s7, s9, 0xff
-; GFX11-FAKE16-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s6, 16
; GFX11-FAKE16-NEXT: s_or_b32 s1, s8, s1
-; GFX11-FAKE16-NEXT: s_and_b32 s7, 0xffff, s7
+; GFX11-FAKE16-NEXT: s_and_b32 s7, s9, 0xff
; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s6
; GFX11-FAKE16-NEXT: s_lshr_b32 s6, s2, 8
; GFX11-FAKE16-NEXT: s_and_b32 s1, 0xffff, s1
@@ -2639,77 +2577,73 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX11-FAKE16-NEXT: s_lshr_b32 s8, s2, 24
; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s6, 8
-; GFX11-FAKE16-NEXT: s_lshr_b32 s9, s3, 8
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-FAKE16-NEXT: s_or_b32 s2, s2, s6
; GFX11-FAKE16-NEXT: s_and_b32 s6, s7, 0xff
+; GFX11-FAKE16-NEXT: s_lshr_b32 s9, s3, 8
; GFX11-FAKE16-NEXT: s_and_b32 s3, s3, 0xff
-; GFX11-FAKE16-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-FAKE16-NEXT: s_and_b32 s2, 0xffff, s2
; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s6, 16
; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 8
-; GFX11-FAKE16-NEXT: s_and_b32 s7, s9, 0xff
-; GFX11-FAKE16-NEXT: s_or_b32 s3, s8, s3
-; GFX11-FAKE16-NEXT: s_and_b32 s7, 0xffff, s7
; GFX11-FAKE16-NEXT: s_or_b32 s2, s2, s6
; GFX11-FAKE16-NEXT: s_lshr_b32 s6, s4, 8
+; GFX11-FAKE16-NEXT: s_or_b32 s3, s8, s3
+; GFX11-FAKE16-NEXT: s_and_b32 s7, s9, 0xff
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_and_b32 s6, s6, 0xff
; GFX11-FAKE16-NEXT: s_and_b32 s3, 0xffff, s3
; GFX11-FAKE16-NEXT: s_lshl_b32 s7, s7, 16
-; GFX11-FAKE16-NEXT: s_and_b32 s6, s6, 0xff
-; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_and_b32 s8, s4, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s6, 8
; GFX11-FAKE16-NEXT: s_or_b32 s3, s3, s7
; GFX11-FAKE16-NEXT: s_lshr_b32 s7, s4, 16
-; GFX11-FAKE16-NEXT: s_lshr_b32 s8, s4, 24
-; GFX11-FAKE16-NEXT: s_and_b32 s4, s4, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s6, 8
-; GFX11-FAKE16-NEXT: s_lshr_b32 s9, s5, 8
-; GFX11-FAKE16-NEXT: s_or_b32 s4, s4, s6
-; GFX11-FAKE16-NEXT: s_and_b32 s6, s7, 0xff
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v0
+; GFX11-FAKE16-NEXT: s_or_b32 s6, s8, s6
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v0
+; GFX11-FAKE16-NEXT: s_and_b32 s7, s7, 0xff
; GFX11-FAKE16-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX11-FAKE16-NEXT: s_and_b32 s4, 0xffff, s4
-; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s6, 16
+; GFX11-FAKE16-NEXT: s_lshl_b32 s7, s7, 16
+; GFX11-FAKE16-NEXT: s_lshr_b32 s9, s5, 8
+; GFX11-FAKE16-NEXT: s_or_b32 s6, s6, s7
+; GFX11-FAKE16-NEXT: s_mul_i32 s7, s8, 0xffffffe8
; GFX11-FAKE16-NEXT: s_and_b32 s5, s5, 0xff
-; GFX11-FAKE16-NEXT: s_or_b32 s4, s4, s6
-; GFX11-FAKE16-NEXT: s_mul_i32 s6, s7, 0xffffffe8
+; GFX11-FAKE16-NEXT: s_mul_hi_u32 s7, s8, s7
+; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s4, 24
+; GFX11-FAKE16-NEXT: s_add_i32 s8, s8, s7
; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s5, 8
-; GFX11-FAKE16-NEXT: s_mul_hi_u32 s6, s7, s6
-; GFX11-FAKE16-NEXT: s_or_b32 s5, s8, s5
-; GFX11-FAKE16-NEXT: s_add_i32 s7, s7, s6
-; GFX11-FAKE16-NEXT: s_and_b32 s8, s9, 0xff
-; GFX11-FAKE16-NEXT: s_mul_hi_u32 s6, s4, s7
-; GFX11-FAKE16-NEXT: s_and_b32 s8, 0xffff, s8
-; GFX11-FAKE16-NEXT: s_mulk_i32 s6, 0xffe8
-; GFX11-FAKE16-NEXT: s_and_b32 s5, 0xffff, s5
-; GFX11-FAKE16-NEXT: s_lshl_b32 s8, s8, 16
-; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, s6
-; GFX11-FAKE16-NEXT: s_or_b32 s5, s5, s8
-; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s4, 24
-; GFX11-FAKE16-NEXT: s_cselect_b32 s6, 1, 0
-; GFX11-FAKE16-NEXT: s_sub_i32 s8, s4, 24
-; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s6, 0
-; GFX11-FAKE16-NEXT: s_cselect_b32 s4, s8, s4
+; GFX11-FAKE16-NEXT: s_mul_hi_u32 s7, s6, s8
+; GFX11-FAKE16-NEXT: s_or_b32 s4, s4, s5
+; GFX11-FAKE16-NEXT: s_and_b32 s5, s9, 0xff
+; GFX11-FAKE16-NEXT: s_mulk_i32 s7, 0xffe8
+; GFX11-FAKE16-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s5, 16
+; GFX11-FAKE16-NEXT: s_add_i32 s6, s6, s7
+; GFX11-FAKE16-NEXT: s_or_b32 s4, s4, s5
+; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s6, 24
+; GFX11-FAKE16-NEXT: s_cselect_b32 s5, 1, 0
+; GFX11-FAKE16-NEXT: s_sub_i32 s7, s6, 24
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s5, 0
+; GFX11-FAKE16-NEXT: s_cselect_b32 s5, s7, s6
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s4, 24
+; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s5, 24
; GFX11-FAKE16-NEXT: s_cselect_b32 s6, 1, 0
-; GFX11-FAKE16-NEXT: s_sub_i32 s8, s4, 24
+; GFX11-FAKE16-NEXT: s_sub_i32 s7, s5, 24
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s6, 0
-; GFX11-FAKE16-NEXT: s_cselect_b32 s4, s8, s4
+; GFX11-FAKE16-NEXT: s_cselect_b32 s5, s7, s5
; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s2, 1
-; GFX11-FAKE16-NEXT: s_sub_i32 s6, 23, s4
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, s4
-; GFX11-FAKE16-NEXT: s_mul_hi_u32 s4, s5, s7
+; GFX11-FAKE16-NEXT: s_sub_i32 s6, 23, s5
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, s5
+; GFX11-FAKE16-NEXT: s_mul_hi_u32 s5, s4, s8
; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s2, s6
-; GFX11-FAKE16-NEXT: s_mulk_i32 s4, 0xffe8
+; GFX11-FAKE16-NEXT: s_mulk_i32 s5, 0xffe8
; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s2
-; GFX11-FAKE16-NEXT: s_add_i32 s5, s5, s4
+; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, s5
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s5, 24
+; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s4, 24
; GFX11-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-FAKE16-NEXT: s_sub_i32 s4, s5, 24
+; GFX11-FAKE16-NEXT: s_sub_i32 s5, s4, 24
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s2, 0
-; GFX11-FAKE16-NEXT: s_cselect_b32 s2, s4, s5
+; GFX11-FAKE16-NEXT: s_cselect_b32 s2, s5, s4
; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s2, 24
; GFX11-FAKE16-NEXT: s_cselect_b32 s4, 1, 0
; GFX11-FAKE16-NEXT: s_sub_i32 s5, s2, 24
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
index 11b62d825c965..33fb88a011002 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
@@ -69,11 +69,10 @@ define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX8-NEXT: s_add_i32 s4, s2, -7
; GFX8-NEXT: s_cmp_lg_u32 s3, 0
; GFX8-NEXT: s_cselect_b32 s2, s4, s2
-; GFX8-NEXT: s_and_b32 s1, s1, 0x7f
; GFX8-NEXT: s_sub_i32 s3, 6, s2
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
+; GFX8-NEXT: s_and_b32 s1, s1, 0x7f
; GFX8-NEXT: s_and_b32 s2, s2, 0x7f
-; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
; GFX8-NEXT: s_and_b32 s3, s3, 0x7f
; GFX8-NEXT: s_lshl_b32 s0, s0, s3
; GFX8-NEXT: s_lshr_b32 s1, s1, s2
@@ -105,11 +104,10 @@ define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX9-NEXT: s_cmp_lg_u32 s3, 0
; GFX9-NEXT: s_cselect_b32 s2, s4, s2
; GFX9-NEXT: s_sub_i32 s3, 6, s2
-; GFX9-NEXT: s_and_b32 s1, s1, 0x7f
; GFX9-NEXT: s_lshl_b32 s0, s0, 1
; GFX9-NEXT: s_and_b32 s3, s3, 0x7f
; GFX9-NEXT: s_and_b32 s2, s2, 0x7f
-; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX9-NEXT: s_and_b32 s1, s1, 0x7f
; GFX9-NEXT: s_lshl_b32 s0, s0, s3
; GFX9-NEXT: s_lshr_b32 s1, s1, s2
; GFX9-NEXT: s_or_b32 s0, s0, s1
@@ -139,12 +137,11 @@ define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX10-NEXT: s_add_i32 s4, s2, -7
; GFX10-NEXT: s_cmp_lg_u32 s3, 0
; GFX10-NEXT: s_cselect_b32 s2, s4, s2
-; GFX10-NEXT: s_and_b32 s1, s1, 0x7f
-; GFX10-NEXT: s_sub_i32 s3, 6, s2
; GFX10-NEXT: s_lshl_b32 s0, s0, 1
-; GFX10-NEXT: s_and_b32 s2, s2, 0x7f
+; GFX10-NEXT: s_sub_i32 s3, 6, s2
+; GFX10-NEXT: s_and_b32 s1, s1, 0x7f
; GFX10-NEXT: s_and_b32 s3, s3, 0x7f
-; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX10-NEXT: s_and_b32 s2, s2, 0x7f
; GFX10-NEXT: s_lshl_b32 s0, s0, s3
; GFX10-NEXT: s_lshr_b32 s1, s1, s2
; GFX10-NEXT: s_or_b32 s0, s0, s1
@@ -180,12 +177,11 @@ define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX11-NEXT: s_add_i32 s4, s2, -7
; GFX11-NEXT: s_cmp_lg_u32 s3, 0
; GFX11-NEXT: s_cselect_b32 s2, s4, s2
-; GFX11-NEXT: s_and_b32 s1, s1, 0x7f
-; GFX11-NEXT: s_sub_i32 s3, 6, s2
; GFX11-NEXT: s_lshl_b32 s0, s0, 1
-; GFX11-NEXT: s_and_b32 s2, s2, 0x7f
+; GFX11-NEXT: s_sub_i32 s3, 6, s2
+; GFX11-NEXT: s_and_b32 s1, s1, 0x7f
; GFX11-NEXT: s_and_b32 s3, s3, 0x7f
-; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX11-NEXT: s_and_b32 s2, s2, 0x7f
; GFX11-NEXT: s_lshl_b32 s0, s0, s3
; GFX11-NEXT: s_lshr_b32 s1, s1, s2
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -415,11 +411,10 @@ define amdgpu_ps i8 @s_fshr_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
;
; GFX8-LABEL: s_fshr_i8:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_and_b32 s1, s1, 0xff
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
; GFX8-NEXT: s_andn2_b32 s3, 7, s2
; GFX8-NEXT: s_and_b32 s2, s2, 7
-; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX8-NEXT: s_and_b32 s1, s1, 0xff
; GFX8-NEXT: s_lshl_b32 s0, s0, s3
; GFX8-NEXT: s_lshr_b32 s1, s1, s2
; GFX8-NEXT: s_or_b32 s0, s0, s1
@@ -427,11 +422,10 @@ define amdgpu_ps i8 @s_fshr_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
;
; GFX9-LABEL: s_fshr_i8:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_and_b32 s1, s1, 0xff
; GFX9-NEXT: s_lshl_b32 s0, s0, 1
; GFX9-NEXT: s_andn2_b32 s3, 7, s2
; GFX9-NEXT: s_and_b32 s2, s2, 7
-; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX9-NEXT: s_and_b32 s1, s1, 0xff
; GFX9-NEXT: s_lshl_b32 s0, s0, s3
; GFX9-NEXT: s_lshr_b32 s1, s1, s2
; GFX9-NEXT: s_or_b32 s0, s0, s1
@@ -439,11 +433,10 @@ define amdgpu_ps i8 @s_fshr_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
;
; GFX10-LABEL: s_fshr_i8:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_and_b32 s1, s1, 0xff
; GFX10-NEXT: s_lshl_b32 s0, s0, 1
; GFX10-NEXT: s_andn2_b32 s3, 7, s2
; GFX10-NEXT: s_and_b32 s2, s2, 7
-; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX10-NEXT: s_and_b32 s1, s1, 0xff
; GFX10-NEXT: s_lshl_b32 s0, s0, s3
; GFX10-NEXT: s_lshr_b32 s1, s1, s2
; GFX10-NEXT: s_or_b32 s0, s0, s1
@@ -451,11 +444,10 @@ define amdgpu_ps i8 @s_fshr_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
;
; GFX11-LABEL: s_fshr_i8:
; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_lshl_b32 s0, s0, 1
; GFX11-NEXT: s_and_not1_b32 s3, 7, s2
; GFX11-NEXT: s_and_b32 s2, s2, 7
-; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_lshl_b32 s0, s0, s3
; GFX11-NEXT: s_lshr_b32 s1, s1, s2
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -559,7 +551,6 @@ define amdgpu_ps i8 @s_fshr_i8_4(i8 inreg %lhs, i8 inreg %rhs) {
; GFX8-LABEL: s_fshr_i8_4:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_and_b32 s1, s1, 0xff
-; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
; GFX8-NEXT: s_lshl_b32 s0, s0, 4
; GFX8-NEXT: s_lshr_b32 s1, s1, 4
; GFX8-NEXT: s_or_b32 s0, s0, s1
@@ -568,7 +559,6 @@ define amdgpu_ps i8 @s_fshr_i8_4(i8 inreg %lhs, i8 inreg %rhs) {
; GFX9-LABEL: s_fshr_i8_4:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s1, s1, 0xff
-; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_lshl_b32 s0, s0, 4
; GFX9-NEXT: s_lshr_b32 s1, s1, 4
; GFX9-NEXT: s_or_b32 s0, s0, s1
@@ -578,7 +568,6 @@ define amdgpu_ps i8 @s_fshr_i8_4(i8 inreg %lhs, i8 inreg %rhs) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s1, s1, 0xff
; GFX10-NEXT: s_lshl_b32 s0, s0, 4
-; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
; GFX10-NEXT: s_lshr_b32 s1, s1, 4
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
@@ -587,9 +576,8 @@ define amdgpu_ps i8 @s_fshr_i8_4(i8 inreg %lhs, i8 inreg %rhs) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_lshl_b32 s0, s0, 4
-; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_lshr_b32 s1, s1, 4
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_or_b32 s0, s0, s1
; GFX11-NEXT: ; return to shader part epilog
%result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 4)
@@ -666,7 +654,6 @@ define amdgpu_ps i8 @s_fshr_i8_5(i8 inreg %lhs, i8 inreg %rhs) {
; GFX8-LABEL: s_fshr_i8_5:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_and_b32 s1, s1, 0xff
-; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
; GFX8-NEXT: s_lshl_b32 s0, s0, 3
; GFX8-NEXT: s_lshr_b32 s1, s1, 5
; GFX8-NEXT: s_or_b32 s0, s0, s1
@@ -675,7 +662,6 @@ define amdgpu_ps i8 @s_fshr_i8_5(i8 inreg %lhs, i8 inreg %rhs) {
; GFX9-LABEL: s_fshr_i8_5:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s1, s1, 0xff
-; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_lshl_b32 s0, s0, 3
; GFX9-NEXT: s_lshr_b32 s1, s1, 5
; GFX9-NEXT: s_or_b32 s0, s0, s1
@@ -685,7 +671,6 @@ define amdgpu_ps i8 @s_fshr_i8_5(i8 inreg %lhs, i8 inreg %rhs) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s1, s1, 0xff
; GFX10-NEXT: s_lshl_b32 s0, s0, 3
-; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
; GFX10-NEXT: s_lshr_b32 s1, s1, 5
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
@@ -694,9 +679,8 @@ define amdgpu_ps i8 @s_fshr_i8_5(i8 inreg %lhs, i8 inreg %rhs) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_lshl_b32 s0, s0, 3
-; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_lshr_b32 s1, s1, 5
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_or_b32 s0, s0, s1
; GFX11-NEXT: ; return to shader part epilog
%result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 5)
@@ -789,23 +773,21 @@ define amdgpu_ps i16 @s_fshr_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
;
; GFX8-LABEL: s_fshr_v2i8:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_lshr_b32 s4, s1, 8
-; GFX8-NEXT: s_and_b32 s1, s1, 0xff
; GFX8-NEXT: s_lshr_b32 s3, s0, 8
+; GFX8-NEXT: s_lshr_b32 s4, s1, 8
; GFX8-NEXT: s_lshr_b32 s5, s2, 8
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
; GFX8-NEXT: s_andn2_b32 s6, 7, s2
; GFX8-NEXT: s_and_b32 s2, s2, 7
-; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX8-NEXT: s_and_b32 s1, s1, 0xff
; GFX8-NEXT: s_lshl_b32 s0, s0, s6
; GFX8-NEXT: s_lshr_b32 s1, s1, s2
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: s_lshl_b32 s1, s3, 1
; GFX8-NEXT: s_andn2_b32 s2, 7, s5
-; GFX8-NEXT: s_and_b32 s3, s4, 0xff
; GFX8-NEXT: s_lshl_b32 s1, s1, s2
; GFX8-NEXT: s_and_b32 s2, s5, 7
-; GFX8-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX8-NEXT: s_and_b32 s3, s4, 0xff
; GFX8-NEXT: s_lshr_b32 s2, s3, s2
; GFX8-NEXT: s_or_b32 s1, s1, s2
; GFX8-NEXT: s_and_b32 s1, s1, 0xff
@@ -816,23 +798,21 @@ define amdgpu_ps i16 @s_fshr_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
;
; GFX9-LABEL: s_fshr_v2i8:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_lshr_b32 s4, s1, 8
-; GFX9-NEXT: s_and_b32 s1, s1, 0xff
; GFX9-NEXT: s_lshr_b32 s3, s0, 8
+; GFX9-NEXT: s_lshr_b32 s4, s1, 8
; GFX9-NEXT: s_lshr_b32 s5, s2, 8
; GFX9-NEXT: s_lshl_b32 s0, s0, 1
; GFX9-NEXT: s_andn2_b32 s6, 7, s2
; GFX9-NEXT: s_and_b32 s2, s2, 7
-; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX9-NEXT: s_and_b32 s1, s1, 0xff
; GFX9-NEXT: s_lshl_b32 s0, s0, s6
; GFX9-NEXT: s_lshr_b32 s1, s1, s2
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: s_lshl_b32 s1, s3, 1
; GFX9-NEXT: s_andn2_b32 s2, 7, s5
-; GFX9-NEXT: s_and_b32 s3, s4, 0xff
; GFX9-NEXT: s_lshl_b32 s1, s1, s2
; GFX9-NEXT: s_and_b32 s2, s5, 7
-; GFX9-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX9-NEXT: s_and_b32 s3, s4, 0xff
; GFX9-NEXT: s_lshr_b32 s2, s3, s2
; GFX9-NEXT: s_or_b32 s1, s1, s2
; GFX9-NEXT: s_and_b32 s1, s1, 0xff
@@ -843,20 +823,18 @@ define amdgpu_ps i16 @s_fshr_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
;
; GFX10-LABEL: s_fshr_v2i8:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_lshr_b32 s4, s1, 8
; GFX10-NEXT: s_lshr_b32 s3, s0, 8
+; GFX10-NEXT: s_lshr_b32 s4, s1, 8
; GFX10-NEXT: s_lshl_b32 s0, s0, 1
; GFX10-NEXT: s_andn2_b32 s5, 7, s2
; GFX10-NEXT: s_lshr_b32 s6, s2, 8
-; GFX10-NEXT: s_and_b32 s4, s4, 0xff
; GFX10-NEXT: s_lshl_b32 s0, s0, s5
-; GFX10-NEXT: s_and_b32 s1, s1, 0xff
; GFX10-NEXT: s_lshl_b32 s3, s3, 1
; GFX10-NEXT: s_andn2_b32 s5, 7, s6
; GFX10-NEXT: s_and_b32 s6, s6, 7
-; GFX10-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX10-NEXT: s_and_b32 s4, s4, 0xff
; GFX10-NEXT: s_and_b32 s2, s2, 7
-; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX10-NEXT: s_and_b32 s1, s1, 0xff
; GFX10-NEXT: s_lshl_b32 s3, s3, s5
; GFX10-NEXT: s_lshr_b32 s4, s4, s6
; GFX10-NEXT: s_lshr_b32 s1, s1, s2
@@ -870,20 +848,18 @@ define amdgpu_ps i16 @s_fshr_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
;
; GFX11-LABEL: s_fshr_v2i8:
; GFX11: ; %bb.0:
-; GFX11-NEXT: s_lshr_b32 s4, s1, 8
; GFX11-NEXT: s_lshr_b32 s3, s0, 8
+; GFX11-NEXT: s_lshr_b32 s4, s1, 8
; GFX11-NEXT: s_lshl_b32 s0, s0, 1
; GFX11-NEXT: s_and_not1_b32 s5, 7, s2
; GFX11-NEXT: s_lshr_b32 s6, s2, 8
-; GFX11-NEXT: s_and_b32 s4, s4, 0xff
; GFX11-NEXT: s_lshl_b32 s0, s0, s5
-; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_lshl_b32 s3, s3, 1
; GFX11-NEXT: s_and_not1_b32 s5, 7, s6
; GFX11-NEXT: s_and_b32 s6, s6, 7
-; GFX11-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX11-NEXT: s_and_b32 s4, s4, 0xff
; GFX11-NEXT: s_and_b32 s2, s2, 7
-; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_lshl_b32 s3, s3, s5
; GFX11-NEXT: s_lshr_b32 s4, s4, s6
; GFX11-NEXT: s_lshr_b32 s1, s1, s2
@@ -1129,37 +1105,34 @@ define amdgpu_ps i32 @s_fshr_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
;
; GFX8-LABEL: s_fshr_v4i8:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_lshr_b32 s6, s1, 8
-; GFX8-NEXT: s_lshr_b32 s7, s1, 16
-; GFX8-NEXT: s_lshr_b32 s8, s1, 24
-; GFX8-NEXT: s_and_b32 s1, s1, 0xff
; GFX8-NEXT: s_lshr_b32 s3, s0, 8
; GFX8-NEXT: s_lshr_b32 s4, s0, 16
; GFX8-NEXT: s_lshr_b32 s5, s0, 24
+; GFX8-NEXT: s_lshr_b32 s6, s1, 8
+; GFX8-NEXT: s_lshr_b32 s7, s1, 16
+; GFX8-NEXT: s_lshr_b32 s8, s1, 24
; GFX8-NEXT: s_lshr_b32 s9, s2, 8
; GFX8-NEXT: s_lshr_b32 s10, s2, 16
; GFX8-NEXT: s_lshr_b32 s11, s2, 24
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
; GFX8-NEXT: s_andn2_b32 s12, 7, s2
; GFX8-NEXT: s_and_b32 s2, s2, 7
-; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX8-NEXT: s_and_b32 s1, s1, 0xff
; GFX8-NEXT: s_lshl_b32 s0, s0, s12
; GFX8-NEXT: s_lshr_b32 s1, s1, s2
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: s_lshl_b32 s1, s3, 1
; GFX8-NEXT: s_andn2_b32 s2, 7, s9
-; GFX8-NEXT: s_and_b32 s3, s6, 0xff
; GFX8-NEXT: s_lshl_b32 s1, s1, s2
; GFX8-NEXT: s_and_b32 s2, s9, 7
-; GFX8-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX8-NEXT: s_and_b32 s3, s6, 0xff
; GFX8-NEXT: s_lshr_b32 s2, s3, s2
; GFX8-NEXT: s_or_b32 s1, s1, s2
; GFX8-NEXT: s_lshl_b32 s2, s4, 1
; GFX8-NEXT: s_andn2_b32 s3, 7, s10
-; GFX8-NEXT: s_and_b32 s4, s7, 0xff
; GFX8-NEXT: s_lshl_b32 s2, s2, s3
; GFX8-NEXT: s_and_b32 s3, s10, 7
-; GFX8-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX8-NEXT: s_and_b32 s4, s7, 0xff
; GFX8-NEXT: s_lshr_b32 s3, s4, s3
; GFX8-NEXT: s_or_b32 s2, s2, s3
; GFX8-NEXT: s_lshl_b32 s3, s5, 1
@@ -1182,37 +1155,34 @@ define amdgpu_ps i32 @s_fshr_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
;
; GFX9-LABEL: s_fshr_v4i8:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_lshr_b32 s6, s1, 8
-; GFX9-NEXT: s_lshr_b32 s7, s1, 16
-; GFX9-NEXT: s_lshr_b32 s8, s1, 24
-; GFX9-NEXT: s_and_b32 s1, s1, 0xff
; GFX9-NEXT: s_lshr_b32 s3, s0, 8
; GFX9-NEXT: s_lshr_b32 s4, s0, 16
; GFX9-NEXT: s_lshr_b32 s5, s0, 24
+; GFX9-NEXT: s_lshr_b32 s6, s1, 8
+; GFX9-NEXT: s_lshr_b32 s7, s1, 16
+; GFX9-NEXT: s_lshr_b32 s8, s1, 24
; GFX9-NEXT: s_lshr_b32 s9, s2, 8
; GFX9-NEXT: s_lshr_b32 s10, s2, 16
; GFX9-NEXT: s_lshr_b32 s11, s2, 24
; GFX9-NEXT: s_lshl_b32 s0, s0, 1
; GFX9-NEXT: s_andn2_b32 s12, 7, s2
; GFX9-NEXT: s_and_b32 s2, s2, 7
-; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX9-NEXT: s_and_b32 s1, s1, 0xff
; GFX9-NEXT: s_lshl_b32 s0, s0, s12
; GFX9-NEXT: s_lshr_b32 s1, s1, s2
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: s_lshl_b32 s1, s3, 1
; GFX9-NEXT: s_andn2_b32 s2, 7, s9
-; GFX9-NEXT: s_and_b32 s3, s6, 0xff
; GFX9-NEXT: s_lshl_b32 s1, s1, s2
; GFX9-NEXT: s_and_b32 s2, s9, 7
-; GFX9-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX9-NEXT: s_and_b32 s3, s6, 0xff
; GFX9-NEXT: s_lshr_b32 s2, s3, s2
; GFX9-NEXT: s_or_b32 s1, s1, s2
; GFX9-NEXT: s_lshl_b32 s2, s4, 1
; GFX9-NEXT: s_andn2_b32 s3, 7, s10
-; GFX9-NEXT: s_and_b32 s4, s7, 0xff
; GFX9-NEXT: s_lshl_b32 s2, s2, s3
; GFX9-NEXT: s_and_b32 s3, s10, 7
-; GFX9-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX9-NEXT: s_and_b32 s4, s7, 0xff
; GFX9-NEXT: s_lshr_b32 s3, s4, s3
; GFX9-NEXT: s_or_b32 s2, s2, s3
; GFX9-NEXT: s_lshl_b32 s3, s5, 1
@@ -1235,18 +1205,16 @@ define amdgpu_ps i32 @s_fshr_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
;
; GFX10-LABEL: s_fshr_v4i8:
; GFX10: ; %bb.0:
+; GFX10-NEXT: s_lshr_b32 s3, s0, 8
; GFX10-NEXT: s_lshr_b32 s6, s1, 8
; GFX10-NEXT: s_lshr_b32 s7, s1, 16
; GFX10-NEXT: s_lshr_b32 s8, s1, 24
-; GFX10-NEXT: s_and_b32 s1, s1, 0xff
-; GFX10-NEXT: s_lshr_b32 s3, s0, 8
; GFX10-NEXT: s_lshr_b32 s9, s2, 8
; GFX10-NEXT: s_lshr_b32 s10, s2, 16
; GFX10-NEXT: s_lshr_b32 s11, s2, 24
; GFX10-NEXT: s_andn2_b32 s12, 7, s2
; GFX10-NEXT: s_and_b32 s2, s2, 7
-; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX10-NEXT: s_and_b32 s6, s6, 0xff
+; GFX10-NEXT: s_and_b32 s1, s1, 0xff
; GFX10-NEXT: s_lshr_b32 s4, s0, 16
; GFX10-NEXT: s_lshr_b32 s5, s0, 24
; GFX10-NEXT: s_lshl_b32 s0, s0, 1
@@ -1254,19 +1222,18 @@ define amdgpu_ps i32 @s_fshr_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX10-NEXT: s_lshl_b32 s2, s3, 1
; GFX10-NEXT: s_andn2_b32 s3, 7, s9
; GFX10-NEXT: s_and_b32 s9, s9, 7
-; GFX10-NEXT: s_and_b32 s6, 0xffff, s6
+; GFX10-NEXT: s_and_b32 s6, s6, 0xff
; GFX10-NEXT: s_lshl_b32 s0, s0, s12
; GFX10-NEXT: s_lshl_b32 s2, s2, s3
; GFX10-NEXT: s_lshr_b32 s3, s6, s9
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: s_or_b32 s1, s2, s3
; GFX10-NEXT: s_lshl_b32 s2, s4, 1
-; GFX10-NEXT: s_and_b32 s4, s7, 0xff
; GFX10-NEXT: s_andn2_b32 s3, 7, s10
-; GFX10-NEXT: s_and_b32 s6, s10, 7
-; GFX10-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX10-NEXT: s_and_b32 s4, s10, 7
+; GFX10-NEXT: s_and_b32 s6, s7, 0xff
; GFX10-NEXT: s_lshl_b32 s2, s2, s3
-; GFX10-NEXT: s_lshr_b32 s3, s4, s6
+; GFX10-NEXT: s_lshr_b32 s3, s6, s4
; GFX10-NEXT: s_lshl_b32 s4, s5, 1
; GFX10-NEXT: s_andn2_b32 s5, 7, s11
; GFX10-NEXT: s_and_b32 s6, s11, 7
@@ -1288,18 +1255,16 @@ define amdgpu_ps i32 @s_fshr_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
;
; GFX11-LABEL: s_fshr_v4i8:
; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b32 s3, s0, 8
; GFX11-NEXT: s_lshr_b32 s6, s1, 8
; GFX11-NEXT: s_lshr_b32 s7, s1, 16
; GFX11-NEXT: s_lshr_b32 s8, s1, 24
-; GFX11-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-NEXT: s_lshr_b32 s3, s0, 8
; GFX11-NEXT: s_lshr_b32 s9, s2, 8
; GFX11-NEXT: s_lshr_b32 s10, s2, 16
; GFX11-NEXT: s_lshr_b32 s11, s2, 24
; GFX11-NEXT: s_and_not1_b32 s12, 7, s2
; GFX11-NEXT: s_and_b32 s2, s2, 7
-; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX11-NEXT: s_and_b32 s6, s6, 0xff
+; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_lshr_b32 s4, s0, 16
; GFX11-NEXT: s_lshr_b32 s5, s0, 24
; GFX11-NEXT: s_lshl_b32 s0, s0, 1
@@ -1307,19 +1272,18 @@ define amdgpu_ps i32 @s_fshr_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX11-NEXT: s_lshl_b32 s2, s3, 1
; GFX11-NEXT: s_and_not1_b32 s3, 7, s9
; GFX11-NEXT: s_and_b32 s9, s9, 7
-; GFX11-NEXT: s_and_b32 s6, 0xffff, s6
+; GFX11-NEXT: s_and_b32 s6, s6, 0xff
; GFX11-NEXT: s_lshl_b32 s0, s0, s12
; GFX11-NEXT: s_lshl_b32 s2, s2, s3
; GFX11-NEXT: s_lshr_b32 s3, s6, s9
; GFX11-NEXT: s_or_b32 s0, s0, s1
; GFX11-NEXT: s_or_b32 s1, s2, s3
; GFX11-NEXT: s_lshl_b32 s2, s4, 1
-; GFX11-NEXT: s_and_b32 s4, s7, 0xff
; GFX11-NEXT: s_and_not1_b32 s3, 7, s10
-; GFX11-NEXT: s_and_b32 s6, s10, 7
-; GFX11-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX11-NEXT: s_and_b32 s4, s10, 7
+; GFX11-NEXT: s_and_b32 s6, s7, 0xff
; GFX11-NEXT: s_lshl_b32 s2, s2, s3
-; GFX11-NEXT: s_lshr_b32 s3, s4, s6
+; GFX11-NEXT: s_lshr_b32 s3, s6, s4
; GFX11-NEXT: s_lshl_b32 s4, s5, 1
; GFX11-NEXT: s_and_not1_b32 s5, 7, s11
; GFX11-NEXT: s_and_b32 s6, s11, 7
@@ -2038,51 +2002,45 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: v_readfirstlane_b32 s2, v0
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT: s_and_b32 s3, s9, 0xff
; GFX6-NEXT: s_lshl_b32 s11, s11, 8
+; GFX6-NEXT: s_or_b32 s10, s10, s11
; GFX6-NEXT: s_and_b32 s7, s7, 0xff
-; GFX6-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX6-NEXT: s_and_b32 s3, s9, 0xff
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX6-NEXT: s_or_b32 s10, s10, s11
-; GFX6-NEXT: s_and_b32 s7, 0xffff, s7
-; GFX6-NEXT: s_lshl_b32 s3, s3, 16
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: s_and_b32 s10, 0xffff, s10
; GFX6-NEXT: s_lshl_b32 s7, s7, 16
-; GFX6-NEXT: s_or_b32 s2, s2, s3
-; GFX6-NEXT: s_lshr_b32 s3, s4, 16
+; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_bfe_u32 s11, s4, 0x80008
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: s_or_b32 s7, s10, s7
+; GFX6-NEXT: s_or_b32 s2, s2, s3
+; GFX6-NEXT: s_lshr_b32 s3, s4, 16
; GFX6-NEXT: s_and_b32 s10, s4, 0xff
; GFX6-NEXT: s_lshl_b32 s11, s11, 8
-; GFX6-NEXT: s_and_b32 s3, s3, 0xff
; GFX6-NEXT: s_or_b32 s10, s10, s11
-; GFX6-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX6-NEXT: s_and_b32 s3, s3, 0xff
; GFX6-NEXT: s_and_b32 s10, 0xffff, s10
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
-; GFX6-NEXT: v_mov_b32_e32 v1, s4
-; GFX6-NEXT: v_readfirstlane_b32 s4, v0
; GFX6-NEXT: s_or_b32 s3, s10, s3
-; GFX6-NEXT: s_mul_i32 s10, s4, 0xffffffe8
-; GFX6-NEXT: v_mul_hi_u32 v0, v0, s10
+; GFX6-NEXT: v_readfirstlane_b32 s10, v0
+; GFX6-NEXT: s_mul_i32 s11, s10, 0xffffffe8
+; GFX6-NEXT: v_mul_hi_u32 v0, v0, s11
; GFX6-NEXT: s_lshr_b32 s9, s5, 8
; GFX6-NEXT: s_and_b32 s5, s5, 0xff
-; GFX6-NEXT: s_and_b32 s9, s9, 0xff
-; GFX6-NEXT: v_readfirstlane_b32 s10, v0
-; GFX6-NEXT: s_add_i32 s4, s4, s10
-; GFX6-NEXT: v_mov_b32_e32 v0, s4
-; GFX6-NEXT: v_mul_hi_u32 v0, s3, v0
+; GFX6-NEXT: v_mov_b32_e32 v1, s4
; GFX6-NEXT: v_alignbit_b32 v1, s5, v1, 24
-; GFX6-NEXT: s_and_b32 s9, 0xffff, s9
-; GFX6-NEXT: v_readfirstlane_b32 s5, v1
+; GFX6-NEXT: v_readfirstlane_b32 s5, v0
+; GFX6-NEXT: s_add_i32 s5, s10, s5
+; GFX6-NEXT: v_mov_b32_e32 v0, s5
+; GFX6-NEXT: v_mul_hi_u32 v0, s3, v0
+; GFX6-NEXT: s_and_b32 s9, s9, 0xff
+; GFX6-NEXT: v_readfirstlane_b32 s4, v1
; GFX6-NEXT: s_lshl_b32 s9, s9, 16
-; GFX6-NEXT: s_or_b32 s5, s5, s9
+; GFX6-NEXT: s_or_b32 s4, s4, s9
; GFX6-NEXT: v_readfirstlane_b32 s9, v0
-; GFX6-NEXT: s_and_b32 s6, s6, 0xff
; GFX6-NEXT: s_mulk_i32 s9, 0xffe8
+; GFX6-NEXT: s_and_b32 s6, s6, 0xff
; GFX6-NEXT: s_and_b32 s8, 0xffff, s8
-; GFX6-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX6-NEXT: s_and_b32 s1, 0xffff, s1
; GFX6-NEXT: s_add_i32 s3, s3, s9
; GFX6-NEXT: s_cmp_ge_u32 s3, 24
; GFX6-NEXT: s_cselect_b32 s9, 1, 0
@@ -2092,42 +2050,42 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_cmp_ge_u32 s3, 24
; GFX6-NEXT: s_cselect_b32 s9, 1, 0
; GFX6-NEXT: s_sub_i32 s10, s3, 24
-; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mov_b32_e32 v0, s5
; GFX6-NEXT: s_cmp_lg_u32 s9, 0
-; GFX6-NEXT: v_mul_hi_u32 v0, s5, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX6-NEXT: s_cselect_b32 s3, s10, s3
; GFX6-NEXT: s_lshl_b32 s6, s6, 17
; GFX6-NEXT: s_lshl_b32 s8, s8, 1
; GFX6-NEXT: s_sub_i32 s9, 23, s3
; GFX6-NEXT: s_or_b32 s6, s6, s8
-; GFX6-NEXT: s_lshl_b32 s4, s6, s9
+; GFX6-NEXT: s_lshl_b32 s5, s6, s9
; GFX6-NEXT: s_lshr_b32 s3, s7, s3
-; GFX6-NEXT: s_or_b32 s4, s4, s3
+; GFX6-NEXT: s_or_b32 s5, s5, s3
; GFX6-NEXT: v_readfirstlane_b32 s3, v0
; GFX6-NEXT: s_mulk_i32 s3, 0xffe8
-; GFX6-NEXT: s_add_i32 s5, s5, s3
-; GFX6-NEXT: s_cmp_ge_u32 s5, 24
+; GFX6-NEXT: s_add_i32 s4, s4, s3
+; GFX6-NEXT: s_cmp_ge_u32 s4, 24
; GFX6-NEXT: s_cselect_b32 s3, 1, 0
-; GFX6-NEXT: s_sub_i32 s6, s5, 24
+; GFX6-NEXT: s_sub_i32 s6, s4, 24
; GFX6-NEXT: s_cmp_lg_u32 s3, 0
-; GFX6-NEXT: s_cselect_b32 s3, s6, s5
+; GFX6-NEXT: s_cselect_b32 s3, s6, s4
; GFX6-NEXT: s_cmp_ge_u32 s3, 24
-; GFX6-NEXT: s_cselect_b32 s5, 1, 0
+; GFX6-NEXT: s_cselect_b32 s4, 1, 0
; GFX6-NEXT: s_sub_i32 s6, s3, 24
-; GFX6-NEXT: s_cmp_lg_u32 s5, 0
+; GFX6-NEXT: s_cmp_lg_u32 s4, 0
; GFX6-NEXT: s_cselect_b32 s3, s6, s3
; GFX6-NEXT: s_lshl_b32 s1, s1, 17
; GFX6-NEXT: s_lshl_b32 s0, s0, 1
-; GFX6-NEXT: s_sub_i32 s5, 23, s3
+; GFX6-NEXT: s_sub_i32 s4, 23, s3
; GFX6-NEXT: s_or_b32 s0, s1, s0
-; GFX6-NEXT: s_lshl_b32 s0, s0, s5
+; GFX6-NEXT: s_lshl_b32 s0, s0, s4
; GFX6-NEXT: s_lshr_b32 s1, s2, s3
-; GFX6-NEXT: s_bfe_u32 s2, s4, 0x80008
+; GFX6-NEXT: s_bfe_u32 s2, s5, 0x80008
; GFX6-NEXT: s_or_b32 s1, s0, s1
-; GFX6-NEXT: s_and_b32 s0, s4, 0xff
+; GFX6-NEXT: s_and_b32 s0, s5, 0xff
; GFX6-NEXT: s_lshl_b32 s2, s2, 8
; GFX6-NEXT: s_or_b32 s0, s0, s2
-; GFX6-NEXT: s_bfe_u32 s2, s4, 0x80010
+; GFX6-NEXT: s_bfe_u32 s2, s5, 0x80010
; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_or_b32 s0, s0, s2
; GFX6-NEXT: s_and_b32 s2, s1, 0xff
@@ -2160,34 +2118,31 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX8-NEXT: s_lshr_b32 s10, s2, 24
; GFX8-NEXT: s_and_b32 s2, s2, 0xff
; GFX8-NEXT: s_lshl_b32 s8, s8, 8
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX8-NEXT: s_lshr_b32 s11, s3, 8
; GFX8-NEXT: s_or_b32 s2, s2, s8
; GFX8-NEXT: s_and_b32 s8, s9, 0xff
-; GFX8-NEXT: s_and_b32 s8, 0xffff, s8
-; GFX8-NEXT: s_lshr_b32 s11, s3, 8
+; GFX8-NEXT: s_and_b32 s3, s3, 0xff
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_and_b32 s2, 0xffff, s2
; GFX8-NEXT: s_lshl_b32 s8, s8, 16
-; GFX8-NEXT: s_and_b32 s3, s3, 0xff
-; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
-; GFX8-NEXT: s_or_b32 s2, s2, s8
; GFX8-NEXT: s_lshl_b32 s3, s3, 8
-; GFX8-NEXT: s_and_b32 s8, s11, 0xff
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX8-NEXT: s_or_b32 s2, s2, s8
; GFX8-NEXT: s_or_b32 s3, s10, s3
-; GFX8-NEXT: s_and_b32 s8, 0xffff, s8
+; GFX8-NEXT: s_and_b32 s8, s11, 0xff
; GFX8-NEXT: s_and_b32 s3, 0xffff, s3
; GFX8-NEXT: s_lshl_b32 s8, s8, 16
; GFX8-NEXT: s_or_b32 s3, s3, s8
; GFX8-NEXT: s_lshr_b32 s8, s4, 8
-; GFX8-NEXT: s_and_b32 s8, s8, 0xff
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX8-NEXT: s_and_b32 s8, s8, 0xff
+; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: s_lshr_b32 s9, s4, 16
; GFX8-NEXT: s_lshr_b32 s10, s4, 24
; GFX8-NEXT: s_and_b32 s4, s4, 0xff
; GFX8-NEXT: s_lshl_b32 s8, s8, 8
-; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: s_or_b32 s4, s4, s8
; GFX8-NEXT: s_and_b32 s8, s9, 0xff
-; GFX8-NEXT: s_and_b32 s8, 0xffff, s8
; GFX8-NEXT: s_and_b32 s4, 0xffff, s4
; GFX8-NEXT: s_lshl_b32 s8, s8, 16
; GFX8-NEXT: s_or_b32 s4, s4, s8
@@ -2203,16 +2158,13 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX8-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX8-NEXT: s_and_b32 s9, s11, 0xff
-; GFX8-NEXT: s_and_b32 s9, 0xffff, s9
; GFX8-NEXT: s_and_b32 s5, 0xffff, s5
; GFX8-NEXT: s_lshl_b32 s9, s9, 16
; GFX8-NEXT: s_or_b32 s5, s5, s9
; GFX8-NEXT: v_readfirstlane_b32 s9, v0
; GFX8-NEXT: s_mulk_i32 s9, 0xffe8
; GFX8-NEXT: s_and_b32 s0, 0xffff, s0
-; GFX8-NEXT: s_and_b32 s6, 0xffff, s6
; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX8-NEXT: s_and_b32 s7, 0xffff, s7
; GFX8-NEXT: s_add_i32 s4, s4, s9
; GFX8-NEXT: s_cmp_ge_u32 s4, 24
; GFX8-NEXT: s_cselect_b32 s9, 1, 0
@@ -2290,43 +2242,39 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_lshr_b32 s10, s2, 24
; GFX9-NEXT: s_and_b32 s2, s2, 0xff
; GFX9-NEXT: s_lshl_b32 s8, s8, 8
+; GFX9-NEXT: s_lshr_b32 s11, s3, 8
; GFX9-NEXT: s_or_b32 s2, s2, s8
; GFX9-NEXT: s_and_b32 s8, s9, 0xff
-; GFX9-NEXT: s_and_b32 s8, 0xffff, s8
-; GFX9-NEXT: s_lshr_b32 s11, s3, 8
+; GFX9-NEXT: s_and_b32 s3, s3, 0xff
; GFX9-NEXT: s_and_b32 s2, 0xffff, s2
; GFX9-NEXT: s_lshl_b32 s8, s8, 16
-; GFX9-NEXT: s_and_b32 s3, s3, 0xff
-; GFX9-NEXT: s_or_b32 s2, s2, s8
; GFX9-NEXT: s_lshl_b32 s3, s3, 8
-; GFX9-NEXT: s_and_b32 s8, s11, 0xff
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX9-NEXT: s_or_b32 s2, s2, s8
; GFX9-NEXT: s_or_b32 s3, s10, s3
-; GFX9-NEXT: s_and_b32 s8, 0xffff, s8
+; GFX9-NEXT: s_and_b32 s8, s11, 0xff
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_and_b32 s3, 0xffff, s3
; GFX9-NEXT: s_lshl_b32 s8, s8, 16
-; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX9-NEXT: s_or_b32 s3, s3, s8
; GFX9-NEXT: s_lshr_b32 s8, s4, 8
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_and_b32 s8, s8, 0xff
; GFX9-NEXT: s_lshr_b32 s9, s4, 16
; GFX9-NEXT: s_lshr_b32 s10, s4, 24
; GFX9-NEXT: s_and_b32 s4, s4, 0xff
; GFX9-NEXT: s_lshl_b32 s8, s8, 8
-; GFX9-NEXT: s_or_b32 s4, s4, s8
-; GFX9-NEXT: s_and_b32 s8, s9, 0xff
-; GFX9-NEXT: s_and_b32 s8, 0xffff, s8
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: s_lshr_b32 s11, s5, 8
-; GFX9-NEXT: s_and_b32 s4, 0xffff, s4
-; GFX9-NEXT: s_lshl_b32 s8, s8, 16
+; GFX9-NEXT: s_or_b32 s4, s4, s8
+; GFX9-NEXT: s_and_b32 s8, s9, 0xff
; GFX9-NEXT: s_and_b32 s5, s5, 0xff
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: s_or_b32 s4, s4, s8
+; GFX9-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX9-NEXT: s_lshl_b32 s8, s8, 16
; GFX9-NEXT: s_lshl_b32 s5, s5, 8
-; GFX9-NEXT: s_and_b32 s8, s11, 0xff
+; GFX9-NEXT: s_or_b32 s4, s4, s8
; GFX9-NEXT: s_or_b32 s5, s10, s5
-; GFX9-NEXT: s_and_b32 s8, 0xffff, s8
+; GFX9-NEXT: s_and_b32 s8, s11, 0xff
; GFX9-NEXT: s_and_b32 s5, 0xffff, s5
; GFX9-NEXT: s_lshl_b32 s8, s8, 16
; GFX9-NEXT: s_or_b32 s5, s5, s8
@@ -2337,9 +2285,7 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_mul_hi_u32 s9, s4, s8
; GFX9-NEXT: s_mulk_i32 s9, 0xffe8
; GFX9-NEXT: s_and_b32 s0, 0xffff, s0
-; GFX9-NEXT: s_and_b32 s6, 0xffff, s6
; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX9-NEXT: s_and_b32 s7, 0xffff, s7
; GFX9-NEXT: s_add_i32 s4, s4, s9
; GFX9-NEXT: s_cmp_ge_u32 s4, 24
; GFX9-NEXT: s_cselect_b32 s9, 1, 0
@@ -2401,8 +2347,8 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX10-NEXT: s_and_b32 s1, s1, 0xff
; GFX10-NEXT: s_lshr_b32 s6, s0, 8
; GFX10-NEXT: s_lshr_b32 s8, s0, 24
-; GFX10-NEXT: s_lshl_b32 s1, s1, 8
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX10-NEXT: s_lshl_b32 s1, s1, 8
; GFX10-NEXT: s_and_b32 s6, s6, 0xff
; GFX10-NEXT: s_or_b32 s1, s8, s1
; GFX10-NEXT: s_lshr_b32 s8, s2, 8
@@ -2417,80 +2363,74 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX10-NEXT: s_lshr_b32 s10, s2, 24
; GFX10-NEXT: s_and_b32 s2, s2, 0xff
; GFX10-NEXT: s_lshl_b32 s8, s8, 8
-; GFX10-NEXT: s_lshr_b32 s11, s3, 8
+; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: s_or_b32 s2, s2, s8
; GFX10-NEXT: s_and_b32 s8, s9, 0xff
+; GFX10-NEXT: s_lshr_b32 s11, s3, 8
; GFX10-NEXT: s_and_b32 s3, s3, 0xff
-; GFX10-NEXT: s_and_b32 s8, 0xffff, s8
-; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: s_and_b32 s2, 0xffff, s2
; GFX10-NEXT: s_lshl_b32 s8, s8, 16
; GFX10-NEXT: s_lshl_b32 s3, s3, 8
-; GFX10-NEXT: s_and_b32 s9, s11, 0xff
-; GFX10-NEXT: s_or_b32 s3, s10, s3
-; GFX10-NEXT: s_and_b32 s9, 0xffff, s9
; GFX10-NEXT: s_or_b32 s2, s2, s8
; GFX10-NEXT: s_lshr_b32 s8, s4, 8
+; GFX10-NEXT: s_or_b32 s3, s10, s3
+; GFX10-NEXT: s_and_b32 s9, s11, 0xff
+; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX10-NEXT: s_and_b32 s8, s8, 0xff
; GFX10-NEXT: s_and_b32 s3, 0xffff, s3
; GFX10-NEXT: s_lshl_b32 s9, s9, 16
-; GFX10-NEXT: s_and_b32 s8, s8, 0xff
-; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX10-NEXT: s_and_b32 s10, s4, 0xff
+; GFX10-NEXT: s_lshl_b32 s8, s8, 8
; GFX10-NEXT: s_or_b32 s3, s3, s9
; GFX10-NEXT: s_lshr_b32 s9, s4, 16
-; GFX10-NEXT: s_lshr_b32 s10, s4, 24
-; GFX10-NEXT: s_and_b32 s4, s4, 0xff
-; GFX10-NEXT: s_lshl_b32 s8, s8, 8
-; GFX10-NEXT: s_lshr_b32 s11, s5, 8
-; GFX10-NEXT: s_or_b32 s4, s4, s8
-; GFX10-NEXT: s_and_b32 s8, s9, 0xff
-; GFX10-NEXT: v_readfirstlane_b32 s9, v0
+; GFX10-NEXT: s_or_b32 s8, s10, s8
+; GFX10-NEXT: v_readfirstlane_b32 s10, v0
+; GFX10-NEXT: s_and_b32 s9, s9, 0xff
; GFX10-NEXT: s_and_b32 s8, 0xffff, s8
-; GFX10-NEXT: s_and_b32 s4, 0xffff, s4
-; GFX10-NEXT: s_lshl_b32 s8, s8, 16
+; GFX10-NEXT: s_lshl_b32 s9, s9, 16
+; GFX10-NEXT: s_lshr_b32 s11, s5, 8
+; GFX10-NEXT: s_or_b32 s8, s8, s9
+; GFX10-NEXT: s_mul_i32 s9, s10, 0xffffffe8
; GFX10-NEXT: s_and_b32 s5, s5, 0xff
-; GFX10-NEXT: s_or_b32 s4, s4, s8
-; GFX10-NEXT: s_mul_i32 s8, s9, 0xffffffe8
+; GFX10-NEXT: s_mul_hi_u32 s9, s10, s9
+; GFX10-NEXT: s_lshr_b32 s4, s4, 24
+; GFX10-NEXT: s_add_i32 s10, s10, s9
; GFX10-NEXT: s_lshl_b32 s5, s5, 8
-; GFX10-NEXT: s_mul_hi_u32 s8, s9, s8
-; GFX10-NEXT: s_or_b32 s5, s10, s5
-; GFX10-NEXT: s_add_i32 s9, s9, s8
-; GFX10-NEXT: s_and_b32 s10, s11, 0xff
-; GFX10-NEXT: s_mul_hi_u32 s8, s4, s9
-; GFX10-NEXT: s_and_b32 s10, 0xffff, s10
-; GFX10-NEXT: s_mulk_i32 s8, 0xffe8
-; GFX10-NEXT: s_and_b32 s5, 0xffff, s5
-; GFX10-NEXT: s_lshl_b32 s10, s10, 16
-; GFX10-NEXT: s_add_i32 s4, s4, s8
+; GFX10-NEXT: s_mul_hi_u32 s9, s8, s10
+; GFX10-NEXT: s_or_b32 s4, s4, s5
+; GFX10-NEXT: s_and_b32 s5, s11, 0xff
+; GFX10-NEXT: s_mulk_i32 s9, 0xffe8
+; GFX10-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX10-NEXT: s_lshl_b32 s5, s5, 16
+; GFX10-NEXT: s_add_i32 s8, s8, s9
; GFX10-NEXT: s_and_b32 s0, 0xffff, s0
-; GFX10-NEXT: s_and_b32 s6, 0xffff, s6
; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX10-NEXT: s_and_b32 s7, 0xffff, s7
-; GFX10-NEXT: s_or_b32 s5, s5, s10
-; GFX10-NEXT: s_cmp_ge_u32 s4, 24
-; GFX10-NEXT: s_cselect_b32 s8, 1, 0
-; GFX10-NEXT: s_sub_i32 s10, s4, 24
-; GFX10-NEXT: s_cmp_lg_u32 s8, 0
-; GFX10-NEXT: s_cselect_b32 s4, s10, s4
-; GFX10-NEXT: s_cmp_ge_u32 s4, 24
+; GFX10-NEXT: s_or_b32 s4, s4, s5
+; GFX10-NEXT: s_cmp_ge_u32 s8, 24
+; GFX10-NEXT: s_cselect_b32 s5, 1, 0
+; GFX10-NEXT: s_sub_i32 s9, s8, 24
+; GFX10-NEXT: s_cmp_lg_u32 s5, 0
+; GFX10-NEXT: s_cselect_b32 s5, s9, s8
+; GFX10-NEXT: s_cmp_ge_u32 s5, 24
; GFX10-NEXT: s_cselect_b32 s8, 1, 0
-; GFX10-NEXT: s_sub_i32 s10, s4, 24
+; GFX10-NEXT: s_sub_i32 s9, s5, 24
; GFX10-NEXT: s_cmp_lg_u32 s8, 0
-; GFX10-NEXT: s_cselect_b32 s4, s10, s4
+; GFX10-NEXT: s_cselect_b32 s5, s9, s5
; GFX10-NEXT: s_lshl_b32 s6, s6, 17
; GFX10-NEXT: s_lshl_b32 s0, s0, 1
-; GFX10-NEXT: s_sub_i32 s8, 23, s4
+; GFX10-NEXT: s_sub_i32 s8, 23, s5
; GFX10-NEXT: s_or_b32 s0, s6, s0
-; GFX10-NEXT: s_mul_hi_u32 s6, s5, s9
+; GFX10-NEXT: s_mul_hi_u32 s6, s4, s10
; GFX10-NEXT: s_lshl_b32 s0, s0, s8
; GFX10-NEXT: s_mulk_i32 s6, 0xffe8
-; GFX10-NEXT: s_lshr_b32 s2, s2, s4
-; GFX10-NEXT: s_add_i32 s5, s5, s6
+; GFX10-NEXT: s_lshr_b32 s2, s2, s5
+; GFX10-NEXT: s_add_i32 s4, s4, s6
; GFX10-NEXT: s_or_b32 s0, s0, s2
-; GFX10-NEXT: s_cmp_ge_u32 s5, 24
+; GFX10-NEXT: s_cmp_ge_u32 s4, 24
; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_sub_i32 s4, s5, 24
+; GFX10-NEXT: s_sub_i32 s5, s4, 24
; GFX10-NEXT: s_cmp_lg_u32 s2, 0
-; GFX10-NEXT: s_cselect_b32 s2, s4, s5
+; GFX10-NEXT: s_cselect_b32 s2, s5, s4
; GFX10-NEXT: s_cmp_ge_u32 s2, 24
; GFX10-NEXT: s_cselect_b32 s4, 1, 0
; GFX10-NEXT: s_sub_i32 s5, s2, 24
@@ -2635,8 +2575,8 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-FAKE16-NEXT: s_lshr_b32 s6, s0, 8
; GFX11-FAKE16-NEXT: s_lshr_b32 s8, s0, 24
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 8
; GFX11-FAKE16-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 8
; GFX11-FAKE16-NEXT: s_and_b32 s6, s6, 0xff
; GFX11-FAKE16-NEXT: s_or_b32 s1, s8, s1
; GFX11-FAKE16-NEXT: s_lshr_b32 s8, s2, 8
@@ -2651,82 +2591,76 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX11-FAKE16-NEXT: s_lshr_b32 s10, s2, 24
; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s8, s8, 8
-; GFX11-FAKE16-NEXT: s_lshr_b32 s11, s3, 8
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-FAKE16-NEXT: s_or_b32 s2, s2, s8
; GFX11-FAKE16-NEXT: s_and_b32 s8, s9, 0xff
+; GFX11-FAKE16-NEXT: s_lshr_b32 s11, s3, 8
; GFX11-FAKE16-NEXT: s_and_b32 s3, s3, 0xff
-; GFX11-FAKE16-NEXT: s_and_b32 s8, 0xffff, s8
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-FAKE16-NEXT: s_and_b32 s2, 0xffff, s2
; GFX11-FAKE16-NEXT: s_lshl_b32 s8, s8, 16
; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 8
-; GFX11-FAKE16-NEXT: s_and_b32 s9, s11, 0xff
-; GFX11-FAKE16-NEXT: s_or_b32 s3, s10, s3
-; GFX11-FAKE16-NEXT: s_and_b32 s9, 0xffff, s9
; GFX11-FAKE16-NEXT: s_or_b32 s2, s2, s8
; GFX11-FAKE16-NEXT: s_lshr_b32 s8, s4, 8
+; GFX11-FAKE16-NEXT: s_or_b32 s3, s10, s3
+; GFX11-FAKE16-NEXT: s_and_b32 s9, s11, 0xff
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_and_b32 s8, s8, 0xff
; GFX11-FAKE16-NEXT: s_and_b32 s3, 0xffff, s3
; GFX11-FAKE16-NEXT: s_lshl_b32 s9, s9, 16
-; GFX11-FAKE16-NEXT: s_and_b32 s8, s8, 0xff
-; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_and_b32 s10, s4, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s8, s8, 8
; GFX11-FAKE16-NEXT: s_or_b32 s3, s3, s9
; GFX11-FAKE16-NEXT: s_lshr_b32 s9, s4, 16
-; GFX11-FAKE16-NEXT: s_lshr_b32 s10, s4, 24
-; GFX11-FAKE16-NEXT: s_and_b32 s4, s4, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s8, s8, 8
-; GFX11-FAKE16-NEXT: s_lshr_b32 s11, s5, 8
-; GFX11-FAKE16-NEXT: s_or_b32 s4, s4, s8
-; GFX11-FAKE16-NEXT: s_and_b32 s8, s9, 0xff
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v0
+; GFX11-FAKE16-NEXT: s_or_b32 s8, s10, s8
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s10, v0
+; GFX11-FAKE16-NEXT: s_and_b32 s9, s9, 0xff
; GFX11-FAKE16-NEXT: s_and_b32 s8, 0xffff, s8
-; GFX11-FAKE16-NEXT: s_and_b32 s4, 0xffff, s4
-; GFX11-FAKE16-NEXT: s_lshl_b32 s8, s8, 16
+; GFX11-FAKE16-NEXT: s_lshl_b32 s9, s9, 16
+; GFX11-FAKE16-NEXT: s_lshr_b32 s11, s5, 8
+; GFX11-FAKE16-NEXT: s_or_b32 s8, s8, s9
+; GFX11-FAKE16-NEXT: s_mul_i32 s9, s10, 0xffffffe8
; GFX11-FAKE16-NEXT: s_and_b32 s5, s5, 0xff
-; GFX11-FAKE16-NEXT: s_or_b32 s4, s4, s8
-; GFX11-FAKE16-NEXT: s_mul_i32 s8, s9, 0xffffffe8
+; GFX11-FAKE16-NEXT: s_mul_hi_u32 s9, s10, s9
+; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s4, 24
+; GFX11-FAKE16-NEXT: s_add_i32 s10, s10, s9
; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s5, 8
-; GFX11-FAKE16-NEXT: s_mul_hi_u32 s8, s9, s8
-; GFX11-FAKE16-NEXT: s_or_b32 s5, s10, s5
-; GFX11-FAKE16-NEXT: s_add_i32 s9, s9, s8
-; GFX11-FAKE16-NEXT: s_and_b32 s10, s11, 0xff
-; GFX11-FAKE16-NEXT: s_mul_hi_u32 s8, s4, s9
-; GFX11-FAKE16-NEXT: s_and_b32 s10, 0xffff, s10
-; GFX11-FAKE16-NEXT: s_mulk_i32 s8, 0xffe8
-; GFX11-FAKE16-NEXT: s_and_b32 s5, 0xffff, s5
-; GFX11-FAKE16-NEXT: s_lshl_b32 s10, s10, 16
-; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, s8
+; GFX11-FAKE16-NEXT: s_mul_hi_u32 s9, s8, s10
+; GFX11-FAKE16-NEXT: s_or_b32 s4, s4, s5
+; GFX11-FAKE16-NEXT: s_and_b32 s5, s11, 0xff
+; GFX11-FAKE16-NEXT: s_mulk_i32 s9, 0xffe8
+; GFX11-FAKE16-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s5, 16
+; GFX11-FAKE16-NEXT: s_add_i32 s8, s8, s9
; GFX11-FAKE16-NEXT: s_and_b32 s0, 0xffff, s0
-; GFX11-FAKE16-NEXT: s_and_b32 s6, 0xffff, s6
; GFX11-FAKE16-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX11-FAKE16-NEXT: s_and_b32 s7, 0xffff, s7
-; GFX11-FAKE16-NEXT: s_or_b32 s5, s5, s10
-; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s4, 24
-; GFX11-FAKE16-NEXT: s_cselect_b32 s8, 1, 0
-; GFX11-FAKE16-NEXT: s_sub_i32 s10, s4, 24
-; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s8, 0
-; GFX11-FAKE16-NEXT: s_cselect_b32 s4, s10, s4
+; GFX11-FAKE16-NEXT: s_or_b32 s4, s4, s5
+; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s8, 24
+; GFX11-FAKE16-NEXT: s_cselect_b32 s5, 1, 0
+; GFX11-FAKE16-NEXT: s_sub_i32 s9, s8, 24
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s5, 0
+; GFX11-FAKE16-NEXT: s_cselect_b32 s5, s9, s8
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s4, 24
+; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s5, 24
; GFX11-FAKE16-NEXT: s_cselect_b32 s8, 1, 0
-; GFX11-FAKE16-NEXT: s_sub_i32 s10, s4, 24
+; GFX11-FAKE16-NEXT: s_sub_i32 s9, s5, 24
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s8, 0
-; GFX11-FAKE16-NEXT: s_cselect_b32 s4, s10, s4
+; GFX11-FAKE16-NEXT: s_cselect_b32 s5, s9, s5
; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s6, 17
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, 1
-; GFX11-FAKE16-NEXT: s_sub_i32 s8, 23, s4
+; GFX11-FAKE16-NEXT: s_sub_i32 s8, 23, s5
; GFX11-FAKE16-NEXT: s_or_b32 s0, s6, s0
-; GFX11-FAKE16-NEXT: s_mul_hi_u32 s6, s5, s9
+; GFX11-FAKE16-NEXT: s_mul_hi_u32 s6, s4, s10
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, s8
; GFX11-FAKE16-NEXT: s_mulk_i32 s6, 0xffe8
-; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s2, s4
-; GFX11-FAKE16-NEXT: s_add_i32 s5, s5, s6
+; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s2, s5
+; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, s6
; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s2
-; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s5, 24
+; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s4, 24
; GFX11-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-FAKE16-NEXT: s_sub_i32 s4, s5, 24
+; GFX11-FAKE16-NEXT: s_sub_i32 s5, s4, 24
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s2, 0
-; GFX11-FAKE16-NEXT: s_cselect_b32 s2, s4, s5
+; GFX11-FAKE16-NEXT: s_cselect_b32 s2, s5, s4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s2, 24
; GFX11-FAKE16-NEXT: s_cselect_b32 s4, 1, 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
index 344e16addf8a9..83e6d007f299a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
@@ -108,25 +108,22 @@ define amdgpu_ps i8 @s_lshr_i8(i8 inreg %value, i8 inreg %amount) {
;
; GFX8-LABEL: s_lshr_i8:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_and_b32 s0, s0, 0xff
; GFX8-NEXT: s_and_b32 s1, s1, 0xff
-; GFX8-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX8-NEXT: s_and_b32 s0, s0, 0xff
; GFX8-NEXT: s_lshr_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_lshr_i8:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_and_b32 s0, s0, 0xff
; GFX9-NEXT: s_and_b32 s1, s1, 0xff
-; GFX9-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX9-NEXT: s_and_b32 s0, s0, 0xff
; GFX9-NEXT: s_lshr_b32 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: s_lshr_i8:
; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xff
; GFX10PLUS-NEXT: s_and_b32 s1, s1, 0xff
-; GFX10PLUS-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xff
; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s1
; GFX10PLUS-NEXT: ; return to shader part epilog
%result = lshr i8 %value, %amount
@@ -142,21 +139,18 @@ define amdgpu_ps i8 @s_lshr_i8_7(i8 inreg %value) {
; GFX8-LABEL: s_lshr_i8_7:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_and_b32 s0, s0, 0xff
-; GFX8-NEXT: s_and_b32 s0, 0xffff, s0
; GFX8-NEXT: s_lshr_b32 s0, s0, 7
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_lshr_i8_7:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s0, s0, 0xff
-; GFX9-NEXT: s_and_b32 s0, 0xffff, s0
; GFX9-NEXT: s_lshr_b32 s0, s0, 7
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: s_lshr_i8_7:
; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xff
-; GFX10PLUS-NEXT: s_and_b32 s0, 0xffff, s0
; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, 7
; GFX10PLUS-NEXT: ; return to shader part epilog
%result = lshr i8 %value, 7
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
index 2530e82e6e015..9ccbeee37a03a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
@@ -31,11 +31,9 @@ define amdgpu_kernel void @v3i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1)
; GFX906-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX906-NEXT: v_lshrrev_b32_e32 v0, 8, v4
; GFX906-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX906-NEXT: v_and_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX906-NEXT: v_lshlrev_b16_e32 v0, 8, v0
-; GFX906-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX906-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX906-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX906-NEXT: v_and_b32_sdwa v1, v4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX906-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX906-NEXT: v_mov_b32_e32 v1, 0
; GFX906-NEXT: global_store_short v1, v0, s[6:7]
diff --git a/llvm/test/CodeGen/AMDGPU/anyext.ll b/llvm/test/CodeGen/AMDGPU/anyext.ll
index 3ede850bb0a9c..29b45774f395e 100644
--- a/llvm/test/CodeGen/AMDGPU/anyext.ll
+++ b/llvm/test/CodeGen/AMDGPU/anyext.ll
@@ -102,7 +102,6 @@ define amdgpu_kernel void @s_anyext_i16_i32(ptr addrspace(1) %out, ptr addrspace
; GFX8-NEXT: v_add_u16_e32 v0, v2, v0
; GFX8-NEXT: v_xor_b32_e32 v0, -1, v0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX8-NEXT: s_endpgm
;
@@ -121,7 +120,6 @@ define amdgpu_kernel void @s_anyext_i16_i32(ptr addrspace(1) %out, ptr addrspace
; GFX9-NEXT: v_add_u16_e32 v0, v2, v3
; GFX9-NEXT: v_xor_b32_e32 v0, -1, v0
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll
index 361ee48e0db68..d3e89cd1e469b 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16.ll
@@ -18840,26 +18840,21 @@ define amdgpu_ps i32 @s_fabs_bf16(bfloat inreg %a) #0 {
; GFX8-LABEL: s_fabs_bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_and_b32 s0, s0, 0x7fff
-; GFX8-NEXT: s_and_b32 s0, 0xffff, s0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_fabs_bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s0, s0, 0x7fff
-; GFX9-NEXT: s_and_b32 s0, 0xffff, s0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_fabs_bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s0, s0, 0x7fff
-; GFX10-NEXT: s_and_b32 s0, 0xffff, s0
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: s_fabs_bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_and_b32 s0, s0, 0x7fff
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s0, 0xffff, s0
; GFX11-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: s_fabs_bf16:
@@ -18869,8 +18864,6 @@ define amdgpu_ps i32 @s_fabs_bf16(bfloat inreg %a) #0 {
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT: s_and_b32 s0, s0, 0x7fff
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: s_and_b32 s0, 0xffff, s0
; GFX1250-NEXT: ; return to shader part epilog
%op = call bfloat @llvm.fabs.bf16(bfloat %a)
%cast = bitcast bfloat %op to i16
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
index fd469c3f069bf..c17376861d370 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
@@ -3669,7 +3669,6 @@ define void @store_v2i6(<2 x i6> %data, ptr addrspace(8) inreg %buf) {
; SDAG-NEXT: v_and_b32_e32 v0, 63, v0
; SDAG-NEXT: v_or_b32_e32 v0, v0, v1
; SDAG-NEXT: v_and_b32_e32 v0, 0xfff, v0
-; SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SDAG-NEXT: buffer_store_short v0, off, s[16:19], 0
; SDAG-NEXT: s_waitcnt vmcnt(0)
; SDAG-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
index 27d66a1886d0e..6bc5844c40324 100644
--- a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
@@ -871,34 +871,24 @@ define double @v_uitofp_to_f64_lshr24_mask255(i32 %arg0) nounwind {
}
define double @v_uitofp_i8_to_f64(i8 %arg0) nounwind {
-; SI-LABEL: v_uitofp_i8_to_f64:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_cvt_f64_u32_e32 v[0:1], v0
-; SI-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-LABEL: v_uitofp_i8_to_f64:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v1, 0xffff
-; VI-NEXT: v_and_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT: v_cvt_f64_u32_e32 v[0:1], v0
-; VI-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_uitofp_i8_to_f64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GCN-NEXT: v_cvt_f64_u32_e32 v[0:1], v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_uitofp_i8_to_f64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v1, 0xffff
-; GFX10-NEXT: v_and_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX10-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX10-NEXT: v_cvt_f64_u32_e32 v[0:1], v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_uitofp_i8_to_f64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b32 s4, 0xffff
-; GFX9-NEXT: v_and_b32_sdwa v0, s4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX9-NEXT: v_cvt_f64_u32_e32 v[0:1], v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -915,8 +905,7 @@ define double @v_uitofp_i8_to_f64(i8 %arg0) nounwind {
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f64_u32_e32 v[0:1], v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cvt = uitofp i8 %arg0 to double
diff --git a/llvm/test/CodeGen/AMDGPU/fabs.bf16.ll b/llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
index 179929a09592b..be4d3e4c0fcdb 100644
--- a/llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
@@ -240,8 +240,6 @@ define amdgpu_kernel void @s_fabs_v4bf16(ptr addrspace(1) %out, <4 x bfloat> %in
; VI-NEXT: s_lshr_b32 s2, s2, 16
; VI-NEXT: s_and_b32 s3, s3, 0x7fff
; VI-NEXT: s_and_b32 s2, s2, 0x7fff
-; VI-NEXT: s_and_b32 s4, 0xffff, s4
-; VI-NEXT: s_and_b32 s5, 0xffff, s5
; VI-NEXT: s_lshl_b32 s3, s3, 16
; VI-NEXT: s_lshl_b32 s2, s2, 16
; VI-NEXT: s_or_b32 s3, s4, s3
diff --git a/llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir b/llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir
index d4d8c28e8a5f5..ec8f1ef0ca1ff 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir
@@ -52,3 +52,105 @@ body: |
%4:vgpr_32 = V_AND_B32_e64 %3:sreg_32, killed %2:vgpr_32, implicit $exec
%5:vgpr_32 = V_MUL_U32_U24_e64 killed %4:vgpr_32, %1:sreg_32, 0, implicit $exec
...
+
+---
+name: no_fold_redundant_and_scc_live
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $sgpr2
+ ; GCN-LABEL: name: no_fold_redundant_and_scc_live
+ ; GCN: liveins: $sgpr0, $sgpr1, $sgpr2
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 255, implicit-def $scc
+ ; GCN-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_AND_B32_]], 4095, implicit-def $scc
+ ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GCN-NEXT: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY1]], [[COPY2]], implicit $scc
+ ; GCN-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_1]], implicit [[S_CSELECT_B32_]]
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 %0:sreg_32, 255, implicit-def $scc
+ %2:sreg_32 = S_AND_B32 %1:sreg_32, 4095, implicit-def $scc
+ %3:sreg_32 = COPY $sgpr1
+ %4:sreg_32 = COPY $sgpr2
+ %5:sreg_32 = S_CSELECT_B32 %3:sreg_32, %4:sreg_32, implicit $scc
+ S_ENDPGM 0, implicit %2:sreg_32, implicit %5:sreg_32
+...
+
+---
+name: fold_redundant_and_scc_dead
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; GCN-LABEL: name: fold_redundant_and_scc_dead
+ ; GCN: liveins: $sgpr0
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 16383, implicit-def dead $scc
+ ; GCN-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 %0:sreg_32, 16383, implicit-def dead $scc
+ %2:sreg_32 = S_AND_B32 %1:sreg_32, 32767, implicit-def dead $scc
+ S_ENDPGM 0, implicit %2:sreg_32
+...
+
+---
+name: fold_redundant_and_imm_in_src0
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; GCN-LABEL: name: fold_redundant_and_imm_in_src0
+ ; GCN: liveins: $sgpr0
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 127, [[COPY]], implicit-def dead $scc
+ ; GCN-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 127, %0:sreg_32, implicit-def dead $scc
+ %2:sreg_32 = S_AND_B32 255, %1:sreg_32, implicit-def dead $scc
+ S_ENDPGM 0, implicit %2:sreg_32
+...
+
+---
+name: fold_redundant_and_mixed_imm_positions
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; GCN-LABEL: name: fold_redundant_and_mixed_imm_positions
+ ; GCN: liveins: $sgpr0
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1023, implicit-def dead $scc
+ ; GCN-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 %0:sreg_32, 1023, implicit-def dead $scc
+ %2:sreg_32 = S_AND_B32 2047, %1:sreg_32, implicit-def dead $scc
+ S_ENDPGM 0, implicit %2:sreg_32
+...
+
+---
+name: fold_redundant_and_mixed_imm_positions_2
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; GCN-LABEL: name: fold_redundant_and_mixed_imm_positions_2
+ ; GCN: liveins: $sgpr0
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 8191, [[COPY]], implicit-def dead $scc
+ ; GCN-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 8191, %0:sreg_32, implicit-def dead $scc
+ %2:sreg_32 = S_AND_B32 %1:sreg_32, 65535, implicit-def dead $scc
+ S_ENDPGM 0, implicit %2:sreg_32
+...
diff --git a/llvm/test/CodeGen/AMDGPU/freeze.ll b/llvm/test/CodeGen/AMDGPU/freeze.ll
index 433dc96366e62..5d520d8e88e14 100644
--- a/llvm/test/CodeGen/AMDGPU/freeze.ll
+++ b/llvm/test/CodeGen/AMDGPU/freeze.ll
@@ -14301,16 +14301,15 @@ define void @freeze_v3i8(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX6-GISEL-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64
; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX6-GISEL-NEXT: v_lshrrev_b32_e32 v1, 8, v0
-; GFX6-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX6-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX6-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX6-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX6-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX6-GISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX6-GISEL-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX6-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX6-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v4
+; GFX6-GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX6-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX6-GISEL-NEXT: v_or_b32_e32 v0, v0, v4
; GFX6-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX6-GISEL-NEXT: buffer_store_short v0, v[2:3], s[4:7], 0 addr64
; GFX6-GISEL-NEXT: buffer_store_byte v1, v[2:3], s[4:7], 0 addr64 offset:2
@@ -14341,16 +14340,15 @@ define void @freeze_v3i8(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX7-GISEL-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v1, 8, v0
-; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX7-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX7-GISEL-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX7-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v4
+; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v4
; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX7-GISEL-NEXT: buffer_store_short v0, v[2:3], s[4:7], 0 addr64
; GFX7-GISEL-NEXT: buffer_store_byte v1, v[2:3], s[4:7], 0 addr64 offset:2
@@ -14379,11 +14377,9 @@ define void @freeze_v3i8(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX8-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX8-GISEL-NEXT: v_lshrrev_b32_e32 v6, 8, v4
-; GFX8-GISEL-NEXT: v_and_b32_sdwa v5, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX8-GISEL-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX8-GISEL-NEXT: v_lshlrev_b16_e32 v6, 8, v6
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX8-GISEL-NEXT: v_and_b32_sdwa v5, v4, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_or_b32_sdwa v4, v4, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_lshrrev_b32_e32 v5, 16, v4
@@ -14409,11 +14405,9 @@ define void @freeze_v3i8(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0xff
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v4, 8, v0
-; GFX9-GISEL-NEXT: v_and_b32_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX9-GISEL-NEXT: v_lshlrev_b16_e32 v4, 8, v4
-; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-GISEL-NEXT: v_and_b32_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-GISEL-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-GISEL-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-GISEL-NEXT: global_store_short v[2:3], v0, off
@@ -14437,11 +14431,9 @@ define void @freeze_v3i8(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 0xff
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10-GISEL-NEXT: v_lshrrev_b32_e32 v4, 8, v0
-; GFX10-GISEL-NEXT: v_and_b32_sdwa v5, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX10-GISEL-NEXT: v_and_b32_sdwa v1, v4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-GISEL-NEXT: v_and_b32_e32 v4, 0xffff, v5
-; GFX10-GISEL-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v4
+; GFX10-GISEL-NEXT: v_and_b32_sdwa v4, v4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_and_b32_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-GISEL-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-GISEL-NEXT: global_store_short v[2:3], v0, off
; GFX10-GISEL-NEXT: global_store_byte_d16_hi v[2:3], v0, off offset:2
@@ -14463,15 +14455,14 @@ define void @freeze_v3i8(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX11-GISEL-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v1, 8, v0
-; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v0
+; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-GISEL-NEXT: v_lshlrev_b16 v1, 8, v1
-; GFX11-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v4
-; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-GISEL-NEXT: v_or_b32_e32 v1, v4, v1
+; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX11-GISEL-NEXT: s_clause 0x1
; GFX11-GISEL-NEXT: global_store_b16 v[2:3], v0, off
; GFX11-GISEL-NEXT: global_store_d16_hi_b8 v[2:3], v0, off offset:2
@@ -17040,128 +17031,59 @@ define double @freeze_fabs_double(float %a, double %b, double %c) {
}
define <4 x float> @freeze_fabs_v4float(<4 x float> %A, <4 x float> %B) {
-; GFX6-SDAG-LABEL: freeze_fabs_v4float:
-; GFX6-SDAG: ; %bb.0:
-; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-SDAG-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; GFX6-SDAG-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; GFX6-SDAG-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX6-SDAG-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX6-GISEL-LABEL: freeze_fabs_v4float:
-; GFX6-GISEL: ; %bb.0:
-; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-GISEL-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; GFX6-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; GFX6-GISEL-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX6-GISEL-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; GFX6-GISEL-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; GFX6-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; GFX6-GISEL-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX6-GISEL-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX7-SDAG-LABEL: freeze_fabs_v4float:
-; GFX7-SDAG: ; %bb.0:
-; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; GFX7-SDAG-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX7-SDAG-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX7-GISEL-LABEL: freeze_fabs_v4float:
-; GFX7-GISEL: ; %bb.0:
-; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX7-GISEL-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX7-GISEL-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-SDAG-LABEL: freeze_fabs_v4float:
-; GFX8-SDAG: ; %bb.0:
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; GFX8-SDAG-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; GFX8-SDAG-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX8-SDAG-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: freeze_fabs_v4float:
-; GFX8-GISEL: ; %bb.0:
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; GFX8-GISEL-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX8-GISEL-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; GFX8-GISEL-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; GFX8-GISEL-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX8-GISEL-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX6-LABEL: freeze_fabs_v4float:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
+; GFX6-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-GISEL-LABEL: freeze_fabs_v4float:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX9-GISEL-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX9-GISEL-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX7-LABEL: freeze_fabs_v4float:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; GFX7-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX7-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
+; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-SDAG-LABEL: freeze_fabs_v4float:
-; GFX10-SDAG: ; %bb.0:
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; GFX10-SDAG-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; GFX10-SDAG-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX10-SDAG-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: freeze_fabs_v4float:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: freeze_fabs_v4float:
-; GFX10-GISEL: ; %bb.0:
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX10-GISEL-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX10-GISEL-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: freeze_fabs_v4float:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX9-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; GFX9-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX9-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-SDAG-LABEL: freeze_fabs_v4float:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; GFX11-SDAG-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; GFX11-SDAG-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX11-SDAG-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: freeze_fabs_v4float:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX10-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; GFX10-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX10-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-GISEL-LABEL: freeze_fabs_v4float:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; GFX11-GISEL-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX11-GISEL-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; GFX11-GISEL-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX11-GISEL-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: freeze_fabs_v4float:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX11-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; GFX11-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX11-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%A0 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %A)
%F1 = freeze <4 x float> %A0
%A1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %F1)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll b/llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
index 259074ef4c2d0..90ed943e88068 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
@@ -367,7 +367,6 @@ define i32 @func_fpmode_i32_environment_gfx6() {
; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX678-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 0, 19)
; GFX678-NEXT: s_and_b32 s4, 0x7f3ff, s4
-; GFX678-NEXT: s_and_b32 s4, s4, 0x7f3ff
; GFX678-NEXT: v_mov_b32_e32 v0, s4
; GFX678-NEXT: s_setpc_b64 s[30:31]
;
@@ -409,7 +408,6 @@ define i32 @func_fpmode_i32_environment_gfx9() {
; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX678-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 0, 19)
; GFX678-NEXT: s_and_b32 s4, 0x7f3ff, s4
-; GFX678-NEXT: s_and_b32 s4, s4, 0x87f3ff
; GFX678-NEXT: v_mov_b32_e32 v0, s4
; GFX678-NEXT: s_setpc_b64 s[30:31]
;
@@ -418,7 +416,6 @@ define i32 @func_fpmode_i32_environment_gfx9() {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 0, 24)
; GFX9-NEXT: s_and_b32 s4, 0x87f3ff, s4
-; GFX9-NEXT: s_and_b32 s4, s4, 0x87f3ff
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -427,7 +424,6 @@ define i32 @func_fpmode_i32_environment_gfx9() {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 0, 24)
; GFX10-NEXT: s_and_b32 s4, 0x87f3ff, s4
-; GFX10-NEXT: s_and_b32 s4, s4, 0x87f3ff
; GFX10-NEXT: v_mov_b32_e32 v0, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -436,7 +432,6 @@ define i32 @func_fpmode_i32_environment_gfx9() {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 0, 24)
; GFX11-NEXT: s_and_b32 s0, 0x87f3ff, s0
-; GFX11-NEXT: s_and_b32 s0, s0, 0x87f3ff
; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fpmode = call i32 @llvm.get.fpmode.i32()
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
index f6585c596115f..037384edd0906 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
@@ -37,7 +37,6 @@ define amdgpu_kernel void @sgpr_isnan_f16(ptr addrspace(1) %out, half %x) {
; GFX7GLISEL-NEXT: s_mov_b32 s2, -1
; GFX7GLISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX7GLISEL-NEXT: s_and_b32 s3, s3, 0x7fff
-; GFX7GLISEL-NEXT: s_and_b32 s3, 0xffff, s3
; GFX7GLISEL-NEXT: s_cmpk_gt_u32 s3, 0x7c00
; GFX7GLISEL-NEXT: s_cselect_b32 s3, -1, 0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v0, s3
@@ -274,7 +273,6 @@ define i1 @snan_f16(half %x) nounwind {
; GFX7GLISEL: ; %bb.0:
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xffff83ff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x1ff
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
@@ -349,7 +347,6 @@ define i1 @qnan_f16(half %x) nounwind {
; GFX7GLISEL: ; %bb.0:
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7e00
; GFX7GLISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
@@ -577,8 +574,7 @@ define i1 @posnormal_f16(half %x) nounwind {
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v1
-; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v2
+; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v1
; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v1
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
@@ -663,8 +659,7 @@ define i1 @negnormal_f16(half %x) nounwind {
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v1
-; GFX7GLISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], v0, v2
+; GFX7GLISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], v0, v1
; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v1
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
@@ -823,8 +818,7 @@ define i1 @negsubnormal_f16(half %x) nounwind {
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v1
-; GFX7GLISEL-NEXT: v_cmp_ne_u32_e32 vcc, v0, v2
+; GFX7GLISEL-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: v_add_i32_e64 v0, s[4:5], -1, v1
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x3ff
@@ -1116,7 +1110,6 @@ define i1 @negfinite_f16(half %x) nounwind {
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7GLISEL-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: v_mov_b32_e32 v0, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v1, v0
@@ -1192,7 +1185,6 @@ define i1 @isnan_f16(half %x) nounwind {
; GFX7GLISEL: ; %bb.0:
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
@@ -1266,7 +1258,6 @@ define i1 @not_isnan_f16(half %x) {
; GFX7GLISEL: ; %bb.0:
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c01
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
@@ -1346,10 +1337,8 @@ define <2 x i1> @isnan_v2f16(<2 x half> %x) nounwind {
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v1
-; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v0, v2
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v1, v2
@@ -1483,13 +1472,10 @@ define <3 x i1> @isnan_v3f16(<3 x half> %x) nounwind {
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v3, 0x7c00
; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0x7fff, v2
-; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v1
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v0, v3
-; GFX7GLISEL-NEXT: v_and_b32_e32 v4, 0xffff, v1
+; GFX7GLISEL-NEXT: v_and_b32_e32 v4, 0x7fff, v1
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v2, v3
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
@@ -1657,18 +1643,14 @@ define <4 x i1> @isnan_v4f16(<4 x half> %x) nounwind {
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v4, 0x7c00
; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0x7fff, v2
-; GFX7GLISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v1
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v0, v4
-; GFX7GLISEL-NEXT: v_and_b32_e32 v5, 0xffff, v1
-; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v3
+; GFX7GLISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX7GLISEL-NEXT: v_and_b32_e32 v5, 0x7fff, v1
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v2, v4
-; GFX7GLISEL-NEXT: v_and_b32_e32 v3, 0xffff, v1
+; GFX7GLISEL-NEXT: v_and_b32_e32 v3, 0x7fff, v3
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v5, v4
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
@@ -1849,7 +1831,6 @@ define i1 @isnan_f16_strictfp(half %x) strictfp nounwind {
; GFX7GLISEL: ; %bb.0:
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
@@ -1923,7 +1904,6 @@ define i1 @isinf_f16(half %x) nounwind {
; GFX7GLISEL: ; %bb.0:
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
@@ -2000,7 +1980,6 @@ define i1 @isfinite_f16(half %x) nounwind {
; GFX7GLISEL: ; %bb.0:
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
@@ -2063,22 +2042,13 @@ define i1 @isfinite_f16(half %x) nounwind {
}
define i1 @issubnormal_or_zero_f16(half %x) {
-; GFX7SELDAG-LABEL: issubnormal_or_zero_f16:
-; GFX7SELDAG: ; %bb.0: ; %entry
-; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7c00, v0
-; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX7GLISEL-LABEL: issubnormal_or_zero_f16:
-; GFX7GLISEL: ; %bb.0: ; %entry
-; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7c00, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX7CHECK-LABEL: issubnormal_or_zero_f16:
+; GFX7CHECK: ; %bb.0: ; %entry
+; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7CHECK-NEXT: v_and_b32_e32 v0, 0x7c00, v0
+; GFX7CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX7CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX7CHECK-NEXT: s_setpc_b64 s[30:31]
;
; GFX8CHECK-LABEL: issubnormal_or_zero_f16:
; GFX8CHECK: ; %bb.0: ; %entry
@@ -2150,10 +2120,9 @@ define i1 @not_issubnormal_or_zero_f16(half %x) {
; GFX7GLISEL: ; %bb.0: ; %entry
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
-; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
+; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
+; GFX7GLISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v1
; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
-; GFX7GLISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v2
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
@@ -2313,14 +2282,12 @@ define i1 @not_isnormal_f16(half %x) {
; GFX7GLISEL: ; %bb.0:
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7c00, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
+; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7c00, v0
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v1
-; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v2
+; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v0, v2
+; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v1, v2
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2401,15 +2368,13 @@ define i1 @not_is_plus_normal_f16(half %x) {
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v3, 0xffff, v1
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7c00, v0
-; GFX7GLISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], v2, v3
+; GFX7GLISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], v2, v1
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7c00, v0
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], v3, v2
+; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], v1, v2
; GFX7GLISEL-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
-; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v3, v2
+; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v1, v2
; GFX7GLISEL-NEXT: s_or_b64 s[6:7], s[6:7], vcc
; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v1
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -2496,15 +2461,13 @@ define i1 @not_is_neg_normal_f16(half %x) {
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v3, 0xffff, v1
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7c00, v0
-; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v2, v3
+; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v2, v1
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7c00, v0
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], v3, v2
+; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], v1, v2
; GFX7GLISEL-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
-; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v3, v2
+; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v1, v2
; GFX7GLISEL-NEXT: s_or_b64 s[6:7], s[6:7], vcc
; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v1
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -2664,12 +2627,11 @@ define i1 @not_issubnormal_f16(half %x) {
; GFX7GLISEL: ; %bb.0:
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
-; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
-; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2
+; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
+; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v1
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v1, v2
+; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -2736,22 +2698,13 @@ define i1 @not_issubnormal_f16(half %x) {
}
define i1 @iszero_f16(half %x) {
-; GFX7SELDAG-LABEL: iszero_f16:
-; GFX7SELDAG: ; %bb.0:
-; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX7GLISEL-LABEL: iszero_f16:
-; GFX7GLISEL: ; %bb.0:
-; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX7CHECK-LABEL: iszero_f16:
+; GFX7CHECK: ; %bb.0:
+; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v0
+; GFX7CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX7CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX7CHECK-NEXT: s_setpc_b64 s[30:31]
;
; GFX8CHECK-LABEL: iszero_f16:
; GFX8CHECK: ; %bb.0:
@@ -2826,11 +2779,10 @@ define i1 @not_iszero_f16(half %x) {
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
-; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
-; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
-; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2
+; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
+; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v1
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v1, v2
+; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -2995,7 +2947,6 @@ define i1 @not_ispositive_f16(half %x) {
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v1, v2
@@ -3084,7 +3035,6 @@ define i1 @isnegative_f16(half %x) {
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v1, v2
@@ -3170,9 +3120,8 @@ define i1 @not_isnegative_f16(half %x) {
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c01
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v2
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v1
-; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
-; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1
+; GFX7GLISEL-NEXT: v_mov_b32_e32 v0, 0x7c00
+; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v1, v0
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
@@ -3249,7 +3198,6 @@ define i1 @iszero_or_nan_f16(half %x) {
; GFX7GLISEL: ; %bb.0: ; %entry
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xffff83ff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0xffff8400
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
@@ -3329,7 +3277,6 @@ define i1 @iszero_or_nan_f_daz(half %x) #0 {
; GFX7GLISEL: ; %bb.0: ; %entry
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xffff83ff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0xffff8400
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
@@ -3409,7 +3356,6 @@ define i1 @iszero_or_nan_f_maybe_daz(half %x) #1 {
; GFX7GLISEL: ; %bb.0: ; %entry
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xffff83ff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0xffff8400
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
@@ -3493,9 +3439,8 @@ define i1 @not_iszero_or_nan_f16(half %x) {
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
-; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
-; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
-; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2
+; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
+; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v1
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -3582,9 +3527,8 @@ define i1 @not_iszero_or_nan_f_daz(half %x) #0 {
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
-; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
-; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
-; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2
+; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
+; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v1
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -3671,9 +3615,8 @@ define i1 @not_iszero_or_nan_f_maybe_daz(half %x) #1 {
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
-; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
-; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
-; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2
+; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
+; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v1
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -3756,7 +3699,6 @@ define i1 @iszero_or_qnan_f16(half %x) {
; GFX7GLISEL: ; %bb.0: ; %entry
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xffff8200, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0xffff8201
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
@@ -3839,7 +3781,6 @@ define i1 @iszero_or_snan_f16(half %x) {
; GFX7GLISEL: ; %bb.0: ; %entry
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xffff83ff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x1ff
@@ -3937,11 +3878,10 @@ define i1 @not_iszero_or_qnan_f16(half %x) {
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
-; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
-; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
-; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2
+; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
+; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v1
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; GFX7GLISEL-NEXT: v_add_i32_e32 v1, vcc, 0xffff83ff, v1
+; GFX7GLISEL-NEXT: v_add_i32_e32 v1, vcc, 0xffff83ff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x1ff
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
@@ -4040,12 +3980,11 @@ define i1 @not_iszero_or_snan_f16(half %x) {
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
-; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
-; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
-; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2
-; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7e00
+; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
+; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v1
+; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7e00
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; GFX7GLISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
+; GFX7GLISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -4127,7 +4066,6 @@ define i1 @isinf_or_nan_f16(half %x) {
; GFX7GLISEL: ; %bb.0: ; %entry
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
@@ -4205,7 +4143,6 @@ define i1 @not_isinf_or_nan_f16(half %x) {
; GFX7GLISEL: ; %bb.0: ; %entry
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
@@ -4282,7 +4219,6 @@ define i1 @isfinite_or_nan_f(half %x) {
; GFX7GLISEL: ; %bb.0: ; %entry
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
@@ -4359,7 +4295,6 @@ define i1 @not_isfinite_or_nan_f(half %x) {
; GFX7GLISEL: ; %bb.0: ; %entry
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
index 9b2524929edf7..70d0d38eb656a 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
@@ -5562,10 +5562,8 @@ define amdgpu_kernel void @constant_zextload_v2i1_to_v2i64(ptr addrspace(1) %out
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 1, v2
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX12-TRUE16-NEXT: global_store_b128 v1, v[0:3], s[0:1]
; GFX12-TRUE16-NEXT: s_endpgm
@@ -5581,10 +5579,8 @@ define amdgpu_kernel void @constant_zextload_v2i1_to_v2i64(ptr addrspace(1) %out
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 1, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX12-FAKE16-NEXT: global_store_b128 v1, v[0:3], s[0:1]
; GFX12-FAKE16-NEXT: s_endpgm
@@ -5606,9 +5602,8 @@ define amdgpu_kernel void @constant_zextload_v2i1_to_v2i64(ptr addrspace(1) %out
; GFX1250-TRUE16-NEXT: s_and_b32 s3, 0xffff, s2
; GFX1250-TRUE16-NEXT: s_and_b32 s2, s2, 1
; GFX1250-TRUE16-NEXT: s_lshr_b32 s3, s3, 1
-; GFX1250-TRUE16-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-TRUE16-NEXT: s_and_b32 s3, 0xffff, s3
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s3
; GFX1250-TRUE16-NEXT: global_store_b128 v1, v[0:3], s[0:1]
; GFX1250-TRUE16-NEXT: s_endpgm
@@ -5628,8 +5623,7 @@ define amdgpu_kernel void @constant_zextload_v2i1_to_v2i64(ptr addrspace(1) %out
; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v0
; GFX1250-FAKE16-NEXT: v_dual_lshrrev_b32 v2, 1, v2 :: v_dual_bitop2_b32 v0, 1, v0 bitop3:0x40
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX1250-FAKE16-NEXT: global_store_b128 v1, v[0:3], s[0:1]
; GFX1250-FAKE16-NEXT: s_endpgm
@@ -5865,14 +5859,13 @@ define amdgpu_kernel void @constant_zextload_v3i1_to_v3i64(ptr addrspace(1) %out
; GFX12-TRUE16-NEXT: global_load_d16_u8 v0, v5, s[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v0
-; GFX12-TRUE16-NEXT: v_bfe_u32 v2, v0, 1, 1
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v3, v5 :: v_dual_and_b32 v0, 1, v0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 2, v1
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_and_b32 v2, 0xffff, v2
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v0, 1, 1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 2, v1
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v5
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_and_b32 v4, 0xffff, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v6
; GFX12-TRUE16-NEXT: s_clause 0x1
; GFX12-TRUE16-NEXT: global_store_b64 v5, v[4:5], s[0:1] offset:16
; GFX12-TRUE16-NEXT: global_store_b128 v5, v[0:3], s[0:1]
@@ -5886,14 +5879,13 @@ define amdgpu_kernel void @constant_zextload_v3i1_to_v3i64(ptr addrspace(1) %out
; GFX12-FAKE16-NEXT: global_load_u8 v0, v5, s[2:3]
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v0
-; GFX12-FAKE16-NEXT: v_bfe_u32 v2, v0, 1, 1
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v3, v5 :: v_dual_and_b32 v0, 1, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 2, v1
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_and_b32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX12-FAKE16-NEXT: v_bfe_u32 v6, v0, 1, 1
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 2, v1
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v5
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_and_b32 v4, 0xffff, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v6
; GFX12-FAKE16-NEXT: s_clause 0x1
; GFX12-FAKE16-NEXT: global_store_b64 v5, v[4:5], s[0:1] offset:16
; GFX12-FAKE16-NEXT: global_store_b128 v5, v[0:3], s[0:1]
@@ -5918,10 +5910,9 @@ define amdgpu_kernel void @constant_zextload_v3i1_to_v3i64(ptr addrspace(1) %out
; GFX1250-TRUE16-NEXT: s_lshr_b32 s3, s3, 2
; GFX1250-TRUE16-NEXT: s_and_b32 s2, s2, 1
; GFX1250-TRUE16-NEXT: s_and_b32 s3, 0xffff, s3
-; GFX1250-TRUE16-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v0, s3
; GFX1250-TRUE16-NEXT: s_and_b32 s3, 0xffff, s4
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v2, s3
; GFX1250-TRUE16-NEXT: global_store_b64 v1, v[0:1], s[0:1] offset:16
; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0
@@ -5937,20 +5928,18 @@ define amdgpu_kernel void @constant_zextload_v3i1_to_v3i64(ptr addrspace(1) %out
; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v5, 0
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v3, v5
; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-FAKE16-NEXT: global_load_u8 v0, v5, s[2:3] nv
+; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v3, v5
; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v0
-; GFX1250-FAKE16-NEXT: v_bfe_u32 v2, v0, 1, 1
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1250-FAKE16-NEXT: v_dual_lshrrev_b32 v4, 2, v1 :: v_dual_bitop2_b32 v0, 1, v0 bitop3:0x40
+; GFX1250-FAKE16-NEXT: v_bfe_u32 v6, v0, 1, 1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_dual_lshrrev_b32 v2, 2, v1 :: v_dual_bitop2_b32 v0, 1, v0 bitop3:0x40
; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v1, v5
-; GFX1250-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1250-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX1250-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v2
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v6
; GFX1250-FAKE16-NEXT: s_clause 0x1
; GFX1250-FAKE16-NEXT: global_store_b64 v5, v[4:5], s[0:1] offset:16
; GFX1250-FAKE16-NEXT: global_store_b128 v5, v[0:3], s[0:1]
@@ -6246,10 +6235,9 @@ define amdgpu_kernel void @constant_zextload_v4i1_to_v4i64(ptr addrspace(1) %out
; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_b32 s3, 0xffff, s3
-; GFX12-TRUE16-NEXT: s_and_b32 s2, 0xffff, s2
; GFX12-TRUE16-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:16
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s3
; GFX12-TRUE16-NEXT: global_store_b128 v1, v[0:3], s[0:1]
; GFX12-TRUE16-NEXT: s_endpgm
@@ -6276,10 +6264,9 @@ define amdgpu_kernel void @constant_zextload_v4i1_to_v4i64(ptr addrspace(1) %out
; GFX12-FAKE16-NEXT: s_and_b32 s2, s2, 1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_b32 s3, 0xffff, s3
-; GFX12-FAKE16-NEXT: s_and_b32 s2, 0xffff, s2
; GFX12-FAKE16-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:16
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s3
; GFX12-FAKE16-NEXT: global_store_b128 v1, v[0:3], s[0:1]
; GFX12-FAKE16-NEXT: s_endpgm
@@ -6306,7 +6293,6 @@ define amdgpu_kernel void @constant_zextload_v4i1_to_v4i64(ptr addrspace(1) %out
; GFX1250-TRUE16-NEXT: s_bfe_u32 s3, s2, 0x10001
; GFX1250-TRUE16-NEXT: s_and_b32 s2, s2, 1
; GFX1250-TRUE16-NEXT: s_and_b32 s3, 0xffff, s3
-; GFX1250-TRUE16-NEXT: s_and_b32 s2, 0xffff, s2
; GFX1250-TRUE16-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:16
; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0
; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s3
@@ -6338,7 +6324,6 @@ define amdgpu_kernel void @constant_zextload_v4i1_to_v4i64(ptr addrspace(1) %out
; GFX1250-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX1250-FAKE16-NEXT: s_and_b32 s2, s2, 1
; GFX1250-FAKE16-NEXT: s_and_b32 s3, 0xffff, s3
-; GFX1250-FAKE16-NEXT: s_and_b32 s2, 0xffff, s2
; GFX1250-FAKE16-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:16
; GFX1250-FAKE16-NEXT: s_wait_xcnt 0x0
; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s3
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
index b72378e801b01..2c7e9c0d047a5 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
@@ -9526,10 +9526,8 @@ define amdgpu_kernel void @constant_zextload_v2i8_to_v2i16(ptr addrspace(1) %out
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 8, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX12-FAKE16-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12-FAKE16-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
index 57f33f2fdb4ef..7fd10a09d032d 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
@@ -280,15 +280,15 @@ define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack(half %src0, half %src1, ha
; SDAG-GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SDAG-GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-VI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SDAG-VI-NEXT: v_mac_f32_e32 v2, v0, v1
-; SDAG-VI-NEXT: v_cvt_f16_f32_sdwa v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; VI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; VI-NEXT: v_mac_f32_e32 v2, v0, v1
+; VI-NEXT: v_cvt_f16_f32_sdwa v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; VI-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:
; SDAG-CI: ; %bb.0:
@@ -318,18 +318,6 @@ define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack(half %src0, half %src1, ha
; GISEL-GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GISEL-GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-VI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GISEL-VI-NEXT: v_mac_f32_e32 v2, v0, v1
-; GISEL-VI-NEXT: v_cvt_f16_f32_e32 v0, v2
-; GISEL-VI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GISEL-VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
-;
; GISEL-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -338,7 +326,6 @@ define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack(half %src0, half %src1, ha
; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v2, v2
; GISEL-CI-NEXT: v_mac_f32_e32 v2, v0, v1
; GISEL-CI-NEXT: v_cvt_f16_f32_e32 v0, v2
-; GISEL-CI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GISEL-CI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GISEL-CI-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
@@ -752,4 +739,3 @@ attributes #0 = { nounwind denormal_fpenv(float: preservesign) }
attributes #1 = { nounwind readnone speculatable }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GISEL-GFX11-FAKE16: {{.*}}
-; VI: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
index cfa2fa199dc0d..2361da33368b2 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
@@ -2590,12 +2590,12 @@ define i32 @mixlo_zext(float %src0, float %src1, float %src2) #0 {
; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX906-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-VI-LABEL: mixlo_zext:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-VI-NEXT: v_mac_f32_e32 v2, v0, v1
-; SDAG-VI-NEXT: v_cvt_f16_f32_e32 v0, v2
-; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: mixlo_zext:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_mac_f32_e32 v2, v0, v1
+; VI-NEXT: v_cvt_f16_f32_e32 v0, v2
+; VI-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-CI-LABEL: mixlo_zext:
; SDAG-CI: ; %bb.0:
@@ -2612,20 +2612,11 @@ define i32 @mixlo_zext(float %src0, float %src1, float %src2) #0 {
; GISEL-GFX1100-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-VI-LABEL: mixlo_zext:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-VI-NEXT: v_mac_f32_e32 v2, v0, v1
-; GISEL-VI-NEXT: v_cvt_f16_f32_e32 v0, v2
-; GISEL-VI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
-;
; GISEL-CI-LABEL: mixlo_zext:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-CI-NEXT: v_mac_f32_e32 v2, v0, v1
; GISEL-CI-NEXT: v_cvt_f16_f32_e32 v0, v2
-; GISEL-CI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GISEL-CI-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.fmuladd.f32(float %src0, float %src1, float %src2)
%cvt.result = fptrunc float %result to half
diff --git a/llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-fail.ll b/llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-fail.ll
index 0e7c225cadef1..15d27a04883a0 100644
--- a/llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-fail.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-fail.ll
@@ -20,17 +20,15 @@ define void @quux(i32 %arg, i1 %arg1, i1 %arg2) {
; CHECK-NEXT: v_and_b32_e32 v1, 0x3ff, v31
; CHECK-NEXT: v_mov_b32_e32 v2, 0
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; CHECK-NEXT: v_mov_b32_e32 v0, 24
; CHECK-NEXT: v_mul_u32_u24_e32 v1, 5, v1
; CHECK-NEXT: global_load_ushort v1, v[1:2], off offset:3
-; CHECK-NEXT: v_mov_b32_e32 v2, 0xffff
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: v_and_b32_sdwa v0, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; CHECK-NEXT: v_mov_b32_e32 v1, 24
+; CHECK-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; CHECK-NEXT: v_mov_b32_e32 v2, 0xff
-; CHECK-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo
-; CHECK-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; CHECK-NEXT: v_and_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; CHECK-NEXT: v_or_b32_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; CHECK-NEXT: v_lshrrev_b32_sdwa v0, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; CHECK-NEXT: v_and_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; CHECK-NEXT: v_or_b32_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; CHECK-NEXT: .LBB0_2: ; %bb9
; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s4
; CHECK-NEXT: v_mov_b32_e32 v2, 0
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll b/llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll
index c0c7c075d8e9b..13cfd59db90e6 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll
@@ -47,7 +47,6 @@ define <2 x half> @v_constrained_fptrunc_v2f32_to_v2f16_fpexcept_strict(<2 x flo
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -99,12 +98,10 @@ define <3 x half> @v_constrained_fptrunc_v3f32_to_v3f16_fpexcept_strict(<3 x flo
; SI-LABEL: v_constrained_fptrunc_v3f32_to_v3f16_fpexcept_strict:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_cvt_f16_f32_e32 v3, v1
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v0, v0, v2
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -347,7 +344,6 @@ define void @v_constrained_fptrunc_v2f32_to_v2f16_fpexcept_strict_noabi(<2 x flo
; SI-NEXT: s_mov_b32 s6, 0
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s6
; SI-NEXT: v_or_b32_e32 v0, v0, v1
diff --git a/llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll b/llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll
index 643956f6bda9b..6fcf0247747ef 100644
--- a/llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll
+++ b/llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll
@@ -116,7 +116,6 @@ define <2 x half> @v2f16_return(<2 x float> %arg) #0 {
; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-NEXT: s_setpc_b64 s[30:31]
%fptrunc = call <2 x half> @llvm.experimental.constrained.fptrunc.v2f16.v2f32(<2 x float> %arg, metadata !"round.tonearest", metadata !"fpexcept.strict")
@@ -127,12 +126,10 @@ define <3 x half> @v3f16_return(<3 x float> %arg) #0 {
; GFX7-LABEL: v3f16_return:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX7-NEXT: v_cvt_f16_f32_e32 v3, v1
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v2
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
; GFX7-NEXT: s_setpc_b64 s[30:31]
%fptrunc = call <3 x half> @llvm.experimental.constrained.fptrunc.v3f16.v3f32(<3 x float> %arg, metadata !"round.tonearest", metadata !"fpexcept.strict")
@@ -143,16 +140,14 @@ define <4 x half> @v4f16_return(<4 x float> %arg) #0 {
; GFX7-LABEL: v4f16_return:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v2
-; GFX7-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX7-NEXT: v_or_b32_e32 v1, v2, v3
; GFX7-NEXT: s_setpc_b64 s[30:31]
%fptrunc = call <4 x half> @llvm.experimental.constrained.fptrunc.v4f16.v4f32(<4 x float> %arg, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret <4 x half> %fptrunc
diff --git a/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll b/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
index d7aea1bc2c327..bfb499108b158 100644
--- a/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
@@ -578,26 +578,17 @@ define amdgpu_kernel void @s_uint_to_fp_i8_to_f64(ptr addrspace(1) %out, i8 %in)
; FIXME: Worse on VI
define double @v_uint_to_fp_i8_to_f64(i8 %in) {
-; SI-LABEL: v_uint_to_fp_i8_to_f64:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_cvt_f64_u32_e32 v[0:1], v0
-; SI-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-LABEL: v_uint_to_fp_i8_to_f64:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v1, 0xffff
-; VI-NEXT: v_and_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT: v_cvt_f64_u32_e32 v[0:1], v0
-; VI-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_uint_to_fp_i8_to_f64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GCN-NEXT: v_cvt_f64_u32_e32 v[0:1], v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_uint_to_fp_i8_to_f64:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: s_mov_b32 s0, 0xffff
-; GFX942-NEXT: v_and_b32_sdwa v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX942-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX942-NEXT: v_cvt_f64_u32_e32 v[0:1], v0
; GFX942-NEXT: s_setpc_b64 s[30:31]
%fp = uitofp i8 %in to double
>From d85d7f11638b4fdb8fdc0500d6345a54d6c8d9b1 Mon Sep 17 00:00:00 2001
From: John Lu <John.Lu at amd.com>
Date: Tue, 18 Aug 2026 14:20:00 -0500
Subject: [PATCH 2/3] Put and instruction analysis in method and return result
in struct
Signed-off-by: John Lu <John.Lu at amd.com>
---
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 72 ++++++++++++-----------
1 file changed, 39 insertions(+), 33 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 02812c9170490..cc1ce99d8de4a 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -248,6 +248,14 @@ class SIFoldOperandsImpl {
SmallVectorImpl<FoldCandidate> &FoldList,
SmallVectorImpl<MachineInstr *> &CopiesToReplace) const;
+ struct AndMaskResult {
+ int64_t Mask;
+ Register Reg;
+ unsigned RegIdx;
+ };
+
+ std::optional<AndMaskResult> getAndMaskRegOperand(MachineInstr &AndMI) const;
+
bool tryConstantFoldOp(MachineInstr *MI) const;
bool tryFoldCndMask(MachineInstr &MI) const;
bool tryFoldRedundantAnd(MachineInstr &ChildMI) const;
@@ -1855,6 +1863,27 @@ bool SIFoldOperandsImpl::tryFoldCndMask(MachineInstr &MI) const {
return true;
}
+// Extract mask, register, and register operand index from an AND instruction.
+// Immediate can be in operand 1 or 2.
+std::optional<SIFoldOperandsImpl::AndMaskResult>
+SIFoldOperandsImpl::getAndMaskRegOperand(MachineInstr &AndMI) const {
+ unsigned Opc = AndMI.getOpcode();
+ if (Opc != AMDGPU::V_AND_B32_e64 && Opc != AMDGPU::V_AND_B32_e32 &&
+ Opc != AMDGPU::S_AND_B32)
+ return std::nullopt;
+
+ std::optional<int64_t> MaskImm =
+ TII->getImmOrMaterializedImm(AndMI.getOperand(1));
+ if (MaskImm && AndMI.getOperand(2).isReg())
+ return AndMaskResult{*MaskImm, AndMI.getOperand(2).getReg(), 2};
+
+ MaskImm = TII->getImmOrMaterializedImm(AndMI.getOperand(2));
+ if (MaskImm && AndMI.getOperand(1).isReg())
+ return AndMaskResult{*MaskImm, AndMI.getOperand(1).getReg(), 1};
+
+ return std::nullopt;
+}
+
// Eliminate redundant AND operations by detecting when ChildMI's mask contains
// ParentMI's mask.
//
@@ -1870,40 +1899,17 @@ bool SIFoldOperandsImpl::tryFoldRedundantAnd(MachineInstr &ChildMI) const {
if (!ChildMI.allImplicitDefsAreDead())
return false;
- // Helper to extract mask, register, and register operand index from an AND
- // instruction. Mask can be detected in either operand 1 or 2. Returns {mask,
- // register, operand_index}.
- auto getMaskAndReg = [this](MachineInstr &AndMI)
- -> std::optional<std::tuple<int64_t, Register, unsigned>> {
- unsigned Opc = AndMI.getOpcode();
- if (Opc != AMDGPU::V_AND_B32_e64 && Opc != AMDGPU::V_AND_B32_e32 &&
- Opc != AMDGPU::S_AND_B32)
- return std::nullopt;
-
- std::optional<int64_t> MaskImm =
- TII->getImmOrMaterializedImm(AndMI.getOperand(1));
- if (MaskImm && AndMI.getOperand(2).isReg())
- return std::make_tuple(*MaskImm, AndMI.getOperand(2).getReg(), 2);
-
- MaskImm = TII->getImmOrMaterializedImm(AndMI.getOperand(2));
- if (MaskImm && AndMI.getOperand(1).isReg())
- return std::make_tuple(*MaskImm, AndMI.getOperand(1).getReg(), 1);
-
- return std::nullopt;
- };
-
- auto ChildMaskAndReg = getMaskAndReg(ChildMI);
- if (!ChildMaskAndReg)
+ std::optional<AndMaskResult> ChildResult = getAndMaskRegOperand(ChildMI);
+ if (!ChildResult)
return false;
- auto [ChildMask, ChildReg, ChildRegIdx] = *ChildMaskAndReg;
- MachineInstr *ParentMI = MRI->getVRegDef(ChildReg);
+ MachineInstr *ParentMI = MRI->getVRegDef(ChildResult->Reg);
int64_t ParentMask;
- auto ParentMaskAndReg = getMaskAndReg(*ParentMI);
- if (ParentMaskAndReg) {
+ std::optional<AndMaskResult> ParentResult = getAndMaskRegOperand(*ParentMI);
+ if (ParentResult) {
// Parent is an AND - extract its mask.
- ParentMask = std::get<0>(*ParentMaskAndReg);
+ ParentMask = ParentResult->Mask;
} else if (ST->zeroesHigh16BitsOfDest(ParentMI->getOpcode())) {
// Parent instruction implicitly zeros high 16 bits.
ParentMask = 0xffff;
@@ -1912,15 +1918,15 @@ bool SIFoldOperandsImpl::tryFoldRedundantAnd(MachineInstr &ChildMI) const {
}
// Check if ChildMI is not redundant.
- if ((ParentMask & ChildMask) != ParentMask)
+ if ((ParentMask & ChildResult->Mask) != ParentMask)
return false;
Register Dst = ChildMI.getOperand(0).getReg();
- MRI->replaceRegWith(Dst, ChildReg);
+ MRI->replaceRegWith(Dst, ChildResult->Reg);
// Clear kill flags if the register operand is not marked as kill.
- if (!ChildMI.getOperand(ChildRegIdx).isKill())
- MRI->clearKillFlags(ChildReg);
+ if (!ChildMI.getOperand(ChildResult->RegIdx).isKill())
+ MRI->clearKillFlags(ChildResult->Reg);
ChildMI.eraseFromParent();
return true;
>From 7aa863ded7a0001efc43949f7ad5ffb833381650 Mon Sep 17 00:00:00 2001
From: John Lu <John.Lu at amd.com>
Date: Tue, 18 Aug 2026 17:35:30 -0500
Subject: [PATCH 3/3] Add extensive testing
Signed-off-by: John Lu <John.Lu at amd.com>
---
.../fold-zero-high-bits-clear-kill-flags.mir | 102 -----
...eroed-16-bit-ops.mir => redundant-and.mir} | 378 ++++++++++++++++++
2 files changed, 378 insertions(+), 102 deletions(-)
rename llvm/test/CodeGen/AMDGPU/{high-bits-zeroed-16-bit-ops.mir => redundant-and.mir} (86%)
diff --git a/llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir b/llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir
index ec8f1ef0ca1ff..d4d8c28e8a5f5 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir
@@ -52,105 +52,3 @@ body: |
%4:vgpr_32 = V_AND_B32_e64 %3:sreg_32, killed %2:vgpr_32, implicit $exec
%5:vgpr_32 = V_MUL_U32_U24_e64 killed %4:vgpr_32, %1:sreg_32, 0, implicit $exec
...
-
----
-name: no_fold_redundant_and_scc_live
-tracksRegLiveness: true
-
-body: |
- bb.0:
- liveins: $sgpr0, $sgpr1, $sgpr2
- ; GCN-LABEL: name: no_fold_redundant_and_scc_live
- ; GCN: liveins: $sgpr0, $sgpr1, $sgpr2
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 255, implicit-def $scc
- ; GCN-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_AND_B32_]], 4095, implicit-def $scc
- ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
- ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
- ; GCN-NEXT: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY1]], [[COPY2]], implicit $scc
- ; GCN-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_1]], implicit [[S_CSELECT_B32_]]
- %0:sreg_32 = COPY $sgpr0
- %1:sreg_32 = S_AND_B32 %0:sreg_32, 255, implicit-def $scc
- %2:sreg_32 = S_AND_B32 %1:sreg_32, 4095, implicit-def $scc
- %3:sreg_32 = COPY $sgpr1
- %4:sreg_32 = COPY $sgpr2
- %5:sreg_32 = S_CSELECT_B32 %3:sreg_32, %4:sreg_32, implicit $scc
- S_ENDPGM 0, implicit %2:sreg_32, implicit %5:sreg_32
-...
-
----
-name: fold_redundant_and_scc_dead
-tracksRegLiveness: true
-
-body: |
- bb.0:
- liveins: $sgpr0
- ; GCN-LABEL: name: fold_redundant_and_scc_dead
- ; GCN: liveins: $sgpr0
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 16383, implicit-def dead $scc
- ; GCN-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
- %0:sreg_32 = COPY $sgpr0
- %1:sreg_32 = S_AND_B32 %0:sreg_32, 16383, implicit-def dead $scc
- %2:sreg_32 = S_AND_B32 %1:sreg_32, 32767, implicit-def dead $scc
- S_ENDPGM 0, implicit %2:sreg_32
-...
-
----
-name: fold_redundant_and_imm_in_src0
-tracksRegLiveness: true
-
-body: |
- bb.0:
- liveins: $sgpr0
- ; GCN-LABEL: name: fold_redundant_and_imm_in_src0
- ; GCN: liveins: $sgpr0
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 127, [[COPY]], implicit-def dead $scc
- ; GCN-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
- %0:sreg_32 = COPY $sgpr0
- %1:sreg_32 = S_AND_B32 127, %0:sreg_32, implicit-def dead $scc
- %2:sreg_32 = S_AND_B32 255, %1:sreg_32, implicit-def dead $scc
- S_ENDPGM 0, implicit %2:sreg_32
-...
-
----
-name: fold_redundant_and_mixed_imm_positions
-tracksRegLiveness: true
-
-body: |
- bb.0:
- liveins: $sgpr0
- ; GCN-LABEL: name: fold_redundant_and_mixed_imm_positions
- ; GCN: liveins: $sgpr0
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1023, implicit-def dead $scc
- ; GCN-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
- %0:sreg_32 = COPY $sgpr0
- %1:sreg_32 = S_AND_B32 %0:sreg_32, 1023, implicit-def dead $scc
- %2:sreg_32 = S_AND_B32 2047, %1:sreg_32, implicit-def dead $scc
- S_ENDPGM 0, implicit %2:sreg_32
-...
-
----
-name: fold_redundant_and_mixed_imm_positions_2
-tracksRegLiveness: true
-
-body: |
- bb.0:
- liveins: $sgpr0
- ; GCN-LABEL: name: fold_redundant_and_mixed_imm_positions_2
- ; GCN: liveins: $sgpr0
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 8191, [[COPY]], implicit-def dead $scc
- ; GCN-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
- %0:sreg_32 = COPY $sgpr0
- %1:sreg_32 = S_AND_B32 8191, %0:sreg_32, implicit-def dead $scc
- %2:sreg_32 = S_AND_B32 %1:sreg_32, 65535, implicit-def dead $scc
- S_ENDPGM 0, implicit %2:sreg_32
-...
diff --git a/llvm/test/CodeGen/AMDGPU/high-bits-zeroed-16-bit-ops.mir b/llvm/test/CodeGen/AMDGPU/redundant-and.mir
similarity index 86%
rename from llvm/test/CodeGen/AMDGPU/high-bits-zeroed-16-bit-ops.mir
rename to llvm/test/CodeGen/AMDGPU/redundant-and.mir
index a360abc4ddeaf..c62b54e44ffbb 100644
--- a/llvm/test/CodeGen/AMDGPU/high-bits-zeroed-16-bit-ops.mir
+++ b/llvm/test/CodeGen/AMDGPU/redundant-and.mir
@@ -3,7 +3,13 @@
# RUN: llc -mtriple=amdgpu9.06-amd-amdhsa -run-pass=si-fold-operands -o - %s | FileCheck -check-prefix=GFX9 %s
# RUN: llc -mtriple=amdgpu10.30-amd-amdhsa -run-pass=si-fold-operands -o - %s | FileCheck -check-prefix=GFX10 %s
+# Tests for tryFoldRedundantAnd optimization.
+# This optimization eliminates a child AND instruction when its mask is a superset
+# of the parent instruction's mask. The parent can be either an explicit AND
+# instruction or an instruction that implicitly zeros high bits.
+
# Test we recognize all forms of and with mask as clearing the high bits.
+# Tests in this section have a parent instruction that implicitly zeros high bits.
---
name: v_cvt_f16_f32_altmask
tracksRegLiveness: true
@@ -2189,3 +2195,375 @@ body: |
$vgpr0 = COPY %and
...
+
+# Tests in this section have a parent AND instruction.
+#
+# Variations tested:
+# - S_AND_B32 with live vs. dead SCC (implicit def liveness)
+# - S_AND_B32 with different operand positions (imm in src0 vs src1)
+# - V_AND_B32_e32, V_AND_B32_e64 in various parent/child combinations
+# - Mixed scalar/vector: S_AND parent with V_AND child using materialized VGPR immediate
+# - Non-contiguous masks (e.g., 0xf0f, 0x5ff) to verify bitwise subset checking
+#
+# Negative tests verify optimization does NOT occur when:
+# - SCC implicit def is live
+# - Child mask doesn't fully contain parent mask
+
+---
+name: fold_redundant_and_scc_dead
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; GFX8-LABEL: name: fold_redundant_and_scc_dead
+ ; GFX8: liveins: $sgpr0
+ ; GFX8-NEXT: {{ $}}
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX8-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 16383, implicit-def dead $scc
+ ; GFX8-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
+ ;
+ ; GFX9-LABEL: name: fold_redundant_and_scc_dead
+ ; GFX9: liveins: $sgpr0
+ ; GFX9-NEXT: {{ $}}
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 16383, implicit-def dead $scc
+ ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
+ ;
+ ; GFX10-LABEL: name: fold_redundant_and_scc_dead
+ ; GFX10: liveins: $sgpr0
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 16383, implicit-def dead $scc
+ ; GFX10-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 %0:sreg_32, 16383, implicit-def dead $scc
+ %2:sreg_32 = S_AND_B32 %1:sreg_32, 32767, implicit-def dead $scc
+ S_ENDPGM 0, implicit %2:sreg_32
+...
+
+---
+---
+name: fold_redundant_and_imm_in_src0
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; GFX8-LABEL: name: fold_redundant_and_imm_in_src0
+ ; GFX8: liveins: $sgpr0
+ ; GFX8-NEXT: {{ $}}
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX8-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 127, [[COPY]], implicit-def dead $scc
+ ; GFX8-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
+ ;
+ ; GFX9-LABEL: name: fold_redundant_and_imm_in_src0
+ ; GFX9: liveins: $sgpr0
+ ; GFX9-NEXT: {{ $}}
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 127, [[COPY]], implicit-def dead $scc
+ ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
+ ;
+ ; GFX10-LABEL: name: fold_redundant_and_imm_in_src0
+ ; GFX10: liveins: $sgpr0
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 127, [[COPY]], implicit-def dead $scc
+ ; GFX10-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 127, %0:sreg_32, implicit-def dead $scc
+ %2:sreg_32 = S_AND_B32 1535, %1:sreg_32, implicit-def dead $scc
+ S_ENDPGM 0, implicit %2:sreg_32
+...
+
+---
+name: fold_redundant_and_mixed_imm_positions
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; GFX8-LABEL: name: fold_redundant_and_mixed_imm_positions
+ ; GFX8: liveins: $sgpr0
+ ; GFX8-NEXT: {{ $}}
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX8-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1023, implicit-def dead $scc
+ ; GFX8-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
+ ;
+ ; GFX9-LABEL: name: fold_redundant_and_mixed_imm_positions
+ ; GFX9: liveins: $sgpr0
+ ; GFX9-NEXT: {{ $}}
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1023, implicit-def dead $scc
+ ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
+ ;
+ ; GFX10-LABEL: name: fold_redundant_and_mixed_imm_positions
+ ; GFX10: liveins: $sgpr0
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1023, implicit-def dead $scc
+ ; GFX10-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 %0:sreg_32, 1023, implicit-def dead $scc
+ %2:sreg_32 = S_AND_B32 2047, %1:sreg_32, implicit-def dead $scc
+ S_ENDPGM 0, implicit %2:sreg_32
+...
+
+---
+name: fold_redundant_and_mixed_imm_positions_2
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; GFX8-LABEL: name: fold_redundant_and_mixed_imm_positions_2
+ ; GFX8: liveins: $sgpr0
+ ; GFX8-NEXT: {{ $}}
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX8-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 8191, [[COPY]], implicit-def dead $scc
+ ; GFX8-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
+ ;
+ ; GFX9-LABEL: name: fold_redundant_and_mixed_imm_positions_2
+ ; GFX9: liveins: $sgpr0
+ ; GFX9-NEXT: {{ $}}
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 8191, [[COPY]], implicit-def dead $scc
+ ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
+ ;
+ ; GFX10-LABEL: name: fold_redundant_and_mixed_imm_positions_2
+ ; GFX10: liveins: $sgpr0
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 8191, [[COPY]], implicit-def dead $scc
+ ; GFX10-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 8191, %0:sreg_32, implicit-def dead $scc
+ %2:sreg_32 = S_AND_B32 %1:sreg_32, 65535, implicit-def dead $scc
+ S_ENDPGM 0, implicit %2:sreg_32
+...
+
+---
+name: fold_redundant_and_vector_e32_e64
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; GFX8-LABEL: name: fold_redundant_and_vector_e32_e64
+ ; GFX8: liveins: $vgpr0
+ ; GFX8-NEXT: {{ $}}
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX8-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 63, [[COPY]], implicit $exec
+ ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 127
+ ; GFX8-NEXT: S_NOP 0, implicit [[V_AND_B32_e32_]]
+ ;
+ ; GFX9-LABEL: name: fold_redundant_and_vector_e32_e64
+ ; GFX9: liveins: $vgpr0
+ ; GFX9-NEXT: {{ $}}
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX9-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 63, [[COPY]], implicit $exec
+ ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 127
+ ; GFX9-NEXT: S_NOP 0, implicit [[V_AND_B32_e32_]]
+ ;
+ ; GFX10-LABEL: name: fold_redundant_and_vector_e32_e64
+ ; GFX10: liveins: $vgpr0
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 63, [[COPY]], implicit $exec
+ ; GFX10-NEXT: S_NOP 0, implicit [[V_AND_B32_e32_]]
+ %0:vgpr_32 = COPY $vgpr0
+ %1:vgpr_32 = V_AND_B32_e32 63, %0:vgpr_32, implicit $exec
+ %2:sreg_32 = S_MOV_B32 127
+ %3:vgpr_32 = V_AND_B32_e64 %2:sreg_32, %1:vgpr_32, implicit $exec
+ S_NOP 0, implicit %3:vgpr_32
+...
+
+---
+name: fold_redundant_and_vector_e64_e32
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; GFX8-LABEL: name: fold_redundant_and_vector_e64_e32
+ ; GFX8: liveins: $vgpr0
+ ; GFX8-NEXT: {{ $}}
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX8-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], 31, implicit $exec
+ ; GFX8-NEXT: S_NOP 0, implicit [[V_AND_B32_e64_]]
+ ;
+ ; GFX9-LABEL: name: fold_redundant_and_vector_e64_e32
+ ; GFX9: liveins: $vgpr0
+ ; GFX9-NEXT: {{ $}}
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX9-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], 31, implicit $exec
+ ; GFX9-NEXT: S_NOP 0, implicit [[V_AND_B32_e64_]]
+ ;
+ ; GFX10-LABEL: name: fold_redundant_and_vector_e64_e32
+ ; GFX10: liveins: $vgpr0
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], 31, implicit $exec
+ ; GFX10-NEXT: S_NOP 0, implicit [[V_AND_B32_e64_]]
+ %0:vgpr_32 = COPY $vgpr0
+ %1:sreg_32 = S_MOV_B32 31
+ %2:vgpr_32 = V_AND_B32_e64 %0:vgpr_32, %1:sreg_32, implicit $exec
+ %3:vgpr_32 = V_AND_B32_e32 255, %2:vgpr_32, implicit $exec
+ S_NOP 0, implicit %3:vgpr_32
+...
+
+---
+name: fold_redundant_and_vector_e64_e64
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; GFX8-LABEL: name: fold_redundant_and_vector_e64_e64
+ ; GFX8: liveins: $vgpr0
+ ; GFX8-NEXT: {{ $}}
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX8-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 15, [[COPY]], implicit $exec
+ ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 511
+ ; GFX8-NEXT: S_NOP 0, implicit [[V_AND_B32_e64_]]
+ ;
+ ; GFX9-LABEL: name: fold_redundant_and_vector_e64_e64
+ ; GFX9: liveins: $vgpr0
+ ; GFX9-NEXT: {{ $}}
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX9-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 15, [[COPY]], implicit $exec
+ ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 511
+ ; GFX9-NEXT: S_NOP 0, implicit [[V_AND_B32_e64_]]
+ ;
+ ; GFX10-LABEL: name: fold_redundant_and_vector_e64_e64
+ ; GFX10: liveins: $vgpr0
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 15, [[COPY]], implicit $exec
+ ; GFX10-NEXT: S_NOP 0, implicit [[V_AND_B32_e64_]]
+ %0:vgpr_32 = COPY $vgpr0
+ %1:sreg_32 = S_MOV_B32 15
+ %2:vgpr_32 = V_AND_B32_e64 %1:sreg_32, %0:vgpr_32, implicit $exec
+ %3:sreg_32 = S_MOV_B32 511
+ %4:vgpr_32 = V_AND_B32_e64 %2:vgpr_32, %3:sreg_32, implicit $exec
+ S_NOP 0, implicit %4:vgpr_32
+...
+
+---
+name: fold_redundant_and_scalar_parent_vgpr_imm_child
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; GFX8-LABEL: name: fold_redundant_and_scalar_parent_vgpr_imm_child
+ ; GFX8: liveins: $sgpr0
+ ; GFX8-NEXT: {{ $}}
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX8-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 255, implicit-def dead $scc
+ ; GFX8-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 511, implicit $exec
+ ; GFX8-NEXT: S_NOP 0, implicit [[S_AND_B32_]]
+ ;
+ ; GFX9-LABEL: name: fold_redundant_and_scalar_parent_vgpr_imm_child
+ ; GFX9: liveins: $sgpr0
+ ; GFX9-NEXT: {{ $}}
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 255, implicit-def dead $scc
+ ; GFX9-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 511, implicit $exec
+ ; GFX9-NEXT: S_NOP 0, implicit [[S_AND_B32_]]
+ ;
+ ; GFX10-LABEL: name: fold_redundant_and_scalar_parent_vgpr_imm_child
+ ; GFX10: liveins: $sgpr0
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 255, implicit-def dead $scc
+ ; GFX10-NEXT: S_NOP 0, implicit [[S_AND_B32_]]
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 %0:sreg_32, 255, implicit-def dead $scc
+ %2:vgpr_32 = V_MOV_B32_e32 511, implicit $exec
+ %3:vgpr_32 = V_AND_B32_e64 %2:vgpr_32, %1:sreg_32, implicit $exec
+ S_NOP 0, implicit %3:vgpr_32
+...
+
+---
+name: no_fold_redundant_and_scc_live
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $sgpr2
+ ; GFX8-LABEL: name: no_fold_redundant_and_scc_live
+ ; GFX8: liveins: $sgpr0, $sgpr1, $sgpr2
+ ; GFX8-NEXT: {{ $}}
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX8-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 255, implicit-def $scc
+ ; GFX8-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_AND_B32_]], 3855, implicit-def $scc
+ ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX8-NEXT: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY1]], [[COPY2]], implicit $scc
+ ; GFX8-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_1]], implicit [[S_CSELECT_B32_]]
+ ;
+ ; GFX9-LABEL: name: no_fold_redundant_and_scc_live
+ ; GFX9: liveins: $sgpr0, $sgpr1, $sgpr2
+ ; GFX9-NEXT: {{ $}}
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 255, implicit-def $scc
+ ; GFX9-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_AND_B32_]], 3855, implicit-def $scc
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX9-NEXT: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY1]], [[COPY2]], implicit $scc
+ ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_1]], implicit [[S_CSELECT_B32_]]
+ ;
+ ; GFX10-LABEL: name: no_fold_redundant_and_scc_live
+ ; GFX10: liveins: $sgpr0, $sgpr1, $sgpr2
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 255, implicit-def $scc
+ ; GFX10-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_AND_B32_]], 3855, implicit-def $scc
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX10-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX10-NEXT: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY1]], [[COPY2]], implicit $scc
+ ; GFX10-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_1]], implicit [[S_CSELECT_B32_]]
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 %0:sreg_32, 255, implicit-def $scc
+ %2:sreg_32 = S_AND_B32 %1:sreg_32, 3855, implicit-def $scc
+ %3:sreg_32 = COPY $sgpr1
+ %4:sreg_32 = COPY $sgpr2
+ %5:sreg_32 = S_CSELECT_B32 %3:sreg_32, %4:sreg_32, implicit $scc
+ S_ENDPGM 0, implicit %2:sreg_32, implicit %5:sreg_32
+...
+
+---
+name: no_fold_redundant_and_child_mask_insufficient
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; GFX8-LABEL: name: no_fold_redundant_and_child_mask_insufficient
+ ; GFX8: liveins: $sgpr0
+ ; GFX8-NEXT: {{ $}}
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX8-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 255, implicit-def dead $scc
+ ; GFX8-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_AND_B32_]], 127, implicit-def dead $scc
+ ; GFX8-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_1]]
+ ;
+ ; GFX9-LABEL: name: no_fold_redundant_and_child_mask_insufficient
+ ; GFX9: liveins: $sgpr0
+ ; GFX9-NEXT: {{ $}}
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 255, implicit-def dead $scc
+ ; GFX9-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_AND_B32_]], 127, implicit-def dead $scc
+ ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_1]]
+ ;
+ ; GFX10-LABEL: name: no_fold_redundant_and_child_mask_insufficient
+ ; GFX10: liveins: $sgpr0
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 255, implicit-def dead $scc
+ ; GFX10-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_AND_B32_]], 127, implicit-def dead $scc
+ ; GFX10-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_1]]
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 %0:sreg_32, 255, implicit-def dead $scc
+ %2:sreg_32 = S_AND_B32 %1:sreg_32, 127, implicit-def dead $scc
+ S_ENDPGM 0, implicit %2:sreg_32
+...
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