[llvm] [VPlan] Fix replaceWithFinalIfReductionStore assert with multiple reductions (PR #217316)

[Luke Lau via llvm-commits]

https://github.com/lukel97 created https://github.com/llvm/llvm-project/pull/217316

A reductions final value can be simplified away to a constant, which https://github.com/llvm/llvm-project/pull/201023 handled.
However constant live ins can have other users, e.g. a different reductions start value, in which case the assertion will fail because we're comparing the backedge value of a different reduction entirely. Relax the assertion to allow any VPIRValue instead

This an alternative to https://github.com/llvm/llvm-project/pull/217306 that fixes #215071


>From 4efd9fe960374c7e2906c3c4764d696e9a6d7b74 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Wed, 19 Aug 2026 20:01:58 +0800
Subject: [PATCH] [VPlan] Fix replaceWithFinalIfReductionStore assert with
 multiple reductions

A reductions final value can be simplified away to a constant, which https://github.com/llvm/llvm-project/pull/201023 handled.
However constant live ins can have other users, e.g. a different reductions start value, in which case the assertion will fail because we're comparing the backedge value of a different reduction entirely. Relax the assertion to allow any VPIRValue instead

This an alternative to https://github.com/llvm/llvm-project/pull/217306 that fixes #215071
---
 .../Transforms/Vectorize/LoopVectorize.cpp    |  2 +-
 .../reduction-with-invariant-store.ll         | 39 +++++++++++++++++++
 2 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 4fe989b9d6a2c..3a246ac4db290 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -6387,7 +6387,7 @@ bool VPRecipeBuilder::replaceWithFinalIfReductionStore(
         Val = Blend;
       [[maybe_unused]] auto *Rdx =
           VPlanPatternMatch::findUserOf<VPReductionPHIRecipe>(Val);
-      assert((!Rdx || Rdx->getBackedgeValue() == Val) &&
+      assert((isa<VPIRValue>(Val) || !Rdx || Rdx->getBackedgeValue() == Val) &&
              "Store of reduction thats not the backedge value?");
       auto *Recipe = new VPReplicateRecipe(
           SI, {Val, Addr}, true /* IsUniform */, nullptr /*Mask*/, *VPI, *VPI,
diff --git a/llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll b/llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll
index 88bd76ec53912..ccfb11b0c4fb6 100644
--- a/llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll
+++ b/llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll
@@ -1332,3 +1332,42 @@ loop:
 exit:
   ret void
 }
+
+; Don't crash if reduction is simplifable to a constant and the constant is also
+; used by another reduction's start value.
+define i32 @multiple_simplifiable_reductions(ptr %p) {
+; CHECK-LABEL: define i32 @multiple_simplifiable_reductions(
+; CHECK-SAME: ptr [[P:%.*]]) {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]
+; CHECK:       [[VECTOR_PH]]:
+; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]
+; CHECK:       [[VECTOR_BODY]]:
+; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[VEC_PHI]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1020
+; CHECK-NEXT:    br i1 [[TMP0]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP88:![0-9]+]]
+; CHECK:       [[MIDDLE_BLOCK]]:
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[VEC_PHI]])
+; CHECK-NEXT:    store i32 0, ptr [[P]], align 4
+; CHECK-NEXT:    br label %[[SCALAR_PH:.*]]
+; CHECK:       [[SCALAR_PH]]:
+;
+entry:
+  br label %loop
+
+loop:
+  %iv = phi i32 [ 1, %entry ], [ %iv.next, %loop ]
+  %rdx.and = phi i32 [ 0, %entry ], [ %rdx.and.next, %loop ]
+  %rdx.or = phi i32 [ 0, %entry ], [ %rdx.or.next, %loop ]
+  %rdx.and.next = and i32 0, %rdx.and
+  store i32 %rdx.and.next, ptr %p
+  %rdx.or.next = or i32 0, %rdx.or
+  %iv.next = add i32 %iv, 1
+  %ec = icmp eq i32 %iv.next, 1024
+  br i1 %ec, label %exit, label %loop
+
+exit:
+  ret i32 %rdx.or.next
+}