[llvm] [AMDGPU] Enable CSE in the GlobalISel post-legalizer combiner (PR #217258)
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llvm-commits at lists.llvm.org
Wed Aug 19 03:09:09 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Keshav Vinayak Jha (keshavvinayak01)
<details>
<summary>Changes</summary>
Enable GISel CSE in the legacy AMDGPU post-legalizer combiner so it matches the new pass-manager path.
Notify GlobalISel observers when register attributes, operands, or instruction parent blocks change, preventing stale CSE profiles. This also updates affected checks and adds a regression test for `CombinerHelper::replaceRegWith`
More context: https://github.com/llvm/llvm-project/pull/216274#pullrequestreview-4964537468
---
Patch is 90.00 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/217258.diff
14 Files Affected:
- (modified) llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp (+9)
- (modified) llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (+50-9)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp (+13-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.postlegal.mir (+20-20)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll (+1-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll (+37-45)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.ll (+17-23)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-ubfx.mir (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll (+28-28)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll (+11-11)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll (+14-18)
- (modified) llvm/test/CodeGen/AMDGPU/div_i128.ll (+121-166)
- (modified) llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll (+4-4)
- (modified) llvm/unittests/CodeGen/GlobalISel/CSETest.cpp (+21)
``````````diff
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 55c4339edc39e..e8b02f3fcce07 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -189,6 +189,13 @@ bool CombinerHelper::isConstantLegalOrBeforeLegalizer(const LLT Ty) const {
void CombinerHelper::replaceRegWith(MachineRegisterInfo &MRI, Register FromReg,
Register ToReg) const {
+ // constrainRegAttrs may change attributes that are part of the CSE profile
+ // for every instruction that references ToReg.
+ SmallVector<MachineInstr *, 4> ToRegInstrs;
+ for (MachineInstr &MI : MRI.reg_instructions(ToReg)) {
+ Observer.changingInstr(MI);
+ ToRegInstrs.push_back(&MI);
+ }
Observer.changingAllUsesOfReg(MRI, FromReg);
if (MRI.constrainRegAttrs(ToReg, FromReg))
@@ -197,6 +204,8 @@ void CombinerHelper::replaceRegWith(MachineRegisterInfo &MRI, Register FromReg,
Builder.buildCopy(FromReg, ToReg);
Observer.finishedChangingAllUsesOfReg();
+ for (MachineInstr *MI : ToRegInstrs)
+ Observer.changedInstr(*MI);
}
void CombinerHelper::replaceRegOpWith(MachineRegisterInfo &MRI,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 38b88d87051c6..6608b67363514 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -24,6 +24,8 @@
#include "SIRegisterInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/ADT/ScopeExit.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
@@ -55,6 +57,26 @@ static cl::opt<bool> EnableNewLegality(
static constexpr unsigned MaxRegisterSize = 1024;
+// Register class is part of the CSE profile for every instruction that
+// references a register, so notify observers before changing it.
+static void setRegClassWithObserver(MachineIRBuilder &B,
+ MachineRegisterInfo &MRI, Register Reg,
+ const TargetRegisterClass *RC) {
+ GISelChangeObserver *Observer = B.getMF().getObserver();
+ if (!Observer) {
+ MRI.setRegClass(Reg, RC);
+ return;
+ }
+ SmallVector<MachineInstr *, 4> RegInstrs;
+ for (MachineInstr &MI : MRI.reg_instructions(Reg)) {
+ Observer->changingInstr(MI);
+ RegInstrs.push_back(&MI);
+ }
+ MRI.setRegClass(Reg, RC);
+ for (MachineInstr *MI : RegInstrs)
+ Observer->changedInstr(*MI);
+}
+
// Round the number of elements to the next power of two elements
static LLT getPow2VectorType(LLT Ty) {
unsigned NElts = Ty.getNumElements();
@@ -3009,8 +3031,11 @@ bool AMDGPULegalizerInfo::legalizeExtract(LegalizerHelper &Helper,
if (DstCount == 1) {
if (DstTy.isPointer())
B.buildIntToPtr(DstReg, Unmerge.getReg(StartIdx));
- else
+ else {
+ Helper.Observer.changingAllUsesOfReg(MRI, DstReg);
MRI.replaceRegWith(DstReg, Unmerge.getReg(StartIdx));
+ Helper.Observer.finishedChangingAllUsesOfReg();
+ }
} else {
SmallVector<Register, 8> MergeVec;
for (unsigned I = 0; I < DstCount; ++I)
@@ -3266,7 +3291,7 @@ bool AMDGPULegalizerInfo::buildPCRelGlobalAddress(Register DstReg, LLT PtrTy,
}
if (!B.getMRI()->getRegClassOrNull(PCReg))
- B.getMRI()->setRegClass(PCReg, &AMDGPU::SReg_64RegClass);
+ setRegClassWithObserver(B, *B.getMRI(), PCReg, &AMDGPU::SReg_64RegClass);
if (PtrTy.getSizeInBits() == 32)
B.buildExtract(DstReg, PCReg, 0);
@@ -3281,7 +3306,7 @@ void AMDGPULegalizerInfo::buildAbsGlobalAddress(
if (RequiresHighHalf && ST.has64BitLiterals()) {
if (!MRI.getRegClassOrNull(DstReg))
- MRI.setRegClass(DstReg, &AMDGPU::SReg_64RegClass);
+ setRegClassWithObserver(B, MRI, DstReg, &AMDGPU::SReg_64RegClass);
B.buildInstr(AMDGPU::S_MOV_B64)
.addDef(DstReg)
.addGlobalAddress(GV, 0, SIInstrInfo::MO_ABS64);
@@ -3297,7 +3322,7 @@ void AMDGPULegalizerInfo::buildAbsGlobalAddress(
: MRI.createGenericVirtualRegister(I32);
if (!MRI.getRegClassOrNull(AddrLo))
- MRI.setRegClass(AddrLo, &AMDGPU::SReg_32RegClass);
+ setRegClassWithObserver(B, MRI, AddrLo, &AMDGPU::SReg_32RegClass);
// Write the lower half.
B.buildInstr(AMDGPU::S_MOV_B32)
@@ -3323,7 +3348,7 @@ void AMDGPULegalizerInfo::buildAbsGlobalAddress(
: MRI.createGenericVirtualRegister(LLT::integer(64));
if (!MRI.getRegClassOrNull(AddrDst))
- MRI.setRegClass(AddrDst, &AMDGPU::SReg_64RegClass);
+ setRegClassWithObserver(B, MRI, AddrDst, &AMDGPU::SReg_64RegClass);
B.buildMergeValues(AddrDst, {AddrLo, AddrHi});
@@ -7773,7 +7798,23 @@ bool AMDGPULegalizerInfo::legalizeTrapEndpgm(
// We need a block split to make the real endpgm a terminator. We also don't
// want to break phis in successor blocks, so we can't just delete to the
// end of the block.
+ // An instruction's parent block is part of its CSE profile, so notify
+ // observers about the instructions moved by the split.
+ GISelChangeObserver *Observer = MF->getObserver();
+ SmallVector<MachineInstr *, 8> MovedInstrs;
+ MachineBasicBlock::iterator SplitPoint(&MI);
+ ++SplitPoint;
+ if (Observer && SplitPoint != BB.end()) {
+ for (MachineInstr &MovedMI : make_range(SplitPoint, BB.end())) {
+ Observer->changingInstr(MovedMI);
+ MovedInstrs.push_back(&MovedMI);
+ }
+ }
BB.splitAt(MI, false /*UpdateLiveIns*/);
+ if (Observer) {
+ for (MachineInstr *MovedMI : MovedInstrs)
+ Observer->changedInstr(*MovedMI);
+ }
MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
MF->push_back(TrapBB);
BuildMI(*TrapBB, TrapBB->end(), DL, B.getTII().get(AMDGPU::S_ENDPGM))
@@ -8119,7 +8160,7 @@ bool AMDGPULegalizerInfo::legalizeConstHwRegRead(MachineInstr &MI,
MachineRegisterInfo &MRI = *B.getMRI();
Register DstReg = MI.getOperand(0).getReg();
if (!MRI.getRegClassOrNull(DstReg))
- MRI.setRegClass(DstReg, &AMDGPU::SReg_32RegClass);
+ setRegClassWithObserver(B, MRI, DstReg, &AMDGPU::SReg_32RegClass);
B.buildInstr(AMDGPU::S_GETREG_B32_const)
.addDef(DstReg)
.addImm(AMDGPU::Hwreg::HwregEncoding::encode(HwReg, LowBit, Width));
@@ -8268,8 +8309,8 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
B.buildBr(*CondBrTarget);
}
- MRI.setRegClass(Def, TRI->getWaveMaskRegClass());
- MRI.setRegClass(Use, TRI->getWaveMaskRegClass());
+ setRegClassWithObserver(B, MRI, Def, TRI->getWaveMaskRegClass());
+ setRegClassWithObserver(B, MRI, Use, TRI->getWaveMaskRegClass());
MI.eraseFromParent();
BrCond->eraseFromParent();
return true;
@@ -8304,7 +8345,7 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
MI.eraseFromParent();
BrCond->eraseFromParent();
- MRI.setRegClass(Reg, TRI->getWaveMaskRegClass());
+ setRegClassWithObserver(B, MRI, Reg, TRI->getWaveMaskRegClass());
return true;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
index 66db3d49656a6..fbf6e73d75c23 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
@@ -16,6 +16,7 @@
#include "AMDGPULegalizerInfo.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
+#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
#include "llvm/CodeGen/GlobalISel/Combiner.h"
#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
@@ -463,10 +464,13 @@ class AMDGPUPostLegalizerCombiner : public MachineFunctionPass {
} // end anonymous namespace
void AMDGPUPostLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addRequired<TargetPassConfig>();
AU.setPreservesCFG();
getSelectionDAGFallbackAnalysisUsage(AU);
AU.addRequired<GISelValueTrackingAnalysisLegacy>();
AU.addPreserved<GISelValueTrackingAnalysisLegacy>();
+ AU.addRequired<GISelCSEAnalysisWrapperPass>();
+ AU.addPreserved<GISelCSEAnalysisWrapperPass>();
if (!IsOptNone) {
AU.addRequired<MachineDominatorTreeWrapperPass>();
}
@@ -482,6 +486,7 @@ AMDGPUPostLegalizerCombiner::AMDGPUPostLegalizerCombiner(bool IsOptNone)
bool AMDGPUPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
if (MF.getProperties().hasFailedISel())
return false;
+ const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
const Function &F = MF.getFunction();
bool EnableOpt =
MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F);
@@ -496,6 +501,10 @@ bool AMDGPUPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
IsOptNone ? nullptr
: &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+ GISelCSEAnalysisWrapper &Wrapper =
+ getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
+ GISelCSEInfo *CSEInfo = &Wrapper.get(TPC.getCSEConfig());
+
CombinerInfo CInfo(/*AllowIllegalOps*/ false, /*ShouldLegalizeIllegal*/ true,
LI, EnableOpt, F.hasOptSize(), F.hasMinSize());
// Disable fixed-point iteration to reduce compile-time
@@ -503,8 +512,8 @@ bool AMDGPUPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass;
// Legalizer performs DCE, so a full DCE pass is unnecessary.
CInfo.EnableFullDCE = false;
- AMDGPUPostLegalizerCombinerImpl Impl(MF, CInfo, *VT, /*CSEInfo*/ nullptr,
- RuleConfig, ST, MDT, LI);
+ AMDGPUPostLegalizerCombinerImpl Impl(MF, CInfo, *VT, CSEInfo, RuleConfig, ST,
+ MDT, LI);
return Impl.combineMachineInstrs();
}
@@ -512,7 +521,9 @@ char AMDGPUPostLegalizerCombiner::ID = 0;
INITIALIZE_PASS_BEGIN(AMDGPUPostLegalizerCombiner, DEBUG_TYPE,
"Combine AMDGPU machine instrs after legalization", false,
false)
+INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy)
+INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass)
INITIALIZE_PASS_END(AMDGPUPostLegalizerCombiner, DEBUG_TYPE,
"Combine AMDGPU machine instrs after legalization", false,
false)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.postlegal.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.postlegal.mir
index 7e83c0d02b43f..5a337b251bab6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.postlegal.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.postlegal.mir
@@ -115,8 +115,8 @@ body: |
; GFX6-NEXT: %narrow:_(s32) = COPY $vgpr0
; GFX6-NEXT: %masklow30:_(s32) = G_CONSTANT i32 1073741823
; GFX6-NEXT: %masked:_(s32) = G_AND %narrow, %masklow30
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %masked, [[C]](s32)
+ ; GFX6-NEXT: %shiftamt:_(s32) = G_CONSTANT i32 2
+ ; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %masked, %shiftamt(s32)
; GFX6-NEXT: %shl:_(s64) = G_ZEXT [[SHL]](s32)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY %shl(s64)
;
@@ -126,8 +126,8 @@ body: |
; GFX9-NEXT: %narrow:_(s32) = COPY $vgpr0
; GFX9-NEXT: %masklow30:_(s32) = G_CONSTANT i32 1073741823
; GFX9-NEXT: %masked:_(s32) = G_AND %narrow, %masklow30
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %masked, [[C]](s32)
+ ; GFX9-NEXT: %shiftamt:_(s32) = G_CONSTANT i32 2
+ ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %masked, %shiftamt(s32)
; GFX9-NEXT: %shl:_(s64) = G_ZEXT [[SHL]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY %shl(s64)
%narrow:_(s32) = COPY $vgpr0
@@ -153,8 +153,8 @@ body: |
; GFX6-NEXT: %narrow:_(s32) = COPY $vgpr0
; GFX6-NEXT: %masklow30:_(s32) = G_CONSTANT i32 1073741823
; GFX6-NEXT: %masked:_(s32) = G_AND %narrow, %masklow30
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %masked, [[C]](s32)
+ ; GFX6-NEXT: %shiftamt:_(s32) = G_CONSTANT i32 2
+ ; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %masked, %shiftamt(s32)
; GFX6-NEXT: %shl:_(s64) = G_ZEXT [[SHL]](s32)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY %shl(s64)
;
@@ -164,8 +164,8 @@ body: |
; GFX9-NEXT: %narrow:_(s32) = COPY $vgpr0
; GFX9-NEXT: %masklow30:_(s32) = G_CONSTANT i32 1073741823
; GFX9-NEXT: %masked:_(s32) = G_AND %narrow, %masklow30
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %masked, [[C]](s32)
+ ; GFX9-NEXT: %shiftamt:_(s32) = G_CONSTANT i32 2
+ ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %masked, %shiftamt(s32)
; GFX9-NEXT: %shl:_(s64) = G_ZEXT [[SHL]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY %shl(s64)
%narrow:_(s32) = COPY $vgpr0
@@ -191,8 +191,8 @@ body: |
; GFX6-NEXT: %narrow:_(s32) = COPY $vgpr0
; GFX6-NEXT: %masklow30:_(s32) = G_CONSTANT i32 1073741823
; GFX6-NEXT: %masked:_(s32) = G_AND %narrow, %masklow30
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %masked, [[C]](s32)
+ ; GFX6-NEXT: %shiftamt:_(s32) = G_CONSTANT i32 2
+ ; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %masked, %shiftamt(s32)
; GFX6-NEXT: %shl:_(s64) = G_ZEXT [[SHL]](s32)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY %shl(s64)
;
@@ -202,8 +202,8 @@ body: |
; GFX9-NEXT: %narrow:_(s32) = COPY $vgpr0
; GFX9-NEXT: %masklow30:_(s32) = G_CONSTANT i32 1073741823
; GFX9-NEXT: %masked:_(s32) = G_AND %narrow, %masklow30
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %masked, [[C]](s32)
+ ; GFX9-NEXT: %shiftamt:_(s32) = G_CONSTANT i32 2
+ ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %masked, %shiftamt(s32)
; GFX9-NEXT: %shl:_(s64) = G_ZEXT [[SHL]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY %shl(s64)
%narrow:_(s32) = COPY $vgpr0
@@ -229,8 +229,8 @@ body: |
; GFX6-NEXT: %narrow:_(s32) = COPY $vgpr0
; GFX6-NEXT: %masklow30:_(s32) = G_CONSTANT i32 1073741823
; GFX6-NEXT: %masked:_(s32) = G_AND %narrow, %masklow30
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %masked, [[C]](s32)
+ ; GFX6-NEXT: %shiftamt:_(s32) = G_CONSTANT i32 2
+ ; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %masked, %shiftamt(s32)
; GFX6-NEXT: %shl:_(s64) = G_ZEXT [[SHL]](s32)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY %shl(s64)
;
@@ -240,8 +240,8 @@ body: |
; GFX9-NEXT: %narrow:_(s32) = COPY $vgpr0
; GFX9-NEXT: %masklow30:_(s32) = G_CONSTANT i32 1073741823
; GFX9-NEXT: %masked:_(s32) = G_AND %narrow, %masklow30
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %masked, [[C]](s32)
+ ; GFX9-NEXT: %shiftamt:_(s32) = G_CONSTANT i32 2
+ ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %masked, %shiftamt(s32)
; GFX9-NEXT: %shl:_(s64) = G_ZEXT [[SHL]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY %shl(s64)
%narrow:_(s32) = COPY $vgpr0
@@ -348,14 +348,14 @@ body: |
; GFX6-LABEL: name: do_not_shl_s32_zero_by_16_from_zext_s16
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: %shl:_(s32) = G_CONSTANT i32 0
- ; GFX6-NEXT: $vgpr0 = COPY %shl(s32)
+ ; GFX6-NEXT: %extend:_(s32) = G_CONSTANT i32 0
+ ; GFX6-NEXT: $vgpr0 = COPY %extend(s32)
;
; GFX9-LABEL: name: do_not_shl_s32_zero_by_16_from_zext_s16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: %shl:_(s32) = G_CONSTANT i32 0
- ; GFX9-NEXT: $vgpr0 = COPY %shl(s32)
+ ; GFX9-NEXT: %extend:_(s32) = G_CONSTANT i32 0
+ ; GFX9-NEXT: $vgpr0 = COPY %extend(s32)
%zero:_(s16) = G_CONSTANT i16 0
%extend:_(s32) = G_ZEXT %zero:_(s16)
%shiftamt:_(s16) = G_CONSTANT i16 16
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
index 8240c94454757..dd2b0c81727f3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
@@ -10,9 +10,8 @@ define amdgpu_kernel void @stack_write_fi() {
; CHECK-NEXT: s_add_u32 s0, s0, s17
; CHECK-NEXT: s_addc_u32 s1, s1, 0
; CHECK-NEXT: s_mov_b32 s5, 0
-; CHECK-NEXT: s_mov_b32 s6, 0
; CHECK-NEXT: s_mov_b32 s4, 0
-; CHECK-NEXT: v_mov_b32_e32 v0, s6
+; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: v_mov_b32_e32 v1, s5
; CHECK-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
; CHECK-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
index 5739d01e61d95..04cdd48f8f78e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
@@ -220,13 +220,12 @@ define amdgpu_ps ptr addrspace(8) @num_records_i16_raw_buffer(ptr inreg %p, i16
; CHECK45-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_AND_B64_]].sub0
; CHECK45-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 25
; CHECK45-NEXT: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY4]], [[S_MOV_B32_1]], implicit-def dead $scc
- ; CHECK45-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 0
- ; CHECK45-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_2]], %subreg.sub0, [[S_LSHL_B32_]], %subreg.sub1
+ ; CHECK45-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_LSHL_B32_]], %subreg.sub1
; CHECK45-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[REG_SEQUENCE]], [[REG_SEQUENCE2]], implicit-def dead $scc
- ; CHECK45-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 7
- ; CHECK45-NEXT: [[S_LSHR_B64_:%[0-9]+]]:sreg_64 = S_LSHR_B64 [[S_AND_B64_]], [[S_MOV_B32_3]], implicit-def dead $scc
- ; CHECK45-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 28
- ; CHECK45-NEXT: [[S_LSHL_B32_1:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY3]], [[S_MOV_B32_4]], implicit-def dead $scc
+ ; CHECK45-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 7
+ ; CHECK45-NEXT: [[S_LSHR_B64_:%[0-9]+]]:sreg_64 = S_LSHR_B64 [[S_AND_B64_]], [[S_MOV_B32_2]], implicit-def dead $scc
+ ; CHECK45-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 28
+ ; CHECK45-NEXT: [[S_LSHL_B32_1:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY3]], [[S_MOV_B32_3]], implicit-def dead $scc
; CHECK45-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_LSHL_B32_1]], %subreg.sub1
; CHECK45-NEXT: [[S_OR_B64_1:%[0-9]+]]:sreg_64 = S_OR_B64 [[S_LSHR_B64_]], [[REG_SEQUENCE3]], implicit-def dead $scc
; CHECK45-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_OR_B64_]].sub0
@@ -289,13 +288,12 @@ define amdgpu_ps ptr addrspace(8) @num_records_i32_raw_buffer(ptr inreg %p, i32
; CHECK45-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE1]].sub0
; CHECK45-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 25
; CHECK45-NEXT: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY4]], [[S_MOV_B32_1]], implicit-def dead $scc
- ; CHECK45-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 0
- ; CHECK45-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_2]], %subreg.sub0, [[S_LSHL_B32_]], %subreg.sub1
+ ; CHECK45-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_LSHL_B32_]], %subreg.sub1
; CHECK45-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[REG_SEQUENCE]], [[REG_SEQUENCE2]], implicit-def dead $scc
- ; CHECK45-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 7
- ; CHECK45-NEXT: [[S_LSHR_B64_:%[0-9]+]]:sreg_64...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/217258
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